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authorjaseg <git@jaseg.de>2020-11-26 12:38:52 +0100
committerjaseg <git@jaseg.de>2020-11-26 12:38:52 +0100
commit451904a0c5fae3bd28d35c7128df3a9db1a04b26 (patch)
treeb406c126b08032219894db3ff16a2ccf87c667d6 /.gitmodules
parente282a5eb373ec4b44d36f580fe642483f2e52794 (diff)
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Add CRC32 implementation
Diffstat (limited to '.gitmodules')
-rw-r--r--.gitmodules3
1 files changed, 3 insertions, 0 deletions
diff --git a/.gitmodules b/.gitmodules
index c7286ab..9c01adf 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -22,3 +22,6 @@
path = prototype/fw/upstream/stm32square
url = https://gitlab.com/neinseg/stm32square
branch = release
+[submodule "prototype/fw/upstream/PyCortexMDebug"]
+ path = prototype/fw/upstream/PyCortexMDebug
+ url = https://github.com/bnahill/PyCortexMDebug