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8seg: Gigantic low-cost segmented alphanumeric display light installation
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driver.kicad_pcb
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2023-11-06
Final PCB revision (center R7/driver R8)
jaseg
1
-13272
/
+27555
2023-09-25
Driver schematic revision 8
jaseg
1
-12319
/
+12431
2023-08-28
Waveform interleaving seems to work
jaseg
1
-6702
/
+12092
2023-08-27
new driver blinkenlights
jaseg
1
-3
/
+19
2023-05-29
PCB revision WIP
jaseg
1
-35251
/
+43106
2023-05-25
Driver Filter WIP
jaseg
1
-48753
/
+43387
2022-07-24
Update PCBs
jaseg
1
-8203
/
+47785
2022-05-08
Update PCBs
jaseg
1
-9719
/
+9171
2019-04-25
driver: Finish R4 artwork and gerber export
jaseg
1
-211
/
+144
2019-04-24
driver: Fix ALL the PCB issues in R3
jaseg
1
-6395
/
+7963
2019-02-02
driver: fix a few misplaced vias, set grid origin, fix bottom mask
jaseg
1
-35
/
+37
2019-01-31
driver: Prettify heatsink mounting holes a bit
jaseg
1
-63
/
+102
2019-01-31
driver: Add board revision, fix up mask
jaseg
1
-62
/
+75
2019-01-31
driver: Add mounting holes for heatsink
jaseg
1
-470
/
+640
2019-01-31
driver: Move traces away from board edge
jaseg
1
-295
/
+321
2019-01-31
Small adjustments, fix silk
jaseg
1
-1016
/
+1077
2019-01-30
Throw out a bunch, use a different microcontroller
jaseg
1
-2812
/
+3642
2019-01-30
Fix lcd connector position
jaseg
1
-1531
/
+310
2019-01-29
driver: Add mounting holes for RS485 adapter
jaseg
1
-2269
/
+2034
2019-01-29
Modify temp sensor to MSOP fp, add fan conn
jaseg
1
-227
/
+292
2019-01-23
Fix R1 footprint
jaseg
1
-135
/
+142
0603 -> 1206
2019-01-20
Fix up a couple of dimensions
jaseg
1
-43
/
+44
2019-01-19
driver: Fatten a few power traces
jaseg
1
-231
/
+232
2019-01-19
driver: Fixup SWD header, swap driver outputs for VSW split, finish silk
jaseg
1
-1614
/
+1911
2019-01-18
driver: initial DRC done
jaseg
1
-94
/
+107
2019-01-18
driver: Finish initial routing
jaseg
1
-1316
/
+1547
2019-01-18
driver: Initial layout almost done
jaseg
1
-1203
/
+1676
2019-01-17
driver: Continue layout
jaseg
1
-2063
/
+3475
2019-01-17
driver: Initial layout
jaseg
1
-1
/
+6033
2019-01-15
Add initial driver schematic draft
jaseg
1
-0
/
+1