aboutsummaryrefslogtreecommitdiff
path: root/center_fw
diff options
context:
space:
mode:
Diffstat (limited to 'center_fw')
-rw-r--r--center_fw/Makefile13
-rw-r--r--center_fw/main.c194
2 files changed, 15 insertions, 192 deletions
diff --git a/center_fw/Makefile b/center_fw/Makefile
index 5987b9f..98c0f5b 100644
--- a/center_fw/Makefile
+++ b/center_fw/Makefile
@@ -14,7 +14,7 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
-CUBE_PATH ?= $(wildcard ~)/ref/stm32cube/STM32CubeF0
+CUBE_PATH ?= $(wildcard ~)/ref/STM32CubeF0
CMSIS_PATH ?= $(CUBE_PATH)/Drivers/CMSIS
CMSIS_DEV_PATH ?= $(CMSIS_PATH)/Device/ST/STM32F0xx
HAL_PATH ?= $(CUBE_PATH)/Drivers/STM32F0xx_HAL_Driver
@@ -79,7 +79,7 @@ sources.tar.xz.zip: sources.tar.xz
sources.c: sources.tar.xz.zip
xxd -i $< | head -n -1 | sed 's/=/__attribute__((section(".source_tarball"))) =/' > $@
-main.elf: main.c startup_stm32f030x6.s system_stm32f0xx.c $(HAL_PATH)/Src/stm32f0xx_ll_utils.c base.c cmsis_exports.c ../common/8b10b.c adc.c protocol.c 8seg_protocol.c transmit.c
+main.elf: main.c startup_stm32f030x6.s system_stm32f0xx.c base.c
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
$(OBJCOPY) -O ihex $@ $(@:.elf=.hex)
$(OBJCOPY) -O binary $@ $(@:.elf=.bin)
@@ -89,15 +89,6 @@ main.elf: main.c startup_stm32f030x6.s system_stm32f0xx.c $(HAL_PATH)/Src/stm32f
program: main.elf openocd.cfg
openocd -f openocd.cfg -c "program $< verify reset exit"
-8b10b_test_encode: 8b10b_test_encode.c 8b10b.c
- gcc -o $@ $^
-
-8b10b_test_decode: 8b10b_test_decode.c 8b10b.c
- gcc -o $@ $^
-
-protocol_test: protocol.c protocol_test.c
- gcc -o $@ -O0 -Wall -Wextra -g -I../common $^
-
clean:
rm -f **.o
rm -f main.elf main.hex main.bin main.map main.lst
diff --git a/center_fw/main.c b/center_fw/main.c
index 71d3f00..3008dd2 100644
--- a/center_fw/main.c
+++ b/center_fw/main.c
@@ -17,113 +17,6 @@
#include "global.h"
-#include "adc.h"
-#include "8seg_protocol.h"
-#include "transmit.h"
-
-volatile unsigned int sys_time = 0;
-volatile unsigned int sys_time_seconds = 0;
-uint16_t jitter_meas_avg_ns = 0;
-
-void TIM1_BRK_UP_TRG_COM_Handler() {
- TIM1->SR &= ~TIM_SR_UIF_Msk;
-}
-
-void set_drv_gpios(uint8_t val) {
- val = ~val;
- int a=!(val&1), b=!(val&2), c=!(val&4), d=!(val&8);
- GPIOA->BSRR = (((!a)<<3 | (!b)<<7 | (!c)<<6 | (!d)<<4)<<16) | ((a<<3) | (b<<7) | (c<<6) | (d<<4));
-}
-
-uint8_t out_state = 0x0f;
-void set_outputs(uint8_t val[8]) {
- /* TODO implement BCM for digital brightness control */
- int x = 0;
- for (int i=0; i<8; i++)
- if (val[i] > 127)
- x |= 1<<i;
- out_state = x;
-}
-
-void set_outputs_binary(int mask, int global_brightness) {
- uint8_t val[8];
- for (int i=0; i<8; i++)
- val[i] = (mask & (1<<i)) ? global_brightness : 0;
- set_outputs(val);
-}
-
-void set_load(bool load) {
- GPIOA->BSRR = (1<<2) << (load ? 0 : 16);
-}
-
-void blank(void) {
- GPIOA->BRR = (1<<9) | (1<<10);
- set_drv_gpios(0);
-}
-
-bool has_sync = 0;
-void unblank_low(int bit) {
- if (backchannel_frame) { /* Set from protocol.c */
- if (tx_next_bit() == 1)
- set_load(1);
- else /* 0; but also TX_IDLE */
- set_load(0);
-
- } else if (has_sync) {
- if (bit) {
- //GPIOA->BSRR = (1<<10);
- set_drv_gpios(out_state & 0xf);
-
- } else {
- //GPIOA->BSRR = (1<<9);
- set_drv_gpios(out_state >> 4);
- }
- }
-}
-
-int sync_ctr = 0xffff;
-void TIM3_IRQHandler(void) {
- if (TIM3->SR & TIM_SR_CC2IF) {
- if (sync_ctr > 10)
- has_sync = 0;
- else
- sync_ctr += 1;
- EXTI->IMR = (1<<0);
- GPIOB->BSRR = (1<<1);
- GPIOA->BRR = (1<<9) | (1<<10);
-
- } else if (TIM3->SR & TIM_SR_CC3IF) {
- int bit = GPIOA->IDR & (1<<5); /* Sample current polarity */
- unblank_low(!bit);
-
- } else {
- blank();
- }
-
- TIM3->SR = 0;
-}
-
-void EXTI0_1_IRQHandler(void) {
- static uint32_t jitter_meas_sum = 0, jitter_meas_cnt = 0;
- EXTI->PR = (1<<0);
-
- /* Store old counter value for jitter measurement. Let it overflow to handle negative offsets. */
- int16_t cnt = (int16_t)TIM3->CNT;
- /* Re-initialize the counter to align it with the signal edge */
- TIM3->EGR |= TIM_EGR_UG;
-
- /* Don't handle overflow of _sum here since this value is only for monitoring anyway */
- jitter_meas_sum += (cnt >= 0) ? cnt : -cnt;
- if (++jitter_meas_cnt == 1000) { /* One measurement roughly every 800ms */
- jitter_meas_avg_ns = jitter_meas_sum;
- }
-
- EXTI->IMR = 0;
- GPIOB->BRR = (1<<1);
- has_sync = 1;
- sync_ctr = 0;
-}
-
int main(void) {
//RCC->CR |= RCC_CR_HSEON;
//while (!(RCC->CR&RCC_CR_HSERDY));
@@ -133,82 +26,30 @@ int main(void) {
while (!(RCC->CR&RCC_CR_PLLRDY));
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
SystemCoreClockUpdate();
- SysTick_Config(SystemCoreClock/1000); /* 1ms interval */
/* Turn on lots of neat things */
- RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN;
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN| RCC_APB2ENR_DBGMCUEN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM1EN;;
- RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
-
- /* TIM3 foo */
- TIM3->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
- TIM3->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
- TIM3->CCER = TIM_CCER_CC3E; /* Enable capture/compare unit 3 for unblank interrupt */
- TIM3->CCER = TIM_CCER_CC2E;
-
- TIM3->PSC = 48-1; /* 48MHz -> 1MHz */
- TIM3->CCR2 = 800-1-1;
- TIM3->CCR3 = 100-1; /* CC3 is used for unblanking in the ISR, fires 30us after beginning of cycle. */
- TIM3->CCR4 = 800-100-1; /* CC4 is ADC trigger, fire 30us before end of cycle. */
- TIM3->ARR = 800-1; /* 1MHz -> 5kHz */
-
- TIM3->DIER |= TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE | TIM_DIER_UIE;
-
- TIM3->CR1 |= TIM_CR1_CEN;
- NVIC_EnableIRQ(TIM3_IRQn);
- NVIC_SetPriority(TIM3_IRQn, 3<<5);
-
- GPIOB->MODER |= (1<<GPIO_MODER_MODER1_Pos);
- GPIOB->OSPEEDR |= (2<<GPIO_OSPEEDR_OSPEEDR1_Pos);
-
- EXTI->IMR = (1<<0); /* PA0 Vmeas_A for sync */
- EXTI->RTSR |= (1<<0);
- NVIC_EnableIRQ(EXTI0_1_IRQn);
- NVIC_SetPriority(EXTI0_1_IRQn, 4<<5);
+ RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
GPIOA->MODER |=
- (0<<GPIO_MODER_MODER0_Pos) /* PA0 - Vmeas_A to ADC */
- | (0<<GPIO_MODER_MODER1_Pos) /* PA1 - Unused */
- | (1<<GPIO_MODER_MODER2_Pos) /* PA2 - LOAD */
- | (1<<GPIO_MODER_MODER3_Pos) /* PA3 - CH0 */
- | (1<<GPIO_MODER_MODER4_Pos) /* PA4 - CH3 */
- | (0<<GPIO_MODER_MODER5_Pos) /* PA5 - TP1 */
- | (1<<GPIO_MODER_MODER6_Pos) /* PA6 - CH2 */
- | (1<<GPIO_MODER_MODER7_Pos) /* PA7 - CH1 */
- | (1<<GPIO_MODER_MODER9_Pos) /* PA9 - synchronous rectifier bypass A */
- | (1<<GPIO_MODER_MODER10_Pos);/* PA10 - synchronous rectifier bypass B */
-
- GPIOA->PUPDR |= (2<<GPIO_PUPDR_PUPDR5_Pos);
-
- /* Set shift register IO GPIO output speed */
- GPIOA->OSPEEDR |=
- (2<<GPIO_OSPEEDR_OSPEEDR2_Pos) /* LOAD */
- | (2<<GPIO_OSPEEDR_OSPEEDR3_Pos) /* CH0 */
- | (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* CH3 */
- | (2<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* CH2 */
- | (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* CH1 */
- | (2<<GPIO_OSPEEDR_OSPEEDR9_Pos) /* synchronous rectifier bypass A */
- | (2<<GPIO_OSPEEDR_OSPEEDR10_Pos); /* synchronous rectifier bypass B */
-
- set_drv_gpios(0);
-
- protocol_init();
+ (1<<GPIO_MODER_MODER0_Pos)
+ | (1<<GPIO_MODER_MODER1_Pos);
int cnt = 0;
- int seg_c = 0;
+ int ph = 0;
while (42) {
- /*
- if (cnt > 10000) {
+ if (cnt > 5000) {
cnt = 0;
- seg_c += 1;
- if (seg_c == 8)
- seg_c = 0;
- set_outputs_binary(1<<seg_c, 255);
+ ph += 1;
+ ph %= 4;
} else {
cnt = cnt+1;
}
- */
- /* idle */
+ switch (ph) {
+ case 0: GPIOA->ODR = 1; break;
+ case 1: GPIOA->ODR = 3; break;
+ case 2: GPIOA->ODR = 2; break;
+ case 3: GPIOA->ODR = 0; break;
+ }
}
}
@@ -230,12 +71,3 @@ void PendSV_Handler(void) {
asm volatile ("bkpt");
}
-void SysTick_Handler(void) {
- static int n = 0;
- sys_time++;
- if (n++ == 1000) {
- n = 0;
- sys_time_seconds++;
- }
-}
-