aboutsummaryrefslogtreecommitdiff
path: root/center
diff options
context:
space:
mode:
authorjaseg <git@jaseg.de>2023-05-25 22:23:09 +0200
committerjaseg <git@jaseg.de>2023-05-25 22:23:09 +0200
commitfec02919c34a00e8829fed788fea33debaae6884 (patch)
tree326328a2a3b66309561e87f26ec2850170f68987 /center
parentf74d787c99ddbe9e4c879be761f87deba3af0ef2 (diff)
download8seg-fec02919c34a00e8829fed788fea33debaae6884.tar.gz
8seg-fec02919c34a00e8829fed788fea33debaae6884.tar.bz2
8seg-fec02919c34a00e8829fed788fea33debaae6884.zip
Driver Filter WIP
Diffstat (limited to 'center')
-rw-r--r--center/center.kicad_prl2
-rw-r--r--center/center.kicad_pro53
2 files changed, 40 insertions, 15 deletions
diff --git a/center/center.kicad_prl b/center/center.kicad_prl
index a6d5f9f..c9069a7 100644
--- a/center/center.kicad_prl
+++ b/center/center.kicad_prl
@@ -3,10 +3,12 @@
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
+ "hidden_netclasses": [],
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
+ "images": 0.6,
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
diff --git a/center/center.kicad_pro b/center/center.kicad_pro
index f72e7e1..c1f3153 100644
--- a/center/center.kicad_pro
+++ b/center/center.kicad_pro
@@ -1,5 +1,6 @@
{
"board": {
+ "3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
@@ -455,7 +456,7 @@
"net_settings": {
"classes": [
{
- "bus_width": 12.0,
+ "bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@@ -469,10 +470,10 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
- "wire_width": 6.0
+ "wire_width": 6
},
{
- "bus_width": 12.0,
+ "bus_width": 12,
"clearance": 0.6,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@@ -481,27 +482,49 @@
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "HV",
- "nets": [
- "+VSW",
- "/Q0",
- "/Q1",
- "/Q2",
- "/Q3",
- "/VIN_A",
- "/VIN_B"
- ],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
- "wire_width": 6.0
+ "wire_width": 6
}
],
"meta": {
- "version": 2
+ "version": 3
},
- "net_colors": null
+ "net_colors": null,
+ "netclass_assignments": null,
+ "netclass_patterns": [
+ {
+ "netclass": "HV",
+ "pattern": "+VSW"
+ },
+ {
+ "netclass": "HV",
+ "pattern": "/Q0"
+ },
+ {
+ "netclass": "HV",
+ "pattern": "/Q1"
+ },
+ {
+ "netclass": "HV",
+ "pattern": "/Q2"
+ },
+ {
+ "netclass": "HV",
+ "pattern": "/Q3"
+ },
+ {
+ "netclass": "HV",
+ "pattern": "/VIN_A"
+ },
+ {
+ "netclass": "HV",
+ "pattern": "/VIN_B"
+ }
+ ]
},
"pcbnew": {
"last_paths": {