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| author | jaseg <git@jaseg.net> | 2019-04-23 18:48:26 +0900 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2019-04-23 18:48:26 +0900 |
| commit | c6bf873e9f938c3dcab0347f8cf6cc76dcff2264 (patch) | |
| tree | 977c0ea83dd5ffe683ee746d2df7f395fd71035e | |
| parent | 69ead15835f72aa0fb1159c15a2b483cebf793e0 (diff) | |
| download | 8seg-c6bf873e9f938c3dcab0347f8cf6cc76dcff2264.tar.gz 8seg-c6bf873e9f938c3dcab0347f8cf6cc76dcff2264.tar.bz2 8seg-c6bf873e9f938c3dcab0347f8cf6cc76dcff2264.zip | |
driver: Make fw not short-circuit itself on startup
| -rw-r--r-- | driver/driver.sch | 2 | ||||
| -rw-r--r-- | driver_fw/main.c | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/driver/driver.sch b/driver/driver.sch index c0eff77..1d3261b 100644 --- a/driver/driver.sch +++ b/driver/driver.sch @@ -2745,7 +2745,7 @@ F 3 "~" H 17400 2950 50 0001 C CNN 1 0 0 -1 $EndComp Text Notes 7600 10050 0 50 ~ 0 -TODO:\n* RS485 drv fp is wide, should be narrow SOIC-8\n* Heatsink holes are plated-through, shouln't be\n* Add thermal reliefs in upper logic ground plane\n* GND/VCC input labels are swapped\n* White label field for MAC\n* Remove optoisolators\n* Add series resistor to RS485 GND\n* Add decoupling cap next to mosfet temp sensor\n* Add INA226 filter network (see datasheet p.14) +TODO:\n* RS485 drv fp is wide, should be narrow SOIC-8\n* Heatsink holes are plated-through, shouln't be\n* Add thermal reliefs in upper logic ground plane\n* GND/VCC input labels are swapped\n* White label field for MAC\n* Remove optoisolators\n* Add series resistor to RS485 GND\n* Add decoupling cap next to mosfet temp sensor\n* Add INA226 filter network (see datasheet p.14)\n* Add voltage test points\n* Add pulldowns plus filter caps for CTRL_A, CTRL_B NoConn ~ 14600 2800 Text Notes 14100 9650 0 50 ~ 0 I2C addr=010'0111 diff --git a/driver_fw/main.c b/driver_fw/main.c index dbd1d55..d64bca4 100644 --- a/driver_fw/main.c +++ b/driver_fw/main.c @@ -175,6 +175,8 @@ int main(void) { TIM3->CR1 = 0; /* Disable ARR preload (double-buffering) */ TIM3->PSC = 48-1; /* Prescaler 48 -> f=1MHz/T=1us */ TIM3->DIER = TIM_DIER_UIE; /* Enable update (overflow) interrupt */ + TIM3->CCR1 = 0xffff; + TIM3->CCR4 = 0xffff; TIM3->CCMR1 = 6<<TIM_CCMR1_OC1M_Pos | TIM_CCMR1_OC1PE; /* Configure output compare unit 1 to PWM mode 1, enable CCR1 preload */ TIM3->CCMR2 = 6<<TIM_CCMR2_OC4M_Pos | TIM_CCMR2_OC4PE; /* Configure output compare unit 4 to PWM mode 1, enable CCR4 preload */ TIM3->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P; /* Confiugre CH1 to complementary outputs */ |