diff options
| author | jaseg <git@jaseg.de> | 2023-09-25 23:57:36 +0200 |
|---|---|---|
| committer | jaseg <git@jaseg.de> | 2023-09-25 23:57:36 +0200 |
| commit | 8cc05c79cea62609d02231492c054a0cca2b2289 (patch) | |
| tree | e39d40456adefe9bb70bcd77ebdf97be1dcdc028 | |
| parent | 583ac10d1450610a4110849c26cc16f03154d26e (diff) | |
| download | 8seg-8cc05c79cea62609d02231492c054a0cca2b2289.tar.gz 8seg-8cc05c79cea62609d02231492c054a0cca2b2289.tar.bz2 8seg-8cc05c79cea62609d02231492c054a0cca2b2289.zip | |
Center firmware WIP
46 files changed, 15253 insertions, 1255 deletions
diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..69c5be9 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "upstream/upstream/musl"] + path = upstream/musl + url = git://git.musl-libc.org/musl diff --git a/center-control/center.kicad_pro b/center-control/center.kicad_pro index 124f5ad..da7f5ca 100644 --- a/center-control/center.kicad_pro +++ b/center-control/center.kicad_pro @@ -56,14 +56,7 @@ "width": 0.0 } ], - "drc_exclusions": [ - "courtyards_overlap|196360001|102626502|00000000-0000-0000-0000-00005de9b522|99d59f94-0300-4758-95c1-fe9bbbbfa783", - "courtyards_overlap|197763171|110797068|00000000-0000-0000-0000-00005de9b522|c4833d2e-2c9e-4440-8866-6140984cca80", - "text_thickness|152631995|101175000|00000000-0000-0000-0000-00005de93595|00000000-0000-0000-0000-000000000000", - "text_thickness|156049472|101175000|00000000-0000-0000-0000-00005de935c0|00000000-0000-0000-0000-000000000000", - "text_thickness|178000000|68444662|e1e8791b-f102-4509-9948-1986c49e1265|00000000-0000-0000-0000-000000000000", - "unresolved_variable|206814520|80002996|002cb8c7-b00a-4e5f-a820-e69219752984|00000000-0000-0000-0000-000000000000" - ], + "drc_exclusions": [], "meta": { "filename": "board_design_settings.json", "version": 2 diff --git a/center-control/center.kicad_sch b/center-control/center.kicad_sch index 789df8d..06f4dae 100644 --- a/center-control/center.kicad_sch +++ b/center-control/center.kicad_sch @@ -1,11 +1,11 @@ -(kicad_sch (version 20230409) (generator eeschema) +(kicad_sch (version 20230819) (generator eeschema) (uuid 90842322-b56e-42c7-bb4b-462bae6a0a0f) (paper "A3") (lib_symbols - (symbol "Amplifier_Operational:MCP6001-OT" (pin_names (offset 0.127)) (in_bom yes) (on_board yes) + (symbol "Amplifier_Operational:MCP6001-OT" (pin_names (offset 0.127)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "U" (at -1.27 6.35 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -18,10 +18,10 @@ (property "Datasheet" "http://ww1.microchip.com/downloads/en/DeviceDoc/21733j.pdf" (at 0 5.08 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_keywords" "single opamp" (at 0 0 0) + (property "Description" "1MHz, Low-Power Op Amp, SOT-23-5" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "1MHz, Low-Power Op Amp, SOT-23-5" (at 0 0 0) + (property "ki_keywords" "single opamp" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "ki_fp_filters" "SOT?23*" (at 0 0 0) @@ -62,7 +62,7 @@ ) ) ) - (symbol "Connector:TestPoint" (pin_numbers hide) (pin_names (offset 0.762) hide) (in_bom yes) (on_board yes) + (symbol "Connector:TestPoint" (pin_numbers hide) (pin_names (offset 0.762) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "TP" (at 0 6.858 0) (effects (font (size 1.27 1.27))) ) @@ -75,10 +75,10 @@ (property "Datasheet" "~" (at 5.08 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_keywords" "test point tp" (at 0 0 0) + (property "Description" "test point" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "test point" (at 0 0 0) + (property "ki_keywords" "test point tp" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "ki_fp_filters" "Pin* Test*" (at 0 0 0) @@ -97,7 +97,7 @@ ) ) ) - (symbol "Connector_Generic:Conn_02x07_Odd_Even" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (symbol "Connector_Generic:Conn_02x07_Odd_Even" (pin_names (offset 1.016) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "J" (at 1.27 10.16 0) (effects (font (size 1.27 1.27))) ) @@ -110,10 +110,10 @@ (property "Datasheet" "~" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_keywords" "connector" (at 0 0 0) + (property "Description" "Generic connector, double row, 02x07, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "Generic connector, double row, 02x07, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)" (at 0 0 0) + (property "ki_keywords" "connector" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "ki_fp_filters" "Connector*:*_2x??_*" (at 0 0 0) @@ -238,7 +238,7 @@ ) ) ) - (symbol "Connector_Generic:Conn_02x10_Top_Bottom" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (symbol "Connector_Generic:Conn_02x10_Top_Bottom" (pin_names (offset 1.016) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "J" (at 1.27 12.7 0) (effects (font (size 1.27 1.27))) ) @@ -251,10 +251,10 @@ (property "Datasheet" "~" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_keywords" "connector" (at 0 0 0) + (property "Description" "Generic connector, double row, 02x10, top/bottom pin numbering scheme (row 1: 1...pins_per_row, row2: pins_per_row+1 ... num_pins), script generated (kicad-library-utils/schlib/autogen/connector/)" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "Generic connector, double row, 02x10, top/bottom pin numbering scheme (row 1: 1...pins_per_row, row2: pins_per_row+1 ... num_pins), script generated (kicad-library-utils/schlib/autogen/connector/)" (at 0 0 0) + (property "ki_keywords" "connector" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "ki_fp_filters" "Connector*:*_2x??_*" (at 0 0 0) @@ -427,7 +427,7 @@ ) ) ) - (symbol "MCU_ST_STM32G0:STM32G030F6Px" (in_bom yes) (on_board yes) + (symbol "MCU_ST_STM32G0:STM32G030F6Px" (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "U" (at -20.32 16.51 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -440,15 +440,15 @@ (property "Datasheet" "https://www.st.com/resource/en/datasheet/stm32g030f6.pdf" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "ARM Cortex-M0+ MCU, 32KB flash, 8KB RAM, 64MHz, 2-3.6V, 26 GPIO, TSSOP-20" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_locked" "" (at 0 0 0) (effects (font (size 1.27 1.27))) ) (property "ki_keywords" "ARM Cortex-M0+ STM32G0 STM32G0x0 Value line" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "ARM Cortex-M0+ MCU, 32KB flash, 8KB RAM, 64MHz, 2-3.6V, 26 GPIO, TSSOP-20" (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) (property "ki_fp_filters" "TSSOP*4.4x6.5mm*P0.65mm*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -636,7 +636,7 @@ ) ) ) - (symbol "Transistor_FET:AO3400A" (pin_names hide) (in_bom yes) (on_board yes) + (symbol "Transistor_FET:AO3400A" (pin_names hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "Q" (at 5.08 1.905 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -649,10 +649,10 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 0 0 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) - (property "ki_keywords" "N-Channel MOSFET" (at 0 0 0) + (property "Description" "30V Vds, 5.7A Id, N-Channel MOSFET, SOT-23" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "30V Vds, 5.7A Id, N-Channel MOSFET, SOT-23" (at 0 0 0) + (property "ki_keywords" "N-Channel MOSFET" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "ki_fp_filters" "SOT?23*" (at 0 0 0) @@ -784,7 +784,7 @@ ) ) ) - (symbol "Transistor_FET:AO3401A" (pin_names hide) (in_bom yes) (on_board yes) + (symbol "Transistor_FET:AO3401A" (pin_names hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "Q" (at 5.08 1.905 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -797,10 +797,10 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf" (at 0 0 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) - (property "ki_keywords" "P-Channel MOSFET" (at 0 0 0) + (property "Description" "-4.0A Id, -30V Vds, P-Channel MOSFET, SOT-23" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) - (property "ki_description" "-4.0A Id, -30V Vds, P-Channel MOSFET, SOT-23" (at 0 0 0) + (property "ki_keywords" "P-Channel MOSFET" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) (property "ki_fp_filters" "SOT?23*" (at 0 0 0) @@ -932,7 +932,7 @@ ) ) ) - (symbol "center-rescue:+12V-power" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes) + (symbol "center-rescue:+12V-power" (power) (pin_names (offset 0)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "#PWR" (at 0 -3.81 0) (effects (font (size 1.27 1.27)) hide) ) @@ -945,6 +945,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (symbol "+12V-power_0_1" (polyline (pts @@ -978,7 +981,7 @@ ) ) ) - (symbol "center-rescue:+3.3V-power" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes) + (symbol "center-rescue:+3.3V-power" (power) (pin_names (offset 0)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "#PWR" (at 0 -3.81 0) (effects (font (size 1.27 1.27)) hide) ) @@ -991,6 +994,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (symbol "+3.3V-power_0_1" (polyline (pts @@ -1024,7 +1030,7 @@ ) ) ) - (symbol "center-rescue:+VSW-power" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes) + (symbol "center-rescue:+VSW-power" (power) (pin_names (offset 0)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "#PWR" (at 0 -3.81 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1037,6 +1043,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (symbol "+VSW-power_0_1" (polyline (pts @@ -1070,7 +1079,7 @@ ) ) ) - (symbol "center-rescue:AP1117-33-Regulator_Linear" (pin_names (offset 0.254)) (in_bom yes) (on_board yes) + (symbol "center-rescue:AP1117-33-Regulator_Linear" (pin_names (offset 0.254)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "U" (at -3.81 3.175 0) (effects (font (size 1.27 1.27))) ) @@ -1083,6 +1092,9 @@ (property "Datasheet" "http://www.diodes.com/datasheets/AP1117.pdf" (at 2.54 -6.35 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "SOT?223*TabPin2*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1111,7 +1123,7 @@ ) ) ) - (symbol "center-rescue:CP_Small-Device" (pin_numbers hide) (pin_names (offset 0.254) hide) (in_bom yes) (on_board yes) + (symbol "center-rescue:CP_Small-Device" (pin_numbers hide) (pin_names (offset 0.254) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "C" (at 0.254 1.778 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -1124,6 +1136,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "CP_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1164,7 +1179,7 @@ ) ) ) - (symbol "center-rescue:C_Small-Device" (pin_numbers hide) (pin_names (offset 0.254) hide) (in_bom yes) (on_board yes) + (symbol "center-rescue:C_Small-Device" (pin_numbers hide) (pin_names (offset 0.254) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "C" (at 0.254 1.778 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -1177,6 +1192,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "C_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1209,7 +1227,7 @@ ) ) ) - (symbol "center-rescue:D_Schottky_ALT-Device" (pin_numbers hide) (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (symbol "center-rescue:D_Schottky_ALT-Device" (pin_numbers hide) (pin_names (offset 1.016) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "D" (at 0 2.54 0) (effects (font (size 1.27 1.27))) ) @@ -1222,6 +1240,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "TO-???* *_Diode_* *SingleDiode* D_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1268,7 +1289,7 @@ ) ) ) - (symbol "center-rescue:D_Zener_ALT-Device" (pin_numbers hide) (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (symbol "center-rescue:D_Zener_ALT-Device" (pin_numbers hide) (pin_names (offset 1.016) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "D" (at 0 2.54 0) (effects (font (size 1.27 1.27))) ) @@ -1281,6 +1302,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "TO-???* *_Diode_* *SingleDiode* D_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1324,7 +1348,7 @@ ) ) ) - (symbol "center-rescue:GND-power" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes) + (symbol "center-rescue:GND-power" (power) (pin_names (offset 0)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "#PWR" (at 0 -6.35 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1337,6 +1361,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (symbol "GND-power_0_1" (polyline (pts @@ -1358,7 +1385,7 @@ ) ) ) - (symbol "center-rescue:L-Device" (pin_numbers hide) (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (symbol "center-rescue:L-Device" (pin_numbers hide) (pin_names (offset 1.016) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "L" (at -1.27 0 90) (effects (font (size 1.27 1.27))) ) @@ -1371,6 +1398,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "Choke_* *Coil* Inductor_* L_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1403,7 +1433,7 @@ ) ) ) - (symbol "center-rescue:R-Device" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes) + (symbol "center-rescue:R-Device" (pin_numbers hide) (pin_names (offset 0)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "R" (at 2.032 0 90) (effects (font (size 1.27 1.27))) ) @@ -1416,6 +1446,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "R_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1436,7 +1469,7 @@ ) ) ) - (symbol "center-rescue:R_Small-Device" (pin_numbers hide) (pin_names (offset 0.254) hide) (in_bom yes) (on_board yes) + (symbol "center-rescue:R_Small-Device" (pin_numbers hide) (pin_names (offset 0.254) hide) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "R" (at 0.762 0.508 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -1449,6 +1482,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "ki_fp_filters" "R_*" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) @@ -1469,7 +1505,7 @@ ) ) ) - (symbol "center-rescue:bom_item-4xxx" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (symbol "center-rescue:bom_item-4xxx" (pin_names (offset 1.016)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "E" (at -2.54 0 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -1482,6 +1518,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (symbol "bom_item-4xxx_0_1" (circle (center -3.048 0) (radius 0.254) (stroke (width 0) (type default)) @@ -1489,7 +1528,7 @@ ) ) ) - (symbol "components:TX4138" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (symbol "components:TX4138" (pin_names (offset 1.016)) (exclude_from_sim no) (in_bom yes) (on_board yes) (property "Reference" "U" (at 0 0 0) (effects (font (size 1.27 1.27))) ) @@ -1502,6 +1541,9 @@ (property "Datasheet" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) (symbol "TX4138_0_1" (rectangle (start -7.62 -10.16) (end 7.62 15.24) (stroke (width 0) (type default)) @@ -1567,9 +1609,6 @@ (junction (at 140.97 113.03) (diameter 0) (color 0 0 0 0) (uuid 14367394-2468-465c-be30-3c5e94dccae5) ) - (junction (at 87.63 59.69) (diameter 1.016) (color 0 0 0 0) - (uuid 14cb0de5-09bb-40a0-9723-f48f2d625508) - ) (junction (at 279.4 106.68) (diameter 1.016) (color 0 0 0 0) (uuid 1902937b-befe-4123-b4c3-fc837aa5e5d4) ) @@ -1648,6 +1687,12 @@ (junction (at 191.77 96.52) (diameter 1.016) (color 0 0 0 0) (uuid 6ebb07f6-783d-4800-a555-14d6a44036f2) ) + (junction (at 93.98 59.69) (diameter 0) (color 0 0 0 0) + (uuid 6f381564-de62-4c2c-a583-ea0695e12420) + ) + (junction (at 87.63 64.77) (diameter 0) (color 0 0 0 0) + (uuid 714904ed-ecb3-41bd-8f07-53327a25c3dc) + ) (junction (at 125.73 96.52) (diameter 0) (color 0 0 0 0) (uuid 73cd9081-c3e2-4955-807b-0c723bb54b69) ) @@ -1738,9 +1783,6 @@ (junction (at 270.51 106.68) (diameter 1.016) (color 0 0 0 0) (uuid c7c97226-3c88-4371-b911-f313077f135d) ) - (junction (at 93.98 64.77) (diameter 1.016) (color 0 0 0 0) - (uuid ca5b7ac4-3b46-4ace-9a2a-0429ad236cd1) - ) (junction (at 154.94 96.52) (diameter 1.016) (color 0 0 0 0) (uuid d91c0d8a-e388-4583-8076-e8314c19f84c) ) @@ -1909,9 +1951,9 @@ (stroke (width 0) (type solid)) (uuid 2096b6aa-457d-483a-9a63-d887d39f5af4) ) - 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(in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c19682a) (property "Reference" "U1" (at 322.58 92.9132 0) (effects (font (size 1.27 1.27))) @@ -3087,6 +3129,9 @@ (property "Datasheet" "http://www.diodes.com/datasheets/AP1117.pdf" (at 325.12 105.41 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 322.58 99.06 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347222" (at 322.58 99.06 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3104,7 +3149,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 165.1 91.44 90) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c199ccc) (property "Reference" "D2" (at 167.1066 90.2716 90) (effects (font (size 1.27 1.27)) (justify right)) @@ -3118,6 +3163,9 @@ (property "Datasheet" "~" (at 165.1 91.44 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 165.1 91.44 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C65010" (at 165.1 91.44 90) (effects (font (size 1.27 1.27)) hide) ) @@ -3133,7 +3181,7 @@ ) (symbol (lib_id "center-rescue:CP_Small-Device") (at 288.29 99.06 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1a6a7d) (property "Reference" "C4" (at 284.48 95.25 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3147,6 +3195,9 @@ (property "Datasheet" "~" (at 288.29 99.06 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 288.29 99.06 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Mfg" "CapXon" (at 297.18 99.06 90) (effects (font (size 1.27 1.27)) (justify left) hide) ) @@ -3168,7 +3219,7 @@ ) (symbol (lib_id "center-rescue:CP_Small-Device") (at 336.55 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1a7520) (property "Reference" "C8" (at 338.7852 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3182,6 +3233,9 @@ (property "Datasheet" "~" (at 336.55 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 336.55 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "PN" "25YXF47MFFC5X11" (at 336.55 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3203,7 +3257,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 299.72 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1aafa9) (property "Reference" "C6" (at 302.0568 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3217,6 +3271,9 @@ (property "Datasheet" "~" (at 299.72 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 299.72 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C39232" (at 299.72 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3232,7 +3289,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 308.61 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1af3bd) (property "Reference" "C7" (at 310.9468 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3246,6 +3303,9 @@ (property "Datasheet" "~" (at 308.61 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 308.61 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C15725" (at 308.61 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3261,7 +3321,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 347.98 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1afb91) (property "Reference" "C9" (at 350.3168 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3275,6 +3335,9 @@ (property "Datasheet" "~" (at 347.98 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 347.98 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C95841" (at 347.98 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3290,7 +3353,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 356.87 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1b07a6) (property "Reference" "C10" (at 359.2068 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3304,6 +3367,9 @@ (property "Datasheet" "~" (at 356.87 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 356.87 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C15725" (at 356.87 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3319,7 +3385,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 82.55 104.14 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c1b72f8) (property "Reference" "R5" (at 84.0486 102.9716 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3333,6 +3399,9 @@ (property "Datasheet" "~" (at 82.55 104.14 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 82.55 104.14 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 9266827e-3b55-4861-8ea5-0377a3c6edf1)) (pin "2" (uuid bb3ca044-a9fd-4af8-ba9c-b23d86d107c7)) (instances @@ -3345,7 +3414,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 365.76 99.06 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c2174d4) (property "Reference" "#PWR03" (at 361.95 99.06 0) (effects (font (size 1.27 1.27)) hide) @@ -3359,6 +3428,9 @@ (property "Datasheet" "" (at 365.76 99.06 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 365.76 99.06 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid a5507133-e9a6-402d-a227-7a739c435ae8)) (instances (project "center" @@ -3370,7 +3442,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 365.76 128.27 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c21cdd5) (property "Reference" "#PWR04" (at 372.11 128.27 0) (effects (font (size 1.27 1.27)) hide) @@ -3384,6 +3456,9 @@ (property "Datasheet" "" (at 365.76 128.27 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 365.76 128.27 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid be5b2371-005d-43f7-b8a1-1d750f52d5c0)) (instances (project "center" @@ -3395,7 +3470,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 365.76 85.09 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c2201cd) (property "Reference" "#PWR02" (at 361.95 85.09 0) (effects (font (size 1.27 1.27)) hide) @@ -3409,6 +3484,9 @@ (property "Datasheet" "" (at 365.76 85.09 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 365.76 85.09 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid d36b375b-173a-4b89-b688-556a1442c810)) (instances (project "center" @@ -3420,7 +3498,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 99.06 186.69 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c223c57) (property "Reference" "#PWR05" (at 99.06 190.5 0) (effects (font (size 1.27 1.27)) hide) @@ -3434,6 +3512,9 @@ (property "Datasheet" "" (at 99.06 186.69 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 99.06 186.69 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 744aa83f-43b9-449c-a2ea-baf2fad3bdcd)) (instances (project "center" @@ -3445,7 +3526,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 99.06 224.79 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c22656d) (property "Reference" "#PWR013" (at 99.06 231.14 0) (effects (font (size 1.27 1.27)) hide) @@ -3459,6 +3540,9 @@ (property "Datasheet" "" (at 99.06 224.79 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 99.06 224.79 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid f3264b80-1138-44f1-9089-ebe578c1aa1b)) (instances (project "center" @@ -3470,7 +3554,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 162.56 220.98 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c2270d7) (property "Reference" "#PWR015" (at 162.56 227.33 0) (effects (font (size 1.27 1.27)) hide) @@ -3484,6 +3568,9 @@ (property "Datasheet" "" (at 162.56 220.98 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 162.56 220.98 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 09215757-3934-408e-966c-6e1d3b45652b)) (instances (project "center" @@ -3495,7 +3582,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 162.56 187.96 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c227d6b) (property "Reference" "#PWR09" (at 162.56 191.77 0) (effects (font (size 1.27 1.27)) hide) @@ -3509,6 +3596,9 @@ (property "Datasheet" "" (at 162.56 187.96 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 162.56 187.96 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 8d214fc3-ffd6-4e00-91a4-70c7c48adb52)) (instances (project "center" @@ -3520,7 +3610,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 68.58 191.77 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c36fd60) (property "Reference" "R7" (at 66.04 189.23 90) (effects (font (size 1.27 1.27))) @@ -3534,6 +3624,9 @@ (property "Datasheet" "~" (at 68.58 191.77 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 68.58 191.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid b08079c4-b354-43f4-8826-48730e423185)) (pin "2" (uuid 260e90e3-f8b7-412f-8df3-4714bcd3a7bf)) (instances @@ -3546,7 +3639,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 63.5 191.77 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c3785ca) (property "Reference" "#PWR08" (at 67.31 191.77 0) (effects (font (size 1.27 1.27)) hide) @@ -3560,6 +3653,9 @@ (property "Datasheet" "" (at 63.5 191.77 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 63.5 191.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid caf0f95d-755b-4a1a-a026-65ec92621833)) (instances (project "center" @@ -3571,7 +3667,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 64.77 236.22 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c3bbc57) (property "Reference" "#PWR06" (at 60.96 236.22 0) (effects (font (size 1.27 1.27)) hide) @@ -3585,6 +3681,9 @@ (property "Datasheet" "" (at 64.77 236.22 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 64.77 236.22 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid d10c7d60-a13e-45cd-bc76-32c8b1594fe9)) (instances (project "center" @@ -3596,7 +3695,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 52.07 236.22 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005c3d62af) (property "Reference" "#PWR07" (at 45.72 236.22 0) (effects (font (size 1.27 1.27)) hide) @@ -3610,6 +3709,9 @@ (property "Datasheet" "" (at 52.07 236.22 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 52.07 236.22 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 67caf8bf-882f-4c20-bb31-d4ff787f958a)) (instances (project "center" @@ -3621,7 +3723,7 @@ ) (symbol (lib_id "components:TX4138") (at 217.17 109.22 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005de7ff76) (property "Reference" "U2" (at 217.17 89.789 0) (effects (font (size 1.27 1.27))) @@ -3635,6 +3737,9 @@ (property "Datasheet" "" (at 217.17 109.22 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 217.17 109.22 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C329267" (at 217.17 109.22 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3657,7 +3762,7 @@ ) (symbol (lib_id "center-rescue:D_Zener_ALT-Device") (at 82.55 119.38 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005deb348d) (property "Reference" "D6" (at 84.5566 118.2116 90) (effects (font (size 1.27 1.27)) (justify left)) @@ -3671,6 +3776,9 @@ (property "Datasheet" "~" (at 82.55 119.38 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 82.55 119.38 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Mfg" "DIODES inc." (at 82.55 119.38 90) (effects (font (size 1.27 1.27)) hide) ) @@ -3692,7 +3800,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 198.12 101.6 270) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005deb5134) (property "Reference" "R4" (at 198.12 106.8578 90) (effects (font (size 1.27 1.27))) @@ -3706,6 +3814,9 @@ (property "Datasheet" "~" (at 198.12 101.6 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 198.12 101.6 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Mfg" "Ralec" (at 198.12 101.6 90) (effects (font (size 1.27 1.27)) hide) ) @@ -3727,7 +3838,7 @@ ) (symbol (lib_id "center-rescue:+VSW-power") (at 173.99 85.09 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005dec7be3) (property "Reference" "#PWR01" (at 173.99 88.9 0) (effects (font (size 1.27 1.27)) hide) @@ -3741,6 +3852,9 @@ (property "Datasheet" "" (at 173.99 85.09 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 173.99 85.09 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid afe48b6c-70f8-49f1-8fa1-58ef4b8707bb)) (instances (project "center" @@ -3752,7 +3866,7 @@ ) (symbol (lib_id "center-rescue:L-Device") (at 254 95.25 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005ded4544) (property "Reference" "L1" (at 255.3208 94.0816 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3766,6 +3880,9 @@ (property "Datasheet" "~" (at 254 95.25 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 254 95.25 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C526031" (at 254 95.25 0) (effects (font (size 1.27 1.27)) hide) ) @@ -3781,7 +3898,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 247.65 95.25 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df04917) (property "Reference" "R1" (at 249.428 92.9386 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3795,6 +3912,9 @@ (property "Datasheet" "~" (at 247.65 95.25 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 247.65 95.25 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 249.428 97.5614 0) (effects (font (size 1.27 1.27)) (justify left)) ) @@ -3810,7 +3930,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 290.83 215.9 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df15485) (property "Reference" "#PWR0101" (at 290.83 219.71 0) (effects (font (size 1.27 1.27)) hide) @@ -3824,6 +3944,9 @@ (property "Datasheet" "" (at 290.83 215.9 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 290.83 215.9 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 83cc1d05-318f-4243-ab13-7f1323b6f758)) (instances (project "center" @@ -3835,7 +3958,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 279.4 100.33 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df1b471) (property "Reference" "R3" (at 281.178 99.1616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3849,6 +3972,9 @@ (property "Datasheet" "~" (at 279.4 100.33 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 279.4 100.33 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 7e43d64f-8807-4847-bc7f-9077f62c71db)) (pin "2" (uuid b1defd3d-e59d-413c-9d2a-69139135b93c)) (instances @@ -3861,7 +3987,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 279.4 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df1be4c) (property "Reference" "R6" (at 281.178 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3875,6 +4001,9 @@ (property "Datasheet" "~" (at 279.4 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 279.4 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 2e6cee16-39eb-4113-8b8f-d0ab24de261b)) (pin "2" (uuid 6d79725d-b2c4-4775-910c-c54a9436cacb)) (instances @@ -3887,7 +4016,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 270.51 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df24754) (property "Reference" "C5" (at 272.8468 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3901,6 +4030,9 @@ (property "Datasheet" "~" (at 270.51 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 270.51 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 35f0d3c4-019d-4607-ba68-157c093bff2b)) (pin "2" (uuid f84e9db1-46d3-41b3-bf2c-3b7057811d94)) (instances @@ -3913,7 +4045,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 274.32 242.57 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df278bf) (property "Reference" "#PWR0102" (at 274.32 248.92 0) (effects (font (size 1.27 1.27)) hide) @@ -3927,6 +4059,9 @@ (property "Datasheet" "" (at 274.32 242.57 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 274.32 242.57 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid ff9df5b0-d49f-47a6-80a2-c9b899f921e5)) (instances (project "center" @@ -3938,7 +4073,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 274.32 220.98 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df2c541) (property "Reference" "R11" (at 275.8186 219.8116 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3952,6 +4087,9 @@ (property "Datasheet" "~" (at 274.32 220.98 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 274.32 220.98 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid d6a7821b-c536-4507-906c-9c97a0e400ac)) (pin "2" (uuid 09d700d6-9afb-49da-9f13-953fee5d78e9)) (instances @@ -3964,7 +4102,7 @@ ) (symbol (lib_id "center-rescue:CP_Small-Device") (at 176.53 104.14 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df2dad7) (property "Reference" "C1" (at 172.72 100.33 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -3978,6 +4116,9 @@ (property "Datasheet" "~" (at 176.53 104.14 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 176.53 104.14 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Mfg" "Rubycon" (at 181.61 115.57 90) (effects (font (size 1.27 1.27)) (justify left) hide) ) @@ -3999,7 +4140,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 191.77 115.57 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df3d7ed) (property "Reference" "C2" (at 187.7568 113.1316 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4013,6 +4154,9 @@ (property "Datasheet" "~" (at 191.77 115.57 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 191.77 115.57 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C15725" (at 191.77 115.57 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4028,7 +4172,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 241.3 99.06 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df449c0) (property "Reference" "C3" (at 243.6368 97.8916 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4042,6 +4186,9 @@ (property "Datasheet" "~" (at 241.3 99.06 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 241.3 99.06 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C15725" (at 241.3 99.06 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4057,7 +4204,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 233.68 96.52 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df4cc98) (property "Reference" "R2" (at 233.68 91.2622 90) (effects (font (size 1.27 1.27))) @@ -4071,6 +4218,9 @@ (property "Datasheet" "~" (at 233.68 96.52 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 233.68 96.52 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 54233e6d-cf87-4cf5-8fe5-8c5b2e8ae0b5)) (pin "2" (uuid 03802c15-909b-426e-a6d7-6024743750d3)) (instances @@ -4083,7 +4233,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 207.01 242.57 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df6a33e) (property "Reference" "#PWR0105" (at 207.01 248.92 0) (effects (font (size 1.27 1.27)) hide) @@ -4097,6 +4247,9 @@ (property "Datasheet" "" (at 207.01 242.57 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 207.01 242.57 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 6171aa07-ef97-41ed-9a91-bea92d3098a4)) (instances (project "center" @@ -4108,7 +4261,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 223.52 215.9 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df6a35f) (property "Reference" "#PWR0106" (at 223.52 219.71 0) (effects (font (size 1.27 1.27)) hide) @@ -4122,6 +4275,9 @@ (property "Datasheet" "" (at 223.52 215.9 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 223.52 215.9 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 25c44136-0101-419f-b8e0-fa1e9011be1f)) (instances (project "center" @@ -4133,7 +4289,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 207.01 220.98 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df6a371) (property "Reference" "R12" (at 208.5086 219.8116 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4147,6 +4303,9 @@ (property "Datasheet" "~" (at 207.01 220.98 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 207.01 220.98 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 004741c9-c81b-41cb-8c54-726035cd8f08)) (pin "2" (uuid cd2990ba-f2cc-4beb-a070-410740b57350)) (instances @@ -4159,7 +4318,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 207.01 172.72 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df6dd8b) (property "Reference" "#PWR0103" (at 207.01 176.53 0) (effects (font (size 1.27 1.27)) hide) @@ -4173,6 +4332,9 @@ (property "Datasheet" "" (at 207.01 172.72 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 207.01 172.72 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 2246873e-1a51-4c74-bd49-d6580eca6e57)) (instances (project "center" @@ -4184,7 +4346,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 274.32 199.39 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df76e8a) (property "Reference" "#PWR0107" (at 274.32 205.74 0) (effects (font (size 1.27 1.27)) hide) @@ -4198,6 +4360,9 @@ (property "Datasheet" "" (at 274.32 199.39 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 274.32 199.39 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid ab9f8291-4d50-4f39-b1f8-516a8d58c157)) (instances (project "center" @@ -4209,7 +4374,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 290.83 172.72 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df76eab) (property "Reference" "#PWR0108" (at 290.83 176.53 0) (effects (font (size 1.27 1.27)) hide) @@ -4223,6 +4388,9 @@ (property "Datasheet" "" (at 290.83 172.72 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 290.83 172.72 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 3a9a093a-e093-45d3-a90a-5ba3fb613b36)) (instances (project "center" @@ -4234,7 +4402,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 207.01 177.8 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df76eb9) (property "Reference" "R14" (at 208.5086 176.6316 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4248,6 +4416,9 @@ (property "Datasheet" "~" (at 207.01 177.8 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 207.01 177.8 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 7f2bf0e6-e986-4c7f-ac41-aa9e9bcae82c)) (pin "2" (uuid ba993ea0-4dc1-4da1-856a-f30194ec8d78)) (instances @@ -4260,7 +4431,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 274.32 177.8 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df76ede) (property "Reference" "R13" (at 275.8186 176.6316 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4274,6 +4445,9 @@ (property "Datasheet" "~" (at 274.32 177.8 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 274.32 177.8 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 330ead73-9f59-4ccb-a796-f25f26d1dced)) (pin "2" (uuid 883f25af-1230-416d-8d0e-6f66464c01d0)) (instances @@ -4286,7 +4460,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 223.52 172.72 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df76f0d) (property "Reference" "#PWR0109" (at 223.52 176.53 0) (effects (font (size 1.27 1.27)) hide) @@ -4300,6 +4474,9 @@ (property "Datasheet" "" (at 223.52 172.72 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 223.52 172.72 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 3accd1c5-4105-4d5b-b76b-ee7062369a24)) (instances (project "center" @@ -4311,7 +4488,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 207.01 199.39 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df76f1f) (property "Reference" "#PWR0110" (at 207.01 205.74 0) (effects (font (size 1.27 1.27)) hide) @@ -4325,6 +4502,9 @@ (property "Datasheet" "" (at 207.01 199.39 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 207.01 199.39 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 7bbb4bab-f0ee-464e-a8e8-a1d1f95c0230)) (instances (project "center" @@ -4336,7 +4516,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 274.32 172.72 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df7d96a) (property "Reference" "#PWR0104" (at 274.32 176.53 0) (effects (font (size 1.27 1.27)) hide) @@ -4350,6 +4530,9 @@ (property "Datasheet" "" (at 274.32 172.72 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 274.32 172.72 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 14e98cfe-7af6-4088-9627-fe3c8d1c2c94)) (instances (project "center" @@ -4361,7 +4544,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 207.01 215.9 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005df985a9) (property "Reference" "#PWR0111" (at 207.01 219.71 0) (effects (font (size 1.27 1.27)) hide) @@ -4375,6 +4558,9 @@ (property "Datasheet" "" (at 207.01 215.9 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 207.01 215.9 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 843a6863-43e7-4d9a-b8e3-225137c3e9d1)) (instances (project "center" @@ -4386,7 +4572,7 @@ ) (symbol (lib_id "center-rescue:+12V-power") (at 274.32 215.9 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005dfadeb5) (property "Reference" "#PWR0112" (at 274.32 219.71 0) (effects (font (size 1.27 1.27)) hide) @@ -4400,6 +4586,9 @@ (property "Datasheet" "" (at 274.32 215.9 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 274.32 215.9 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 3882e7cb-13f4-44aa-8de9-e2957782c625)) (instances (project "center" @@ -4411,7 +4600,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 165.1 104.14 90) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005e02dc22) (property "Reference" "D4" (at 167.1066 102.9716 90) (effects (font (size 1.27 1.27)) (justify right)) @@ -4425,6 +4614,9 @@ (property "Datasheet" "~" (at 165.1 104.14 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 165.1 104.14 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C65010" (at 165.1 104.14 90) (effects (font (size 1.27 1.27)) hide) ) @@ -4440,7 +4632,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 154.94 91.44 90) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005e0395c8) (property "Reference" "D1" (at 156.9466 90.2716 90) (effects (font (size 1.27 1.27)) (justify right)) @@ -4454,6 +4646,9 @@ (property "Datasheet" "~" (at 154.94 91.44 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 154.94 91.44 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C65010" (at 154.94 91.44 90) (effects (font (size 1.27 1.27)) hide) ) @@ -4469,7 +4664,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 154.94 104.14 90) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005e03ecdb) (property "Reference" "D3" (at 156.9466 102.9716 90) (effects (font (size 1.27 1.27)) (justify right)) @@ -4483,6 +4678,9 @@ (property "Datasheet" "~" (at 154.94 104.14 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 154.94 104.14 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C65010" (at 154.94 104.14 90) (effects (font (size 1.27 1.27)) hide) ) @@ -4498,7 +4696,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 254 118.11 90) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005e0408ec) (property "Reference" "D5" (at 256.0066 116.9416 90) (effects (font (size 1.27 1.27)) (justify right)) @@ -4512,6 +4710,9 @@ (property "Datasheet" "~" (at 254 118.11 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 254 118.11 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C65010" (at 254 118.11 90) (effects (font (size 1.27 1.27)) hide) ) @@ -4527,7 +4728,7 @@ ) (symbol (lib_id "center-rescue:bom_item-4xxx") (at 92.71 248.92 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 00000000-0000-0000-0000-00005e05c19d) (property "Reference" "E1" (at 90.6272 247.7516 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4541,6 +4742,9 @@ (property "Datasheet" "" (at 92.71 248.92 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 92.71 248.92 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Reichelt" "KAB 100-2,5" (at 92.71 248.92 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4557,7 +4761,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 297.18 191.77 0) (mirror y) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 0394cd05-cad5-403d-b0d2-a8f4641c4508) (property "Reference" "D12" (at 295.91 194.31 0) (effects (font (size 1.27 1.27)) (justify right)) @@ -4571,6 +4775,9 @@ (property "Datasheet" "~" (at 297.18 191.77 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 297.18 191.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C1884573" (at 297.18 191.77 90) (effects (font (size 1.27 1.27)) hide) ) @@ -4586,7 +4793,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 160.02 209.55 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 07f12d14-73c9-4875-85ec-b2ac9b66e7bb) (property "Reference" "Q3" (at 165.2271 208.7891 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4600,6 +4807,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 160.02 209.55 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 160.02 209.55 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347475" (at 160.02 209.55 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4616,7 +4826,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 234.95 238.76 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 0cbeb26e-fa45-4b62-a8df-aee0ae5a76f1) (property "Reference" "R9" (at 236.4486 237.5916 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4630,6 +4840,9 @@ (property "Datasheet" "~" (at 234.95 238.76 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 234.95 238.76 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid a6574e72-9b05-4482-aa04-838b88056ee3)) (pin "2" (uuid 4d80411f-e9c5-4055-9380-fcb4dd9cb6e6)) (instances @@ -4642,7 +4855,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 74.93 107.95 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 11d909ab-4e63-4976-b472-62ac7f7782f6) (property "Reference" "R10" (at 76.4286 106.7816 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4656,6 +4869,9 @@ (property "Datasheet" "~" (at 74.93 107.95 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 74.93 107.95 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid e2cf1cd1-0823-495b-88e1-cdea25ff33a8)) (pin "2" (uuid da5af302-b894-4130-89a0-7c497e190e56)) (instances @@ -4668,7 +4884,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 102.87 53.34 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 1abbac34-1eea-492c-92c5-828617706d37) (property "Reference" "#PWR0115" (at 102.87 57.15 0) (effects (font (size 1.27 1.27)) hide) @@ -4682,6 +4898,9 @@ (property "Datasheet" "" (at 102.87 53.34 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 102.87 53.34 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 2fb1c779-b58e-4087-8f0b-8eea0e3bcfd9)) (instances (project "center" @@ -4693,7 +4912,7 @@ ) (symbol (lib_id "Transistor_FET:AO3401A") (at 220.98 182.88 0) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 1d45aa94-aba4-4197-bf36-33dc749dba62) (property "Reference" "Q11" (at 226.1871 182.1191 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4707,6 +4926,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf" (at 220.98 182.88 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 220.98 182.88 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347476" (at 220.98 182.88 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4723,7 +4945,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 133.35 119.38 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 1d611c54-34fc-4c6b-a7d7-a9c7954ba624) (property "Reference" "R22" (at 135.128 117.0686 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4737,6 +4959,9 @@ (property "Datasheet" "~" (at 133.35 119.38 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 133.35 119.38 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 65b55c84-fdd6-4600-8eb4-4e26e9214b30)) (pin "2" (uuid 6d8b4d69-0725-4a7c-891e-c5fe8580be46)) (instances @@ -4749,7 +4974,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 302.26 195.58 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 211c42c9-4898-43b8-88e2-8ba04fd55d93) (property "Reference" "R24" (at 303.7586 194.4116 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4763,6 +4988,9 @@ (property "Datasheet" "~" (at 302.26 195.58 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 302.26 195.58 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 6330d9a9-6a78-4980-8350-c0f30c42508c)) (pin "2" (uuid 0d216562-42aa-4654-8bd7-ffc244749ff9)) (instances @@ -4775,7 +5003,7 @@ ) (symbol (lib_id "Transistor_FET:AO3401A") (at 220.98 226.06 0) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 2252a19a-d8ad-4d34-ab1a-8d44f38bb7a5) (property "Reference" "Q7" (at 226.1871 225.2991 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4789,6 +5017,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf" (at 220.98 226.06 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 220.98 226.06 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347476" (at 220.98 226.06 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4805,7 +5036,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 204.47 234.95 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 240e9737-9c4d-42a4-bbe1-3d90981e2c32) (property "Reference" "Q6" (at 209.6771 234.1891 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4819,6 +5050,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 204.47 234.95 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 204.47 234.95 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347475" (at 204.47 234.95 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4835,7 +5069,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 229.87 191.77 0) (mirror y) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 242f07ce-a20a-487e-a19a-1e94c0850a37) (property "Reference" "D7" (at 228.6 194.31 0) (effects (font (size 1.27 1.27)) (justify right)) @@ -4849,6 +5083,9 @@ (property "Datasheet" "~" (at 229.87 191.77 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 229.87 191.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C1884573" (at 229.87 191.77 90) (effects (font (size 1.27 1.27)) hide) ) @@ -4864,7 +5101,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 302.26 242.57 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 31c9e228-f089-420a-827c-aabf16176783) (property "Reference" "#PWR012" (at 302.26 248.92 0) (effects (font (size 1.27 1.27)) hide) @@ -4878,6 +5115,9 @@ (property "Datasheet" "" (at 302.26 242.57 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 302.26 242.57 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid f1f53cd6-6358-4daa-8b8a-41bd0d665fac)) (instances (project "center" @@ -4889,7 +5129,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 102.87 77.47 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 38ef0425-7906-4242-a362-4783122b83e4) (property "Reference" "#PWR0113" (at 102.87 83.82 0) (effects (font (size 1.27 1.27)) hide) @@ -4903,6 +5143,9 @@ (property "Datasheet" "" (at 102.87 77.47 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 102.87 77.47 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid f05932bc-4506-4246-b498-aa0aeb830221)) (instances (project "center" @@ -4914,7 +5157,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 69.85 118.11 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 3a29c16a-9073-48d5-b432-6616ca7a5350) (property "Reference" "C13" (at 65.8368 115.6716 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -4928,6 +5171,9 @@ (property "Datasheet" "~" (at 69.85 118.11 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 69.85 118.11 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid e0fa4727-69c7-49b7-b98c-7e4219646569)) (pin "2" (uuid acb3d74a-c75a-47a5-bfde-77998fc0d52b)) (instances @@ -4940,7 +5186,7 @@ ) (symbol (lib_id "Connector_Generic:Conn_02x07_Odd_Even") (at 35.56 95.25 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 3fac0ef7-b07d-4bad-a2dc-f5441cc8074e) (property "Reference" "J1" (at 36.83 83.5279 0) (effects (font (size 1.27 1.27))) @@ -4954,6 +5200,9 @@ (property "Datasheet" "~" (at 35.56 95.25 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 35.56 95.25 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C71397" (at 35.56 95.25 0) (effects (font (size 1.27 1.27)) hide) ) @@ -4981,7 +5230,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 52.07 251.46 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 41701355-9175-41d1-8932-092fa5b6ed1e) (property "Reference" "#PWR0121" (at 45.72 251.46 0) (effects (font (size 1.27 1.27)) hide) @@ -4995,6 +5244,9 @@ (property "Datasheet" "" (at 52.07 251.46 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 52.07 251.46 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid ac5df682-487f-4999-9fe4-101db578e96a)) (instances (project "center" @@ -5006,7 +5258,7 @@ ) (symbol (lib_id "Connector:TestPoint") (at 66.04 219.71 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 48d9a037-f6dc-48af-9ccb-b93cfbfc8147) (property "Reference" "TP4" (at 62.738 216.2429 90) (effects (font (size 1.27 1.27))) @@ -5020,6 +5272,9 @@ (property "Datasheet" "~" (at 66.04 214.63 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 66.04 219.71 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 66.04 219.71 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5034,7 +5289,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 64.77 259.08 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 4b016a47-7d70-4bca-a8f3-345053a927d5) (property "Reference" "#PWR0122" (at 71.12 259.08 0) (effects (font (size 1.27 1.27)) hide) @@ -5048,6 +5303,9 @@ (property "Datasheet" "" (at 64.77 259.08 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 64.77 259.08 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 67042614-42f4-43df-a764-a0b8411c277f)) (instances (project "center" @@ -5059,7 +5317,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 93.98 54.61 0) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 4b718589-4db0-48c1-823c-32e1d9540875) (property "Reference" "R19" (at 95.4786 55.7784 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5073,6 +5331,9 @@ (property "Datasheet" "~" (at 93.98 54.61 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 93.98 54.61 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 4db7c1e1-869b-470b-ac9f-fa50d8b9828a)) (pin "2" (uuid 6460ff6d-db55-4b1d-a949-a3962e4c7c9f)) (instances @@ -5085,7 +5346,7 @@ ) (symbol (lib_id "Connector_Generic:Conn_02x10_Top_Bottom") (at 57.15 246.38 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 549c845d-c338-4f0d-b4e1-befba4b5d69d) (property "Reference" "J2" (at 58.42 232.1179 0) (effects (font (size 1.27 1.27))) @@ -5099,6 +5360,9 @@ (property "Datasheet" "~" (at 57.15 246.38 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 57.15 246.38 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 57.15 246.38 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5132,7 +5396,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 113.03 77.47 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 571bbf1b-18f5-4a95-85ec-9e968c6784a6) (property "Reference" "C14" (at 115.3668 76.3016 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5146,6 +5410,9 @@ (property "Datasheet" "~" (at 113.03 77.47 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 113.03 77.47 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C15725" (at 113.03 77.47 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5161,7 +5428,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 204.47 191.77 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 590fb119-a9f0-44e3-87a0-aec3a61af02a) (property "Reference" "Q10" (at 209.6771 191.0091 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5175,6 +5442,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 204.47 191.77 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 204.47 191.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347475" (at 204.47 191.77 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5191,7 +5461,7 @@ ) (symbol (lib_id "Connector:TestPoint") (at 62.23 209.55 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 5b730b53-80c0-4f9e-8483-157934fa2ed2) (property "Reference" "TP5" (at 58.928 206.0829 90) (effects (font (size 1.27 1.27))) @@ -5205,6 +5475,9 @@ (property "Datasheet" "~" (at 62.23 204.47 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 62.23 209.55 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 62.23 209.55 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5219,7 +5492,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 302.26 199.39 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 6ad2443a-24d1-4d4c-a479-2725a42edf4c) (property "Reference" "#PWR014" (at 302.26 205.74 0) (effects (font (size 1.27 1.27)) hide) @@ -5233,6 +5506,9 @@ (property "Datasheet" "" (at 302.26 199.39 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 302.26 199.39 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 08bc84d5-595b-4cb2-8166-d09c3cf1331f)) (instances (project "center" @@ -5244,7 +5520,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 82.55 64.77 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 72b938c8-a63a-4176-a322-72132867b104) (property "Reference" "R17" (at 83.7184 66.2686 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5258,6 +5534,9 @@ (property "Datasheet" "~" (at 82.55 64.77 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 82.55 64.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 5f5e181e-6fb8-4111-a177-db43e7952bd6)) (pin "2" (uuid 6d85db3e-ceb5-4541-8f84-6b89b170d6b2)) (instances @@ -5270,7 +5549,7 @@ ) (symbol (lib_id "Connector:TestPoint") (at 127 207.01 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 7631aaaa-43ec-4000-83ff-460feb9b6a4d) (property "Reference" "TP2" (at 131.699 206.4155 90) (effects (font (size 1.27 1.27)) (justify left)) @@ -5284,6 +5563,9 @@ (property "Datasheet" "~" (at 127 212.09 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 127 207.01 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 127 207.01 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5298,7 +5580,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 52.07 259.08 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 7ad1af41-b58d-4c17-a7a4-f300cb7bb10b) (property "Reference" "#PWR0120" (at 55.88 259.08 0) (effects (font (size 1.27 1.27)) hide) @@ -5312,6 +5594,9 @@ (property "Datasheet" "" (at 52.07 259.08 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 52.07 259.08 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 38d9ed97-8613-421c-8fa4-cb0dc2dd48b7)) (instances (project "center" @@ -5323,7 +5608,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 271.78 234.95 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 7b7081a2-bd3b-4f59-9eae-cac467b9ae3e) (property "Reference" "Q4" (at 276.9871 234.1891 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5337,6 +5622,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 271.78 234.95 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 271.78 234.95 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347475" (at 271.78 234.95 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5353,7 +5641,7 @@ ) (symbol (lib_id "center-rescue:R-Device") (at 105.41 119.38 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 7be2e193-7b9b-4be6-b590-1884f3a900c6) (property "Reference" "R21" (at 107.188 117.0686 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5367,6 +5655,9 @@ (property "Datasheet" "~" (at 105.41 119.38 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 105.41 119.38 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 9a2d3689-268c-429d-a5ad-9eb344e77f26)) (pin "2" (uuid 40ce76f3-13ca-4dd7-b7a6-368e40681a23)) (instances @@ -5379,7 +5670,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 100.33 113.03 0) (mirror y) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 811252da-b749-434d-b7f9-e6d01d045b74) (property "Reference" "Q1" (at 95.1229 112.2691 0) (effects (font (size 1.27 1.27)) (justify right)) @@ -5393,6 +5684,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 100.33 113.03 0) (effects (font (size 1.27 1.27)) (justify right) hide) ) + (property "Description" "" (at 100.33 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C396097" (at 100.33 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5409,7 +5703,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 74.93 123.19 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 82f5327f-63b5-4718-b2d4-0ce3a1690334) (property "Reference" "#PWR0116" (at 74.93 129.54 0) (effects (font (size 1.27 1.27)) hide) @@ -5423,6 +5717,9 @@ (property "Datasheet" "" (at 74.93 123.19 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 74.93 123.19 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 8dc90c1c-96c2-44ea-a050-1337a13b8b84)) (instances (project "center" @@ -5434,7 +5731,7 @@ ) (symbol (lib_id "Transistor_FET:AO3401A") (at 288.29 182.88 0) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 862404d9-1ea2-4eb4-af57-2aa169f5bf7c) (property "Reference" "Q9" (at 293.4971 182.1191 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5448,6 +5745,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf" (at 288.29 182.88 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 288.29 182.88 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347476" (at 288.29 182.88 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5464,12 +5764,12 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 113.03 74.93 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 96d9cbdd-aab7-4856-8f64-963992c49e8e) (property "Reference" "#PWR0118" (at 113.03 78.74 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Value" "+3V3" (at 115.951 78.0288 90) + (property "Value" "+3V3" (at 110.49 71.12 0) (effects (font (size 1.27 1.27)) (justify left)) ) (property "Footprint" "" (at 113.03 74.93 0) @@ -5478,6 +5778,9 @@ (property "Datasheet" "" (at 113.03 74.93 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 113.03 74.93 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid ecf287e1-955c-4eb2-a04c-ab227738b348)) (instances (project "center" @@ -5489,7 +5792,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 271.78 191.77 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid 9784fd81-6968-46a3-891f-56e8ee46ebf0) (property "Reference" "Q8" (at 276.9871 191.0091 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5503,6 +5806,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 271.78 191.77 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 271.78 191.77 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347475" (at 271.78 191.77 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5519,7 +5825,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 87.63 54.61 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid 99b1b20a-e768-475b-b28c-64789d72202d) (property "Reference" "R18" (at 89.1286 53.4416 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5533,6 +5839,9 @@ (property "Datasheet" "~" (at 87.63 54.61 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 87.63 54.61 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 6fb9ce61-9c68-4ec2-8fdb-f86fd2e7c94c)) (pin "2" (uuid b5a42883-a93c-41e3-8622-b8c62e191d20)) (instances @@ -5545,7 +5854,7 @@ ) (symbol (lib_id "Connector:TestPoint") (at 73.66 207.01 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid a1726701-fcaf-4acd-a5d3-a0fa3a7cad68) (property "Reference" "TP3" (at 70.358 203.5429 90) (effects (font (size 1.27 1.27))) @@ -5559,6 +5868,9 @@ (property "Datasheet" "~" (at 73.66 201.93 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 73.66 207.01 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 73.66 207.01 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5573,7 +5885,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 82.55 59.69 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid a6670c53-03af-4fa5-acfe-377cfe727a92) (property "Reference" "R16" (at 81.3816 58.1914 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5587,6 +5899,9 @@ (property "Datasheet" "~" (at 82.55 59.69 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 82.55 59.69 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 78525149-150e-49d1-860e-85a8f7500488)) (pin "2" (uuid 846f87f2-d1d4-4b56-8049-9c1ba9c63d32)) (instances @@ -5599,7 +5914,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 93.98 69.85 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid aabfeb48-c9bc-4f58-b5e9-7aa0e294e61e) (property "Reference" "R20" (at 95.4786 68.6816 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5613,6 +5928,9 @@ (property "Datasheet" "~" (at 93.98 69.85 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 93.98 69.85 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid b0864949-d2fe-4de3-8c78-928989bf539a)) (pin "2" (uuid c70ef096-43eb-4a69-af0e-64d42b9efc9f)) (instances @@ -5625,7 +5943,7 @@ ) (symbol (lib_id "center-rescue:C_Small-Device") (at 365.76 113.03 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid add0d31e-023f-412b-b4e3-406f5dbc629f) (property "Reference" "C11" (at 368.0968 111.8616 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5639,6 +5957,9 @@ (property "Datasheet" "~" (at 365.76 113.03 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 365.76 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C95841" (at 365.76 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5654,7 +5975,7 @@ ) (symbol (lib_id "Amplifier_Operational:MCP6001-OT") (at 105.41 62.23 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid b2d21e77-d836-437d-9c9c-3aeb38d0ef58) (property "Reference" "U4" (at 107.6961 58.9291 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5668,6 +5989,9 @@ (property "Datasheet" "http://ww1.microchip.com/downloads/en/DeviceDoc/21733j.pdf" (at 105.41 57.15 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 105.41 62.23 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C910875" (at 105.41 62.23 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5686,7 +6010,7 @@ ) (symbol (lib_id "Connector:TestPoint") (at 127 212.09 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid b9acfe7d-3624-444e-a270-0fd85ca9f91d) (property "Reference" "TP6" (at 131.699 211.4955 90) (effects (font (size 1.27 1.27)) (justify left)) @@ -5700,6 +6024,9 @@ (property "Datasheet" "~" (at 127 217.17 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 127 212.09 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 127 212.09 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5714,7 +6041,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 234.95 195.58 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid ba485eea-06b5-4cf0-bc7b-978cebc7bfdf) (property "Reference" "R8" (at 236.4486 194.4116 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -5728,6 +6055,9 @@ (property "Datasheet" "~" (at 234.95 195.58 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 234.95 195.58 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 1f51eb36-e8b5-41a9-898f-49a3c54adc82)) (pin "2" (uuid daef39a3-e6bc-4813-bf0a-ceae70dad3ba)) (instances @@ -5740,7 +6070,7 @@ ) (symbol (lib_id "Transistor_FET:AO3400A") (at 128.27 113.03 0) (mirror y) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid be2156c1-d93e-4138-9442-ab92c04b1d25) (property "Reference" "Q2" (at 123.0629 112.2691 0) (effects (font (size 1.27 1.27)) (justify right)) @@ -5754,6 +6084,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3400A.pdf" (at 128.27 113.03 0) (effects (font (size 1.27 1.27)) (justify right) hide) ) + (property "Description" "" (at 128.27 113.03 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C396097" (at 128.27 113.03 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5770,7 +6103,7 @@ ) (symbol (lib_id "Connector:TestPoint") (at 127 214.63 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid bfe27944-af05-48a3-9640-824c4594e485) (property "Reference" "TP1" (at 131.699 214.0355 90) (effects (font (size 1.27 1.27)) (justify left)) @@ -5784,6 +6117,9 @@ (property "Datasheet" "~" (at 127 219.71 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 127 214.63 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "DNP" "DNP" (at 127 214.63 0) (effects (font (size 1.27 1.27)) hide) ) @@ -5798,7 +6134,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 234.95 242.57 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid c229a593-ce36-4beb-a0b5-8bb718b4ed23) (property "Reference" "#PWR011" (at 234.95 248.92 0) (effects (font (size 1.27 1.27)) hide) @@ -5812,6 +6148,9 @@ (property "Datasheet" "" (at 234.95 242.57 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 234.95 242.57 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid fa6f9b73-f6cb-4b40-8fa3-e7c74ee1d0df)) (instances (project "center" @@ -5823,7 +6162,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 93.98 49.53 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid c342f773-00df-4a8b-b7d2-619a467a63fb) (property "Reference" "#PWR0114" (at 93.98 53.34 0) (effects (font (size 1.27 1.27)) hide) @@ -5837,6 +6176,9 @@ (property "Datasheet" "" (at 93.98 49.53 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 93.98 49.53 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 3b529d31-b768-49c1-9dbc-731cca3bfd48)) (instances (project "center" @@ -5848,7 +6190,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 64.77 243.84 90) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid cd2c7856-7a0e-4c82-879e-613d9c7e0739) (property "Reference" "#PWR0123" (at 71.12 243.84 0) (effects (font (size 1.27 1.27)) hide) @@ -5862,6 +6204,9 @@ (property "Datasheet" "" (at 64.77 243.84 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 64.77 243.84 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 40180649-1d43-4eae-9420-a494fae7dac1)) (instances (project "center" @@ -5873,7 +6218,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 234.95 199.39 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid cd6fed8b-18db-4096-8cac-2cb0b290fbb1) (property "Reference" "#PWR010" (at 234.95 205.74 0) (effects (font (size 1.27 1.27)) hide) @@ -5887,6 +6232,9 @@ (property "Datasheet" "" (at 234.95 199.39 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 234.95 199.39 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 444bd685-5203-4dc3-9b18-f62be0d6889d)) (instances (project "center" @@ -5898,7 +6246,7 @@ ) (symbol (lib_id "center-rescue:D_Zener_ALT-Device") (at 140.97 119.38 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid d07342cc-fd15-4665-b5c8-dcfd74d9f8c7) (property "Reference" "D10" (at 142.9766 118.2116 90) (effects (font (size 1.27 1.27)) (justify left)) @@ -5912,6 +6260,9 @@ (property "Datasheet" "~" (at 140.97 119.38 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 140.97 119.38 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Mfg" "DIODES inc." (at 140.97 119.38 90) (effects (font (size 1.27 1.27)) hide) ) @@ -5933,7 +6284,7 @@ ) (symbol (lib_id "center-rescue:GND-power") (at 113.03 80.01 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid d31b75e0-de74-4c57-ba75-a640c5312516) (property "Reference" "#PWR0119" (at 113.03 86.36 0) (effects (font (size 1.27 1.27)) hide) @@ -5947,6 +6298,9 @@ (property "Datasheet" "" (at 113.03 80.01 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 113.03 80.01 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 3182bc09-a29a-4058-9414-98717a6c1ba5)) (instances (project "center" @@ -5958,7 +6312,7 @@ ) (symbol (lib_id "center-rescue:D_Zener_ALT-Device") (at 113.03 119.38 270) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid e1bf02ea-143c-4d11-a667-05b04efa654b) (property "Reference" "D9" (at 115.0366 118.2116 90) (effects (font (size 1.27 1.27)) (justify left)) @@ -5972,6 +6326,9 @@ (property "Datasheet" "~" (at 113.03 119.38 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 113.03 119.38 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "Mfg" "DIODES inc." (at 113.03 119.38 90) (effects (font (size 1.27 1.27)) hide) ) @@ -5993,7 +6350,7 @@ ) (symbol (lib_id "Transistor_FET:AO3401A") (at 288.29 226.06 0) (mirror x) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid e9273e5d-0e81-494a-a95f-7488be968df5) (property "Reference" "Q5" (at 293.4971 225.2991 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -6007,6 +6364,9 @@ (property "Datasheet" "http://www.aosmd.com/pdfs/datasheet/AO3401A.pdf" (at 288.29 226.06 0) (effects (font (size 1.27 1.27)) (justify left) hide) ) + (property "Description" "" (at 288.29 226.06 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C347476" (at 288.29 226.06 0) (effects (font (size 1.27 1.27)) hide) ) @@ -6023,7 +6383,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 74.93 118.11 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid f1181824-68e0-45a5-ae7e-ae63db9d6233) (property "Reference" "R15" (at 76.4286 116.9416 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -6037,6 +6397,9 @@ (property "Datasheet" "~" (at 74.93 118.11 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 74.93 118.11 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid fc0ace19-90d8-4067-9b8b-63503e3538be)) (pin "2" (uuid 24436446-4fb5-4cc0-850c-c299f95c9e22)) (instances @@ -6049,7 +6412,7 @@ ) (symbol (lib_id "center-rescue:R_Small-Device") (at 302.26 238.76 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid f734aa69-5f45-4488-bcdc-0f0f194cbf1d) (property "Reference" "R23" (at 303.7586 237.5916 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -6063,6 +6426,9 @@ (property "Datasheet" "~" (at 302.26 238.76 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 302.26 238.76 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 2c3fde70-d8d5-4e89-834b-ed635f08d001)) (pin "2" (uuid a67a7657-aa89-4aa7-801b-99dde144f8d0)) (instances @@ -6075,7 +6441,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 297.18 234.95 0) (mirror y) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid f7a9d2eb-ee9d-4a84-a3b8-67d6f1243977) (property "Reference" "D11" (at 295.91 237.49 0) (effects (font (size 1.27 1.27)) (justify right)) @@ -6089,6 +6455,9 @@ (property "Datasheet" "~" (at 297.18 234.95 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 297.18 234.95 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C1884573" (at 297.18 234.95 90) (effects (font (size 1.27 1.27)) hide) ) @@ -6104,7 +6473,7 @@ ) (symbol (lib_id "MCU_ST_STM32G0:STM32G030F6Px") (at 96.52 204.47 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid f91ac3d8-e10f-41a5-97d3-600c50296cb0) (property "Reference" "U3" (at 101.0159 186.3979 0) (effects (font (size 1.27 1.27)) (justify left)) @@ -6118,6 +6487,9 @@ (property "Datasheet" "https://www.st.com/resource/en/datasheet/stm32g030f6.pdf" (at 96.52 204.47 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 96.52 204.47 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C724040" (at 96.52 204.47 0) (effects (font (size 1.27 1.27)) hide) ) @@ -6151,7 +6523,7 @@ ) (symbol (lib_id "center-rescue:D_Schottky_ALT-Device") (at 229.87 234.95 0) (mirror y) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid fc4e7a44-53f9-4396-bed4-0a190f73a426) (property "Reference" "D8" (at 228.6 237.49 0) (effects (font (size 1.27 1.27)) (justify right)) @@ -6165,6 +6537,9 @@ (property "Datasheet" "~" (at 229.87 234.95 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 229.87 234.95 0) + (effects (font (size 1.27 1.27)) hide) + ) (property "LCSC" "C1884573" (at 229.87 234.95 90) (effects (font (size 1.27 1.27)) hide) ) @@ -6180,7 +6555,7 @@ ) (symbol (lib_id "center-rescue:+3.3V-power") (at 74.93 102.87 0) (unit 1) - (in_bom yes) (on_board yes) (dnp no) + (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid ff1bca64-0cbc-429c-b720-84bdbdff176d) (property "Reference" "#PWR0117" (at 74.93 106.68 0) (effects (font (size 1.27 1.27)) hide) @@ -6194,6 +6569,9 @@ (property "Datasheet" "" (at 74.93 102.87 0) (effects (font (size 1.27 1.27)) hide) ) + (property "Description" "" (at 74.93 102.87 0) + (effects (font (size 1.27 1.27)) hide) + ) (pin "1" (uuid 8fc126df-e5c4-4881-9212-9b5b3effca4c)) (instances (project "center" diff --git a/center_fw/.gdbinit b/center_fw/.gdbinit new file mode 100644 index 0000000..2617c8f --- /dev/null +++ b/center_fw/.gdbinit @@ -0,0 +1,20 @@ + +target extended-remote 192.168.1.97:2022 +set print pretty on +set print elements 512 + +# Update GDB's Python paths with the `sys.path` values of the local Python installation, +# whether that is brew'ed Python, a virtualenv, or another system python. + +# Convert GDB to interpret in Python +python +import os,subprocess,sys +# Execute a Python using the user's shell and pull out the sys.path (for site-packages) +paths = subprocess.check_output('python -c "import os,sys;print(os.linesep.join(sys.path).strip())"',shell=True).decode("utf-8").split() +# Extend GDB's Python's search path +sys.path.extend(paths) +end + +source ~/ref/PyCortexMDebug/cmdebug/svd_gdb.py +svd_load ~/ref/stm32square/svd/STM32G030.svd + diff --git a/center_fw/Makefile b/center_fw/Makefile index 98c0f5b..681eb35 100644 --- a/center_fw/Makefile +++ b/center_fw/Makefile @@ -1,102 +1,191 @@ -# Megumin LED display firmware -# Copyright (C) 2018 Sebastian Götte <code@jaseg.net> -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. - -CUBE_PATH ?= $(wildcard ~)/ref/STM32CubeF0 -CMSIS_PATH ?= $(CUBE_PATH)/Drivers/CMSIS -CMSIS_DEV_PATH ?= $(CMSIS_PATH)/Device/ST/STM32F0xx -HAL_PATH ?= $(CUBE_PATH)/Drivers/STM32F0xx_HAL_Driver - -MAC_ADDR ?= 0xdeadbeef - -CC := arm-none-eabi-gcc -LD := arm-none-eabi-ld -OBJCOPY := arm-none-eabi-objcopy -OBJDUMP := arm-none-eabi-objdump -SIZE := arm-none-eabi-size - -CFLAGS = -g -Wall -std=gnu11 -O0 -fdump-rtl-expand -DMAC_ADDR=$(MAC_ADDR) -DADC_BUFSIZE=1024 -CFLAGS += -mlittle-endian -mcpu=cortex-m0 -march=armv6-m -mthumb -#CFLAGS += -ffunction-sections -fdata-sections -LDFLAGS = -nostartfiles -#LDFLAGS += -specs=rdimon.specs -DSEMIHOSTING -LDFLAGS += -Wl,-Map=main.map -nostdlib -#LDFLAGS += -Wl,--gc-sections -LIBS = -lgcc -#LIBS += -lrdimon - -# Technically we're using an STM32F030F4, but apart from the TSSOP20 package that one is largely identical to the -# STM32F030*6 and there is no separate device header provided for it, so we're faking a *6 device here. This is -# even documented in stm32f0xx.h. Thanks ST! -CFLAGS += -DSTM32F030x6 -DHSE_VALUE=8000000 - -LDFLAGS += -Tstm32_flash.ld -CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig -Wno-unused -I../common -LDFLAGS += -L$(CMSIS_PATH)/Lib/GCC -larm_cortexM0l_math - -################################################### - -.PHONY: program clean - -all: main.elf - -.clang: - echo flags = $(CFLAGS) > .clang - -cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/core_cm0.h - python3 tools/gen_cmsis_exports.py $^ > $@ - -%.o: %.c - $(CC) -c $(CFLAGS) -o $@ $^ -# $(CC) -E $(CFLAGS) -o $(@:.o=.pp) $^ - -%.o: %.s - $(CC) -c $(CFLAGS) -o $@ $^ -# $(CC) -E $(CFLAGS) -o $(@:.o=.pp) $^ + +######################################################################################################################## +# Dependency directories +######################################################################################################################## + +MUSL_DIR ?= upstream/musl + +######################################################################################################################## +# Algorithm parameters +######################################################################################################################## + +# - none - + +######################################################################################################################## +# High-level build parameters +######################################################################################################################## + +DEBUG ?= 1 +OPT ?= 0 + +BUILDDIR ?= build +BINARY := main.elf +LDSCRIPT := generic_stm32.ld +DEVICE := STM32G030F4 + + +######################################################################################################################## +# Sources +######################################################################################################################## + +ASM_SOURCES := startup.s + +C_SOURCES := src/main.c common/8b10b.c + +CPP_SOURCES := # - none - + +MUSL_SOURCES := # - none - +MUSL_SOURCES := $(addprefix $(MUSL_DIR)/src/,$(MUSL_SOURCES)) + +C_SOURCES += $(MUSL_SOURCES) + + +######################################################################################################################## +# Low-level build parameters +######################################################################################################################## + +PREFIX ?= arm-none-eabi- + +HOSTCC := gcc +CC := $(PREFIX)gcc +CPP := $(PREFIX)cpp +CXX := $(PREFIX)g++ +LD := $(PREFIX)gcc +AR := $(PREFIX)ar +AS := $(PREFIX)as +SIZE := $(PREFIX)size +NM := $(PREFIX)nm +OBJCOPY := $(PREFIX)objcopy +OBJDUMP := $(PREFIX)objdump +GDB := $(PREFIX)gdb + +HOST_CC ?= $(HOST_PREFIX)gcc +HOST_CXX ?= $(HOST_PREFIX)g++ +HOST_LD ?= $(HOST_PREFIX)gcc +HOST_AR ?= $(HOST_PREFIX)ar +HOST_AS ?= $(HOST_PREFIX)as +HOST_OBJCOPY ?= $(HOST_PREFIX)objcopy +HOST_OBJDUMP ?= $(HOST_PREFIX)objdump + +PYTHON3 ?= python3 +DOT ?= dot + +MUSL_DIR_ABS := $(abspath $(MUSL_DIR)) +CMSIS_DEVICE_DIR_ABS := $(abspath $(CMSIS_DEVICE_DIR)) + +DEVICE_FAMILY := $(shell echo $(DEVICE) | grep -Eio 'STM32[a-z]{1,2}[0-9]'|cut -c 6-) +DEVICE_DEFINES := -DSTM32$(DEVICE_FAMILY) $(addprefix -D,$(shell cat stm32_buildinfo.defines)) + +ARCH_FLAGS ?= -mthumb -mcpu=cortex-m0 -mfloat-abi=soft +SYSTEM_FLAGS ?= -nostdlib -ffreestanding -nostartfiles + +COMMON_CFLAGS += -I$(abspath include) -I$(abspath common) +COMMON_CFLAGS += -I$(BUILDDIR) + +CFLAGS += -I$(abspath tools/musl_include_shims) +CFLAGS += -I$(abspath upstream/libusb_stm32/inc) +CFLAGS += -I$(CMSIS_DEVICE_DIR_ABS)/Include + +CFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS) +CFLAGS += -fno-common -ffunction-sections -fdata-sections + +COMMON_CFLAGS += -O$(OPT) -std=gnu2x -g +COMMON_CFLAGS += $(DEVICE_DEFINES) +COMMON_CFLAGS += -DDEBUG=$(DEBUG) + +GEN_HEADERS := $(BUILDDIR)/generated/waveform_tables.h + +HOST_CFLAGS += $(COMMON_CFLAGS) + +# for musl +CFLAGS += -Dhidden= + +SIM_CFLAGS += -lm -DSIMULATION +SIM_CFLAGS += -Wall -Wextra -Wpedantic -Wshadow -Wimplicit-function-declaration -Wundef -Wno-unused-parameter + +INT_CFLAGS += -Wall -Wextra -Wpedantic -Wshadow -Wimplicit-function-declaration -Wundef -Wno-unused-parameter +INT_CFLAGS += -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes + +CXXFLAGS += -Os -g +CXXFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS) +CXXFLAGS += -fno-common -ffunction-sections -fdata-sections +CXXFLAGS += -Wall -Wextra -Wshadow -Wundef -Wredundant-decls +CXXFLAGS += -I. + +LDFLAGS += $(ARCH_FLAGS) $(SYSTEM_FLAGS) + +LIBS += -lgcc +#LDFLAGS += -Wl,--gc-sections + +LINKMEM_FLAGS ?= --trim-stubs=startup.o --trace-sections .isr_vector --highlight-subdirs $(BUILDDIR) + +OBJS := $(addprefix $(BUILDDIR)/,$(C_SOURCES:.c=.o) $(CXX_SOURCES:.cpp=.o) $(ASM_SOURCES:.s=.o)) +ALL_OBJS := $(OBJS) +ALL_OBJS += $(BUILDDIR)/system.o +# Add generated source here. + +######################################################################################################################## +# Rules +######################################################################################################################## + +all: binsize + +.PHONY: binsize +binsize: $(BUILDDIR)/$(BINARY) $(BUILDDIR)/$(BINARY:.elf=-symbol-sizes.pdf) + $(LD) -T$(LDSCRIPT) $(LDFLAGS) -Wl,--print-memory-usage -o /dev/null $(ALL_OBJS) $(LIBS) + @echo + @echo "▐▬▬▬▌ SyMbOL sIzE HiGhScORe LiSt ▐▬▬▬▌" + $(NM) --print-size --size-sort --radix=d $< | tail -n 20 + +.PRECIOUS: $(BUILDDIR)/$(BINARY) +$(BUILDDIR)/$(BINARY) $(BUILDDIR)/$(BINARY:.elf=.map) &: $(ALL_OBJS) + $(LD) -T$(LDSCRIPT) $(LDFLAGS) -o $@ -Wl,-Map=$(BUILDDIR)/$(BINARY:.elf=.map) $(ALL_OBJS) $(LIBS) + +build/$(BINARY:.elf=-symbol-sizes.dot): $(ALL_OBJS) + $(PYTHON3) tools/linkmem.py $(LINKMEM_FLAGS) $(LD) -T$(LDSCRIPT) $(LDFLAGS) $^ $(LIBS) > $@ + +%.pdf: %.dot + $(DOT) -T pdf $< -o $@ %.dot: %.elf - r2 -a arm -qc 'aa;agC' $< 2>/dev/null >$@ - -sources.tar.xz: main.c adc.c ../common/8b10b.c Makefile - tar -caf $@ $^ - -# don't ask... -sources.tar.xz.zip: sources.tar.xz - zip $@ $^ - -sources.c: sources.tar.xz.zip - xxd -i $< | head -n -1 | sed 's/=/__attribute__((section(".source_tarball"))) =/' > $@ - -main.elf: main.c startup_stm32f030x6.s system_stm32f0xx.c base.c - $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS) - $(OBJCOPY) -O ihex $@ $(@:.elf=.hex) - $(OBJCOPY) -O binary $@ $(@:.elf=.bin) - $(OBJDUMP) -St $@ >$(@:.elf=.lst) - $(SIZE) $@ - -program: main.elf openocd.cfg - openocd -f openocd.cfg -c "program $< verify reset exit" + r2 -a arm -qc 'aa;agRd' $< 2>/dev/null >$@ + +$(BUILDDIR)/src/%.o: src/%.s + mkdir -p $(@D) + $(CC) $(COMMON_CFLAGS) $(CFLAGS) $(INT_CFLAGS) -o $@ -c $< + +$(BUILDDIR)/src/%.o: src/%.c $(GEN_HEADERS) + mkdir -p $(@D) + $(CC) $(COMMON_CFLAGS) $(CFLAGS) $(INT_CFLAGS) -o $@ -c $< + +$(BUILDDIR)/src/%.o: src/%.cpp + mkdir -p $(@D) + $(CXX) $(CXXFLAGS) -o $@ -c $< + +$(BUILDDIR)/%.o: %.c + mkdir -p $(@D) + $(CC) $(COMMON_CFLAGS) $(CFLAGS) $(EXT_CFLAGS) -o $@ -c $< + +$(BUILDDIR)/%.o: %.s + mkdir -p $(@D) + $(CC) $(COMMON_CFLAGS) $(CFLAGS) $(EXT_CFLAGS) -o $@ -c $< + +venv: + test -d venv || python3 -m venv --system-site-packages venv + source venv/bin/activate && pip install cxxfilt pyelftools libarchive matplotlib clean: - rm -f **.o - rm -f main.elf main.hex main.bin main.map main.lst - rm -f **.expand - rm -f cmsis_exports.c - rm -f sources.tar.xz - rm -f sources.tar.xz.zip - rm -f sources.c - rm -f *.dot - rm -f protocol_test + rm -rf $(BUILDDIR)/src + rm -rf $(BUILDDIR)/generated + rm -f $(BUILDDIR)/**.o + rm -f $(BUILDDIR)/$(BINARY) + rm -f $(BUILDDIR)/$(BINARY:.elf=.map) + rm -f $(BUILDDIR)/$(BINARY:.elf=-symbol-sizes.dot) + rm -f $(BUILDDIR)/$(BINARY:.elf=-symbol-sizes.pdf) + +mrproper: clean + rm -rf build + +.PHONY: clean mrproper +-include $(OBJS:.o=.d) diff --git a/center_fw/Scope.ipynb b/center_fw/Scope.ipynb index 9222f06..afd8027 100644 --- a/center_fw/Scope.ipynb +++ b/center_fw/Scope.ipynb @@ -34,9 +34,7 @@ { "cell_type": "code", "execution_count": 47, - "metadata": { - "scrolled": false - }, + "metadata": {}, "outputs": [ { "data": { @@ -839,9 +837,7 @@ { "cell_type": "code", "execution_count": 74, - "metadata": { - "scrolled": false - }, + "metadata": {}, "outputs": [ { "data": { @@ -1657,7 +1653,7 @@ ], "metadata": { "kernelspec": { - "display_name": "Python 3", + "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, @@ -1671,9 +1667,9 @@ "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", - "version": "3.6.7" + "version": "3.11.5" } }, "nbformat": 4, - "nbformat_minor": 2 + "nbformat_minor": 4 } diff --git a/center_fw/generic_stm32.ld b/center_fw/generic_stm32.ld new file mode 100644 index 0000000..ef1f057 --- /dev/null +++ b/center_fw/generic_stm32.ld @@ -0,0 +1,125 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +INCLUDE memory_map.ldi +} + +/* Highest address of the user mode stack */ +PROVIDE(_estack = ORIGIN(RAM) + LENGTH(RAM)); + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/center_fw/global.h b/center_fw/global.h deleted file mode 100644 index 413c22b..0000000 --- a/center_fw/global.h +++ /dev/null @@ -1,52 +0,0 @@ -/* Megumin LED display firmware - * Copyright (C) 2018 Sebastian Götte <code@jaseg.net> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __GLOBAL_H__ -#define __GLOBAL_H__ - -/* Workaround for sub-par ST libraries */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#include <stm32f0xx.h> -#include <stm32f0xx_ll_utils.h> -#include <stm32f0xx_ll_spi.h> -#pragma GCC diagnostic pop - -#include <system_stm32f0xx.h> - -#include <stdint.h> -#include <stdbool.h> -#include <string.h> -#include <unistd.h> - -/* Microcontroller part number: STM32F030F4C6 */ - -/* Things used for module status reporting. */ -#define FIRMWARE_VERSION 1 -#define HARDWARE_VERSION 0 - -#define TS_CAL1 (*(uint16_t *)0x1FFFF7B8) -#define VREFINT_CAL (*(uint16_t *)0x1FFFF7BA) - -#define VMEAS_R_HIGH 10000 /* kiloohms */ -#define VMEAS_R_LOW 3300 /* kiloohms */ - -extern volatile unsigned int sys_time; -extern volatile unsigned int sys_time_seconds; -extern uint16_t jitter_meas_avg_ns; - -#endif/*__GLOBAL_H__*/ diff --git a/center_fw/include/cmsis_compiler.h b/center_fw/include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/center_fw/include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include <stdint.h> + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include <cmsis_iccarm.h> + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include <cmsis_ccs.h> + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include <cmsis_csm.h> + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/center_fw/include/cmsis_gcc.h b/center_fw/include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/center_fw/include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; i<pTable->wlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; i<pTable->wlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/center_fw/include/cmsis_version.h b/center_fw/include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/center_fw/include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/center_fw/include/core_cm0.h b/center_fw/include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/center_fw/include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/center_fw/include/core_cm0plus.h b/center_fw/include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/center_fw/include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/center_fw/include/global.h b/center_fw/include/global.h new file mode 100644 index 0000000..f01b849 --- /dev/null +++ b/center_fw/include/global.h @@ -0,0 +1,66 @@ + +#ifndef __GLOBAL_H__ +#define __GLOBAL_H__ + +#include <stdbool.h> +#include <stdint.h> +#include <sys/types.h> +#include <assert.h> +#include <string.h> + +/* The IRQ header must be included before stm32_device.h since ST defines a bunch of messy macros there. */ +#include <stm32_irqs.h> /* Header generated from stm32***_startup.s in Makefile */ + +#include <stm32g0xx.h> +#include <core_cm0plus.h> + +#define COUNT_OF(x) ((sizeof(x)/sizeof(0[x])) / ((size_t)(!(sizeof(x) % sizeof(0[x]))))) + +#define AFRL(pin, val) ((val) << ((pin)*4)) +#define AFRH(pin, val) ((val) << (((pin)-8)*4)) +#define AF(pin) (2<<(2*(pin))) +#define OUT(pin) (1<<(2*(pin))) +#define IN(pin) (0) +#define ANALOG(pin) (3<<(2*(pin))) +#define CLEAR(pin) (~(3<<(2*(pin)))) +#define PULLUP(pin) (1<<(2*pin)) +#define PULLDOWN(pin) (2<<(2*pin)) +#define BSRR_CLEAR(pin) ((1<<pin)<<16) +#define BSRR_SET(pin) (1<<pin) +#define BSRR_VALUE(pin, value) ((((!(value))<<pin)<<16) | ((!!(value))<<pin)) + +#ifndef SYSTICK_INTERVAL_US +#define SYSTICK_INTERVAL_US 1000 +#endif /* SYSTICK_INTERVAL_US */ + +#define FIRMWARE_VERSION 1 +#define HARDWARE_VERSION 0 + +#define TS_CAL1 (*(uint16_t *)0x1FFFF7B8) +#define VREFINT_CAL (*(uint16_t *)0x1FFFF7BA) + +#define VMEAS_R_HIGH 10000 /* kiloohms */ +#define VMEAS_R_LOW 3300 /* kiloohms */ + + +enum ErrorCode { + ERR_SUCCESS = 0, + ERR_TIMEOUT, + ERR_PHYSICAL_LAYER, + ERR_FRAMING, + ERR_PROTOCOL, + ERR_DMA, + ERR_BUSY, + ERR_BUFFER_OVERFLOW, + ERR_RX_OVERRUN, + ERR_TX_OVERRUN, +}; + +typedef enum ErrorCode ErrorCode; + +void delay_us(int duration_us); + +extern volatile uint64_t sys_time_us; +extern uint16_t jitter_meas_avg_ns; + +#endif /* __GLOBAL_H__ */ diff --git a/center_fw/include/iomacros.h b/center_fw/include/iomacros.h new file mode 100644 index 0000000..8d84c9e --- /dev/null +++ b/center_fw/include/iomacros.h @@ -0,0 +1,14 @@ +#ifndef __IOMACROS_H__ +#define __IOMACROS_H__ + +#define IN(pin) (0) +#define OUT(pin) (1<<(2*(pin))) +#define AF(pin) (2<<(2*(pin))) +#define ANALOG(pin) (3<<(2*(pin))) + +#define CLEAR(pin) (~(3<<(2*(pin)))) + +#define AFRL(pin, val) ((val) << ((pin)*4)) +#define AFRH(pin, val) ((val) << (((pin)-8)*4)) + +#endif __IOMACROS_H__ diff --git a/center_fw/include/mpu_armv7.h b/center_fw/include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/center_fw/include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/center_fw/include/stm32_irqs.h b/center_fw/include/stm32_irqs.h new file mode 100644 index 0000000..86d1312 --- /dev/null +++ b/center_fw/include/stm32_irqs.h @@ -0,0 +1,54 @@ +/* AUTOGENERATED FILE! DO NOT MODIFY! */ +/* Generated 2023-07-10 20:34:05.404513 from startup.s by gen_isr_header.py */ + +void _estack(void); /* 0 */ +void Reset_Handler(void); /* 1 */ +void NMI_Handler(void); /* 2 */ +void HardFault_Handler(void); /* 3 */ +/* IRQ 4 is undefined for this part. */ +/* IRQ 5 is undefined for this part. */ +/* IRQ 6 is undefined for this part. */ +/* IRQ 7 is undefined for this part. */ +/* IRQ 8 is undefined for this part. */ +/* IRQ 9 is undefined for this part. */ +/* IRQ 10 is undefined for this part. */ +void SVC_Handler(void); /* 11 */ +/* IRQ 12 is undefined for this part. */ +/* IRQ 13 is undefined for this part. */ +void PendSV_Handler(void); /* 14 */ +void SysTick_Handler(void); /* 15 */ +void WWDG_IRQHandler(void); /* 16 */ +/* IRQ 17 is undefined for this part. */ +void RTC_TAMP_IRQHandler(void); /* 18 */ +void FLASH_IRQHandler(void); /* 19 */ +void RCC_IRQHandler(void); /* 20 */ +void EXTI0_1_IRQHandler(void); /* 21 */ +void EXTI2_3_IRQHandler(void); /* 22 */ +void EXTI4_15_IRQHandler(void); /* 23 */ +/* IRQ 24 is undefined for this part. */ +void DMA1_Channel1_IRQHandler(void); /* 25 */ +void DMA1_Channel2_3_IRQHandler(void); /* 26 */ +void DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler(void); /* 27 */ +void ADC1_IRQHandler(void); /* 28 */ +void TIM1_BRK_UP_TRG_COM_IRQHandler(void); /* 29 */ +void TIM1_CC_IRQHandler(void); /* 30 */ +/* IRQ 31 is undefined for this part. */ +void TIM3_IRQHandler(void); /* 32 */ +void TIM6_IRQHandler(void); /* 33 */ +void TIM7_IRQHandler(void); /* 34 */ +void TIM14_IRQHandler(void); /* 35 */ +void TIM15_IRQHandler(void); /* 36 */ +void TIM16_IRQHandler(void); /* 37 */ +void TIM17_IRQHandler(void); /* 38 */ +void I2C1_IRQHandler(void); /* 39 */ +void I2C2_IRQHandler(void); /* 40 */ +void SPI1_IRQHandler(void); /* 41 */ +void SPI2_IRQHandler(void); /* 42 */ +void USART1_IRQHandler(void); /* 43 */ +void USART2_IRQHandler(void); /* 44 */ +void USART3_4_IRQHandler(void); /* 45 */ + +#define NUM_IRQs 46 +extern uint32_t g_pfnVectors[NUM_IRQs]; +#define isr_vector g_pfnVectors + diff --git a/center_fw/include/stm32g030xx.h b/center_fw/include/stm32g030xx.h new file mode 100644 index 0000000..af20715 --- /dev/null +++ b/center_fw/include/stm32g030xx.h @@ -0,0 +1,7439 @@ +/** + ****************************************************************************** + * @file stm32g030xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32g030xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g030xx + * @{ + */ + +#ifndef STM32G030xx_H +#define STM32G030xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g030xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include <stdint.h> + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + + + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x24--0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x34--0x38 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ +#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ + +#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR1_LT1 ADC_AWD1TR_LT1 +#define ADC_TR1_LT1_0 ADC_AWD1TR_LT1_0 +#define ADC_TR1_LT1_1 ADC_AWD1TR_LT1_1 +#define ADC_TR1_LT1_2 ADC_AWD1TR_LT1_2 +#define ADC_TR1_LT1_3 ADC_AWD1TR_LT1_3 +#define ADC_TR1_LT1_4 ADC_AWD1TR_LT1_4 +#define ADC_TR1_LT1_5 ADC_AWD1TR_LT1_5 +#define ADC_TR1_LT1_6 ADC_AWD1TR_LT1_6 +#define ADC_TR1_LT1_7 ADC_AWD1TR_LT1_7 +#define ADC_TR1_LT1_8 ADC_AWD1TR_LT1_8 +#define ADC_TR1_LT1_9 ADC_AWD1TR_LT1_9 +#define ADC_TR1_LT1_10 ADC_AWD1TR_LT1_10 +#define ADC_TR1_LT1_11 ADC_AWD1TR_LT1_11 + +#define ADC_TR1_HT1 ADC_AWD1TR_HT1 +#define ADC_TR1_HT1_0 ADC_AWD1TR_HT1_0 +#define ADC_TR1_HT1_1 ADC_AWD1TR_HT1_1 +#define ADC_TR1_HT1_2 ADC_AWD1TR_HT1_2 +#define ADC_TR1_HT1_3 ADC_AWD1TR_HT1_3 +#define ADC_TR1_HT1_4 ADC_AWD1TR_HT1_4 +#define ADC_TR1_HT1_5 ADC_AWD1TR_HT1_5 +#define ADC_TR1_HT1_6 ADC_AWD1TR_HT1_6 +#define ADC_TR1_HT1_7 ADC_AWD1TR_HT1_7 +#define ADC_TR1_HT1_8 ADC_AWD1TR_HT1_8 +#define ADC_TR1_HT1_9 ADC_AWD1TR_HT1_9 +#define ADC_TR1_HT1_10 ADC_AWD1TR_HT1_10 +#define ADC_TR1_HT1_11 ADC_AWD1TR_HT1_11 + +/******************** Bit definition for ADC_AWD2TR register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR2_LT2 ADC_AWD2TR_LT2 +#define ADC_TR2_LT2_0 ADC_AWD2TR_LT2_0 +#define ADC_TR2_LT2_1 ADC_AWD2TR_LT2_1 +#define ADC_TR2_LT2_2 ADC_AWD2TR_LT2_2 +#define ADC_TR2_LT2_3 ADC_AWD2TR_LT2_3 +#define ADC_TR2_LT2_4 ADC_AWD2TR_LT2_4 +#define ADC_TR2_LT2_5 ADC_AWD2TR_LT2_5 +#define ADC_TR2_LT2_6 ADC_AWD2TR_LT2_6 +#define ADC_TR2_LT2_7 ADC_AWD2TR_LT2_7 +#define ADC_TR2_LT2_8 ADC_AWD2TR_LT2_8 +#define ADC_TR2_LT2_9 ADC_AWD2TR_LT2_9 +#define ADC_TR2_LT2_10 ADC_AWD2TR_LT2_10 +#define ADC_TR2_LT2_11 ADC_AWD2TR_LT2_11 + +#define ADC_TR2_HT2 ADC_AWD2TR_HT2 +#define ADC_TR2_HT2_0 ADC_AWD2TR_HT2_0 +#define ADC_TR2_HT2_1 ADC_AWD2TR_HT2_1 +#define ADC_TR2_HT2_2 ADC_AWD2TR_HT2_2 +#define ADC_TR2_HT2_3 ADC_AWD2TR_HT2_3 +#define ADC_TR2_HT2_4 ADC_AWD2TR_HT2_4 +#define ADC_TR2_HT2_5 ADC_AWD2TR_HT2_5 +#define ADC_TR2_HT2_6 ADC_AWD2TR_HT2_6 +#define ADC_TR2_HT2_7 ADC_AWD2TR_HT2_7 +#define ADC_TR2_HT2_8 ADC_AWD2TR_HT2_8 +#define ADC_TR2_HT2_9 ADC_AWD2TR_HT2_9 +#define ADC_TR2_HT2_10 ADC_AWD2TR_HT2_10 +#define ADC_TR2_HT2_11 ADC_AWD2TR_HT2_11 + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/* Legacy definitions */ +#define ADC_TR3_LT3 ADC_AWD3TR_LT3 +#define ADC_TR3_LT3_0 ADC_AWD3TR_LT3_0 +#define ADC_TR3_LT3_1 ADC_AWD3TR_LT3_1 +#define ADC_TR3_LT3_2 ADC_AWD3TR_LT3_2 +#define ADC_TR3_LT3_3 ADC_AWD3TR_LT3_3 +#define ADC_TR3_LT3_4 ADC_AWD3TR_LT3_4 +#define ADC_TR3_LT3_5 ADC_AWD3TR_LT3_5 +#define ADC_TR3_LT3_6 ADC_AWD3TR_LT3_6 +#define ADC_TR3_LT3_7 ADC_AWD3TR_LT3_7 +#define ADC_TR3_LT3_8 ADC_AWD3TR_LT3_8 +#define ADC_TR3_LT3_9 ADC_AWD3TR_LT3_9 +#define ADC_TR3_LT3_10 ADC_AWD3TR_LT3_10 +#define ADC_TR3_LT3_11 ADC_AWD3TR_LT3_11 + +#define ADC_TR3_HT3 ADC_AWD3TR_HT3 +#define ADC_TR3_HT3_0 ADC_AWD3TR_HT3_0 +#define ADC_TR3_HT3_1 ADC_AWD3TR_HT3_1 +#define ADC_TR3_HT3_2 ADC_AWD3TR_HT3_2 +#define ADC_TR3_HT3_3 ADC_AWD3TR_HT3_3 +#define ADC_TR3_HT3_4 ADC_AWD3TR_HT3_4 +#define ADC_TR3_HT3_5 ADC_AWD3TR_HT3_5 +#define ADC_TR3_HT3_6 ADC_AWD3TR_HT3_6 +#define ADC_TR3_HT3_7 ADC_AWD3TR_HT3_7 +#define ADC_TR3_HT3_8 ADC_AWD3TR_HT3_8 +#define ADC_TR3_HT3_9 ADC_AWD3TR_HT3_9 +#define ADC_TR3_HT3_10 ADC_AWD3TR_HT3_10 +#define ADC_TR3_HT3_11 ADC_AWD3TR_HT3_11 + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x82A8FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/* Note: No specific macro feature on this device */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU_Pos (2U) +#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ +#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_WINR_WIN_Pos (0U) +#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ +#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/* Note: No specific macro feature on this device */ + +/******************** Bit definition for PWR_CR1 register ********************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_FPD_STOP_Pos (3U) +#define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */ +#define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */ +#define PWR_CR1_FPD_LPRUN_Pos (4U) +#define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos) /*!< 0x00000010 */ +#define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk /*!< Flash power down mode during run */ +#define PWR_CR1_FPD_LPSLP_Pos (5U) +#define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos) /*!< 0x00000020 */ +#define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk /*!< Flash power down mode during sleep */ +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */ +#define PWR_CR1_VOS_Pos (9U) +#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ +#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling */ +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 0 */ +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 1 */ +#define PWR_CR1_LPR_Pos (14U) +#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ +#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */ + + +/******************** Bit definition for PWR_CR3 register ********************/ +#define PWR_CR3_EWUP_Pos (0U) +#define PWR_CR3_EWUP_Msk (0x2BUL << PWR_CR3_EWUP_Pos) /*!< 0x0000002B */ +#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all Wake-Up Pins */ +#define PWR_CR3_EWUP1_Pos (0U) +#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ +#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable WKUP pin 1 */ +#define PWR_CR3_EWUP2_Pos (1U) +#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ +#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CR3_EWUP4_Pos (3U) +#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ +#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable WKUP pin 4 */ +#define PWR_CR3_EWUP6_Pos (5U) +#define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */ +#define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable WKUP pin 6 */ +#define PWR_CR3_APC_Pos (10U) +#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ +#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */ +#define PWR_CR3_EIWUL_Pos (15U) +#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */ +#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */ + +/******************** Bit definition for PWR_CR4 register ********************/ +#define PWR_CR4_WP_Pos (0U) +#define PWR_CR4_WP_Msk (0x2BUL << PWR_CR4_WP_Pos) /*!< 0x0000002B */ +#define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Pin polarity */ +#define PWR_CR4_WP1_Pos (0U) +#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ +#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */ +#define PWR_CR4_WP2_Pos (1U) +#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ +#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */ +#define PWR_CR4_WP4_Pos (3U) +#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ +#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */ +#define PWR_CR4_WP6_Pos (5U) +#define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */ +#define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Pin 6 polarity */ +#define PWR_CR4_VBE_Pos (8U) +#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */ +#define PWR_CR4_VBRS_Pos (9U) +#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_WUF_Pos (0U) +#define PWR_SR1_WUF_Msk (0x2BUL << PWR_SR1_WUF_Pos) /*!< 0x0000002B */ +#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */ +#define PWR_SR1_WUF1_Pos (0U) +#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */ +#define PWR_SR1_WUF2_Pos (1U) +#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */ +#define PWR_SR1_WUF4_Pos (3U) +#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */ +#define PWR_SR1_WUF6_Pos (5U) +#define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */ +#define PWR_SR1_SBF_Pos (8U) +#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */ +#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */ +#define PWR_SR1_WUFI_Pos (15U) +#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ +#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */ + +/******************** Bit definition for PWR_SR2 register ********************/ +#define PWR_SR2_FLASH_RDY_Pos (7U) +#define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */ +#define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */ +#define PWR_SR2_REGLPS_Pos (8U) +#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ +#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Regulator Low Power started */ +#define PWR_SR2_REGLPF_Pos (9U) +#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ +#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */ +#define PWR_SR2_VOSF_Pos (10U) +#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ +#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */ + +/******************** Bit definition for PWR_SCR register ********************/ +#define PWR_SCR_CWUF_Pos (0U) +#define PWR_SCR_CWUF_Msk (0x2BUL << PWR_SCR_CWUF_Pos) /*!< 0x0000002B */ +#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */ +#define PWR_SCR_CWUF1_Pos (0U) +#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ +#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */ +#define PWR_SCR_CWUF2_Pos (1U) +#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */ +#define PWR_SCR_CWUF4_Pos (3U) +#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */ +#define PWR_SCR_CWUF6_Pos (5U) +#define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */ +#define PWR_SCR_CSBF_Pos (8U) +#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */ +#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */ + +/******************** Bit definition for PWR_PUCRA register *****************/ +#define PWR_PUCRA_PU0_Pos (0U) +#define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */ +#define PWR_PUCRA_PU1_Pos (1U) +#define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */ +#define PWR_PUCRA_PU2_Pos (2U) +#define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */ +#define PWR_PUCRA_PU3_Pos (3U) +#define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */ +#define PWR_PUCRA_PU4_Pos (4U) +#define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */ +#define PWR_PUCRA_PU5_Pos (5U) +#define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */ +#define PWR_PUCRA_PU6_Pos (6U) +#define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */ +#define PWR_PUCRA_PU7_Pos (7U) +#define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */ +#define PWR_PUCRA_PU8_Pos (8U) +#define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */ +#define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */ +#define PWR_PUCRA_PU9_Pos (9U) +#define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */ +#define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */ +#define PWR_PUCRA_PU10_Pos (10U) +#define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */ +#define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */ +#define PWR_PUCRA_PU11_Pos (11U) +#define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */ +#define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */ +#define PWR_PUCRA_PU12_Pos (12U) +#define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */ +#define PWR_PUCRA_PU13_Pos (13U) +#define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */ +#define PWR_PUCRA_PU14_Pos (14U) +#define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */ +#define PWR_PUCRA_PU15_Pos (15U) +#define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRA register *****************/ +#define PWR_PDCRA_PD0_Pos (0U) +#define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */ +#define PWR_PDCRA_PD1_Pos (1U) +#define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */ +#define PWR_PDCRA_PD2_Pos (2U) +#define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */ +#define PWR_PDCRA_PD3_Pos (3U) +#define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */ +#define PWR_PDCRA_PD4_Pos (4U) +#define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */ +#define PWR_PDCRA_PD5_Pos (5U) +#define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */ +#define PWR_PDCRA_PD6_Pos (6U) +#define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */ +#define PWR_PDCRA_PD7_Pos (7U) +#define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */ +#define PWR_PDCRA_PD8_Pos (8U) +#define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */ +#define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */ +#define PWR_PDCRA_PD9_Pos (9U) +#define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */ +#define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */ +#define PWR_PDCRA_PD10_Pos (10U) +#define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */ +#define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */ +#define PWR_PDCRA_PD11_Pos (11U) +#define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */ +#define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */ +#define PWR_PDCRA_PD12_Pos (12U) +#define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */ +#define PWR_PDCRA_PD13_Pos (13U) +#define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */ +#define PWR_PDCRA_PD14_Pos (14U) +#define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */ +#define PWR_PDCRA_PD15_Pos (15U) +#define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRB register *****************/ +#define PWR_PUCRB_PU0_Pos (0U) +#define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */ +#define PWR_PUCRB_PU1_Pos (1U) +#define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */ +#define PWR_PUCRB_PU2_Pos (2U) +#define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */ +#define PWR_PUCRB_PU3_Pos (3U) +#define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */ +#define PWR_PUCRB_PU4_Pos (4U) +#define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */ +#define PWR_PUCRB_PU5_Pos (5U) +#define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */ +#define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */ +#define PWR_PUCRB_PU6_Pos (6U) +#define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */ +#define PWR_PUCRB_PU7_Pos (7U) +#define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */ +#define PWR_PUCRB_PU8_Pos (8U) +#define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */ +#define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */ +#define PWR_PUCRB_PU9_Pos (9U) +#define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */ +#define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */ +#define PWR_PUCRB_PU10_Pos (10U) +#define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */ +#define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */ +#define PWR_PUCRB_PU11_Pos (11U) +#define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */ +#define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */ +#define PWR_PUCRB_PU12_Pos (12U) +#define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */ +#define PWR_PUCRB_PU13_Pos (13U) +#define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */ +#define PWR_PUCRB_PU14_Pos (14U) +#define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */ +#define PWR_PUCRB_PU15_Pos (15U) +#define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRB register *****************/ +#define PWR_PDCRB_PD0_Pos (0U) +#define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */ +#define PWR_PDCRB_PD1_Pos (1U) +#define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */ +#define PWR_PDCRB_PD2_Pos (2U) +#define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */ +#define PWR_PDCRB_PD3_Pos (3U) +#define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */ +#define PWR_PDCRB_PD4_Pos (4U) +#define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */ +#define PWR_PDCRB_PD5_Pos (5U) +#define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */ +#define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */ +#define PWR_PDCRB_PD6_Pos (6U) +#define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */ +#define PWR_PDCRB_PD7_Pos (7U) +#define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */ +#define PWR_PDCRB_PD8_Pos (8U) +#define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */ +#define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */ +#define PWR_PDCRB_PD9_Pos (9U) +#define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */ +#define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */ +#define PWR_PDCRB_PD10_Pos (10U) +#define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */ +#define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */ +#define PWR_PDCRB_PD11_Pos (11U) +#define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */ +#define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */ +#define PWR_PDCRB_PD12_Pos (12U) +#define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */ +#define PWR_PDCRB_PD13_Pos (13U) +#define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */ +#define PWR_PDCRB_PD14_Pos (14U) +#define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */ +#define PWR_PDCRB_PD15_Pos (15U) +#define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRC register *****************/ +#define PWR_PUCRC_PU6_Pos (6U) +#define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */ +#define PWR_PUCRC_PU7_Pos (7U) +#define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */ +#define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */ +#define PWR_PUCRC_PU13_Pos (13U) +#define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */ +#define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */ +#define PWR_PUCRC_PU14_Pos (14U) +#define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */ +#define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */ +#define PWR_PUCRC_PU15_Pos (15U) +#define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */ +#define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRC register *****************/ +#define PWR_PDCRC_PD6_Pos (6U) +#define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */ +#define PWR_PDCRC_PD7_Pos (7U) +#define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */ +#define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */ +#define PWR_PDCRC_PD13_Pos (13U) +#define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */ +#define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */ +#define PWR_PDCRC_PD14_Pos (14U) +#define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */ +#define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */ +#define PWR_PDCRC_PD15_Pos (15U) +#define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */ +#define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRD register *****************/ +#define PWR_PUCRD_PU0_Pos (0U) +#define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */ +#define PWR_PUCRD_PU1_Pos (1U) +#define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */ +#define PWR_PUCRD_PU2_Pos (2U) +#define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */ +#define PWR_PUCRD_PU3_Pos (3U) +#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */ +#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRD register *****************/ +#define PWR_PDCRD_PD0_Pos (0U) +#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */ +#define PWR_PDCRD_PD1_Pos (1U) +#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */ +#define PWR_PDCRD_PD2_Pos (2U) +#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */ +#define PWR_PDCRD_PD3_Pos (3U) +#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */ + +/******************** Bit definition for PWR_PUCRF register *****************/ +#define PWR_PUCRF_PU0_Pos (0U) +#define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */ +#define PWR_PUCRF_PU1_Pos (1U) +#define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */ +#define PWR_PUCRF_PU2_Pos (2U) +#define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */ +#define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */ + +/******************** Bit definition for PWR_PDCRF register *****************/ +#define PWR_PDCRF_PD0_Pos (0U) +#define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */ +#define PWR_PDCRF_PD1_Pos (1U) +#define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */ +#define PWR_PDCRF_PD2_Pos (2U) +#define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions (not present on all devices in the STM32G0 series) +*/ + +/******************** Bit definition for RCC_CR register *****************/ +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (11U) +#define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ + +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ + +/******************** Bit definition for RCC_ICSCR register ***************/ +/*!< HSICAL configuration */ +#define RCC_ICSCR_HSICAL_Pos (0U) +#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ +#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */ + +/*!< HSITRIM configuration */ +#define RCC_ICSCR_HSITRIM_Pos (8U) +#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */ +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */ +#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */ +#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CFGR register ***************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (8U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */ + +/*!< PPRE configuration */ +#define RCC_CFGR_PPRE_Pos (12U) +#define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */ +#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */ +#define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */ +#define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */ + + +/*!< MCOSEL configuration */ +#define RCC_CFGR_MCOSEL_Pos (24U) +#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */ +#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ + +/*!< MCO Prescaler configuration */ +#define RCC_CFGR_MCOPRE_Pos (28U) +#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */ +#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLLSRC_Pos (0U) +#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk +#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */ + +#define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL) /*!< No clock sent to PLL */ +#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U) +#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI source clock selected */ +#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U) +#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */ +#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE source clock selected */ + +#define RCC_PLLCFGR_PLLM_Pos (4U) +#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */ +#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk +#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ +#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ + +#define RCC_PLLCFGR_PLLN_Pos (8U) +#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */ +#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk +#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ +#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ +#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ + +#define RCC_PLLCFGR_PLLPEN_Pos (16U) +#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk + +#define RCC_PLLCFGR_PLLP_Pos (17U) +#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */ +#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk +#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */ + + +#define RCC_PLLCFGR_PLLREN_Pos (28U) +#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk + +#define RCC_PLLCFGR_PLLR_Pos (29U) +#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */ +#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk +#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLLRDYIE_Pos (5U) +#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLLRDYF_Pos (5U) +#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk +#define RCC_CIFR_CSSF_Pos (8U) +#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLLRDYC_Pos (5U) +#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk +#define RCC_CICR_CSSC_Pos (8U) +#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk + +/******************** Bit definition for RCC_IOPRSTR register ****************/ +#define RCC_IOPRSTR_GPIOARST_Pos (0U) +#define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk +#define RCC_IOPRSTR_GPIOBRST_Pos (1U) +#define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk +#define RCC_IOPRSTR_GPIOCRST_Pos (2U) +#define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk +#define RCC_IOPRSTR_GPIODRST_Pos (3U) +#define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk +#define RCC_IOPRSTR_GPIOFRST_Pos (5U) +#define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk + +/******************** Bit definition for RCC_AHBRSTR register ***************/ +#define RCC_AHBRSTR_DMA1RST_Pos (0U) +#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk +#define RCC_AHBRSTR_FLASHRST_Pos (8U) +#define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */ +#define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk +#define RCC_AHBRSTR_CRCRST_Pos (12U) +#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk + +/******************** Bit definition for RCC_APBRSTR1 register **************/ +#define RCC_APBRSTR1_TIM3RST_Pos (1U) +#define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk +#define RCC_APBRSTR1_SPI2RST_Pos (14U) +#define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk +#define RCC_APBRSTR1_USART2RST_Pos (17U) +#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk +#define RCC_APBRSTR1_I2C1RST_Pos (21U) +#define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk +#define RCC_APBRSTR1_I2C2RST_Pos (22U) +#define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk +#define RCC_APBRSTR1_DBGRST_Pos (27U) +#define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */ +#define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk +#define RCC_APBRSTR1_PWRRST_Pos (28U) +#define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk + +/******************** Bit definition for RCC_APBRSTR2 register **************/ +#define RCC_APBRSTR2_SYSCFGRST_Pos (0U) +#define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */ +#define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk +#define RCC_APBRSTR2_TIM1RST_Pos (11U) +#define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk +#define RCC_APBRSTR2_SPI1RST_Pos (12U) +#define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk +#define RCC_APBRSTR2_USART1RST_Pos (14U) +#define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk +#define RCC_APBRSTR2_TIM14RST_Pos (15U) +#define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */ +#define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk +#define RCC_APBRSTR2_TIM16RST_Pos (17U) +#define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk +#define RCC_APBRSTR2_TIM17RST_Pos (18U) +#define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk +#define RCC_APBRSTR2_ADCRST_Pos (20U) +#define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */ +#define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk + +/******************** Bit definition for RCC_IOPENR register ****************/ +#define RCC_IOPENR_GPIOAEN_Pos (0U) +#define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk +#define RCC_IOPENR_GPIOBEN_Pos (1U) +#define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk +#define RCC_IOPENR_GPIOCEN_Pos (2U) +#define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk +#define RCC_IOPENR_GPIODEN_Pos (3U) +#define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk +#define RCC_IOPENR_GPIOFEN_Pos (5U) +#define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk + +/******************** Bit definition for RCC_AHBENR register ****************/ +#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk +#define RCC_AHBENR_FLASHEN_Pos (8U) +#define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk +#define RCC_AHBENR_CRCEN_Pos (12U) +#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk + +/******************** Bit definition for RCC_APBENR1 register ***************/ +#define RCC_APBENR1_TIM3EN_Pos (1U) +#define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk +#define RCC_APBENR1_RTCAPBEN_Pos (10U) +#define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ +#define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk +#define RCC_APBENR1_WWDGEN_Pos (11U) +#define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk +#define RCC_APBENR1_SPI2EN_Pos (14U) +#define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk +#define RCC_APBENR1_USART2EN_Pos (17U) +#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk +#define RCC_APBENR1_I2C1EN_Pos (21U) +#define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk +#define RCC_APBENR1_I2C2EN_Pos (22U) +#define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk +#define RCC_APBENR1_DBGEN_Pos (27U) +#define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */ +#define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk +#define RCC_APBENR1_PWREN_Pos (28U) +#define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk + +/******************** Bit definition for RCC_APBENR2 register **************/ +#define RCC_APBENR2_SYSCFGEN_Pos (0U) +#define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */ +#define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk +#define RCC_APBENR2_TIM1EN_Pos (11U) +#define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk +#define RCC_APBENR2_SPI1EN_Pos (12U) +#define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk +#define RCC_APBENR2_USART1EN_Pos (14U) +#define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk +#define RCC_APBENR2_TIM14EN_Pos (15U) +#define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */ +#define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk +#define RCC_APBENR2_TIM16EN_Pos (17U) +#define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk +#define RCC_APBENR2_TIM17EN_Pos (18U) +#define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk +#define RCC_APBENR2_ADCEN_Pos (20U) +#define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */ +#define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk + +/******************** Bit definition for RCC_IOPSMENR register *************/ +#define RCC_IOPSMENR_GPIOASMEN_Pos (0U) +#define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk +#define RCC_IOPSMENR_GPIOBSMEN_Pos (1U) +#define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk +#define RCC_IOPSMENR_GPIOCSMEN_Pos (2U) +#define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk +#define RCC_IOPSMENR_GPIODSMEN_Pos (3U) +#define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */ +#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk +#define RCC_IOPSMENR_GPIOFSMEN_Pos (5U) +#define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */ +#define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk + +/******************** Bit definition for RCC_AHBSMENR register *************/ +#define RCC_AHBSMENR_DMA1SMEN_Pos (0U) +#define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk +#define RCC_AHBSMENR_FLASHSMEN_Pos (8U) +#define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk +#define RCC_AHBSMENR_SRAMSMEN_Pos (9U) +#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ +#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk +#define RCC_AHBSMENR_CRCSMEN_Pos (12U) +#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk + +/******************** Bit definition for RCC_APBSMENR1 register *************/ +#define RCC_APBSMENR1_TIM3SMEN_Pos (1U) +#define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk +#define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U) +#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ +#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk +#define RCC_APBSMENR1_WWDGSMEN_Pos (11U) +#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk +#define RCC_APBSMENR1_SPI2SMEN_Pos (14U) +#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk +#define RCC_APBSMENR1_USART2SMEN_Pos (17U) +#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk +#define RCC_APBSMENR1_I2C1SMEN_Pos (21U) +#define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk +#define RCC_APBSMENR1_I2C2SMEN_Pos (22U) +#define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */ +#define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk +#define RCC_APBSMENR1_DBGSMEN_Pos (27U) +#define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */ +#define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk +#define RCC_APBSMENR1_PWRSMEN_Pos (28U) +#define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */ +#define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk + +/******************** Bit definition for RCC_APBSMENR2 register *************/ +#define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U) +#define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */ +#define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk +#define RCC_APBSMENR2_TIM1SMEN_Pos (11U) +#define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk +#define RCC_APBSMENR2_SPI1SMEN_Pos (12U) +#define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk +#define RCC_APBSMENR2_USART1SMEN_Pos (14U) +#define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk +#define RCC_APBSMENR2_TIM14SMEN_Pos (15U) +#define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */ +#define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk +#define RCC_APBSMENR2_TIM16SMEN_Pos (17U) +#define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk +#define RCC_APBSMENR2_TIM17SMEN_Pos (18U) +#define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk +#define RCC_APBSMENR2_ADCSMEN_Pos (20U) +#define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */ +#define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk + +/******************** Bit definition for RCC_CCIPR register ******************/ +#define RCC_CCIPR_USART1SEL_Pos (0U) +#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk +#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ + + + + +#define RCC_CCIPR_I2C1SEL_Pos (12U) +#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk +#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR_I2S1SEL_Pos (14U) +#define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk +#define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */ + + + + +#define RCC_CCIPR_ADCSEL_Pos (30U) +#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */ +#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk +#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk + +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk + +#define RCC_BDCR_LSCOEN_Pos (24U) +#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk +#define RCC_BDCR_LSCOSEL_Pos (25U) +#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_PWRRSTF_Pos (27U) +#define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define RTC_WAKEUP_SUPPORT +#define RTC_BACKUP_SUPPORT + +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wakeup timer write flag > */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 series) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ + +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ + +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ +#define SPI_CR1_CRCL_Pos (11U) +#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ +#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_NSSP_Pos (3U) +#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ +#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ +#define SPI_CR2_FRF_Pos (4U) +#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ +#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ +#define SPI_CR2_DS_Pos (8U) +#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ +#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ +#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ +#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ +#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ +#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ +#define SPI_CR2_FRXTH_Pos (12U) +#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ +#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ +#define SPI_CR2_LDMARX_Pos (13U) +#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ +#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ +#define SPI_CR2_LDMATX_Pos (14U) +#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ +#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ +#define SPI_SR_FRE_Pos (8U) +#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ +#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ +#define SPI_SR_FRLVL_Pos (9U) +#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ +#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ +#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ +#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ +#define SPI_SR_FTLVL_Pos (11U) +#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ +#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ +#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ +#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN_Pos (0U) +#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ +#define SPI_I2SCFGR_DATLEN_Pos (1U) +#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ +#define SPI_I2SCFGR_CKPOL_Pos (3U) +#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ +#define SPI_I2SCFGR_I2SSTD_Pos (4U) +#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ +#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ +#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ +#define SPI_I2SCFGR_PCMSYNC_Pos (7U) +#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ +#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ +#define SPI_I2SCFGR_I2SCFG_Pos (8U) +#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ +#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ +#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ +#define SPI_I2SCFGR_I2SE_Pos (10U) +#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ +#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ +#define SPI_I2SCFGR_I2SMOD_Pos (11U) +#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ +#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ +#define SPI_I2SCFGR_ASTRTEN_Pos (12U) +#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ +#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV_Pos (0U) +#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ +#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ +#define SPI_I2SPR_ODD_Pos (8U) +#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE_Pos (9U) +#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* SYSCFG */ +/* */ +/******************************************************************************/ +#define SYSCFG_CDEN_SUPPORT +/***************** Bit definition for SYSCFG_CFGR1 register ****************/ +#define SYSCFG_CFGR1_MEM_MODE_Pos (0U) +#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ +#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ +#define SYSCFG_CFGR1_PA11_RMP_Pos (3U) +#define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */ +#define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */ +#define SYSCFG_CFGR1_PA12_RMP_Pos (4U) +#define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */ +#define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */ +#define SYSCFG_CFGR1_IR_POL_Pos (5U) +#define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */ +#define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */ +#define SYSCFG_CFGR1_IR_MOD_Pos (6U) +#define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */ +#define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */ +#define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */ +#define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */ +#define SYSCFG_CFGR1_BOOSTEN_Pos (8U) +#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ +#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) +#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) +#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) +#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) +#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ +#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) +#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ +#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ +#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) +#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ +#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< Enable I2C2 Fast mode plus */ +#define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U) +#define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */ +#define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */ +#define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U) +#define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */ +#define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */ + +/****************** Bit definition for SYSCFG_CFGR2 register ****************/ +#define SYSCFG_CFGR2_CLL_Pos (0U) +#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ +#define SYSCFG_CFGR2_SPL_Pos (1U) +#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ +#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ +#define SYSCFG_CFGR2_ECCL_Pos (3U) +#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECCL */ +#define SYSCFG_CFGR2_SPF_Pos (8U) +#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ +#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity error flag */ +#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ + +#define SYSCFG_CFGR2_PA1_CDEN_Pos (16U) +#define SYSCFG_CFGR2_PA1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos) /* 0x00010000 */ +#define SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN_Msk /*!< PA[1] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PA3_CDEN_Pos (17U) +#define SYSCFG_CFGR2_PA3_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos) /* 0x00020000 */ +#define SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN_Msk /*!< PA[3] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PA5_CDEN_Pos (18U) +#define SYSCFG_CFGR2_PA5_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos) /* 0x00040000 */ +#define SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN_Msk /*!< PA[5] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PA6_CDEN_Pos (19U) +#define SYSCFG_CFGR2_PA6_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos) /* 0x00080000 */ +#define SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN_Msk /*!< PA[6] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PA13_CDEN_Pos (20U) +#define SYSCFG_CFGR2_PA13_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos) /* 0x00100000 */ +#define SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN_Msk /*!< PA[13] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PB0_CDEN_Pos (21U) +#define SYSCFG_CFGR2_PB0_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos) /* 0x00200000 */ +#define SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN_Msk /*!< PB[0] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PB1_CDEN_Pos (22U) +#define SYSCFG_CFGR2_PB1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos) /* 0x00400000 */ +#define SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN_Msk /*!< PB[1] Clamping Diode Enable */ +#define SYSCFG_CFGR2_PB2_CDEN_Pos (23U) +#define SYSCFG_CFGR2_PB2_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos) /* 0x00800000 */ +#define SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN_Msk /*!< PB[2] Clamping Diode Enable */ +/***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/ +#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U) +#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ +#define TIM_CR1_UDIS_Pos (1U) +#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ +#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ +#define TIM_CR1_URS_Pos (2U) +#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ +#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ +#define TIM_CR1_OPM_Pos (3U) +#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ +#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ +#define TIM_CR1_DIR_Pos (4U) +#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ +#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ + +#define TIM_CR1_CMS_Pos (5U) +#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ +#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ +#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ + +#define TIM_CR1_ARPE_Pos (7U) +#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ +#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ + +#define TIM_CR1_CKD_Pos (8U) +#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ +#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ +#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ + +#define TIM_CR1_UIFREMAP_Pos (11U) +#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ +#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ +#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ +#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ +#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS_Pos (4U) +#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ +#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ +#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ +#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ + +#define TIM_CR2_TI1S_Pos (7U) +#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ +#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ +#define TIM_CR2_OIS1_Pos (8U) +#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ +#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N_Pos (9U) +#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ +#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2_Pos (10U) +#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ +#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N_Pos (11U) +#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ +#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3_Pos (12U) +#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ +#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N_Pos (13U) +#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ +#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4_Pos (14U) +#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ +#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ +#define TIM_CR2_OIS5_Pos (16U) +#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ +#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ +#define TIM_CR2_OIS6_Pos (18U) +#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ +#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ + +#define TIM_CR2_MMS2_Pos (20U) +#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ +#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ +#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ +#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ +#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS_Pos (0U) +#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ +#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ +#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ +#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ +#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ + +#define TIM_SMCR_OCCS_Pos (3U) +#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ +#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ + +#define TIM_SMCR_TS_Pos (4U) +#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ +#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ +#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ +#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ +#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */ +#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */ + +#define TIM_SMCR_MSM_Pos (7U) +#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ +#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ + +#define TIM_SMCR_ETF_Pos (8U) +#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ +#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ +#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ +#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ +#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ + +#define TIM_SMCR_ETPS_Pos (12U) +#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ +#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ +#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ + +#define TIM_SMCR_ECE_Pos (14U) +#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ +#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ +#define TIM_SMCR_ETP_Pos (15U) +#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ +#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE_Pos (0U) +#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ +#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ +#define TIM_DIER_CC1IE_Pos (1U) +#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ +#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE_Pos (2U) +#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ +#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE_Pos (3U) +#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ +#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE_Pos (4U) +#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ +#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE_Pos (5U) +#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ +#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ +#define TIM_DIER_TIE_Pos (6U) +#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ +#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ +#define TIM_DIER_BIE_Pos (7U) +#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ +#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ +#define TIM_DIER_UDE_Pos (8U) +#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ +#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ +#define TIM_DIER_CC1DE_Pos (9U) +#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ +#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE_Pos (10U) +#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ +#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE_Pos (11U) +#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ +#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE_Pos (12U) +#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ +#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE_Pos (13U) +#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ +#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ +#define TIM_DIER_TDE_Pos (14U) +#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ +#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF_Pos (0U) +#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ +#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ +#define TIM_SR_CC1IF_Pos (1U) +#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ +#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF_Pos (2U) +#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ +#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF_Pos (3U) +#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ +#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF_Pos (4U) +#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ +#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF_Pos (5U) +#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ +#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ +#define TIM_SR_TIF_Pos (6U) +#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ +#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ +#define TIM_SR_BIF_Pos (7U) +#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ +#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ +#define TIM_SR_B2IF_Pos (8U) +#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ +#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ +#define TIM_SR_CC1OF_Pos (9U) +#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ +#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF_Pos (10U) +#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ +#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF_Pos (11U) +#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ +#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF_Pos (12U) +#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ +#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ +#define TIM_SR_SBIF_Pos (13U) +#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ +#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ +#define TIM_SR_CC5IF_Pos (16U) +#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ +#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ +#define TIM_SR_CC6IF_Pos (17U) +#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ +#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ + + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG_Pos (0U) +#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ +#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ +#define TIM_EGR_CC1G_Pos (1U) +#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ +#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G_Pos (2U) +#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ +#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G_Pos (3U) +#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ +#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G_Pos (4U) +#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ +#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ +#define TIM_EGR_COMG_Pos (5U) +#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ +#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ +#define TIM_EGR_TG_Pos (6U) +#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ +#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ +#define TIM_EGR_BG_Pos (7U) +#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ +#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ +#define TIM_EGR_B2G_Pos (8U) +#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ +#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ + + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S_Pos (0U) +#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ +#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ +#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ + +#define TIM_CCMR1_OC1FE_Pos (2U) +#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE_Pos (3U) +#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M_Pos (4U) +#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ +#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ +#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ +#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ +#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ + +#define TIM_CCMR1_OC1CE_Pos (7U) +#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ + +#define TIM_CCMR1_CC2S_Pos (8U) +#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ +#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ +#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ + +#define TIM_CCMR1_OC2FE_Pos (10U) +#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE_Pos (11U) +#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M_Pos (12U) +#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ +#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ +#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ +#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ +#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ + +#define TIM_CCMR1_OC2CE_Pos (15U) +#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ +#define TIM_CCMR1_IC1PSC_Pos (2U) +#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ +#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ +#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ + +#define TIM_CCMR1_IC1F_Pos (4U) +#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ +#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ +#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ +#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ +#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ + +#define TIM_CCMR1_IC2PSC_Pos (10U) +#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ +#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ +#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ + +#define TIM_CCMR1_IC2F_Pos (12U) +#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ +#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ +#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ +#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ +#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S_Pos (0U) +#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ +#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ +#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ + +#define TIM_CCMR2_OC3FE_Pos (2U) +#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE_Pos (3U) +#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M_Pos (4U) +#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ +#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ +#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ +#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ +#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ + +#define TIM_CCMR2_OC3CE_Pos (7U) +#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S_Pos (8U) +#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ +#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ +#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ + +#define TIM_CCMR2_OC4FE_Pos (10U) +#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE_Pos (11U) +#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M_Pos (12U) +#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ +#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ +#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ +#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ +#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ + +#define TIM_CCMR2_OC4CE_Pos (15U) +#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ +#define TIM_CCMR2_IC3PSC_Pos (2U) +#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ +#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ +#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ + +#define TIM_CCMR2_IC3F_Pos (4U) +#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ +#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ +#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ +#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ +#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ + +#define TIM_CCMR2_IC4PSC_Pos (10U) +#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ +#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ +#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ + +#define TIM_CCMR2_IC4F_Pos (12U) +#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ +#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ +#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ +#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ +#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for TIM_CCMR3 register *******************/ +#define TIM_CCMR3_OC5FE_Pos (2U) +#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ +#define TIM_CCMR3_OC5PE_Pos (3U) +#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ + +#define TIM_CCMR3_OC5M_Pos (4U) +#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ +#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ +#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ +#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ +#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ + +#define TIM_CCMR3_OC5CE_Pos (7U) +#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ + +#define TIM_CCMR3_OC6FE_Pos (10U) +#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ +#define TIM_CCMR3_OC6PE_Pos (11U) +#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ + +#define TIM_CCMR3_OC6M_Pos (12U) +#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ +#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ +#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ +#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ +#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ +#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ + +#define TIM_CCMR3_OC6CE_Pos (15U) +#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E_Pos (0U) +#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ +#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P_Pos (1U) +#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ +#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE_Pos (2U) +#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ +#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP_Pos (3U) +#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ +#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E_Pos (4U) +#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ +#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P_Pos (5U) +#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ +#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE_Pos (6U) +#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ +#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP_Pos (7U) +#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ +#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E_Pos (8U) +#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ +#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P_Pos (9U) +#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ +#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE_Pos (10U) +#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ +#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP_Pos (11U) +#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ +#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E_Pos (12U) +#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ +#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P_Pos (13U) +#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ +#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP_Pos (15U) +#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ +#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ +#define TIM_CCER_CC5E_Pos (16U) +#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ +#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ +#define TIM_CCER_CC5P_Pos (17U) +#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ +#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ +#define TIM_CCER_CC6E_Pos (20U) +#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ +#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ +#define TIM_CCER_CC6P_Pos (21U) +#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ +#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT_Pos (0U) +#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ +#define TIM_CNT_UIFCPY_Pos (31U) +#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ +#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC_Pos (0U) +#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ +#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR_Pos (0U) +#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ +#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP_Pos (0U) +#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ +#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1_Pos (0U) +#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2_Pos (0U) +#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3_Pos (0U) +#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4_Pos (0U) +#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_CCR5 register *******************/ +#define TIM_CCR5_CCR5_Pos (0U) +#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ +#define TIM_CCR5_GC5C1_Pos (29U) +#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ +#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ +#define TIM_CCR5_GC5C2_Pos (30U) +#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ +#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ +#define TIM_CCR5_GC5C3_Pos (31U) +#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ +#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ + +/******************* Bit definition for TIM_CCR6 register *******************/ +#define TIM_CCR6_CCR6_Pos (0U) +#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG_Pos (0U) +#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ +#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ +#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ +#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ +#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ +#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ +#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ +#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ +#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ + +#define TIM_BDTR_LOCK_Pos (8U) +#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ +#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ +#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ + +#define TIM_BDTR_OSSI_Pos (10U) +#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ +#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR_Pos (11U) +#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ +#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ +#define TIM_BDTR_BKE_Pos (12U) +#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ +#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ +#define TIM_BDTR_BKP_Pos (13U) +#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ +#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ +#define TIM_BDTR_AOE_Pos (14U) +#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ +#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ +#define TIM_BDTR_MOE_Pos (15U) +#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ +#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ + +#define TIM_BDTR_BKF_Pos (16U) +#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ +#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ +#define TIM_BDTR_BK2F_Pos (20U) +#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ +#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ + +#define TIM_BDTR_BK2E_Pos (24U) +#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ +#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ +#define TIM_BDTR_BK2P_Pos (25U) +#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ +#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ + +#define TIM_BDTR_BKDSRM_Pos (26U) +#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */ +#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */ +#define TIM_BDTR_BK2DSRM_Pos (27U) +#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */ +#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */ + +#define TIM_BDTR_BKBID_Pos (28U) +#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */ +#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */ +#define TIM_BDTR_BK2BID_Pos (29U) +#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */ +#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA_Pos (0U) +#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ +#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ +#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ +#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ +#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ +#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ + +#define TIM_DCR_DBL_Pos (8U) +#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ +#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ +#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ +#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ +#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ +#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB_Pos (0U) +#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ +#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ + +/******************* Bit definition for TIM1_OR1 register *******************/ +#define TIM1_OR1_OCREF_CLR_Pos (0U) +#define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */ +#define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */ + +/******************* Bit definition for TIM1_AF1 register *******************/ +#define TIM1_AF1_BKINE_Pos (0U) +#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */ +#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */ +#define TIM1_AF1_BKCMP1E_Pos (1U) +#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ +#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ +#define TIM1_AF1_BKCMP2E_Pos (2U) +#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ +#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ +#define TIM1_AF1_BKINP_Pos (9U) +#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */ +#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ +#define TIM1_AF1_BKCMP1P_Pos (10U) +#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ +#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ +#define TIM1_AF1_BKCMP2P_Pos (11U) +#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ +#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ + +#define TIM1_AF1_ETRSEL_Pos (14U) +#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ +#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */ +#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */ +#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ +#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */ +#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ + +/******************* Bit definition for TIM1_AF2 register *******************/ +#define TIM1_AF2_BK2INE_Pos (0U) +#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */ +#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ +#define TIM1_AF2_BK2CMP1E_Pos (1U) +#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */ +#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ +#define TIM1_AF2_BK2CMP2E_Pos (2U) +#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */ +#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ +#define TIM1_AF2_BK2INP_Pos (9U) +#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */ +#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ +#define TIM1_AF2_BK2CMP1P_Pos (10U) +#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */ +#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ +#define TIM1_AF2_BK2CMP2P_Pos (11U) +#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */ +#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ + + +/******************* Bit definition for TIM3_OR1 register *******************/ +#define TIM3_OR1_OCREF_CLR_Pos (0U) +#define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */ +#define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */ + +/******************* Bit definition for TIM3_AF1 register *******************/ +#define TIM3_AF1_ETRSEL_Pos (14U) +#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ +#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */ +#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */ +#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */ +#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */ +#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */ + +/******************* Bit definition for TIM14_AF1 register *******************/ +#define TIM14_AF1_ETRSEL_Pos (14U) +#define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ +#define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM14 ETR source selection) */ +#define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00004000 */ +#define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00008000 */ +#define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00010000 */ +#define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00020000 */ + + +/******************* Bit definition for TIM16_AF1 register ******************/ +#define TIM16_AF1_BKINE_Pos (0U) +#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */ +#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */ +#define TIM16_AF1_BKCMP1E_Pos (1U) +#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ +#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ +#define TIM16_AF1_BKCMP2E_Pos (2U) +#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ +#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ +#define TIM16_AF1_BKINP_Pos (9U) +#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */ +#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ +#define TIM16_AF1_BKCMP1P_Pos (10U) +#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ +#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ +#define TIM16_AF1_BKCMP2P_Pos (11U) +#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ +#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ + +/******************* Bit definition for TIM17_AF1 register ******************/ +#define TIM17_AF1_BKINE_Pos (0U) +#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */ +#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */ +#define TIM17_AF1_BKCMP1E_Pos (1U) +#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ +#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ +#define TIM17_AF1_BKCMP2E_Pos (2U) +#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ +#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ +#define TIM17_AF1_BKINP_Pos (9U) +#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */ +#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ +#define TIM17_AF1_BKCMP1P_Pos (10U) +#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ +#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ +#define TIM17_AF1_BKCMP2P_Pos (11U) +#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ +#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ + +/******************* Bit definition for TIM_TISEL register *********************/ +#define TIM_TISEL_TI1SEL_Pos (0U) +#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ +#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/ +#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */ +#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */ +#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */ +#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */ + +#define TIM_TISEL_TI2SEL_Pos (8U) +#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */ +#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/ +#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */ +#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */ +#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */ +#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */ + +#define TIM_TISEL_TI3SEL_Pos (16U) +#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */ +#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/ +#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */ +#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */ +#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */ +#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */ + +#define TIM_TISEL_TI4SEL_Pos (24U) +#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */ +#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/ +#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */ +#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */ +#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */ +#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */ + + + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_UE_Pos (0U) +#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ +#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ +#define USART_CR1_UESM_Pos (1U) +#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ +#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ +#define USART_CR1_RE_Pos (2U) +#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ +#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ +#define USART_CR1_TE_Pos (3U) +#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ +#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE_Pos (4U) +#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ +#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U) +#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */ +#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */ +#define USART_CR1_TCIE_Pos (6U) +#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE_TXFNFIE_Pos (7U) +#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */ +#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */ +#define USART_CR1_PEIE_Pos (8U) +#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ +#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ +#define USART_CR1_PS_Pos (9U) +#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ +#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ +#define USART_CR1_PCE_Pos (10U) +#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ +#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ +#define USART_CR1_WAKE_Pos (11U) +#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ +#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ +#define USART_CR1_M_Pos (12U) +#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ +#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ +#define USART_CR1_M0_Pos (12U) +#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ +#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ +#define USART_CR1_MME_Pos (13U) +#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ +#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ +#define USART_CR1_CMIE_Pos (14U) +#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ +#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ +#define USART_CR1_OVER8_Pos (15U) +#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ +#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ +#define USART_CR1_DEDT_Pos (16U) +#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ +#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ +#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ +#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ +#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ +#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ +#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ +#define USART_CR1_DEAT_Pos (21U) +#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ +#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ +#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ +#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ +#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ +#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ +#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ +#define USART_CR1_RTOIE_Pos (26U) +#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ +#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ +#define USART_CR1_EOBIE_Pos (27U) +#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ +#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ +#define USART_CR1_M1_Pos (28U) +#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ +#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ +#define USART_CR1_FIFOEN_Pos (29U) +#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ +#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ +#define USART_CR1_TXFEIE_Pos (30U) +#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ +#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ +#define USART_CR1_RXFFIE_Pos (31U) +#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ +#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_SLVEN_Pos (0U) +#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ +#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ +#define USART_CR2_DIS_NSS_Pos (3U) +#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ +#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */ +#define USART_CR2_ADDM7_Pos (4U) +#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ +#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ +#define USART_CR2_LBDL_Pos (5U) +#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ +#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE_Pos (6U) +#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ +#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL_Pos (8U) +#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ +#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA_Pos (9U) +#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ +#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ +#define USART_CR2_CPOL_Pos (10U) +#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ +#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ +#define USART_CR2_CLKEN_Pos (11U) +#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ +#define USART_CR2_STOP_Pos (12U) +#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ +#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ +#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ +#define USART_CR2_LINEN_Pos (14U) +#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ +#define USART_CR2_SWAP_Pos (15U) +#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ +#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ +#define USART_CR2_RXINV_Pos (16U) +#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ +#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ +#define USART_CR2_TXINV_Pos (17U) +#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ +#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ +#define USART_CR2_DATAINV_Pos (18U) +#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ +#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ +#define USART_CR2_MSBFIRST_Pos (19U) +#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ +#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ +#define USART_CR2_ABREN_Pos (20U) +#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ +#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ +#define USART_CR2_ABRMODE_Pos (21U) +#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ +#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ +#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ +#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ +#define USART_CR2_RTOEN_Pos (23U) +#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ +#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ +#define USART_CR2_ADD_Pos (24U) +#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ +#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE_Pos (0U) +#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ +#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ +#define USART_CR3_IREN_Pos (1U) +#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ +#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ +#define USART_CR3_IRLP_Pos (2U) +#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ +#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL_Pos (3U) +#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ +#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ +#define USART_CR3_NACK_Pos (4U) +#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ +#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ +#define USART_CR3_SCEN_Pos (5U) +#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ +#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ +#define USART_CR3_DMAR_Pos (6U) +#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ +#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT_Pos (7U) +#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ +#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE_Pos (8U) +#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ +#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ +#define USART_CR3_CTSE_Pos (9U) +#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ +#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ +#define USART_CR3_CTSIE_Pos (10U) +#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ +#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT_Pos (11U) +#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ +#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ +#define USART_CR3_OVRDIS_Pos (12U) +#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ +#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ +#define USART_CR3_DDRE_Pos (13U) +#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ +#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ +#define USART_CR3_DEM_Pos (14U) +#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ +#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ +#define USART_CR3_DEP_Pos (15U) +#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ +#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ +#define USART_CR3_SCARCNT_Pos (17U) +#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ +#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ +#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ +#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ +#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ +#define USART_CR3_WUS_Pos (20U) +#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ +#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ +#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ +#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ +#define USART_CR3_WUFIE_Pos (22U) +#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ +#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ +#define USART_CR3_TXFTIE_Pos (23U) +#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ +#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ +#define USART_CR3_TCBGTIE_Pos (24U) +#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ +#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ +#define USART_CR3_RXFTCFG_Pos (25U) +#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ +#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ +#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ +#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ +#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ +#define USART_CR3_RXFTIE_Pos (28U) +#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ +#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ +#define USART_CR3_TXFTCFG_Pos (29U) +#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ +#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ +#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ +#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ +#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC_Pos (0U) +#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ +#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_GT_Pos (8U) +#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ +#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ + +/******************* Bit definition for USART_RTOR register *****************/ +#define USART_RTOR_RTO_Pos (0U) +#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ +#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ +#define USART_RTOR_BLEN_Pos (24U) +#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ +#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ + +/******************* Bit definition for USART_RQR register ******************/ +#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ +#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ +#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ +#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ +#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ + +/******************* Bit definition for USART_ISR register ******************/ +#define USART_ISR_PE_Pos (0U) +#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ +#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ +#define USART_ISR_FE_Pos (1U) +#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ +#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ +#define USART_ISR_NE_Pos (2U) +#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ +#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ +#define USART_ISR_ORE_Pos (3U) +#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ +#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ +#define USART_ISR_IDLE_Pos (4U) +#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ +#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ +#define USART_ISR_RXNE_RXFNE_Pos (5U) +#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */ +#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */ +#define USART_ISR_TC_Pos (6U) +#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ +#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ +#define USART_ISR_TXE_TXFNF_Pos (7U) +#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */ +#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */ +#define USART_ISR_LBDF_Pos (8U) +#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ +#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ +#define USART_ISR_CTSIF_Pos (9U) +#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ +#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ +#define USART_ISR_CTS_Pos (10U) +#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ +#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ +#define USART_ISR_RTOF_Pos (11U) +#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ +#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ +#define USART_ISR_EOBF_Pos (12U) +#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ +#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ +#define USART_ISR_UDR_Pos (13U) +#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ +#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */ +#define USART_ISR_ABRE_Pos (14U) +#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ +#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ +#define USART_ISR_ABRF_Pos (15U) +#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ +#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ +#define USART_ISR_BUSY_Pos (16U) +#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ +#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ +#define USART_ISR_CMF_Pos (17U) +#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ +#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ +#define USART_ISR_SBKF_Pos (18U) +#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ +#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ +#define USART_ISR_RWU_Pos (19U) +#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ +#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ +#define USART_ISR_WUF_Pos (20U) +#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ +#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ +#define USART_ISR_TEACK_Pos (21U) +#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ +#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ +#define USART_ISR_REACK_Pos (22U) +#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ +#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ +#define USART_ISR_TXFE_Pos (23U) +#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ +#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */ +#define USART_ISR_RXFF_Pos (24U) +#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ +#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */ +#define USART_ISR_TCBGT_Pos (25U) +#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ +#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ +#define USART_ISR_RXFT_Pos (26U) +#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ +#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */ +#define USART_ISR_TXFT_Pos (27U) +#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ +#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */ + +/******************* Bit definition for USART_ICR register ******************/ +#define USART_ICR_PECF_Pos (0U) +#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ +#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ +#define USART_ICR_FECF_Pos (1U) +#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ +#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ +#define USART_ICR_NECF_Pos (2U) +#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ +#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ +#define USART_ICR_ORECF_Pos (3U) +#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ +#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ +#define USART_ICR_IDLECF_Pos (4U) +#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ +#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ +#define USART_ICR_TXFECF_Pos (5U) +#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ +#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */ +#define USART_ICR_TCCF_Pos (6U) +#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ +#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ +#define USART_ICR_TCBGTCF_Pos (7U) +#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ +#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ +#define USART_ICR_LBDCF_Pos (8U) +#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ +#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ +#define USART_ICR_CTSCF_Pos (9U) +#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ +#define USART_ICR_RTOCF_Pos (11U) +#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ +#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ +#define USART_ICR_EOBCF_Pos (12U) +#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ +#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ +#define USART_ICR_UDRCF_Pos (13U) +#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ +#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ +#define USART_ICR_CMCF_Pos (17U) +#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ +#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ +#define USART_ICR_WUCF_Pos (20U) +#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ +#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ + +/******************* Bit definition for USART_RDR register ******************/ +#define USART_RDR_RDR_Pos (0U) +#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ +#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ + +/******************* Bit definition for USART_TDR register ******************/ +#define USART_TDR_TDR_Pos (0U) +#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ +#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ + +/******************* Bit definition for USART_PRESC register ****************/ +#define USART_PRESC_PRESCALER_Pos (0U) +#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ +#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ +#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ +#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ +#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ +#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ + + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T_Pos (0U) +#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ +#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ +#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ +#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ +#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ +#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ +#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ +#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ + +#define WWDG_CR_WDGA_Pos (7U) +#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ +#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W_Pos (0U) +#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ +#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ +#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ +#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ +#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ +#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ +#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ +#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ + +#define WWDG_CFR_WDGTB_Pos (11U) +#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */ +#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */ +#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */ +#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */ + +#define WWDG_CFR_EWI_Pos (9U) +#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ +#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF_Pos (0U) +#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ +#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBG_IDCODE register *************/ +#define DBG_IDCODE_DEV_ID_Pos (0U) +#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk +#define DBG_IDCODE_REV_ID_Pos (16U) +#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBG_CR register *****************/ +#define DBG_CR_DBG_STOP_Pos (1U) +#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk +#define DBG_CR_DBG_STANDBY_Pos (2U) +#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk + + +/******************** Bit definition for DBG_APB_FZ1 register ***********/ +#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk +#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U) +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */ +#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk + +/******************** Bit definition for DBG_APB_FZ2 register ************/ +#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk + + +/** @addtogroup Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) + + + + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ + ((INSTANCE) == DMA1_Channel2) || \ + ((INSTANCE) == DMA1_Channel3) || \ + ((INSTANCE) == DMA1_Channel4) || \ + ((INSTANCE) == DMA1_Channel5)) +/******************************** DMAMUX Instances ****************************/ +#define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1) + +#define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \ + ((INSTANCE) == DMAMUX1_RequestGenerator1) || \ + ((INSTANCE) == DMAMUX1_RequestGenerator2) || \ + ((INSTANCE) == DMAMUX1_RequestGenerator3)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOF)) +/******************************* GPIO AF Instances ****************************/ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC)) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2)) + + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) + +/****************************** WAKEUP_FROMSTOP Instances *******************************/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/******************************** SPI Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) + + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM14) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM16) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM17) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3))) \ + || \ + (((INSTANCE) == TIM16) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ +#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/************ TIM Instances : Advanced timers ********************************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/****************** UART Instances : SPI Slave selection mode ***************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) + +#define IS_LPUART_INSTANCE(INSTANCE) (0U) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) + + +/******************************************************************************/ +/* For a painless codes migration between the STM32G0xx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32G0 Family */ +/******************************************************************************/ +/* Aliases for IRQn_Type */ +#define SVC_IRQn SVCall_IRQn + +/** + * @} + */ + + /** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32G030xx_H */ + +/** + * @} + */ + + /** + * @} + */ diff --git a/center_fw/include/stm32g0xx.h b/center_fw/include/stm32g0xx.h new file mode 100644 index 0000000..1749bdf --- /dev/null +++ b/center_fw/include/stm32g0xx.h @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file stm32g0xx.h + * @author MCD Application Team + * @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32G0xx device used in the target application + * - To use or not the peripherals drivers in application code(i.e. + * code will be based on direct access to peripherals registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx + * @{ + */ + +#ifndef STM32G0xx_H +#define STM32G0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32G0) +#define STM32G0 +#endif /* STM32G0 */ + +/* Uncomment the line below according to the target STM32G0 device used in your + application + */ + +#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \ + && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \ + && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \ + && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx) + /* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */ + /* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */ + /* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */ + /* #define STM32G070xx */ /*!< STM32G070xx Devices */ + /* #define STM32G071xx */ /*!< STM32G071xx Devices */ + /* #define STM32G081xx */ /*!< STM32G081xx Devices */ + /* #define STM32G050xx */ /*!< STM32G050xx Devices */ + /* #define STM32G051xx */ /*!< STM32G051xx Devices */ + /* #define STM32G061xx */ /*!< STM32G061xx Devices */ + /* #define STM32G030xx */ /*!< STM32G030xx Devices */ + /* #define STM32G031xx */ /*!< STM32G031xx Devices */ + /* #define STM32G041xx */ /*!< STM32G041xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number $VERSION$ + */ +#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ + |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32G0_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32G0B1xx) + #include "stm32g0b1xx.h" +#elif defined(STM32G0C1xx) + #include "stm32g0c1xx.h" +#elif defined(STM32G0B0xx) + #include "stm32g0b0xx.h" +#elif defined(STM32G071xx) + #include "stm32g071xx.h" +#elif defined(STM32G081xx) + #include "stm32g081xx.h" +#elif defined(STM32G070xx) + #include "stm32g070xx.h" +#elif defined(STM32G031xx) + #include "stm32g031xx.h" +#elif defined(STM32G041xx) + #include "stm32g041xx.h" +#elif defined(STM32G030xx) + #include "stm32g030xx.h" +#elif defined(STM32G051xx) + #include "stm32g051xx.h" +#elif defined(STM32G061xx) + #include "stm32g061xx.h" +#elif defined(STM32G050xx) + #include "stm32g050xx.h" +#else + #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of interrupt control for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + SET_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + CLEAR_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + +/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32g0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32G0xx_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/center_fw/include/system_stm32g0xx.h b/center_fw/include/system_stm32g0xx.h new file mode 100644 index 0000000..a1b094c --- /dev/null +++ b/center_fw/include/system_stm32g0xx.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef SYSTEM_STM32G0XX_H +#define SYSTEM_STM32G0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32G0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32G0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*SYSTEM_STM32G0XX_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/center_fw/main.c b/center_fw/main.c deleted file mode 100644 index 3008dd2..0000000 --- a/center_fw/main.c +++ /dev/null @@ -1,73 +0,0 @@ -/* Megumin LED display firmware - * Copyright (C) 2018 Sebastian Götte <code@jaseg.net> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include "global.h" - -int main(void) { - //RCC->CR |= RCC_CR_HSEON; - //while (!(RCC->CR&RCC_CR_HSERDY)); - RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk; - RCC->CFGR |= ((12-2)<<RCC_CFGR_PLLMUL_Pos); /* PLL / 2 * 12 -> 48.0MHz */ - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR&RCC_CR_PLLRDY)); - RCC->CFGR |= (2<<RCC_CFGR_SW_Pos); - SystemCoreClockUpdate(); - - /* Turn on lots of neat things */ - RCC->AHBENR |= RCC_AHBENR_GPIOAEN; - - GPIOA->MODER |= - (1<<GPIO_MODER_MODER0_Pos) - | (1<<GPIO_MODER_MODER1_Pos); - - int cnt = 0; - int ph = 0; - while (42) { - if (cnt > 5000) { - cnt = 0; - ph += 1; - ph %= 4; - } else { - cnt = cnt+1; - } - switch (ph) { - case 0: GPIOA->ODR = 1; break; - case 1: GPIOA->ODR = 3; break; - case 2: GPIOA->ODR = 2; break; - case 3: GPIOA->ODR = 0; break; - } - } -} - -void NMI_Handler(void) { - asm volatile ("bkpt"); -} - -void HardFault_Handler(void) __attribute__((naked)); -void HardFault_Handler() { - asm volatile ("bkpt"); -} - -void SVC_Handler(void) { - asm volatile ("bkpt"); -} - - -void PendSV_Handler(void) { - asm volatile ("bkpt"); -} - diff --git a/center_fw/match_test.ipynb b/center_fw/match_test.ipynb new file mode 100644 index 0000000..6ee0835 --- /dev/null +++ b/center_fw/match_test.ipynb @@ -0,0 +1,502 @@ +{ + "cells": [ + { + "cell_type": "code", + "execution_count": 1, + "id": "1ebba6a4-0f66-4e99-8363-7d9e227b4949", + "metadata": {}, + "outputs": [], + "source": [ + "from matplotlib import pyplot as plt\n", + "import numpy as np\n", + "%matplotlib inline" + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "id": "5f1575d2-d501-46ef-97d5-9d20d1259e4f", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "[<matplotlib.lines.Line2D at 0x7f5ceef33e10>]" + ] + }, + "execution_count": 2, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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6OttJfNHY6mI4GKsDTYkA0d5QjFZLNjoHEmrKmYyNSAA4o6oIAHD4VD/z786GAwmjQY1K0GQ+JCqlXhxKXOMvTxyBmlIXJiWUrL1t+q5tet97rchpprnzzjtxzTXX4Morr0zZfvDgQbS1tWH27Nl0m8vlwmWXXYbNmzcDAHbs2IFIJJKyT0NDA5qamug+W7ZsgdfrxbRp0+g+F198Mbxeb8o+TU1NaGhIpqbOmTMHoVAIO3bsSHvcoVAIfr8/5U8hQdJdlZVij3YFaAqskVOVM4G0OonE4jofCX8QA4S8MQNAfbl8vfQs6b+fHhd7A77EZUdZoh5Lq04uCtaQwOuxKhhGoxOGUUtXv65jQs1zJKEFB070IarjPHH4lHyO//eSsagpc+PshGG0r61H1+M60ikbRjdeOMpQwdTZknVW2urVq/Hhhx9i+/btp33W1iZHq9fWphYEq62txeHDh+k+TqczRWki+5B/39bWhpqa08ux19TUpOwz8HcqKirgdDrpPgN59NFH8eMf/ziT0zQl6TIe9M440pLGSnliD0aEYTQQ4lodWZ58Ax+R6JF1QkdXE8mUG69SLFxDuQf+th4c7w5gggrGl9aoaTTUez1w2qwIx+I43h2gz5PWqHmOI8s9NDPtSGc/zhyhfQxmPC7hcMIAIec4prKIHteP/7wbS2aN19x9FYzEaLbqD66ehKoS8xpGWSlGLS0tuOeee7By5Uq43YPflIG+bUmShvV3D9wn3f657KPkgQcegM/no39aWtRtM8AbJIDu1hln0G16FzLTkspi2ZV2qk8E6A/kkzZZmVFOdiMSb4R6xpTsbpVV3VqVFoGR5XJA/vFucyhGJDaFdTwWANisFjRWytdLL5dKOBpHS8JoUMNdaLVaqGq0Xyd3Wqs/iHA0DofNgvqEym21WjAxERP38tYjunSqP9rVD0mSlVYyl5qVrAyjHTt2oKOjA1OnToXdbofdbsfGjRvxi1/8Ana7nSo4AxWbjo4O+lldXR3C4TC6urqG3Ke9/fQeXidOnEjZZ+DvdHV1IRKJnKYkEVwuF8rKylL+FBLpMh7MHEA3kKpEFtIpEwXbsuJIYqEbU5VcbIhh1NGjj9EgSRIOJBanco86JdeIu/B4d0CV79eSQDiG4wmXoBpGA5AcH4c7+4bZUx2OdPYjLgHFThsdn6wh6uSLmw/pEl5wOGHcNlYUpWTdEXeaXhBjeHRlEfPAft7IyjC64oorsGvXLuzcuZP+ufDCC3HzzTdj586dOPPMM1FXV4cNGzbQfxMOh7Fx40bMmCHXCZk6dSocDkfKPq2trWhubqb7TJ8+HT6fD++//z7dZ9u2bfD5fCn7NDc3o7U1GS+zfv16uFwuTJ06NYdLUTjo8bbBA1WJYOJOoRgBSMacbT1wigak9wSjNObM45CnB70Uo2PdAQSjstuz3utR5TcaqGJkfMPow0Th0jKPHRUqvdGP0TkAm7rRRrDPuiOMS8TZbf78lC5z5SH6kiJfa/KcKl8OyDOqZWzowOMyM1m9hpWWlqKpqSllW3FxMaqqquj2pUuX4pFHHsH48eMxfvx4PPLIIygqKsLChQsBAF6vF7fddhuWLVuGqqoqVFZW4r777sOUKVNoMPfZZ5+Nq6++GosXL8azzz4LALj99tsxb948TJwo912ZPXs2Jk+ejEWLFuHxxx9HZ2cn7rvvPixevLjglKBsIQ/S3KY6UwfQDUTpSsvEvWt20sWcLf9TsuYYacyrtWFEitztOJxUlT9p66FvzyyLTBJX2jETGEa7Eq1biPtFDcYk4ooGppNrRTJVX73Yn3E6xBUpOXQq1R3KS2zokcRxjRaGUfZ8//vfRyAQwB133IGuri5MmzYN69evR2lpMrDxqaeegt1ux4033ohAIIArrrgCv/3tb2Gz2eg+q1atwt13302z1+bPn4+nn36afm6z2bB27VrccccduOSSS+DxeLBw4UL89Kc/ZX1KpqM9UbzsWzPHmt59poS40sLROHpDUZS6zdELLldIi4Xdx334wWvyRKusct3mC2DtrjbNg6+1XAiIYmSGrDSiepFzUoMxicV6x+EudPiDms8fpL+jGi90xCCPKepT6NEnkMaJJdyW5Dnd2dKN//cHuRr2wGr0WkACwsdUquOm5Ym8DaN333035f8tFguWL1+O5cuXD/pv3G43VqxYgRUrVgy6T2VlJVauXDnkb48ePRpr1qzJ5nALHkmSaMxIIalFAFDktNPMjs6+cMEbRqRSLalpBSRjzoBkc80Of0hThY0sBG98dBTPbzoEQL2FgKgrrb4A4nEJVquxVESymAPA7oTR4LBa6YLOejEni/WpvjDadTCMPqMxZ+yfXV6UmcMDXFbkOY0qSiQon1OtOCJcaQKz4g9Gabp6TWnhqEWEymInjnUHcKovnBJoXMgMFnNVnchQC0Xj6AlFUaaRIUkWgr/sSsYPqrUQ1Ja5YbUAkZiEk70hwymo6Rbz9XvasX6PnLzCejEfWe6BBYAEoKtf+1g94vIcWcFeFSMGeTgWw4JfbQEA/OjaybjojEoA2rxIxuMSdReSGluEEpct3T/RhFhcQkuXMIwEJuVEQi0qc9vhcer3oOlFVYlsGHX2igBsAsnSO6e+LGXy9zhtKHXZ0ROK4kRPSDPDiKDFwuuwWVFb5karL4hj3QHDGUZkMQeA2367He09IXx75lhcf/5IAOwWc6UyVV7kQFd/BP/47BStjq6mm4n8diAcQ1e/nCTgC0SYq2LEIJckCTYLEJPkOkJaKjPtPUGEY7IyZB2g0Ba75OXagmSfP63YdawbkZgEu1W9RAieEIZRgUHii4y2ALAiGYBdmJl56SB1nS6dOOK0cTGizIWeE1F0+EM4S+OgVKJkkbYIatFQ7kGrL4jn3juA5fPPMdSzQRZzAIjEZSVYDXUtnTL17HsH8Ox7BwCo62ZK99s//vMe+nfWv22xWOB22NAXjiGg6A2mBYdOJrP9BjbIJYaRBMBbpK1h1HwsWU/MZjB3cy4Iw6jAaE9kpNWWFVZ8EYGk7Isij0nItahKk+I9osSFAyf6dKl+3dUnqwM3XNioqrFC4oz+0tyGO748zlCGkZKeYBSAXICPNUpl6t7f78Sn7b24Yeoo3JIoFqum4Up+e397L773+50A1A8+LnbZ0ReOocihzRJJVLHNn52k2wYGfiuLr/aFonA7tFP8SXJCnYoZjzwhDKMCg8jhtQUYXwQkM9OEKy1JZ0I9q0ojz+tZ/ZqoehUqvx2PVDGLSyuCkRgiCRfMmSPYx84planqEhc+be9FdYlTEzcT+W2fovmz2sHHZR4HOnpCcNrZNi4ejEwDv0nySF8ohiqVBVyl+3TXsW4AgNOmXmA/TwjDqMAgitGIAlWMRFuQ0zmVMBJJvIgSEqCvh2FE4knUaj+gnPgJeqRns4AYDTarRZUeYkqIUhHQuOeg0jBSm+JE/GV/OKrJ7xFV7IV/HMJrHx4FkF4VK3bZEYjE0BtS/7jSGWtbDnRi3opNAMzdW1MYRgVGh7/AFSNhGJ3GkK40ndqCxOISuvuJwaaOYcRLejYLuhNGZLnHoXpZhYoiOQhf61gTf8IwGltVpHqGWJFTXhr7wtrEGBFVzO1IKlTpVLESlw0ne4E+DQw2pfv0e7/fif0auk/1RhhGBQZZ4NRqysk71JUmgq8ByOnBXcQw4siV5g9EQMq2lBepkw1HJv4dh7vwo0TFbz0K57GAGJFela6VElLGQesQXH9QNoy+MLpCdSWvOJEa36+BMqOExIkNBgnA1kIxUrpPiQ08vqZU8/pJeiAMowIjmZVmnEmfJcRdJGKMZPzBCC0cl06ZIYbRnuN+TSsddyYW+jK3HQ6bOnEeZOJXZh7pUTiPBaTXnVeFwocDIWpKv8YZWz4dzlErxYhAjL8rz65Ja5gXk+PS2GDrD8nXoVjHWkpaok1kmYALlFWvC92VdjLRL63QIW60UpcdLvvpkx6ZnE/1hTVtqElS9dVyoynxaJjdoxY+hStNbYqc+qgp/oD8ewMLH6oBUWa0NkCIYvR/po5K+xJCDBOtj4sUBVajsCaPCMOogEipel2gipGyX5rWb4M8QgOvBykYN0Lx1hqNaRdsSwwjtbrEKyGFTp02i6HcZ0q6A/L1Ktegvk0RcTNp/PwQxahMA+OPBF9rEcujpCehGA3WrijpStP22hNVtVC6BQhXWgHR4U9WvdayBgZPFDntcDusCEbi6OwNq1LzxUjQVP0BBgjJ2IrHJdoC4v1Dnap0uE9H1xAB4awhCkhcMm7hU23dTPoYRsTNpIVhVJSYF/o1NkCIYlQ6iCpWooOSFYtLNKapUObLwjhLAQBgX3sPAG0WG56pKnbhWHcAJ/tCGF0AfX+G4lRf+lT9dBlbj/zlE/p3tTO2SIyR2jWMgKQrLRqXEInFVYtpUhOalaZB8DWNMdJYTaGKkQatafRTjIhhNLRipOVxKX9rMIPNbBTGWQoAAAdOyM0JvZ4CN4wS/dJe2HQQo+Z5DKsSsIC40gYay8pU3a//eit6Q1Hcc8V4uk1tl1Nnr4YxRoqegf3hGLweAxpGAR1ijLRWjLRUxXRQjJTKzGBxVHrEPhFjzWGzwKVRwUu9KYyzFAAATvXKE0tFsbbNQHmDLLZ//rhV04BiHukcJFW/psxNM7SIfD6q0kO3qW1MUsVIA8PIabPSdOSAQePOSPC1Fun6ScVIa1dawmjwqP8+TzrZa6nM9AaVykz6+0iPS0ODrVehYqldI4sXhGJkcpTVfT/rkF1pcQkFUdZ9MLRQIYzCyUQPtKGuCXlLDGtY6ZjEGFVq4EqzWCwoctrRG4pq3jSUFTT4WgM1WC/FSJd0fQ2VGRJD5bJbB21FomUdI0IyILxwzIXCOdMCJV2syMZPT2DjpycAGKu6b74QI1GZpm/UFhCsIIpRdcngrrHixISorMqrNp0qtwMZiMdpQ28oqnncDCu6NVSMinWIMQpGYghHZcNcm6w07VWx4eKLAH2Cr3sKLPAaEIaR6VHGivzb//wTe9t6sOD8kfjWzLEAjFXdN1/M1AKCFZnUCyLxDi4NMxm7NEzXB5IB2EGDKkZa1jEiMVmBSAzxuASrBq1BSHyR1QKUONVftop0cKX10Ky7wc9PjwKPw2XKmZHCOdMCRVnW3ZGQZ88cUWzI6r75QozE/91xFL/dfAiAcVtAsOJk7+DtQAjEaNDy7VnLAo+Afu4hFkRjcfpWr0UdI1JkUJKAYDRG3U5q4lfU99HCEKOKkYaxPJkoRnq60kpchRObKgyjAoLET5ih0m8uECNxx+Euus2oLSBYEI9L6OonWWmDG4VEIdBKTQlFk93DtYgxApId441oGPkVQbtaVIV221Oz+LQwjJLFHbVZsop1UIxonaYh7mHSlaZ98LUWY4sXRFZaARFN+OjrygsrjmYgWsbK8IwvEEEs0SdtqExFYjRolbFF4mVsVotm8n2RxsYfS0gD2VKXnRbgVBOr1ZJUETVaoEk7EC0Cr4GkYhSMxDWr+J6Jy0qPliDkuEqEYSQwI6GEYdRYUdhFDclCP6rCU5DuMwIp7ui0WWiMSjrIIqhVxhZtB1Lk1MRtAhjblUYbyGoQeE2g3ecj2izQSTVFm3MsUjRL1apZLs3+GsJlVaIo8KhVr0ei3hZSjJEwjAoI0htMC+mbZ4hhNKIAs9CUnEqk6odj0pD1nPQyjCo1rLeltSrGEp+GVa8JxL2qlUtHy1R9QK5tZU8Y5VqpYj0Z1GkiMUZxSbvn0V+AMUbCMCogSHptsaswY4wIbpqBpF1dHh4hBshw0BgjjYwGpWKkFUVObY0/lmhZw4hAXE1aGZJ+DduBAKS2lbZxRv4Mgq+LnDaQGotaBWD3iqw0gVkJR+OIxGTptdAVI6KAhAy4CLKA1HPapajhNFQ9J4/GRsORzj4ASWNFCzwGVoy0rGFE8GhsNPh0cBeWuOzwB6PaxVFlUEjRYrGgOFGMtC8UA0rVPy6Rri8wLcpibFouODxCgq+NqA6wINt6TklXmjYK27GuAABt6yZ5dGpzwQKt3UyAHoqR9plRRRo3bM0kXR+QFX/ZMNJIMSrAGKPCOdMCh8QXOe1WQ3YPZ4nRi/nlC6nntGrrYfxuewuAoes5aa2mJJuFargIUlXMeJWvuzUs7kjQSzHSouo1odipbQZYpq035DijkGautB5FDalCQRhGBUJ/4iEqLnC1CFAE2haoYUTqOZUqFpmh6jl5NDAalD39WhKKUW8wqllPPyO70ojRoGXwNZlHNDOWg9qrYrRfmkbnSIOvhzFAtG4L0itaggjMChnchR5fBKQGX0uSVDAdoweSaa8rLTK20rn31u5qw9pdbQDUb9fiMXK6fr/2wddaux61TtcHFCUJeFOMnNpWv/aLGCOBWSETWCFZ/YOhLPAYisbpwl9okDFxybiqIes5aRFjpOzpd8/qj/D5iT58/aJG/MvFYwCo365F65IELNGljlEhuNJc2ipGyTiq4WKMtKt+HYomm/cOVV/JbIhVskAgsmtRgafqA0gxhIKRWMEaRkQBmnNO3ZBuKi1agih7+tltsoJ31ogSzdq1FGnsGmIJqUelVcE/QPvrlax8rWXcGemXpr7xF4nFqVE+nDJTomH1615FuxlR+VpgOog6UCxcaXAoircZUSFgBRkTw/XO0zr+JpRQprRs3WJkVxop8BiJa2gYaahaxONS0pWmQ/B1rwaqmNIAySz4WhtXGol7KnLaYNOoCj0PCMOoQCCSd6Gn6hNEkcekoeMZZkxoHaxOFvh6r3ZVyY2aqShJEnpIOrWGbnIts/h6w1EQMUzLGCNi/GlRx0hpgAzX707L4OtCTNUHhCutYCAPd7GIMQIgL/a9oaghXSesIH2uhjOWta4KHUnENNSXezT5PUDhNjHIeCBZfH2hKIhQ1NLZr3kWnxaKEVHEnHarpm5vLeOoMinuSCjWsL6SvwBT9QFhGBUMQjFKhbhpglFjLIRqQBUjx9DTAFkEw9E4YnFJdUk9oENPP4/TWEU/02Xx/fCPu+nf1c7iI4uzFi8WeqTqA8lz1EIxysYASbrS1D8u4uIrtKSdwjrbAobGGBXYAB8Mo7pOWJI0QIaJMXKmBqurPYaIcTJc7BNLPBpXcs4XksXX0tmPf131IYChi3SyRssCjyTwOhqLo8Mf1KzxM0nX1+Ics2m7oWXhyUJsBwIIw6hg6KUFHsUtB5QxRsZYCNWgP5KZYeSyJ2Me+sPqGkaRWBzRhG9ouNgnlhQRVSwWRzQWHzbOQ2+UWXyEoYp0skbLliAkVb+rP4KOnpBmhpGW7tVMizsC2gZfF2qMEd9Pv4AZtPK1SNcHoFSMCjf4uj/D4GuLxaKZwqZchLRVjJK/ZRR3GqBfTJSWneeJm0lriPGnjTKTeYyRlsHX9LgKqIYRIBSjgqFPh7gNnnGRRrIGcZ2wJhaXaOG2TMaEx2lDIBJT3WgghpfdaoHTrt17m8tuhcUCSJI8JowSbEruR3WJU3X3mZIiDcobkADzfW1+uo0ElwPqB5gX6eJKy1wx0sQwIu1ACkwxKqyzLWBI+wehGMlQBaRAg6+V7UAyCcjXqpZRprWVWENUsf6w+sYfS8j9GFNVrJmLCUh1M6nVViddgPn9r++if1c7wLxEy+BrUtk7o6w0+dno6AmpHnMlYowEpoak1QrFSEaL/l88Q87bYkmNIRoMksWnttFAjsutQ/ZkkVM2jIySsg8kFTatDUmipsTiEsKxOFx29r9PAsxf2nIIv//gKABtA8y1dBd2+OXq5ZnYl9RgC8dUj7nqEVlpAjNDFSORrg8guZCEooUZY6RUZjJ52/doVMsokGFtJTXQ6hxZQo5V67Y2RYrf6w/FVDGMSIB5iSK+RY8A82BE/TIVp/pDGe+rTH6Iq1ztvFeH5r08IAyjAoEqRgVm+Q+Gu8BjjAIZZqQRqOtR5esVCMdTfk9LtG59woJMq5ezxm6zwmm3IhyNoz8SQ4WKv6WXoarsK9kXjqpqHPSHhn8eScxVSOH+//BIF6wJg02NmCvhShOYmj6hGKVAXDWFmq6faUYagdb5UT0rLZr4PT0UI2PVMgKUNZ+0TzAuctoQjsYRUNnVFEqc48xxVZoGmDsTPRWjcQn9oRhzw4gYOgBwItEI+GRveNDq5elirpb/eQ/9uxoxV939YQBANF5YyrowjAoE0RIkFbe9sIOvaXHHYapeEzxaxRjpFDMj/6Z8jv0GMpb1qBJOKHba0d0fUb0tCBkTc86p0zTA3GKxwOO0oScYxZHOPtQx7t2XztB5acthvLTlMIDTDR0ScwUAC371D4RjEv5tzgRcNqEGgDoxV75Ecc1wTLsGxTwgVskCIByNIxyTLX5R4FEmGXxdWG9ChGyVGa3cTJlW41aDIqoYqR9sywq9YoyA5NhRO1idnKNLh3N02a3oAXCsKwiMZfvdSkPnm795H519YfzrZWfimnMbAJxu6CiLerodNoRjUZxRVaxqzBWZJ4p0uPZ6IlbJAkC5mOnhouART4H3Sss6xsipkWHEwUJvTFeaPll8QGrpBzXQK/MOUFTIV2GeSK1eLisyE+vKMjJ0SI2vsArJI8TFJ0kSNXpburRrUMwDwjAqAEh8kTMRMClQTHgGWgRZ0p+lMkMVNo0qX+uSlZY4RyO50oI0VkyfGCNAC8VI24B8ZewPYV+bX1XDIByVDSNXhrFixIhXIzQinYvvkb98Qv+udv0oHhCGUQFA5VBR3JFCJpZCVYySwdeZxhhpYxjpqQ6Qhd5IxrK+ihGpp6NN8LVWKmI6w+C3mw/jt5vTx/6wgGSaNZR7MtqfhESo4QEgLj5/IIKF/70NAPDw9U04r7EcgPr1o3hAGEYFAAmOFPFFSUjdFSO5TVhC4mgyzWbSuldapgYbS6hiZKAxQY5VD9ejdoqRtqqYMvbn3t/vxKftvbhh6ijcMuMMAOwNg3hcQiQR3DwqQ8PIRZ9H9q404uJr9QXotvMayzWrH8UDYqUsAEhPHT3cE7xCFaMCbSKbjDHKUDHSOMZIl6w0p/FcadneR5ZoZhglvl+NIpLpUMb+VBU7AQAjSl2qGQbKIrOZGrjuREhESEXFu1DnRgAQAScFAGkgK1L1k5CJRdQx4ivGiIeYGSO50oIaqylKiDH27r4OdPiDqv1O8hy1N5ZpkHNMPSNBOQdlahipqRgRlG7tQnCfKRGGUQEgGsiejqfACzwm6xhlNiaI0RBQ+S1SuNKyI8CBK237oa7TgpVZEtQ4+FoJKerosKm3VJI4R6fNmnHbES0UI/ISVFXiNH0W2kCEYVQAiAayp6OVAsIrWVe+1qoliK6uNG2qe7NEz+ulhQJNmtQC+hh/FQlXmpqGEXUVZlG9XEvFSI/rrjdipSwARAPZ0/FoMLHwTDItPrMpwE3jb9TNQNKzwKMRe6Xp4WYi6eykXQQAmsoOsE1nVyq6etYxCqloLJM5KBsDRAvFKESPq/D0E2EYFQCigezpuBQFHiVJyqjDvJnItou9ZpWvOUjXN5JiRJU/Da9XunT2+1/fRf/OMp1deS9cOtRgc2kQi0hcadkYIG4tFSONgt55QqyUBYBQjE6HTCySJGeFFJpcnLMrTfUYIz2byGpTyZkVkiQpUtm1u14knf3tT9rx5AbZQHpswRSatcUyUDeZkWalXeS1hCpGKlSYJuRigLi0yEqL6hf0rjfCMCoASOVrEWOURPmGHYoUnmGUrcvKo5GaomegrdFcaaFoHFKit6eW14uksx/p7KfbmkZ6VUlnD+m8OGuhGBGXVTbnmHTxqWmwyd+tVZkEnshKm3zmmWdw7rnnoqysDGVlZZg+fTr++te/0s9vvfVWWCyWlD8XX3xxyneEQiEsWbIE1dXVKC4uxvz583H06NGUfbq6urBo0SJ4vV54vV4sWrQI3d3dKfscOXIE1157LYqLi1FdXY27774b4XAYgtOhBR5FVhrFocgAMZLrhBXZuqy0MhpolXZdmsgay5WWS5o3S7RwbZEmz3oYykAyyFlNxSjAqWKUzHgsvBijrM541KhReOyxx/DBBx/ggw8+wKxZs3Dddddh9+7ddJ+rr74ara2t9M9f/vKXlO9YunQp3njjDaxevRqbNm1Cb28v5s2bh1gseYMXLlyInTt3Yt26dVi3bh127tyJRYsW0c9jsRiuueYa9PX1YdOmTVi9ejVee+01LFu2LNfrYGpIgUdRxygVrao580g+dYwkIlOogJ5NZMlv+gMRVevysIJcK4fNomrW1GCQ61VV7FStzo2e4wHQpt4Z+e5sstI0iTGK6nvt9SSrlfLaa69N+f+HH34YzzzzDLZu3YpzzjkHAOByuVBXV5f23/t8Pjz//PN4+eWXceWVVwIAVq5cicbGRrz11luYM2cO9u7di3Xr1mHr1q2YNm0aAOC5557D9OnTsW/fPkycOBHr16/Hnj170NLSgoaGBgDAE088gVtvvRUPP/wwysrKsrsKJocsgqIlSCpuhxW9IeMoBCwJZJmVpjSg1IrJisclOtHrqRjFJKDNF+S+doueNYzk35UX8hK3XbVrpXfKuBaKUS5ZaTR5RJNsOaEYZUwsFsPq1avR19eH6dOn0+3vvvsuampqMGHCBCxevBgdHR30sx07diASiWD27Nl0W0NDA5qamrB582YAwJYtW+D1eqlRBAAXX3wxvF5vyj5NTU3UKAKAOXPmIBQKYceOHbmekmnp09E9wTPuAlWMJEnK2mWldGWo5U5TNvTVM/gaUHchZIUeGWlKSOyJmnEuSZevPouzlopRdun66htsIR0zRPUmawlh165dmD59OoLBIEpKSvDGG29g8uTJAIC5c+fihhtuwJgxY3Dw4EH88Ic/xKxZs7Bjxw64XC60tbXB6XSioqIi5Ttra2vR1tYGAGhra0NNTc1pv1tTU5OyT21tbcrnFRUVcDqddJ90hEIhhELJCq1+vz/b0zck/v4IAHXL2huRQi3yGIrGESdBuxkaIDarBU67FeFoHIFIDBXD/5OsUVac1jJFmNTliceTLsKdLd302rCsy8MSsqDq9cLjVpS8UAteFCMtXFbZGH/aKEbClZYxEydOxM6dO9Hd3Y3XXnsNt9xyCzZu3IjJkyfjpptuovs1NTXhwgsvxJgxY7B27VosWLBg0O8cWEcmXU2ZXPYZyKOPPoof//jHw56j2ehJxBgVmjIyHB4NMjt4RKn4ZNoSBJCvVzgaV61lhjLYU8vU7HR1eR7+y176d5Z1eViid/wNUYy0WJz1Ui00adaag0vUpYFipPf40pOsDSOn04lx48YBAC688EJs374dP//5z/Hss8+etm99fT3GjBmD/fvlSaeurg7hcBhdXV0pqlFHRwdmzJhB92lvbz/tu06cOEFVorq6Omzbti3l866uLkQikdOUJCUPPPAA7r33Xvr/fr8fjY2NmZ66YdF7cuEVtwZvXTxCusc7bVbYswja9Ths8AUiql0vvcYpqcsDADc8uwWBcAz3XjUesybJ23htoBnIMoCeNUS1kMsGqFMkVe84Km0UI75jjPQorKk3eZ+xJEkp7iklp06dQktLC+rr6wEAU6dOhcPhwIYNG+g+ra2taG5upobR9OnT4fP58P7779N9tm3bBp/Pl7JPc3MzWltb6T7r16+Hy+XC1KlTBz1Wl8tFSw2QP2alwx9E8zEfmo/50JeYXI509tNtRsi6UZtCdaUFciyiqHYto2zblLCipsxN6/AQd8boymK6jUc3GqBvlXAgqVpIknpu+lyMBpa4FcafWiQLPGaRlaaBYiRcaRny4IMPYu7cuWhsbERPTw9Wr16Nd999F+vWrUNvby+WL1+Or33ta6ivr8ehQ4fw4IMPorq6Gl/96lcBAF6vF7fddhuWLVuGqqoqVFZW4r777sOUKVNoltrZZ5+Nq6++GosXL6Yq1O2334558+Zh4sSJAIDZs2dj8uTJWLRoER5//HF0dnbivvvuw+LFi01t7GRDOvfAf67bh/9ctw8Av+4BLdEi5ZVHSG2YbGNTqCGplistknSl6YXTbgMQQSTGv7GstxKsvE+haFyVQoBJVUyv4GsteqWRdH3OFKOovjWk9CQrw6i9vR2LFi1Ca2srvF4vzj33XKxbtw5XXXUVAoEAdu3ahZdeegnd3d2or6/Hl7/8Zbz66qsoLS2l3/HUU0/BbrfjxhtvRCAQwBVXXIHf/va3sNmSF3/VqlW4++67afba/Pnz8fTTT9PPbTYb1q5dizvuuAOXXHIJPB4PFi5ciJ/+9Kf5Xg/TQNwDwUgM/+e/tgAA/v26c3DBaNmFyat7QEsKVTGibTeynPDIC22bTx21MdsSAmpQlFhwjFAlPttaVKxx2qywWGTFKBiJocztYP4bevfrcmkSYJ69ASIUI3XJ6ul//vnnB/3M4/HgzTffHPY73G43VqxYgRUrVgy6T2VlJVauXDnk94wePRpr1qwZ9vcKFVK2v7MvWQ38vFHlqpTtNyqeAo8xynZBtSZiSDp6VDKMOIiFK3bJi7sRDCO9r5fFYoHLbkUwElctgSGY41hlBTFAIjEJsbhEq+WzJJcgZy3iI0McKLh6UXhnXGAoHxw1HmojU6h1jLLtk0agbQhUWgT1VkAAYwXkB7m4XkS5UNu9qq9iBKh3jsEcDBBNW5UIxUhgNshD57RZhPtsAIXaEiRpgAz/+JMaP0BS8j90qg/Nx3wA2Nb40VsBAbRJg2YFH9eLGJLqXK9ADlWhWaJ04YUicRQ52f9GKIdzJIHa4Wgc8bikSnmLQq58LQwjk0MGd5nHyW12jV64CjTGiGSlZVLDKF0Q/58/bsWfP5YzQlkG8Qc4qNBuJMWIhzd6tRUjvQPMrVYLnDYrwrG4anFGyZ5k2StGgJwR6Layvz40KFyn+C49EYaRyQnl8NAVCp4CzUrrz8KVpqzx8x9r92DrgU7MmlSDexPGEEsVkmTLuXU0jAylGJHO87peL3UVo2SMkX7zl8ueMIxUPsdcFCPy79UwjvWO79ITYRiZnFwaFBYKRlIHWBLIYsIjQfwAUJf4b3mRQ5Ug/v5I5kqWWrg0qHTMikCEB4VN5RgjUuBRR9XC5bChJxTlKo7KbrPCZrUgpmi8zBq9a0jpiZARTE4uMm2hUKgxRrkGXzsTRkNEJTWFh2BiLSods0LvqtBA0mBRb3FOnKOpVbGEAZKl8admu5J4XEKYGEai8rXAbIQK2E88HIVa4DHXruwVichTtbIb+zlY6I2lGHEQfO1Q93oFchyrLKHVr1VuhZPty6uaRrwynkooRgLTUciZBcNRqAUeTyVqW2XbxaGqRDaMrCr0xAKS90FP1xBd6A1gLAdyKAzIGpfaihEHoQD0BUolpTSXrDRAXcVIeT+FYSQwHXpXjuUZYiweOdVXUL3jfAHZMIrGs5vokwuEidUBu7rnyBI+XI/qxunpnZUGKF1p7M8xFpdon7lsz1FVxUjRaLoQ698Jw8jkFHJZ9+EgE9GJ3jCt1VMIJHszZSndq1zgMZugcLUwlmKk/7OtdmsKHtyFyQBz9QwQ5e9kippu31znCLMgstJMDnmYC3WAD0UhGYvKQo3ElXayJ5RVoUa1U9m5WATt6rpNWJJN2QW1UFMxkiQp5/gblqipGCm/05VlkLOaMZI8uDD1RBhGJqfQB3g6iJHQ0tVPtxEDAWBbzZkX0hVqfOX9FrzyfguAzAo1ql3egIcmsi6VA21ZwoObSU3FKByLIy4lfoeLkgRqBDnL3+m0W7OuXq2mYhTgwCDVE2EYmRya7ipijCjpjIT7X99F/86ymjMvKAs13vbb7WjvCeHbM8fi+vNHAsisUKPailFPSK7LE0zU59EDoxR4lCSJC9ejmsZyMKwIANazjpFdPWM5GQOavQGipmIUKvDYVGEYmZxC9xWngxgJJ3tDuPWF7QCAxxZMoUULzdhTTlmo0ZLIKptYV5JVoUa1A237EoZRf1g/o8QoRT9Jt3dA7/IGaqop8j2wWS1w2PQLAFaz2XQ+MaCqxhhF9Te69UQYRiYn1+JhZoYYCd39YbptUl2pKtWceSQckyc9hy3bYE911ZRwRP94OKMoRsoSEzzU+FHDaFBmKVpUKhGRCVoEX+digGgSY1Sg64YwjExOqMB9xUOhLHoZiUk6Hom2kHOt92YXR6XGGyqJ95IkCYHE9x4+1ZdVUDhLkufIt2FEFlS91RQ1MxV5iXNRN/g6dwNEi6DwQvU0CMPI5IQKuN/NcCizQErdhfMokFL/Iys8Wf07Nd5Q08V7PfKXT+jftY73ouoA5640mpHGjZrCl5uJJS4NFKNcjD91lazCXjcKZzUoUHhId+UVq9UCp03unF3mceh9OJogSVKyhEOWb6lqKEYk3qs3FMXXf70VAPD/u+4cnD+6AoD28V5GUYxonzSdY0CScWfqKUZ6ugoBbRQjVz4xRmq4MTkxSvVCGEYmJ9lEtjAH+HC4HLJhxHuwLSuUC362xrJSMZIkiYlSQeK9OnqSlce/0FiuW7yXmoG2LOHFaEim67O/Xrm2ymCNurE8uc/PWsQ+FWIDWUBUvjY99I2kQAf4cBgl2JYVoTx6ICnjDcLZNlobBuVx6ekaMopixEMNI0Bdo4Eb40/FRrnJc8x+flZTyQrlERRuBsRqaXKSQXSFOcCHwygLIStSU6BzawkCsL9edJzarbqWS1C7WzwruHGlqVlkkJtzLEDFqMBjU4VhZHJEE9mhMUrdGlbkI5E7bVYQMYf19SKTe0WRU9eq4+Q5UdYJ4hGiNJzqCenaAFnVRqZRPtw5aipGNDkml6w0NYtrCleawMwkswvErU5HobnS8gn2tFgsqqVn85IkoHQX8qwaETXlaHdA1wbIarpzaB2jglCMcshKU3HuIte+UD0NYrU0OSJdf2iEYpQdaqVn85IerMzUU6M2DysCnIxXTYofchJjxF3lazWPq8DXDZGVZnJCBZ52ORyFphjlaygnFQKVYox0HqekYGIkJlFXDk+QgpgHT/bRbXo2QNak+KHuhpH8+2E1lJm8WoKY3yjVC2EYmZxkur4QB9Ohdv8v3sjXAFFrMibjlIfsSZfdhkgsyqVixFsDZKVixKqEA4GXWjq8Gn/aKFn6P496IAwjExOLS7T9Q7bF/AoFNf30PJLvhEcDURlPxryoA/IxWNEbApeKESmI+cI/DuG1D48C0LcBstuRmqnI8v7xk67PZ+VrNRUjXmpI6YUwjEyM8k2iUC3/4XCptNDzSpBWvc5tPKimGHGUBUPPkUPFiBTEVLawaRrp1a0gZkpMFmPDiBfVoiAVowL3NBTmWRcIKYaRUIzSUriKUW7jQa3JmJe+WIAxalvxkjHnsFlgTXjPWL9cdPeHAQDRuL73gRaxVEOZycMAUTNbjtaQKtB1QxhGJoZM7E6bFVarftWEeabQFKN86qYA6ilGyaBw/aekZG0efscEWQy/NK5a14KYcgkHdRZofyACQH/ljhjKsbiEKOOK77QkQR6KkSoNfKP5xSIaHf1nIYFqJANtxW0eDDXfBnkklKd7Qq1KxzxlTxpBMSLP9lXn1OpaEBNQb4EORRPxkZzEGAHs54l8DBDyb9QwHImRq3d8l16IGCMTw1NAK6+o2aGaR/J3pamjDvBUN0XNN3FW8FTRXlaMIkzGBClHACRdae3+IC1JoHU5AmBAK5xIDCUudssmnaNzuI8kHi8ciyMel5h6BXiJ79ILYRiZGJ5SoHnFCOoAS/JtKqyWYsRj8LUasRusSFYw1/96sTQk05UjeGnLYby05TAA7csRALK70Gm3IhyNs1eM8slKc6QGvrOsEC6y0gSmhaeAVl5xGyCehCX5jgm1emPxUuARULcxKiuSWUP6Xy+WKiIpRwAAt/zmfZzqC+O7l52Jeec2ANC+HAHBnTCMeCpT4U5p6hxjZhjF4hLCMWEYCUxKSPRJG5ZCU4zIeeZe4FEtxSg/JYslarkLWcKTm5zlmCDlCJRMrC3TrRwBweWwAcGoai8EucTy2G1W2K0WROMS0+MSZV5E8LWp4SkOgVeMkIHEknxjB5JZfGq5FPQfq0ZQjEI8uR5VMiRDMWIs659RS8tUMB4TgXAUANAbiub079UYq6LMizCMTI1oIDs8haYYBfNM1yf/jvUCwVPwtVrGH0t4NCRZv1xEEmOsvtzD9Htzwa1C0c9oLI5EYwL0BCM5fYca6iZ5Fp32wi3zIgwjE1PomQWZUKgxRrkG7aplNORbRoAlahl/LOHppUeNlhmSJNF0/ZEV+htGLhUUI2Ugt5OjZAieEiH0QsQYmRieAlp5peAUozzdq0mjQaV0fQ6ke2MpRvovXmooRsrnkQvjj6FiREoSkHIEAPBpey/NhsymJIEqihFHaqReCMPIxOTbF6sQULMRI4/kqzSoVSmcpwKPyTYx/CpGPLke1VCMlAYIV8aySiUJHnh9F/17NiUJnCoYpeS7gpEYOvxB3QuI6oEwjEyMsPyHR81GjDySf+VrlZvI8qCAcK4YRWJxxOKym4kHo0GNZ4i4rKwWuR+b3lCllME5kpIELZ19+NdVHwEAHlswhWbeZVOSQA2jlKhP/mAUHT0hYRgJzEU+VVULhUJTjPJN81aviSxRN/Ufq7yPCeW156HAoxrXS/lSZ7FwYBgxNEDSlSRoGunNqSSBGm7MQnlJHAphGJkYnt7CeaXQFKN8q6Grphjl0WWcNbyPCWU8CQ9uclUUI47qNAH8GiDEZjyRaKOSDyT26dP2XrqNtGIB9GnHohfCMDIxPGWu8IpLBSmaZ/LvlaaWYsSP29coipHLbuVCTXGpEJPFW2aUGg1bifFXVezMvaJ3It3/ZG/+hlG62Kf7c4x9MjrCMDIxPKVA8wptxBhl34iRR5LGcn6KUZhxajZPvb94L/AY4qgdCKDolWbizCiqGDEcE4HEOTZWFuWsxJDga9LCIx9I7NNfmlvxq3c+B5B77JPREYaRieGpnxKvKEsZhGNxuK3mvlZJtSHfliDsFkHlpM7DWOW9JUiQs1Y/LhXqPgXzbF3DGnXT4rO7j8TlBQD9Yfk7Wjr7qdsrV5cXiX3aeuAU3ZZr7JPREYaRieGp/xSvKK9NKBLnYmFWC6Uyk7srjX1BzCBvqdmcK0a8qSnqKkZ8zF1kTLx/8BSzFPZc72M6l9ebu9vx5u52APm7vHh1IWuJMIxMDG8TKI84bFbYrBbE4hKC0Ri8cOh9SKqhnPByrnytgmJEXL68pGar1fuLFbxlm1JjWZUYI77OcdcxP7MU9lyLmhKXFwD857pP8Pf9J3Hp+Gp8/+pJAPJ3eZFrf94ob0G5z5QIw8jE5Os2KRRcdiv6wzFu69awgkXRPDUVI15Ss42jGPGlprB8fkKcuQvVOI5cY0CV6f71Xvm/Xo+DmcuLjK+Lz6wqmCy0gQjDyMTkG2hbKLgdNvSHY1z3xmJBiEHRPLIIRuMSorE47Lb8x1a+JQRYQ11DnLoUQpzF37jUUIw4iY8k8Twne5PtO1ilsAcS8UEeZ+7nqIaCm0yE4GN86YEwjEyMcKVlhhpvvDzCQplRuuDCrAwjzsapi2GVYzXg73qREg7my0pTM4U9+UKQ+zlWFDkBADaG2bS8KZJ6IAwjE8NbkTRe4d11wgoWyoxyEg9G4kjMy3nB2zh1KRQjSZK4cO8poWoKNwqbGnWM+FC7STzP3/efxH+u+wQAuxR2FuN+hAoxQKSMgIeT51EPhGFkYkKcuSh4hff0bFaweAu3WS1w2CyIxCRmC6GyYCEPEONPkoBITILTzplhxJshqaJipHd8JInnafcH6TZWKewslBk11E3expce8DETCVRBDPDMKBjFiNF4SDbUZLMQ8lahXblQ8Rh3xpurgypGJl6c1TgOFufoUiEeLsRRex69KNwzLwB4m0B5hff0bFawUhCTkzFbxYiXceq0WWkPKh7jzkKcqCkEsrD3hqLoUCgr+cBT7zwg+cx4PXZmKews2p6ooxjxVSpBD/gYdQLmRGNxRONyI51CHuCZIBSj7KC9sRgZDbwE2hIsFosqTUNZEeQs25Rcq7iEFJdTPvA2JshxeBx2Zins5BzzyUpTI4OSN7VOD/h4sgTMUT4ohTzAM6HQYoxYKUasjIZcC92pCc+NZHk1GgA2PbsARR0jbuLO2L88sShJoIZiFOBsfOmBCL42KcoHhZegVl4pHMWIzYTH2migriFOFBCA7zHBi2FEavxEFcbQP1u66fjIp8YPL+dIUKdXGmnZxJtixJcbUw+EYWRSyFu40241fcf4fOFZHWAJKxeMm7VixGFMA88qIi89ENPV+Pn3NXvp31nU+OHFMFLG1bEq4cDCAFHTYOPl2utBVnfkmWeewbnnnouysjKUlZVh+vTp+Otf/0o/lyQJy5cvR0NDAzweDy6//HLs3r075TtCoRCWLFmC6upqFBcXY/78+Th69GjKPl1dXVi0aBG8Xi+8Xi8WLVqE7u7ulH2OHDmCa6+9FsXFxaiursbdd9+NcDgMgQxvKdA8w3qh55UQM8WI7VsqLzVrlAjFaHhunjYaa5bMxJolM+FMVFL/tzkT6Labp43O+bt5GxPk5SmeKOHAAhYuKzXGKat5wshkNepGjRqFxx57DB988AE++OADzJo1C9dddx01fn7yk5/gySefxNNPP43t27ejrq4OV111FXp6euh3LF26FG+88QZWr16NTZs2obe3F/PmzUMslryxCxcuxM6dO7Fu3TqsW7cOO3fuxKJFi+jnsVgM11xzDfr6+rBp0yasXr0ar732GpYtW5bv9TANvEyeRqBQFKMQo1ge1teLx7GqRho0K3gpb1BT5qY1fcixnFFVTLflE6RMX+w4GRNqlHAgcVT5FFJMlkpgqBhxlhGoB1m50q699tqU/3/44YfxzDPPYOvWrZg8eTJ+9rOf4aGHHsKCBQsAAC+++CJqa2vxyiuv4Dvf+Q58Ph+ef/55vPzyy7jyyisBACtXrkRjYyPeeustzJkzB3v37sW6deuwdetWTJs2DQDw3HPPYfr06di3bx8mTpyI9evXY8+ePWhpaUFDQwMA4IknnsCtt96Khx9+GGVlZXlfGKND3rhCkRg6/MGCbQaYCYWiGAUZxfKwvl689f4CksYjy9o8rOAxBsSZUC7CrI1lTtyrpISDJCWMEAbTKYsXAqIYhWNxxONS3mET0VicKmK8XHs9yPnJisViWL16Nfr6+jB9+nQcPHgQbW1tmD17Nt3H5XLhsssuw+bNmwEAO3bsQCQSSdmnoaEBTU1NdJ8tW7bA6/VSowgALr74Yni93pR9mpqaqFEEAHPmzEEoFMKOHTsGPeZQKAS/35/yx6wQadUfjKKjJ6Tz0fBNoShGvAZf87jQ86wY8ZjFR1LOi11swlZ5c6WpUcKBZYwRwGasBhXfkU8ZAaOT9R3ZtWsXSkpK4HK58N3vfhdvvPEGJk+ejLa2NgBAbW1tyv61tbX0s7a2NjidTlRUVAy5T01NzWm/W1NTk7LPwN+pqKiA0+mk+6Tj0UcfpXFLXq8XjY2NWZ69ceCxMB2vFI5ixCYFmnnwNYcLPXnvZlWwkCU8xoAUO2WDiNViGuIs+Bpg+0IgSRLTGCOAzfMospllsjbvJ06ciJ07d6K7uxuvvfYabrnlFmzcuJF+PjBaP5MI/oH7pNs/l30G8sADD+Dee++l/+/3+01nHJEU2k/bk3Fdzcd89O/5pNCaFdbBxLxCK19zqxjxswiS8NpTffwldPCpsLHNjuIxM8rtsMIXYGOARGISEvV383ohsNussFstiMYlNoqRImmHt+bJWpK1YeR0OjFu3DgAwIUXXojt27fj5z//OX7wgx8AkNWc+vp6un9HRwdVd+rq6hAOh9HV1ZWiGnV0dGDGjBl0n/b29tN+98SJEynfs23btpTPu7q6EIlETlOSlLhcLrhc7LsR80S6FNr7X99F/55PCq1ZcakQwMgj7Cpfq9MShKc3VKeNbcwMS1jUv2GNW6UxwZPxRwOdGZyjMoDb7cyz4Krdimg4xkgx4s8g1YO8R50kSQiFQhg7dizq6uqwYcMG+lk4HMbGjRup0TN16lQ4HI6UfVpbW9Hc3Ez3mT59Onw+H95//326z7Zt2+Dz+VL2aW5uRmtrK91n/fr1cLlcmDp1ar6nZGhICu1dXx5Htz22YAqTFFqz4mbc+4tXWBkgrDNhQpxMxh3+IJqP+dB8zIe+UBQA0NIZoNt4cavxmDXEUjHitZ0RfSFgcI7kWbRYkkZ4riQNNnbHxdPY0oOsFKMHH3wQc+fORWNjI3p6erB69Wq8++67WLduHSwWC5YuXYpHHnkE48ePx/jx4/HII4+gqKgICxcuBAB4vV7cdtttWLZsGaqqqlBZWYn77rsPU6ZMoVlqZ599Nq6++mosXrwYzz77LADg9ttvx7x58zBx4kQAwOzZszF58mQsWrQIjz/+ODo7O3Hfffdh8eLFBZ+RVlPmRk2ZG+8f7KTbSPqsID2se3/xSpBRmjdzxYiThT6d2rphbzs27JUVbF7UVh5djywVoyCn7YxoMUUG55hseWLL22XFMiic9m/j6LrrQVaGUXt7OxYtWoTW1lZ4vV6ce+65WLduHa666ioAwPe//30EAgHccccd6OrqwrRp07B+/XqUlpbS73jqqadgt9tx4403IhAI4IorrsBvf/tb2GzJG7Fq1SrcfffdNHtt/vz5ePrpp+nnNpsNa9euxR133IFLLrkEHo8HCxcuxE9/+tO8LoaZYFVroxCgwcQmv2as3gZZV9vlZaG/edpoXDVZdsX/5M1P8N6nJzFzXDXunzsJAJh1Vc8HSZKSrjSO3upZjgleA4BZKkYBhsoMW8WID/VWb7IyjJ5//vkhP7dYLFi+fDmWL18+6D5utxsrVqzAihUrBt2nsrISK1euHPK3Ro8ejTVr1gy5TyFDBvi5I71cTOg8UyiKEbMCj4xdjyFGrUryhaitADDS6wEAlHrsXKmtvDaHZqkiEsOIt3ZGLBUjli8DSTcmu+PiqaaYHvBjjguYQgb4tDMrRRbaMBSKYsS6Jcje434mcTfJ2Cd+JmNn4lh4C75WGu88xd+wVYzYlJVgTbKTPbtzZOGyYplVS93anF17rSnsszcxvLgnjEChKEbsKl/L1+vgqX4mxUN5lO+rShwAkvWMeIEsXFYL4LDxc3RJNxNfagpLqFLKmTLDsq4Yj8+iHgjDyKTwOrnwCM8NQ1kSjDBypTF+m+QxE6a6hKis/BgfQGoGH091ZljGufBY3BFIPjdBzrK/WNYVE8HXMmzqtwu4Q1j+mcM6mJhX8s3+IsVDW31J91m+xUMlKVmYjidXGq8lHIKcGg1sM6P4iDkbSFIxYhh8zWDMs1WM+HtJ0QNhGJkUllkPZkepGGVSqd2o5FsvSI3ioanBxPyMVTW6lrMg2VyVn2sFqFVLhy/jL6kYMUzX51Qx4u3aa40wjEyKkEQzh/j545Jcqt9pN59hJEkSndBzjTEi6ex72/z4t//5GIBcPJRkbeWS/ah8y+VpMuY1IJ9XJViVOBeOFERAoSKyCL5OjCsWveVEjBF7hGFkUnipJmwElDEzoWgMTs7exlkQjsUhJXoz+QNR1JQOvX86SDq7VaGo5Vs8lEzENqsFjjwrALOEqgOcNRbmNZ1aDdWCpzpNgCIrjWW6PgPjL5k8wjIonK9rrzWFffYmRrjSMifVMOLLdcIKZfyUP5hfY1SWk2aI0/RgF30L52s88NhXDlBeL3Z9xHh7qVNDmWGZlcY2XZ+va681fD1dAmYIX3HmWCwWpsGjPKIMInZY2aTrWy35V4PmVbp38aoYcVIMcyAsrxe/Y4KdAcLyxVWNa8/CxWdkhCvNpPD61sUrDpsFoShwvDuAURVFeh8OM0gmWZsik2z3cT8NMM8lk4yoO3EJqCrJ1zDic5yyDCZmCb/Xi6FqwXuAOWe1mlhe+wCn115rhGFkUgJhPgMYeUWOb4mlpKKbATUyyZSTeTgaz+vtkiwQfeEoOvxBbqq0s3SbsCTEMDaFJSxVC1YV2lnjYmr8sat8nSw3Yt5rrzXCMDIpIRFjlBUk4Doc40shyBeSSba/vQff+/0/AeSfSaacNIORWH6GUWKR6e6PoKMnxJFhlFSMeCrhwGuNH7ZxLpyeoyrGHwtXGnuDTRhGAlPCMh3UrBA3EwCasfVpWw8tWpiLm4k3SCZZfzg5meebSSZnkFkQiUl5Z+jwpsgQBgbk87JQ8OtKY9lHrADOkWGogxpNZHkzSrVGGEYmJBqLIxKTV3reJHeeSOdmeu7vB/Hc3w8CyM3NxCsBxgaI225DJBbNeZEgRun+9h66Ld8q2iwZqIrxskjzGjvIsq0Or4YRy3MMhFmm66uQlcbZtdcaYRiZkGBKNeHCHuBDQdxMAHDnqg9xuLMf/zJtNL7+xdEA8s+44gmy2NSVuZicl8thRU8o97dUNWKfWOKwWWGzWhCLS1yl7Idomjdfb/QsK4XTVHbOAoBdTFUxdveRZYwRNdgKfN0QhpEJUT4gvE0uPEHcTABQUeTE4c5+1Ja583Iz8QoZE2eOKGGixOQbbEuM0jUfH8d/bTwAIP/YJ9a47Vb0hWNc9Uvjtc6MSxGjF4tLsFlzj8kqBMWIhjqwcKWJGCPmCMPIhCiLwFnzmKAKCdIGJMxZejYrWLeIcedZAJEYpf/47CTdlm/sE2vcDhv6wjGuFCNeFy6mmYpRvs+RpWLEJl2fYVB4no2mzUJhn71J4fWNi2dKPQ4AMGWfNIC9RJ7M2so3+Jofo2MgPBb95DU4VqlM53u9eD1HliUcWKbFJ8cpQ4ONM0VSa/gaeQImsKyRUSiUe5wAAIdJJwTWb+Gs3p5JUPgXGsu5cJ8pYfkmzgpeFSO7zQp7Qp3O16XDe60mUsIhH1hWvmZZjJQqywWezSwMIxPC6xsXz/Ba0I8VScWIzZhI1q1how5cMq6Ku9IINNiWI/dqTzACgE31ZdawMiR5Nf6Uz06+RghLVZ/GGOV53SOxOKJxkc0MCMPIlASEKy1rWMYP8AjLYE+AXaVj1rFPLKHGH0dGCDGMeDLWCKyCgIOcxrm4FMZC/oYR+8rXrIw1gL+sR60p7LM3KSw7NxcKZleMgsxjjNjENfAcD0crHXNkhISj8hu9i8NYOHaKEZ9jwmGzgOSy5GMsS1KyMCoLA2RgRmCukGfZYhHZzCIrzYQk38ILe3Bng9vOJpiYV1h3zWbVHoFndZMXY1lZod2fUIyOdwW5q9DOKlid17YnFosFbocN/XlmKoZjcVppn2VWGpBfRqAym5mXFjh6IQwjE8LrGxfPmN2VFlBMeixgVeyO13gSQBFsq7NhlLZC+6aDeG4TXxXaXYxdOi4O41xcdiv686xtFQwrCvAyrHwN5Ne7MCSqXlOEYWRCgpxmdfAML+qAWrDONmEVfB0wQIyR3sayskL713+9Fb2hKO65Yjzdxks2HwvFSJIkaljxuEDLxxTJa0wQN5rVIrvn8oVkBEbjUl5GqchmTiIMIxPC2m1SCJC3XdY9xXiBpuszMpZZKWwsu4yzhlWtpnxRVmiPJ2JIJjeUcVUME1Aay7mPCeW/7QlGMIITo4/Aovq1UtFn5bJyO2zoDUXzMkqFpyEJf7ORIG9Eun728FizhiUk+Jp5jJGpFSP+3KtkQeYxOJbFM6T8t/5AJO9jYg2LMaGGMsMiI5C1u93IiCtgQgIc++h5xc2weiyPsE6BdjFyPdKxyqFhxOocWRGJxRFLBO2OKi/S92DSwGJxVj5/dht/y5OLofHHUplhY5Ty68LUGuFKMyHClZY9ZleMmLcEoUXl+KnnwhoXI1WMFUo376hKj45Hkp58niGSeXe8O0C3kaw7gL/MOybKDENFn41RKjwNBGEYmRBeO3DzDMuy+jwSZJxxwqxmDeOK3CzhJfiaQK41r3Vm8lmc02Xe3f/6Lvp3XjLvWLoLWc7PLJUsHl9StEYYRiaE58WGV8yelRYIs1VmmFXbJRW5OVQ33Xa+jOWg4h7yWGeGjokcniGSefdJmx/3/c/HAIDHFkyhAea8Zd6xcBeynJ9ZZASy7qdoZIRhZEJYqwOFgNldaSy7ecvfk/9EHI3FEUkEzfD4lsrbmOC5GCagWJxzMBpI5h0pYAkATSO9HGbe5T8mQiq8DLDICGRdHd/ICEnBhPAct8EryUrOfKgDrGGd/ZVssJr/GyrA52TMm4rIu6sjH8WIwMu1Hoyk8Zf/OR7vCqDDH2R0XCyDwoVZIK6ACQmqENxndugiGI1BknLvN8QjKV2zWWWlMcjiIwHhyu/jiWTlaz6M5QDnCxeLVHbi8m0od3PjPlOSbCyc/7g/eKqftnphdlz5KEa0FASfhreW8PmECfKCd8mdR4gCIklyLyMzoXyL5Cn4WvmGymfMTP7qAEuo6sdhPBbAtvjh+JpSLrLQBsKifpcaTYlZpuvzOr60RMQYmRDhSsse5Vt4MBI31VuTGl2zWbgejeIa4sW9E1Ihm4klLPrn8VzwE0iq8LkoRqQkwZFTfXQbq5IETNP1OR1fWiIMIxPCOtC2EHDarLBYZMUoFIkBHofeh8QM5YTHrgUBWSDMW1COhXuCJUZRjFjE33DrLqSZitmfo5olCVjEd3X1y4HvUZMp5rkgDCMTwnssAo9YLBa47TYEIjHTBWCrsdiwSNfnXh1gENDKEhJ/w68hmX9MVoBx6xrWuPKobUVKEjy78XP8+eNWAOxKErBQjEgLFrOFEuSCMIxMiGgGmBtuh1U2jDiJKWGFGjFn5LvCsThicQk2a/ZKVDJJgM9xymuBR16faxaKEe/xkfk0FiYlCYqcyWWXVUkClmUEeEyE0BphGJkQEWOUG/LkEuFGIWCFGuNBqT6ForGUyT5TkooRnxMxd4oR59eLiWLEuYrIIrauX4XxlKtiROKeAKCzLyxv6wnR2CdeWrFojTCMTIYkSar04ikEeOymzgI1GrUqg9ODkTiKnNl/B+8KiNJdKEmS7plz3AerM4wx4vUcafB1PqpYwl14xaQaZiUJclWM0sU9rd7egtXbWwDw04pFa4RhZDJCnBfN4xkWZfV5JKiC0mCzWuCwWRCJSTlfL94XwVRVLK7788S7IekqhBgjhtmY157XwEyNybWuGIl7AoBvv/QB2nxB3DbzDHz1/FEA+GnFojXCMDIZykmJ1wWHV3hLz2aFWguq225DJBbN+XoFOG9BoDyuUER/w4j/+BsGagrn5+hiUA1djXMkRuknbX50+IMZG1wk7gkASJjgxNpS7lqxaI3wtZgMImPLb/Ti9mZDsqCfuVxpaikzLoWrKRd4b1rpsFlpUDkPAfm0EbCJ1ZQA5/GRLBoLq6GKEcXoUB7VtMlLtVPUMRKGkdmgb+EisyBrzKoYqaXM5NtLLLlA8DtWeXKv0ubQnD7bLBSjIOeuNBb989R4UWHxbJM0/Ybywgu2HohwpZmMoAqdmwsF+jbIwSLIErWUmXyD1ZMLPb9j1e2woT/MR20r3o0GohhFYlLOJRx4z0pzsVCMGJ4jySpr7Q7QbblW0ybnNKqiKO/jMjrCMDIZZAI3U0sLreCtbg0rkooRW6Uh37o1vC/0QFKdyUcFYQXv8TcsSzjwfo6+/nBWsTxKkhXM838eWVXTjsUlhKN8uzG1RBhGJkOtRbAQMKsrjaqIKilGuSpsvLcEAfgq4cB9VhqDEg7cZ6XRwqYSOnpCuRlGDF3bJKtsf3sPvvf7fwLIrZq2cs7j9dpriTCMTAZ1T3A6efIMXQQ5UAdYElQ9xig3o4F3dQBQNkbVf0zwHpisLOGQq8LGfQkHRXxXPC5l/e/jcYm6rFicI8kqU1arzqWadkAxvkXla2EYmY4Q5xMLz+TTB4lnaOVrxm+C7jwrQ/PeMBTgLPia8yaygLKEQ45xZ5zOXySWpz+cHAc7j3bDmoijyjSWR/nSxfI+5vtyQZU6B7tG00ZGGEYmwwhv4byS70LPK0GVeiDl20iW90BbgK8SDtSQ5Dh+0OWwoieU2zOkrNrv5ixTMV0sz//3x93075nG8gQUhhXL+6g0skaUZO/DJNe9iGOjW0uEYWQyknEbfE0sRoCneBKWqBW3kW+xO95jZoD846hYwjJoVy3yydoKx+Ig3inexoSyQvR1T/8DMUnC/XMnYea4agCZx/IEFCqpNYesvcFQvlx4cwju4r3YqtYIw8hkGGGx4ZWkOqD/IsgSmq7PWGnIO12f85gZQKEicqAYGWHxysdYDob5rdqvrBDtdljRF45hTFVR9rE8YXVUUuWYCIRjWY+RgAHctFrC76uHICeMkOnDKzypAyxRKy0+33R9IzQ7pkULdR4TyqBdnp9tWyI+pd0fzPrfkvFg57xqP20km8MLgVruY5vVAmfimgVyGKtGcGtrCb+jT5ATAQMEtPKKWesYJTMV1YkxMmsTWUDZ5kJfw0jpmuL5ehF7psOffVsKoyzOpD5TcQ4vGlT1U0GZIc93LoZRUCUly6iI1dNkiKy03DFr8LVqLUHy7I1liCwrToxl5WLHs2LksJE6PzmoKSoaDSwpccmGUS7HqabxR54jZYB3piSD3vm+9lohYoxMRmef/KYWy6HGRqFj2jpGKtW2ytfNRN2+HGdZ8VL0k/y+U9HYlhdIKjsAhBNj7cDJXtqaItNUdqMoRvkYIGqqpJ48xmry2gutBBCGkeno7o8AAKLCMMoas9Yxol3Z1ap8nW+6Psdvqa48z5EVPLvI06Wyv7bjGF7bcQxA5qnsRnCtAsnjyyuWRxVXWh7HJVxpKQjDyGSQCdxh4+ut0gjwog6wJhRRVzHK5XpFYnGqavKtGPFR4JHnVhnKVPYf/rEZHx3pxtymOtz55XEAskhlN4grLS9lJqxeAD0TJYvza68VWb1+PProo7joootQWlqKmpoaXH/99di3b1/KPrfeeissFkvKn4svvjhln1AohCVLlqC6uhrFxcWYP38+jh49mrJPV1cXFi1aBK/XC6/Xi0WLFqG7uztlnyNHjuDaa69FcXExqqurcffddyMcDmdzSqagwx9E8zEfmo/5cLJXlrRP9YXpto4cMkQKkXxjZnhFLRcFDUzOwfWYEjNjgLo8eqfrhzhu9VNT5qZtKOoSLrOKIgfdlmk/MaO4c9wMYnnUdKXlohj1G6AUhJZkpRht3LgRd955Jy666CJEo1E89NBDmD17Nvbs2YPi4mK639VXX40XXniB/r/TmVpwaunSpfjzn/+M1atXo6qqCsuWLcO8efOwY8cO2BLBewsXLsTRo0exbt06AMDtt9+ORYsW4c9//jMAIBaL4ZprrsGIESOwadMmnDp1CrfccgskScKKFStyuxoGJZ2U/YePjuMPHx0HkLmUXejwkprNkkgsTt2q7LPScnc9kjdUiwU0zZhH+FGM+K/5BChLOPCTys6apAGS+7jnN8aI72uvFVkZRsRIIbzwwguoqanBjh07cOmll9LtLpcLdXV1ab/D5/Ph+eefx8svv4wrr7wSALBy5Uo0Njbirbfewpw5c7B3716sW7cOW7duxbRp0wAAzz33HKZPn459+/Zh4sSJWL9+Pfbs2YOWlhY0NDQAAJ544gnceuutePjhh1FWVpbNqRkapZR91ysf4tCpftw8bTS+8cXRADKXsgsdMwZfKydJ1m+D+TRYDSoWep57MxEVcV+bHx3+YE7d1FlglFY/lcXyS3Au8eFGcefkFWOkokuUKFn5vKgIw0gmr1c1n0/OOqisrEzZ/u6776KmpgYTJkzA4sWL0dHRQT/bsWMHIpEIZs+eTbc1NDSgqakJmzdvBgBs2bIFXq+XGkUAcPHFF8Pr9abs09TURI0iAJgzZw5CoRB27NiR9nhDoRD8fn/KHzOglLJJxsq4mpKspexChyw6kZhkmqw+5STJvFdaHuUNjLLQk+M70hmgmVd6YISGuwBQnXgJsyB7y8gIlb2BpFHD27jn1WAzIjk/ZZIk4d5778XMmTPR1NREt8+dOxerVq3C22+/jSeeeALbt2/HrFmzEArJk0pbWxucTicqKipSvq+2thZtbW10n5qamtN+s6amJmWf2tralM8rKirgdDrpPgN59NFHacyS1+tFY2NjrqfPLaIlSO4oFx29XSesUC6orJUZ6nrMwW1ilDdUXgwRo7g6mGRscX6ONPsrjxgjNZq1ehgclzCMZHLOSrvrrrvw8ccfY9OmTSnbb7rpJvr3pqYmXHjhhRgzZgzWrl2LBQsWDPp9kiSlTNzpJvFc9lHywAMP4N5776X/7/f7TWccRWOy0lHvFSpRtiizo4KRGIpdxk/aVNMAyadXGu/tQEhtnlZfMnGB1OUBMq/NwwqjuZlycq8aoHcewEiZUTErLTclyxjXXitymvmXLFmCP/3pT3jvvfcwatSoIfetr6/HmDFjsH+/HBxcV1eHcDiMrq6uFNWoo6MDM2bMoPu0t7ef9l0nTpygKlFdXR22bduW8nlXVxcikchpShLB5XLB5TJ3vA2pODuy3KPzkRgPa6LfUDgW1z0LiRVqSvf59JbjXTFKl9Bw/+u76N+1TmigbiaOSxsAycW538Qp4548Wm+o2xIkd4NNtARJJavXNUmScNddd+H111/H22+/jbFjxw77b06dOoWWlhbU19cDAKZOnQqHw4ENGzbQfVpbW9Hc3EwNo+nTp8Pn8+H999+n+2zbtg0+ny9ln+bmZrS2ttJ91q9fD5fLhalTp2ZzWqaiX/iK8yKf7uA8ouZbeD5NZHl3+d48bTTWLJmJX3z9fLrtsQVTsGbJTKxZMhM3Txut6fHQKuGcP9cs1BRexwSBKjOcpevTXmmiJUjeZKUY3XnnnXjllVfwxz/+EaWlpTSWx+v1wuPxoLe3F8uXL8fXvvY11NfX49ChQ3jwwQdRXV2Nr371q3Tf2267DcuWLUNVVRUqKytx3333YcqUKTRL7eyzz8bVV1+NxYsX49lnnwUgp+vPmzcPEydOBADMnj0bkydPxqJFi/D444+js7MT9913HxYvXlxQGWlKlB24heWfG26HDT3BqGkMo6TLSr03VBKsnk2rCt7dJjVlbtSUuWlfLAA0mUEPjBJ/w6RfF+fnmFeFaU7rGBllfGlFVorRM888A5/Ph8svvxz19fX0z6uvvgoAsNls2LVrF6677jpMmDABt9xyCyZMmIAtW7agtLSUfs9TTz2F66+/HjfeeCMuueQSFBUV4c9//jOtYQQAq1atwpQpUzB79mzMnj0b5557Ll5++WX6uc1mw9q1a+F2u3HJJZfgxhtvxPXXX4+f/vSn+V4Tw6J8IIRilBu8NA1lRdJlxT6WJ59gdaMsgsogWUnSL1PRKFlphVBLJx8DJOkuZH8f86vIbYxrrxVZKUbDTQwejwdvvvnmsN/jdruxYsWKIQsxVlZWYuXKlUN+z+jRo7FmzZphf69QSKkmzHksAq+Q62aWIo9quqyUY6ylsx+T6jNXao2y0CtdC94ih27HwXtMFoFNjBHfYyIvVUxFdyE9Ls56uBkRvkegICuSD50VVs46cBsFsxV5JItNa3eAeWsYq9UCe2KcKbO3MsEo6kCR4vhKXfoZRkZR2HjN2GIJr6pYXmUEDHLttUIYRibCKIsNz5jNlUYmvIOn+lUpUOi0k1pG2U3GNJiY87Fqt1lpy5J+HVVEwwUmc1b8kCV5ZX+pqMzk2qpEkiTDXHutMH6hFgGFTJ5FTnFbc8Wdx9sgj6hRdoDU+AEAa6Jm2J7jfoyqKAKQWY0fo6RmA/IxhgPxnN7EWRE0SFIFOb5ITEIkFocjiz54RnmxY+FKU7OOUbZhAMoCrUZ4HrVArKAmImCQuA2eod3UDa4YEePl8Mk+uo1VgcJ0NX5+8fZn+MXbnwHIrMYPjTFi3KZEDYqcNvgCEX0NI4OU4VAeXyASy8owMsw55ljYVKnM8JSVphzXvBulWiEMIxMh+t3kDy/d1PNFzQKFyqbF335xO9r8IXzrkjOw4AK52GsmTYs7+8IAgKgBetIlA4qjuh2DUV56nDYrrBYgLsmGTpk787gswyhGieMLx+KIxuKwZ2j8hWNxkOHOU4FHsr/Tbs2q5IaZEYaRiaB9eBzituaKWYKvifHyzLufYe0uud7YYwum0Do8mRgvg0Fq/ABARZETbf4Q6so8WdX48fVHAACRGP/KHFkI9Ywx4r0gJsFiscDjsKEvHMt5geb9HJUvnsFoHCUZGkbBsMJlpWZWWpbKplEMUi3h+/VDkBVqlpsvFMgb+bv7TjDP4tKSmjI3mkZ64XGeXqCwaaSXWZ+vpCGZnZpC4hpcBigrUZRHTAkrjLR45ZI2Ho9LyaKfnM9fLoX7N5sxQa6Hw2bJysWYKWRshKJxxLNQYkVG2ukIacFE9FPFSAzwXCG1ed4/2ImOnpCmjULVIJfMmWwoc8tTSCYTvTJom7jSTvQEaeyT1o1ZM4UYl7nU5mGF0YLVgeyuV0oAMOfzF1HFApFYVi534opVSxFTXrdgNJZxEo6RxpZWCMPIRBgleJFneJfxs4W8DV55dk1e7rPBqCyRv9NuHd4wShf39OoHR/HqB0cBaN+YNVOK8kjPZgUtb2AAhY0GJ+egpgDGeAY9TtkwymZMqK36DVSyMjWMjOLC1BJhGJkIMcBzh6gZvkCYbmOVxaUnxDCa/4WRqhw/McL7MghMTgnafukDtPmCWQdt60HSlaZP8HVKNpMBXnpyyY4KGiwAmJ5jFsaf2sqM1WqBy25FKBrP6trTxuOcB/ZriTCMTEQ/rWPE/+TJG2pmcemJ2m+pxVnE3yiDtsnSN7GuVLfGrJmST5sLFpAmvYAxXnrIMWZzvYwUQwUoOtlnoxiF1a9F5XHaEIrGs3LxCVfa6QjDyEQYpZ8SjxA1Y11zG55+R67HwyqLS08CKhvLJP4mE8VICRmrRgi+zkUdYIkyQ9IfDMPr0a81SSYU5RB8rWxnZARyCTDXQtH3OGzoRoQaYZkggq9PRxhGJoIE9wnLP3uImvH5iV66jWRwGRm1J+OiHNWUcCJNf2Q5/+7JXM+RFcpYne6+CBordDmMjMmlLYjRXuryiaNSVTHKwY0pQjBOxxjmuSAjSI8co0wuPFJssnYqartXiSutP5RlG4LEWB1VWcT8mFijd1aacpGzWPiPv8mlmanRFudciilqkRyTS0sjo7kxtcBcq0CBIypf50+RS752lUUOw7rPlKj9Jk6Nhiwm4nA0TiteG6EYaVEOCggLSELAoVPs27qoiSeXGCODzV35KDNqxxgpfysTRDbz6fA/KwkyJhBJuNKE5Z8zRDHyOO1cLjrZIEkSda+qrRhlk7GV0pvJAJOxXi1BjJoQkIshaTTVIpcq01rFGAHmvvZaIAwjE2G0ty4eKU4oRr0h/fpisULt3kyAIl0/C1camYjtVgucBmkiC2jvSiMJAf9s6cZDf2gGYIyEgHzS9Vu7A+jwB7l/KcnJAKHzs3pjPh83plg3kgjDyESIGKP8KXaReBLjG0ZadM0mReSyq5tiLGUz167l+UISAtoVrWmMkBDgzkVNSex78FS/ISrO5xRjxKkrTYsyAkaD/9c1QcYERFZa3pCFPhKTEI7y3+B0KNTuzQQk1ZS+LBS2foMpm3rXMdKzFUku5NJ0l7zUGYWkKy2LtHhNstKyr68k6hidjlCMTITwFeePMhanPxyF0+7U8Wjyoz+sfkxDLg1WyTg1SiFSqorplZWW+N0zqoq4dZ8poTFGGVwvEmB+2KAB5jlVmFYx8zWXMgJq93AzIsIwMhEixih/HDYrnHYrwtE4+sIxlPOfTT4oahd3BBSux0gMkiRllE4e0GCBYEkuBQtZQhaucxq8XBoJA8nGzWTUAPP8gpxVjDHKo/CkeKFOYoyZSZARRnsT55Vipw3haBz9Bg/A1jI9OBaXEIrGM3rrNFpvpmT6uT7jgcYOGuS5zkZNIQHmv3znM/y1uQ2AMQLMc4mj0qSOkT0Xw0jEGA1EGEYmIRKLIxKTU5DEAM+PIqcdXf0R9BkstmMgWigzRYqxFgjHMjKMSFmJTLt/600y/TyOeFyCVeMmpwGjBavn0D9PeW5GCDDPxZXmC0QAACEVYxdziX0SdYxOxxivbIJhUT6gwlecHyRl3zyKkXqPuT3hegQy75dGs2AMMhErj1MPd5rRmkPn4no0aoB5NufYE0oYRioGmufj4hPrRhJhGJkEYvVbLYDLALVheKaINkY11mQ9kGSMkbrKTLYB2EZL13crGt3qsYAbrc5MLrV0SAbbVZNruXWfKSG1iLIxQIhBpGajXFHgkQ3G0LIFw6Ic3Ebop8QzJYmA4mxS0HlEqzfBYqcd3f2RjI0GLYLCWWK1WuBx2BCIxDRvCwIY73rl1C4jYSx/9fyRxgowH2bMk6w7AOgJyud4rDtAM+9YZ93lEnwtXGmnIwwjk2C02jA8Q2vzGLzIo1YuGE+W16vfYAoIIF/DQCSmi2KUDFY3xvXKpV2G0dyFmRp/6bLu/mvjAfzXxgMA2Gfd5VZGQH5ujf4iyBJhGJkEo8ntPENT0LPsGM8bWlTaBbJ3pRlNAQESz1WfPplpSUPSGNM1aQwcjUuIxOIZFRfVyu3LCo8zM5cVyboDgK89sxmhaBz3zZ6AyyfWAGCfdefJ0o0ZicWRyNlBb1AYRgRjjELBsAQN9lbJM+ZRjLSphJ68XtkZRkYaq7kUsmRF0GCGpFvRCywQiWVkGPWp3OyYNclYnqEDqUnWnSQlK+lPGaVe1l22sU9KZcllkPIZWiAMI5NgNLmdZ5L90oytGGmV/ZWsDJ2tK80400+ylpEOrrSIsVr9OG1WWC1AXJKNujK3Y9h/Y7RQAKXLKpPCpqFoHAlhJiWYnzWZFtcksU+n+kJ02ydtPdSI5bXiuFYYZ2YSDIlwpbEjl/5fPELrBWnkSss8+NpY6gCQW3NOVhjtpcdikYPV+8KZx2QZzb1KgpxjcQmRmASnfWjDSHkdRleqV04/U1dautinBwxQcVwrhGFkEkTKJTuKnWZRjLQxlrM2jAxYoV3PfmlGMxoAWQ3sC8cyMiTD0TiicVlPIfFJvKOcZwORGK3lNRjEre2yW1Ff7lHvuJyZufhI7NNnHb1Y+upOAMaoOK4VxhiFgmERfdLYUeQyh2KklXuiiBqSGbrSNGhuyxoPNf60HxNGNCRJrEsmhpHS2DTK/OWwWWG3WhCNSwhGYvB6hnYXapYhmnimwrE4orE47IPEd5HYJ+XLjBEqjmuFiLYyCUnFSNi6+ULrGBk8+ForFTHpejSn2wRIuiP79XSlGTAmKxOFjcRQOWyWYZUXnsjqHDXKulO+bLR0BYbd3+hznFoYZxQKhiQ5eYpbmi+08rVJ0vXVNkCyr3xtQMNIp6y0WDyZzWQkN3kuRoORzg/IrpgiaS+k9phXdj042tk/7P6kJElDubvg3WdKxCpqEpKLoHHeKnmlWEe3CUu0cllRV1qWKcJGUjfdWcZRsUI5Bo1kSGYTrE4WZ6PNXdkUU6QvAy51z9FisVDjKJNmtUQxmlhbWtBZaAMx1kgUDErAgHEbvFLkModipLUrLdOmu0aMhyNBwVpnpZHfsxisB2J2RoPxshQBwGGVM9FauwPA6Ioh96V1mlR6FpWtR2yJ49p93Ic6r2zsDJZ+n1SyhCmgRFwNk2BUOZpHzKIYaVVN2JOFmiJJkiEXQr1cafQeGqwHYjZtQYzYIgYArDb5frT7g8PuS65DsUudc0yXfv/UW/vx1FvytsHS7/sM6NbWAmEYmQSt4kkKAaoYGT1dny446ioNxVlkpYWicSQysw21EOqVlWa0woeETAsNAsYMxgcAd1YuK3UD6JWtR25/6QMc9wXxfy85A1+7YBSAwdPvkwabMAWUiKthEkQdI3YQxSgcjWfc64lHtMpmyqaOkbJVgZHGara1mlhhVMMoG4XNSFl3SpcVCYr//EQvmo/5AAzusiJFTYtVuo8k/R4AqkpcOO4LorrENWz6vdFasWgF/yNRkBHkTdYtBnjeKF1P/eEYvB7jGUZaZjMVZdFChezjsFkMZXDq5UqjSrCBAtUBZS+xTBQjbSq0syCdy+p/dxzD/+44BmB4l5UWBm5JFnXYSOC7UIxSEVfDJAQSlU6NMLnwjtNuhdNmRTgWR384OmzxNh5RujC0StfPxM1k1Fg44hoSilFmZNNbLpmxxf85Kl1W//7nPXj/UCeuOrsW91w5HkAGLisNVLGqkszT7oVilB5hGJmEoEEnUF4pctkQ7o8btvo1mYi1yGbKZhE0alkJcryZdi1nBTE2DWdIJuahDw53osMfHDIV3Eh1rZQuq1GVHrx/SA6oHs5lRe+jBudYmzg+Ess3FP0aGmxGwjhatmBISPVYka7PhmKDF3kMKJQZtbOZiAwfisYRG2Y2NqoColeMkVEDk4lyvbe1h8bkDEYyS9FYizOpkN+bwcuTltlfZW5Z4fYHI8PuS178jKDWaYkwjExCIJxwpRlsAuUV2ubCoCn7WgbjK8fccO40oyogemWlBQyayp7N8RrVvVqfqBEUjQ2flaalK63ULf9GTzBz17ZYN1IxlokuGJS+kPx2kGmRPcHQ0IBioypGGi6oLrsVVoss3feHYyh1Dx6TZVgFJItKziwx2sJFsrZOKFQikrEFpM/aMuqYGFVRBAAIZpKuH9LOlVaWiIn0B4ZXjIyq1qmNuBomQJIkBBPB10ZVOHij2OCKkZbKjMViQZHTjt5QdFhXk1EVEJIVFolJmpZwCBhMTUmXtXX/67vo39NlbRnN+CMkDZDh5wgy7tUq8KikLKEYZeJKEzFG6RFXwwSEY3GQyA6n3ViTC6/Q/l8GLfKodcFPj9OWMIyGc6UZa6EnuBVFMo909uOsESWa/G7SkDTGVE2ytva2+fFv//MxAOCxBVNocHK6rK1+g50jgRggvgyUGaoYaVB2IRvFSMQYpcdYI1GQApGtexRvBp939NKgwMGKjQmGpziLWiA8olUDWUKx04YTGN6QNKrbxGlLuguPdmlnGBlNTSFZW0pFsGmkd8isLbWLH6oFKeORiTKjdksQJcng66HnLrk9j1CM0iGuhoFJJ1s/9Idm+vfBio0Jhqc4i6KFPKK1AeLJUGEzUpVjJRaLBW67Df2RGHVba0HAoHVmlLW/zJqpSJSZnmAUsbhEm7emQ9OsNE/ClTaMYhSOxRFN3BuhGKVirNlJkAKRrQ+d6sNdr3wEYHjZWpAZRo8x0jqWhzbeHUZhCxisp1/aruXHfBhZ7gGgviqrtfLHCqVhNJzbVKtmx6wpUyQZ9Aaj8BZlknSgRVaafByhaByhaAyuQcIrlIklojBwKsYaiYIUiGwdiiYH+HCytSAzimgdI4MaRjSWR5tHPJnOPpwrzVjp+ulU2V+8/Rl+8fZnANRXZY1mSBIcNiuKnTb0hWNwDFNg1KjVl512KzwOGwKRGHyByKCGUSQWRzimXTmVUpcdFgsgSbKa5SpJ/5vkujvtVtgN1J5HC4RhZAIyqVchyA4SC2DUdP2ke0KbCY9M+Gs+Po4vja8eVEUxmttE2QLizlUf4nBnP/5l2hh8/YuNANRXZY0akwUA5UVO9IUDwwYnG21MKPF6HAhEYkPGGSlfFrRQjKxWC0pcdvQEo/AHIqgepEVIsraS8a672gjDyASQ6swNXrdwnzGCKkYGdaUFNSzwCCSDN9/ZdwIdPaHBDSODKSDKFhA1ZS4c7uxHZbFDM1XWqDFZgByDc6w7gO7+8JD7Gdn4K/PY0eYfOp6HZGrarRY4VW7PQ4/L7ZANoyFemvsM6sLUAqGfmYDeRHHHSfVlIguNEVQxMmjwtdYLaqZv+0GDpusDQAmtD6OdsaxlBXPWeD3Dp7OHo4oAYI3cviwhsVRDnaMemYWZpOyTeEAtMuWMhvFGouA0ehOKEUnTF+SP4WOMNFpQSXByQGFADlXp2Mhuk9pS+TyGy7JiiZHVlHKPE8DQi7Ny3BhxTGTSl0yP4PJMijwKxWhwxBUxAb1BYvmL28kK4ho6fKp/2O7gPKLVgpptpeOkK814Y5VkokXj2qXra9mVnTVETenuH0K1SDS/dti0czOxJBPFSI8iiiQzbaiq3GRsCcXodIw3OwlOg8TBkOaBgvwhk8WpvvCQMTO8opViRIKT/9Lcil+98zmAoUtGGLUuDwCUFw2/0LPGqFlpAGiWViZuJiO6CoHM2oLoEVdHaxkNpRiFjPuSojbiipgAkpUmqpeyw+jqmy+xeIcz6PydDyQ4+UhnP902VMkIstAbrS4PAHiLZNeQVoZRJBZHJCa77YxoOGQUf2Pwxbksm3PUMIaKuvgyCAoXWWmnk5V2+eijj+Kiiy5CaWkpampqcP3112Pfvn0p+0iShOXLl6OhoQEejweXX345du/enbJPKBTCkiVLUF1djeLiYsyfPx9Hjx5N2aerqwuLFi2C1+uF1+vFokWL0N3dnbLPkSNHcO2116K4uBjV1dW4++67EQ4PnQFhRnoTUm2JUIzypsMfRPMxH1oUC33zMR/90+EP6nh0meNPBOSHNOoGXz5EcTslxo6ZSShGGfSgYkEgYuz4G28G16vfwAoikFksDz1HDV1Wyqrcg0EUIyNmPKpNVobRxo0bceedd2Lr1q3YsGEDotEoZs+ejb6+PrrPT37yEzz55JN4+umnsX37dtTV1eGqq65CT08P3Wfp0qV44403sHr1amzatAm9vb2YN28eYrHkRLBw4ULs3LkT69atw7p167Bz504sWrSIfh6LxXDNNdegr68PmzZtwurVq/Haa69h2bJl+VwPQ0J82CXCV5w3q7YdwbwVm3Dbix/Qbfe/vgvzVmzCvBWbsGrbER2PLnPCibYVWikzFQk1xeOwDlkygozVgAHLICRdadq8fBEj0ma1wGnAAnwZKUYaV2hnTUaKkR5ZaZkYbBGhGA1GVqbiunXrUv7/hRdeQE1NDXbs2IFLL70UkiThZz/7GR566CEsWLAAAPDiiy+itrYWr7zyCr7zne/A5/Ph+eefx8svv4wrr7wSALBy5Uo0Njbirbfewpw5c7B3716sW7cOW7duxbRp0wAAzz33HKZPn459+/Zh4sSJWL9+Pfbs2YOWlhY0NDQAAJ544gnceuutePjhh1FWVpb3xTEKJPi6xJXZW7tgcEjMTDwu4bpf/gMSgAe/MgkzzqoGwHebFWX7CjIhHu0O0CwxNdtXEMMoHJMwYpBrJEkSAgmDrdeA2X4ky0orVxpdUB02WCyD9+HiFWJI+oa4XkZWEAFFI9mMDCMNXWkZpesnjsvgYQNqkNdriM8nT7iVlZUAgIMHD6KtrQ2zZ8+m+7hcLlx22WXYvHkzAGDHjh2IRCIp+zQ0NKCpqYnus2XLFni9XmoUAcDFF18Mr9ebsk9TUxM1igBgzpw5CIVC2LFjR9rjDYVC8Pv9KX/MgHClsaOmzI2mkV6c21hO37oayj00bobnIGyids1bsQldicXomXc/10TtIotgLC4NWucnFE3GOw3Wv4lnSDBxIBKjBTTVhLhg3AY3GjJTU4w5d5FYnqHPUXt3YVkGNbf6RIzRoOQ8GiVJwr333ouZM2eiqakJANDW1gYAqK2tTdm3trYWhw8fpvs4nU5UVFSctg/5921tbaipqTntN2tqalL2Gfg7FRUVcDqddJ+BPProo/jxj3+c7alyT69wpalCqdsOXzA6ZMYJT+ipdrkdNto3qrs/nNJElChZysXj8xN9NMBd7UasrChz22GzWmTjLxBR3U0ZNHBGGpBU2IYyGoycpQgoFKMhDBBdFKNMgq+FYjQoOV+Ru+66Cx9//DE2bdp02mcDZV9JkoaVggfuk27/XPZR8sADD+Dee++l/+/3+9HY2DjkcRmBpGEkXGksqSpx4Wh3EEbxYpAMMX8wAlKCcOqYCs3aV1QUORDwxdDVH8GYquT2dLWOHnxj8FpHvGKxWOD1ONDZF0Z3IKK6MWf0VHZiNAQisUG7vBu54CeQTIvnTjHyDF94UihGg5OTYbRkyRL86U9/wnvvvYdRo0bR7XV1dQBkNae+vp5u7+jooOpOXV0dwuEwurq6UlSjjo4OzJgxg+7T3t5+2u+eOHEi5Xu2bduW8nlXVxcikchpShLB5XLB5eI3RiRXekVpd1WoLXMD8Gla6ZgFyrdELV1W5UVOHPcF0TUgOJkoWfvbe/C93/8TwNC1jnimnBhGGsQZ6RG0y5JSd7LLuy8QQU3p4IaRUc+RGH/haBzBSCytiqhP8HUmBR6N7cZUk6xijCRJwl133YXXX38db7/9NsaOHZvy+dixY1FXV4cNGzbQbeFwGBs3bqRGz9SpU+FwOFL2aW1tRXNzM91n+vTp8Pl8eP/99+k+27Ztg8/nS9mnubkZra2tdJ/169fD5XJh6tSp2ZyWoQlH4wgnYjdKhWLElMpi2RXQ1WesEhDk7bXIadPU6KgoTp+1ReK2qhXHQmK2eI/bGgiJMxpo/KlB0OAZW1arZViXTlJNMebiXOy0w5pQlAc7Rz0KKRIlKxCJITJILTNakdug40tNsrpTd955J1555RX88Y9/RGlpKY3l8Xq98Hg8sFgsWLp0KR555BGMHz8e48ePxyOPPIKioiIsXLiQ7nvbbbdh2bJlqKqqQmVlJe677z5MmTKFZqmdffbZuPrqq7F48WI8++yzAIDbb78d8+bNw8SJEwEAs2fPxuTJk7Fo0SI8/vjj6OzsxH333YfFixcXVEaaspeXUIzYUpEwjDo1Ss9mBXlLbCj3aGp0lBcRQzL9AqFlxWi1ILWMhsq0YkWbT66ZZYVBfLlp8Hoc8AUig957o7sLrVYLyjwOdPdH4A+md68GItor+sq+mT3BKH3JSz2umObHZRSyMoyeeeYZAMDll1+esv2FF17ArbfeCgD4/ve/j0AggDvuuANdXV2YNm0a1q9fj9LSUrr/U089BbvdjhtvvBGBQABXXHEFfvvb38JmS96gVatW4e6776bZa/Pnz8fTTz9NP7fZbFi7di3uuOMOXHLJJfB4PFi4cCF++tOfZnUBjA5xo7kdVtgNWOuEZyqLjKkYkbiCMo2zFCuGqfNDlKwzq4sN5T5TQoy/7oD6Y+JEr1x6wSgxbukYLjPN6On6gOy26u6PwDeI24oWUtTQ+LPbrCh22tAXjsEfiKQ1jERLkMHJ6opI0vCxFhaLBcuXL8fy5csH3cftdmPFihVYsWLFoPtUVlZi5cqVQ/7W6NGjsWbNmmGPycyIwGv1IIpRl8GUDrIIlXm0HROkltFg14sc14VnVBjKfaYkk8aorAgZuH0KYbj+cjTOxcCZUcPVMiLGn9Zthso8DtkwGiQAO9kSxLjXXi3EFTE4IlVfPSo0jCdhCZmgvRobRuT3BrtePp2OiyUVVDFSxzBSFuk82hUAID/jWhTpVIPhKkPTBqsGNv6Ga9hKKkxrHStW5nag1RdMG4Adj0sKo9S4114thGFkcGjVa1HckTk0xshwrjR5TJDAV60gRsNgiyBxsRF3lBHJpJpzPqQrbbD581OYt0Iui2KU0gaE8mEMI19iTAwWIGwEhnMXknpBWiszxGB75f3DmFBbkmJQK/vwCcXodMQVMTg0VV8MbuYYNsaIutI0jjEqzkwx0trFx5JylVVEUtoAkGs9fXzUh3nn1uO7l50FwFilDYDhjQbS5FSLSuJqMXzmnT5xVOS4/rKrDXdcPi7FMCI1jCwWOT5VkIpYTQ0OMYxKhWLEHKIY9YVjg9Yo4RFqGGmsGGWalVZuYMNI7RgjUqQTSGajTagt0axIJ2uGM4xCUePHURFD/+1POnDjhY0pBkg8LlF1RnNX2hDPGa16bdA+fGojVlOD00djjMStZI2yBUR3fwR1XmNM3iTWQetYHhp/Y+IYo/Jh3IUs8QX1MXBZQl2PiuuljKMimVzHNGp2rAZkPH94pBsdPSHdXVbk+kaiyd8m1xaQr68Zgt7VRFwVg0OkaK0zHgoBi8WCiiInTvaG0NkXRp3XGJO1fllp8u/1hWMIR+Nw2lMlenJcZLE0IuVUMVLfvUpees6oLlb9t9TCm+Z6pYujWvH2Z1jx9mcAjBdHNVRZDOKyAgB/IAyP06P68aS7vve/ntqC50vj5f6Joh1IesRqanCoYiRcaapQWezAyd6QoTLTSBaK1kpDmdsBqwWIS/JCOPCt3xyK0dDGHyskSaLXa1xNiSq/oQXpstJIHJUvEMHN/y23dXr4+iac11gOwDhxVOmaIw9UZpSK0YneMGq96htG5Pr+tbkNv3xHNjYHtuDZ29YDQA7F6PAHDaXQaYFYTQ0OTdcXwdeqQFwnRspM08uVZrXKTVa7+iPo6k+tAhyOxql8T7quG5EytyOl/9cIlRbx/nAMoUSrn3TF+YwCudfHuwN0ASZ/Pm3vofud11huuDiqTJSZOefUaX1Y9Pq2+4N0G2m/Q9hxuAsAcLI3fJr7TyAMI8PTIxQjVakcJm6GR3w6ZaUBcpyRbBilXi9yTBaLsRMFiPHX3R9Bd39YNcOIGOIuu9Ww7TKAZG+5QCSO9gHKxIlEnJFRIcrMkVN9uOOVjwAklRn5/knYdayb7j9QTVLbGKkpHfz7+8LGzQLUAuPOUAIASVeaiDFSh2QtI2NUv47EksqMHkG75YO0BfElWmiUuR2wWo2dBVNODCMVA7CJYVlZ7DR01pAyA5EoYISTiZYno8o9hnGfKSHKTGNlEd02PpFB+NSGT4dVk9SOo6otS17TqsQ8Rtx/n3Uk1TqtDTYjIFZTg0MKPJYKw0gVKoepzcMbJBgf0EeZGawtiBniiwjeIidwqh8vbT6EMZVFqiwkRDGqMGgxTLIAS5IEmwWIScD2Q500Lb+m1EUVowvGGLdFDCAHXztsFkRiEi1VQdSkP+w8hv/++0EAp8f5qE1ViYvG/NkSLyOZuP+MFPiuFmI1NTi9wpWmKhUGizEiBkiJy65LU2Fay2iAIUlrGBk4I41AVJA/f9yK71x2liqLulIxMiLpFuD/XLcP/7luHwB5AQ4m0smrS4ynFimxWCyoKXXjWHeA9hMlatIfdx6j+w2M81Ebm9WC6hIXOnpCaPfLcUTEYPvlO5/hr81tALQ32IyAWE0NTq9wpalKZXH6hZ5XksUd9RkPFYM0DTWTYqSFcUdctxUGNYyUFbzvXPUhDnf24+Zpo/GNL44GIC/AxEiqLjXmOSppKJcNo3AstdF6m1/fOKqaMtkw6ugJAvBSg01ZaVxrg80IiNXU4NDK18IwUgWj9UsjGWl6td0gRsOm/SfQ4R9L1RRiKBnZMCLuoXg8ufipFZ9B2tBUGlRhU1bwbqwswuHOfnictpQF+EQixmiEwRUjAPRclZlgANDmkxsBz22q00WNqS11oxl+tA8w0I51BzQ/FiMhVlMDI0mSCL5WGaP1S9O7Hxlxpe1p7UlJAzZDcUct4zM6EwqlURUjJVUl8jmc6k1dnE8mYoyqTeC+qU1kgLX3DDCMEobSt780Vpc4KvKbHYrjkiQJx7pkw2jRxWOE+ywNYjU1MKFoHJGEdCtijNSBxhgZxpWmT3FHwmDBwmZwpRH30NuftOPJDbKBpFZ8BlWMTGAYnVElZ231hlJTxE+aSDEiGWAdCmVGkiS0+0KJz/UJLidjUqkY+YNRmq7/4FfO1ryHmxEQq6mBIWoRoF0fnkKDdIwPRuIIhGPcTyJ6FXckbiZlmr7SzURcDEYu7kjcQ4FIDEgYRmrFZ5wyeFaakvG1pQBSSzjE4xI9R7VqQWlJbRpXWmdfGOFYHBbL0DWFtDiuEwrFiKhFlcVO7uczvRCrqYEh8UVFThtNxxSwpcRlh90KROPA/o4enDuqXO9DGhK9ijsO52YiqoGRFSPCaEXdmmgsPsSeuUMUoyoTKEZ1icW51ZdcnLv6w4glYrXMoIrVlBFlJnmO5Hyril2qtY4Z9rjSKEbHE/FFDeXGLZGgNsIwMjA0VV/EF6mGxWJBqVtuc3HgRB/3hlEyK01bA4S4mXpDUXz911sBAMvnn4MLx1QAAB54/WMAyUrIRmZEiYvWrYlLw++fC10mijEizZc7/HLgutVqoYHXlcVOOHQoK8EaoswoXWnESKrXsfl0bZoYo+OJgPCR5er3bTMqYkU1MKS4YzgaF40AVYT0/+oJ8l/92p8YE1orM8ospFK3HT3BKKqKndTNRGIazKAYWa0WNFYW4cCJvpQmoayIxyVaINMUakqpGxYLEI7F0dkfRnWJCyd7ZMOvusT45wckDZCeUBR9oSiKXXaqGOkVXyT/tqwYnegJIRaXYLNaqCutQRhGg2J8U72AIYpRdyCCDoP3HeKNDn8Qzcd8aD7mgzXRkoH8f/MxHzoGpOXygt5ZaUByIWhTuE78JshKU9JYIbvTWjr7mX93TzBK3UxmuF5OuxVVxfICTcYECbw2enFHQonLjuJEvA6Zi3lQjJTVr0lWIEnVF4rR4AjDyMD0KoKvBWxZte0I5q3YhHkrNuHAyT4AwKsfHKXbVm07ovMRpkfvAo8AMIZmIcnHIkmSKeoYKWmslBeVli72hhHJgCxx2eGymyM4lhgHxDAi7UDMEHhNGBiATRSjOh0NI1L9GkgabMeFYTQswpVmQEgG0L520QhQLZSVe//77wfwh53HMaG2BE/e+AUA/JbO17vAIwBMqC3F3/Z2UGOoPxxDlCggBs5KU5JUjNgXyqN90orNYUQCsnGw65gPrX5zKkaAHIB94GQfNYzIf+t0notJ9et2fxBNI71UMRKutMERhpEBEY0A1UcZMzNzfDX+sPM4Ovwh7kvn+zmoF0Syto4k3EykC73TZoXbYQ6RmpyjGopRsuq1OYxIIGkctBPFyISG0cAAbB4UIyBZ/bqjJyTHoyaUo5EVwjAaDGEYGRCiZjy8di+2HDgFQDQCVJMzqooBkFiuoG41SYZDkqRkgUcdDSOiphDDyEfcaEUOWCzmKCvRWKlejFFSMTKRYeRNTdkvBFdaOyeGkbKUQLs/CEkicV/mGV+sEYaRASFqhrL8vGgEqB6jK4tQUSRnpu057kfNRD4No1A0jnCirk5IhWypTCFqytGuAOJxCd0BeaGPxsyTPUmMv5O9YfSHoyhiWGCVxBiZSTGiMUZ+2Y1zstdcWWmAomZQTwi9oSh6EjGgurvSEi9yb+1tx4REsc2R5R7TvKSogTl07QIkFI3h8Cn2b6uC06kpc2Pm+BEAgD2tfp2PZnBIRhqQWhVda+rL3bBZLQhF4zjRG6Luva5+82RPeoscKE0EuB/tYhtn1GVGxWhApiJRU8xUmJYoRh8e7sTuRMxnqduuex9LclzNx/z46EgXAHO0YVETYRgZlIMn+xCLSyh22nDPFeOE+0xlJteXAQD2HOfXMPIrDCM93wYdNiutqnuks58GYZsNtVL2SXCsXtWS1UDpSovFJVrAUpJUqpCpA8QAOdYdxI7DsgFSzYFxq1wbiBHv1bgyvtEQV8egfNreCwCYWFeK7101UeejMT+TG/g1jEiW4kdHuuk2vbMUGyuK0NIZwObPTqJFoajofVwsaaz0YE+rHy9tOYQpI73MzoXUyLKZyNVBDKP+cAwfHekCMYf0anasBqSYIgC0dMolPsp1dIeSeaE/nHSr/+OzkwBkpc4sbm01EIaRQfkskapPfMYCdSGK0YGTffjJuk9w64wzuJlUeMxSHF1ZhM2fn8JTb/F1XCwhsVQbPz2Jjp4Qs/FASy6YyGgoctrhcVgRiMTxh4+O0e2ftPXAnmgJYlRDmRggQUVc31t7TwAAHDb9DJB08wKpjL9udzsqipy4+eIxhr3uaiIMI4NCFKNxNSU6H0lhMKLUhZpSuR7Ir979HF+ZUs/NZEKyFL//v//EnlbZYNY7S5FkbY2pLMLhzn7YbRZEY5Lux8WSRkUz2XwhiyuQDEw+1ReiCpsZFi+nTTaMViqKo5rBUE5ngJByBO8f6sJTGz7VxQAh88KqbYfxu/dbTvv8d9tb8LvtLYa97moiDCOD8mmHUIy0ZnJDGTr2yW+CnX1hPLXhU8w5pxZv7m7HzdNG67Zw1ZS5UeK2Y39HL92md5YiUVMOJ+JvLh5bhU2fndT9uFhAjJiYooPs5s9OYtW2w5jbVI/qEmfWYyLd4vrsewfw7HsHABjXaFAafFUlTviCpPG1Db2hGB78yiTMOKsagHENZV4NEJK9/L0rJ2Da2CosfXUnFl08Bi9vPYxHF0zBFJO8oKiBMIwMiDIjTRhG6kMmd2Umx5bPT+KZjQdgt1rw87/tp1WyV207ooux9MGhLkRiEqpLnFRx0JOBasql46uxKRHfYHTSGTGP/PUTAMDv3m/BNy5qxO+2t2DqmIqMxwNZXH//QQte2nIYgP6qHwvSXSsA6A3JbqeDJ/pw+6VnaX1YTElngCyZNQ4r3v6Mi3tYU+amnoWpYyrw8tbDmGKCFxQ1EYaRAfngcBfNSFMG/AnUId3k/sxG+U3+iQ2f0m0dPSH8/G/7Mba6GD//2366MN48bTT9HuUiSbaxMKBIoc8vjq3C+JoS3RfS0QrDyG234uopdegLx3Q/LhYo28X84m/7sX5PO/3s/11zNsbXlOB321vQ2RdOGQ/pjGfleBhR4sQfdybjb8ygrimv1faDnfjxmj349+vOQZnbgaWv7sTcKXU6HyE7lAbIWSPk//JyD2tKXbjnivGoNFGbGTURhpFKdPiDg06AwOCT48DP0m0jRfwaK0WRLi0gk3tnXxirth3Gm7vbT9vnoTd24YLRFQAAf6KgIVkYycKQbpFUGlC5jpE559Ti9Q+PAgBmTarB/5k6St0LMgREXZMkCS67FaFoHGfXl8EfiNJzNjpEIejwB/GVKfUphtF/rN2LkkTdmr82twJITecfaDwrx8M/j3bDF4jS62YGlK11CBeMrqAL9aS6Mp2OTB14NUBqytz43lUT0OEP4p4rxpviBUVNhGGkEkNNgAAy/izdttmTawAAoyuL9Tm5AoNM7k9t+DStUQQA/zzqwz+PyoGy/7F2LwDg6bdllelPO4+iaWT5oN8/mLKQ6Rip87rRnujPNP2sKibnnCvp1LWPWroxb8UmAMaNlUnH4G4iOY6GjBWiKj70xi6MSvSnOpJI51byZnMbAPkenjeq3NSLF1mozQbvBohZrztrhGGkAh3+IHYlskn2HJf/S94ae0NRFDlsOX0v+Y6PEwuww2YxVdYK79w8bTTGVhdj6as7cdNFo/Dq9qOYUFOCTxVBzwAQjslBuZ+dkBe/X//9EP3s//ujnIVz1ysfwpVoqPqbf8huudXvy9k6f9p5DCWJqsoHT8rf3ZNI4Y7FJQwsFrzraDcAuVbMSJ07ZitdJ+99egI/eXMfF3EWanDztNGYOqYcf93VhhGlLvzi7c8wdUw5dhzuTru/0nh+coNsUH3/f/8JALj1hW041Svf47HVxbhqci0NWjbLc03UFDONgcEQBoixsUhmKj2aJX6/H16vFz6fD2Vl+Uu6xI3wPx+04MVEAOVQ2K1ANA647BaEohJKXLLB1BuKodzjQHcgglEVHtitwKFTQ7cdMNObOM8QF+nUMeX45m+248fzz8GP/rQbP55/Dk70hPD0O5/pdmyT60tx/9xJqCx2cWEoNx/zYd6KTVizZCYXcRZqQs71pW99EZ19YSx9dSduvHAUfv/BUYyu9OBIZ25tQ8RzLRCkh/X6rcQ8Nec5YNW2I5i3YlNGRhEgG0UAEIrKtmlvKEazNboT7R2OdgWGNIq+cVEj1iyZSWNPBOpC3gQri+W3Xm+ii/3UMRW4ukkOJF2WWMi+dckZ8n9nnIGvnT8SAHBOg5xFWFPKviLuntYefPM32zFvxSasUtSKEWhHZbGTBuCSNPTbZp4JAPjx/HOw5MvjAACXT5A/mzJSntAvOasKsybJ/fge/MokrFkyUzzXAoFOCMOIITdPG401S2bipW99kU6AX54oT3aXjKsEAFxzbh1mJ1wN5zeWAwDOTUyO08+qxPQz5f3IAjqprhTjExPt2XXythsvlINrf3bTF/C9qyagiWE7AkFmELfAhNqS09wDJFX93FHlAIAFU0fh/84cCwBY/CU5NfmnN3wBP7vpCwCAmy6S7+fchGE1/7x6zD+vHgBwyTg5ZmjGWfK4mHtOLeacI4+fC8+Qv5+MsSWzxuGlb13EzYJaUK4TxbkODMBVGs9zEvf4+vPle06Mpge+cjbuTbT2mXFWNc1mEs+1QKA9wjBiSE2ZG00jvbh0wgg6AV73BVkpuGGqvFD962XjcPcV4wEAt8w4AwDwrcTk+NBXJuOhayYDUC6g5+GpxAL6ncvkbeRNdFxNiZg4dYIoR5MbvPjeVRPkAO0BxtJQmSlKZWH6mfL9nHOOPGZuv/QsWtvlhqmNAIAbL5THz52zxmPJLHn8/Mu0MwAkx9icc+pw6YQabhZUco14OBa1UZ4r+fukurJBjWeBQMAvIvjagFQWO8VEyyHKgMvJDd7TMlPSLZI8pvYK2DBwPBCU4yDdeBDPtUCgLyL4WqXgLTXrGOnZfkLAnoFjJZc6RmJcCASCQkLN9VsYRipdWIFAIBAIBOogstIEAoFAIBAINEAYRgKBQCAQCAQJhGEkEAgEAoFAkEAYRgKBQCAQCAQJhGEkEAgEAoFAkEAYRgKBQCAQCAQJhGEkEAgEAoFAkEAYRgKBQCAQCAQJhGEkEAgEAoFAkEAYRgKBQCAQCAQJCrqJLOmG4vf7dT4SgUAgEAgEmULWbTW6mhW0YdTT0wMAaGxs1PlIBAKBQCAQZEtPTw+8Xi/T7yzoJrLxeBzHjx9HaWkpLBYL0+/2+/1obGxES0uL6RvUinM1J+JczYk4V3NSiOe6Z88eTJw4EVYr26igglaMrFYrRo0apepvlJWVmX6QEsS5mhNxruZEnKs5KaRzHTlyJHOjCBDB1wKBQCAQCAQUYRgJBAKBQCAQJBCGkUq4XC786Ec/gsvl0vtQVEecqzkR52pOxLmaE3Gu7Cjo4GuBQCAQCAQCJUIxEggEAoFAIEggDCOBQCAQCASCBMIwEggEAoFAIEggDCOBQCAQCASCBMIwUoFf/epXGDt2LNxuN6ZOnYq///3veh9S3jz66KO46KKLUFpaipqaGlx//fXYt29fyj633norLBZLyp+LL75YpyPOneXLl592HnV1dfRzSZKwfPlyNDQ0wOPx4PLLL8fu3bt1POLcOeOMM047V4vFgjvvvBOAse/pe++9h2uvvRYNDQ2wWCz4wx/+kPJ5JvcxFAphyZIlqK6uRnFxMebPn4+jR49qeBaZMdS5RiIR/OAHP8CUKVNQXFyMhoYGfPOb38Tx48dTvuPyyy8/7V5//etf1/hMhme4+5rJmDXDfQWQ9tm1WCx4/PHH6T5GuK+ZrC9aPq/CMGLMq6++iqVLl+Khhx7CRx99hC996UuYO3cujhw5oveh5cXGjRtx5513YuvWrdiwYQOi0Shmz56Nvr6+lP2uvvpqtLa20j9/+ctfdDri/DjnnHNSzmPXrl30s5/85Cd48skn8fTTT2P79u2oq6vDVVddRXvvGYnt27ennOeGDRsAADfccAPdx6j3tK+vD+eddx6efvrptJ9nch+XLl2KN954A6tXr8amTZvQ29uLefPmIRaLaXUaGTHUufb39+PDDz/ED3/4Q3z44Yd4/fXX8emnn2L+/Pmn7bt48eKUe/3ss89qcfhZMdx9BYYfs2a4rwBSzrG1tRW/+c1vYLFY8LWvfS1lP97vaybri6bPqyRgyhe/+EXpu9/9bsq2SZMmSffff79OR6QOHR0dEgBp48aNdNstt9wiXXfddfodFCN+9KMfSeedd17az+LxuFRXVyc99thjdFswGJS8Xq/0X//1XxodoXrcc8890llnnSXF43FJksxzTwFIb7zxBv3/TO5jd3e35HA4pNWrV9N9jh07JlmtVmndunWaHXu2DDzXdLz//vsSAOnw4cN022WXXSbdc8896h4cY9Kd63Bj1sz39brrrpNmzZqVss2I93Xg+qL18yoUI4aEw2Hs2LEDs2fPTtk+e/ZsbN68WaejUgefzwcAqKysTNn+7rvvoqamBhMmTMDixYvR0dGhx+Hlzf79+9HQ0ICxY8fi61//Og4cOAAAOHjwINra2lLuscvlwmWXXWb4exwOh7Fy5Up861vfSmmqbJZ7qiST+7hjxw5EIpGUfRoaGtDU1GT4e+3z+WCxWFBeXp6yfdWqVaiursY555yD++67z5AqKDD0mDXrfW1vb8fatWtx2223nfaZ0e7rwPVF6+e1oJvIsubkyZOIxWKora1N2V5bW4u2tjadjoo9kiTh3nvvxcyZM9HU1ES3z507FzfccAPGjBmDgwcP4oc//CFmzZqFHTt2GKoa67Rp0/DSSy9hwoQJaG9vx3/8x39gxowZ2L17N72P6e7x4cOH9ThcZvzhD39Ad3c3br31VrrNLPd0IJncx7a2NjidTlRUVJy2j5Gf52AwiPvvvx8LFy5MaTZ68803Y+zYsairq0NzczMeeOAB/POf/6TuVaMw3Jg163198cUXUVpaigULFqRsN9p9Tbe+aP28CsNIBZRv24B8owduMzJ33XUXPv74Y2zatCll+0033UT/3tTUhAsvvBBjxozB2rVrT3tYeWbu3Ln071OmTMH06dNx1lln4cUXX6RBnGa8x88//zzmzp2LhoYGus0s93QwcrmPRr7XkUgEX//61xGPx/GrX/0q5bPFixfTvzc1NWH8+PG48MIL8eGHH+KCCy7Q+lBzJtcxa+T7CgC/+c1vcPPNN8PtdqdsN9p9HWx9AbR7XoUrjSHV1dWw2WynWacdHR2nWbpGZcmSJfjTn/6Ed955B6NGjRpy3/r6eowZMwb79+/X6OjUobi4GFOmTMH+/ftpdprZ7vHhw4fx1ltv4dvf/vaQ+5nlnmZyH+vq6hAOh9HV1TXoPkYiEongxhtvxMGDB7Fhw4YUtSgdF1xwARwOh+Hv9cAxa7b7CgB///vfsW/fvmGfX4Dv+zrY+qL18yoMI4Y4nU5MnTr1NIlyw4YNmDFjhk5HxQZJknDXXXfh9ddfx9tvv42xY8cO+29OnTqFlpYW1NfXa3CE6hEKhbB3717U19dTSVp5j8PhMDZu3Gjoe/zCCy+gpqYG11xzzZD7meWeZnIfp06dCofDkbJPa2srmpubDXeviVG0f/9+vPXWW6iqqhr23+zevRuRSMTw93rgmDXTfSU8//zzmDp1Ks4777xh9+Xxvg63vmj+vOYaNS5Iz+rVqyWHwyE9//zz0p49e6SlS5dKxcXF0qFDh/Q+tLz413/9V8nr9Urvvvuu1NraSv/09/dLkiRJPT090rJly6TNmzdLBw8elN555x1p+vTp0siRIyW/36/z0WfHsmXLpHfffVc6cOCAtHXrVmnevHlSaWkpvYePPfaY5PV6pddff13atWuX9I1vfEOqr6833HkSYrGYNHr0aOkHP/hBynaj39Oenh7po48+kj766CMJgPTkk09KH330Ec3EyuQ+fve735VGjRolvfXWW9KHH34ozZo1SzrvvPOkaDSq12mlZahzjUQi0vz586VRo0ZJO3fuTHl+Q6GQJEmS9Nlnn0k//vGPpe3bt0sHDx6U1q5dK02aNEk6//zzDXWumY5ZM9xXgs/nk4qKiqRnnnnmtH9vlPs63PoiSdo+r8IwUoFf/vKX0pgxYySn0yldcMEFKSntRgVA2j8vvPCCJEmS1N/fL82ePVsaMWKE5HA4pNGjR0u33HKLdOTIEX0PPAduuukmqb6+XnI4HFJDQ4O0YMECaffu3fTzeDwu/ehHP5Lq6uokl8slXXrppdKuXbt0POL8ePPNNyUA0r59+1K2G/2evvPOO2nH7C233CJJUmb3MRAISHfddZdUWVkpeTwead68eVye/1DnevDgwUGf33feeUeSJEk6cuSIdOmll0qVlZWS0+mUzjrrLOnuu++WTp06pe+JpWGoc810zJrhvhKeffZZyePxSN3d3af9e6Pc1+HWF0nS9nm1JA5KIBAIBAKBoOARMUYCgUAgEAgECYRhJBAIBAKBQJBAGEYCgUAgEAgECYRhJBAIBAKBQJBAGEYCgUAgEAgECYRhJBAIBAKBQJBAGEYCgUAgEAgECYRhJBAIBAKBQJBAGEYCgUAgEAgECYRhJBAIBAKBQJBAGEYCgUAgEAgECYRhJBAIBAKBQJDg/w+Uk5UJWU9e/AAAAABJRU5ErkJggg==", + "text/plain": [ + "<Figure size 640x480 with 1 Axes>" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "d = np.array([16811, 16732, 16768, 16811, 16799, 16812, 16784, 16725, 16799, 16817, 16819, 16768, 16763, 16760, 16791, 16788, 16773, 16813, 16813, \n", + " 16806, 16818, 16816, 16817, 16816, 16773, 16784, 16766, 16759, 16752, 16756, 16766, 16772, 16770, 16776, 16774, 16759, 16757, 16759, \n", + " 16786, 16766, 16777, 16780, 16780, 16807, 16797, 16791, 16766, 16739, 16730, 16753, 16791, 16788, 16783, 16782, 16799, 16777, 16759, \n", + " 16746, 16740, 16761, 16775, 16762, 16750, 16741, 16783, 16788, 16753, 16732, 16717, 16752, 16776, 16750, 16747, 16732, 16791, 16756, \n", + " 16742, 16751, 16784, 16761, 16738, 16778, 16780, 16781, 16734, 16705, 16748, 16807, 16781, 16742, 16718, 16746, 16757, 16762, 16750, \n", + " 16740, 16721, 16783, 16776, 16762, 16761, 16769, 16765, 16758, 16738, 16732, 16713, 16758, 16788, 16758, 16734, 16754, 16761, 16767, \n", + " 16757, 16741, 16749, 16757, 16736, 16719, 16726, 16725, 16775, 16770, 16753, 16722, 16725, 16752, 16754, 16715, 16720, 16744, 16764, \n", + " 16737, 16730, 16728, 16748, 16767, 16750, 16697, 16712, 16723, 16728, 16748, 16766, 16753, 16771, 16751, 16727, 16705, 16703, 16740, \n", + " 16755, 16769, 16754, 16719, 16725, 16732, 16743, 16769, 16754, 16728, 16706, 16748, 16739, 16742, 16732, 16748, 16727, 16810, 16855, \n", + " 16855, 16914, 16954, 17022, 17069, 17140, 17242, 17291, 17312, 17328, 17461, 17546, 17597, 17695, 17892, 18061, 18165, 18281, 18593, \n", + " 18843, 18916, 18981, 19363, 19653, 19764, 19899, 20397, 20768, 20898, 20932, 21468, 21858, 21995, 21958, 22456, 22917, 23046, 22952, \n", + " 23425, 23944, 24075, 23929, 24355, 24983, 25185, 25034, 25395, 26125, 26359, 26225, 26500, 27240, 27582, 27458, 27641, 28395, 28821, \n", + " 28716, 28859, 29570, 30079, 29944, 30013, 30641, 31246, 31149, 31177, 31690, 32377, 32412, 32491, 33302, 34007, 34034, 33972, 34326, \n", + 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39074, 39002, 38688, 38374, 38208, 38147, \n", + " 37685, 37249, 37064, 37068, 36581, 36102, 35950, 35932, 35392, 34905, 34828, 34794, 34209, 33767, 33680, 33703, 32874, 32091, 32106, \n", + " 32075, 31342, 30903, 30958, 30847, 30125, 29687, 29822, 29624, 28900, 28502, 28574, 28270, 27489, 27210, 27287, 26996, 26308, 26006, \n", + " 26057, 25708, 25081, 24828, 24876, 24542, 23856, 23754, 23784, 23408, 22775, 22652, 22612, 22282, 21778, 21701, 21596, 21298, 20877, \n", + " 20825, 20764, 20478, 20094, 20084, 20030, 19839, 19552, 19577, 19493, 19338, 19091, 19108, 19078, 18930, 18697, 18625, 18494, 18284, \n", + " 18036, 17961, 17868, 17668, 17444, 17349, 17281, 17270, 17239, 17195, 17181, 17145, 17096, 17135, 17114, 17107, 17079, 17051, 17021, \n", + " 17039, 17034, 17040, 17072, 17067, 17106, 17140, 17168, 17233, 17285, 17386, 17466, 17503, 17532, 17592, 17683, 17759, 17815, 18011, \n", + " 18214, 18315, 18371, 18541, 18812, 18938, 19033, 19384, 19689, 19883, 19893, 20257, 20673, 20882, 20915, 21266, 21817, 22068, 22010, \n", + " 22249, 22814, 23085, 23093, 23253, 23870, 24139, 24102, 24164, 24868, 25242, 25202, 25216, 25906, 26362, 26337, 26289, 26988, 27541, \n", + " 27579, 27502, 28098, 28794, 28888, 28766, 29235, 29970, 30115, 30011, 30366, 31072, 31247, 31079, 31357, 32133, 32511, 32267, 32806, \n", + " 33753, 34069, 33912, 34138, 34717, 35112, 35028, 35173, 35672, 36152, 36110, 36249, 36653, 37105, 37073, 37198, 37570, 38021, 38005, \n", + " 38059, 38300, 38670, 38710, 38749, 38908, 39178, 39201, 39243, 39359, 39534, 39551, 39561, 39681, 39829, 39813, 39756, 39892, 40066, \n", + " 40108, 40110, 40228, 40375, 40401, 40408, 40508, 40600, 40662, 40708, 40712, 40738, 40732, 40737, 40758, 40760, 40783, 40750, 40723, \n", + " 40730, 40723, 40740, 40711, 40704, 40706, 40738, 40741, 40677, 40691, 40705, 40722, 40683, 40673, 40711, 40730, 40703, 40707, 40725, \n", + " 40686, 40695, 40702, 40698, 40718, 40717, 40703, 40688, 40739, 40711, 40697, 40697, 40751, 40706, 40677, 40685, 40744, 40734, 40711, \n", + " 40682, 40683, 40696, 40712, 40720, 40720, 40717, 40725, 40705, 40692, 40697, 40686, 40702, 40717, 40718, 40704, 40699, 40688, 40685, \n", + " 40748, 40701, 40737, 40704, 40704, 40706, 40677, 40674, 40690, 40692, 40660, 40695, 40734, 40741, 40703, 40686, 40698, 40704, 40720, \n", + " 40745, 40720, 40684, 40714, 40738, 40728, 40739, 40692, 40706, 40751, 40740, 40709, 40684, 40704, 40724, 40682, 40688, 40706, 40737, \n", + " 40711, 40713, 40696, 40711, 40710, 40717, 40756, 40726, 40722, 40739, 40759, 40734, 40699, 40674, 40735, 40723, 40716, 40699, 40721, \n", + " 40702, 40696, 40708, 40723, 40705, 40700, 40706, 40732, 40740, 40749, 40716, 40748, 40744, 40754, 40731, 40733, 40696, 40678, 40653, \n", + " 40670, 40579, 40510, 40489, 40488, 40410, 40329, 40313, 40300, 40180, 40064, 40080, 40094, 39879, 39742, 39637, 39570, 39359, 39155, \n", + " 39092, 39004, 38616, 38324, 38187, 38044, 37515, 37224, 37113, 36923, 36404, 36042, 36014, 35784, 35195, 34875, 34865, 34644, 33998, \n", + " 33748, 33812, 33493, 32334, 31998, 32137, 31812, 31096, 30914, 31030, 30605, 29897, 29715, 29816, 29356, 28681, 28500, 28543, 28062, \n", + " 27347, 27257, 27288, 26729, 26068, 26046, 26012, 25517, 24900, 24889, 24773, 24261, 23799, 23824, 23656, 23101, 22628, 22709, 22573, \n", + " 22105, 21709, 21703, 21572, 21163, 20841, 20831, 20689, 20372, 20137, 20179, 20055, 19784, 19567, 19575, 19502, 19322, 19147, 19124, \n", + " 19071, 18869, 18669, 18616, 18458, 18192, 17991, 17928, 17789, 17619, 17477, 17399, 17340, 17310, 17269, 17310, 17264, 17253, 17231, \n", + " 17226, 17194, 17217, 17175, 17116, 17130, 17090, 17089, 17087, 17120, 17135, 17183, 17227, 17256, 17290, 17323, 17449, 17504, 17575, \n", + " 17598, 17712, 17765, 17819, 17894, 18138, 18277, 18369, 18414, 18701, 18924, 19028, 19113, 19476, 19799, 19893, 19953, 20419, 20807, \n", + " 20931, 20983, 21511, 21940, 22097, 22014, 22530, 22974, 23112, 23079, 23521, 24083, 24228, 24057, 24465, 25060, 25260, 25119, 25433, \n", + " 26153, 26422, 26286, 26500, 27250, 27598, 27479, 27667, 28431, 28864, 28755, 28874, 29525, 30123, 30029, 30061, 30640, 31206, 31123, \n", + " 31133, 31662, 32543, 32475, 32531, 33211, 34013, 34028, 33945, 34315, 34946, 35082, 35069, 35380, 35957, 36147, 36136, 36398, 36929, \n", + " 37191, 37131, 37327, 37736, 38050, 37994, 38172, 38513, 38771, 38689, 38776, 38989, 39227, 39222, 39267, 39429, 39661, 39582, 39617, \n", + " 39735, 39889, 39827, 39885, 39992, 40098, 40112, 40161, 40235, 40350, 40397, 40494, 40600, 40640, 40649, 40688, 40715, 40730, 40709, \n", + " 40726, 40715, 40678, 40696, 40710, 40701, 40721, 40705, 40672, 40664, 40634, 40633, 40523, 40524, 40539, 40455, 40349, 40294, 40230, \n", + " 40120, 40051, 39994, 40004, 39851, 39757, 39705, 39673, 39401, 39186, 39103, 39083, 38651, 38358, 38213, 38094, 37625, 37248, 37135, \n", + " 36978, 36452, 36129, 36051, 35895, 35277, 34916, 34893, 34705, 34067, 33749, 33799, 33504, 32406, 31951, 32042, 31780, 31077, 30827, \n", + " 30944, 30641, 29892, 29670, 29771, 29323, 28619, 28463, 28512, 28047, 27337, 27239, 27248, 26770, 26110, 26061, 26014, 25524, 24846, \n", + " 24817, 24749, 24279, 23748, 23764, 23638, 23184, 22682, 22710, 22564, 22126, 21704, 21740, 21552, 21193, 20855, 20852, 20723, 20409, \n", + " 20169, 20190, 20074, 19774, 19588, 19607, 19517, 19307, 19160, 19139, 19043, 18829, 18598, 18570, 18458, 18255, 18065, 17967, 17797, \n", + " 17644, 17537, 17507, 17454, 17426, 17392, 17352, 17335, 17335, 17313, 17290, 17269, 17226, 17229, 17216, 17187, 17169, 17164, 17168, \n", + " 17189, 17195, 17199, 17233, 17280, 17333, 17375, 17484, 17590, 17610, 17649, 17756, 17851, 17866, 17894, 18146, 18307, 18384, 18475, \n", + " 18739, 18974, 19057, 19144, 19552, 19782, 19927, 19999, 20462, 20816, 20964, 21006, 21498, 21912, 22063, 22038, 22531, 22981, 23181, \n", + " 23077, 23472, 24007, 24182, 24076, 24436, 25088, 25328, 25213, 25446, 26158, 26480, 26355, 26475, 27230, 27600, 27485, 27621, 28378, \n", + " 28860, 28790, 28866, 29562, 30093, 30021, 30013, 30589, 31198, 31200, 31173, 31666, 32412, 32565, 32368, 33232, 33976, 34059, 34015, \n", + " 34350, 34989, 35157, 35063, 35322, 35943, 36155, 36139, 36399, 36913, 37187, 37137, 37313, 37720, 38034, 38016, 38159, 38477, 38757, \n", + " 38723, 38795, 39013, 39253, 39228, 39296, 39455, 39662, 39545, 39576, 39720, 39794, 39776, 39837, 39949, 40084, 40089, 40121, 40216, \n", + " 40409, 40459, 40473, 40507, 40607, 40619, 40645, 40678, 40709, 40676, 40654, 40683, 40687, 40706, 40712, 40704, 40719, 40693, 40690, \n", + " 40711, 40686, 40684, 40679, 40669, 40664, 40623, 40643, 40634, 40641, 40621, 40688, 40702, 40691, 40679, 40647, 40644, 40645, 40652, \n", + " 40674, 40662, 40651, 40678, 40673, 40665, 40671, 40651, 40658, 40670, 40682, 40659, 40686, 40658, 40664, 40664, 40668, 40668, 40638, \n", + " 40654, 40651, 40661, 40655, 40666, 40652, 40664, 40701, 40680, 40662, 40690, 40673, 40690, 40669, 40655, 40665, 40684, 40695, 40697, \n", + " 40698, 40707, 40684, 40642, 40674, 40719, 40708, 40723, 40713, 40708, 40707, 40701, 40690])\n", + "d = d.reshape(-1, 16).mean(axis=1)\n", + "plt.plot(d, '-+')" + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "id": "ccf1af9a-a47d-4922-84cb-5934fa5d1cd1", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "[<matplotlib.lines.Line2D at 0x7f5ceeff3dd0>]" + ] + }, + "execution_count": 3, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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FKHXZYIlPzh4NF8JjngB6gxHYLCacUkk3AJy4iU70GscwOnBCNCJPqSyESb66UmBCragaam1IknMcXUk/s3RstfiiuLe9Z4g9leXgieTihRNqxbH6VYs2x0Xm0UA4sUaTOdSI82hWhlFvby/mzZuH5557DmVlCRlTEAQ8+eSTuP/++zFnzhw0NDTgpZdegs/nw6uvijULPB4Pnn/+eTz22GO44oorcM4552DZsmXYvn073nvvPQDArl27sHr1avzpT3/ClClTMGXKFDz33HNYuXIldu8Wo/TXrFmDnTt3YtmyZTjnnHNwxRVX4LHHHsNzzz0Hr9eb63UxNN5AGEe6xPTUsVUMVVJVmBKXqBBo/cbLIkQtGl7qQpHDCrPZhPJCcdHR0tlO4otGVxbCRlkdaIgHiPYGo+gJGGNM7I+rKadSNiIB4JQKsdjboQ4f9e/OhP1xo2HahGrqCzKZD4lKqRUH49f42+OHoarYgdPjStauVm3XNq3vvVpkNdPceuutuOqqq3DFFVckbT9w4ABaW1sxffp0aZvD4cAll1yCjRs3AgAaGxsRDoeT9qmrq0NDQ4O0z6ZNm+B2uzF58mRpnwsuuAButztpn4aGBtTV1Un7zJgxA8FgEI2NjSmPOxgMwuv1Jv3JJ0iPtFVftkjbjnT5pb5prPXioU2dW5xESSsJTgJigJA3ZgCoLRWvl1TSXwP2SsdF34AvclhR4hTzT1o0clHQhgRej1bAMBoZN4yau3yajgklz5GEFuw/3oeIhvPEoQ7xHP/vhaNRVeLEGXHDaHdrj6bHdbhTNIyuP2+EroKpMyXjrLQVK1bgs88+w9atW0/6rLVVjFavrq5O2l5dXY1Dhw5J+9jt9iSliexD/n1rayuqqk6uwFpVVZW0T//fKSsrg91ul/bpz8MPP4wHHnggndM0JKkyHrTOOFKT+nJxYg+EuWHUH+JaHV6aeAMfViROfMc1dDWRTLmxCsXC1ZW64G3twbFuP8YpYHypjZJGQ63bBbvFjFA0hmPdful5Uhslz3F4qUvKTDvc6cOpw9SPwYzFBByKGyDkHEeVF0jH9cDbO7DwsrGqu68C4aiUrfrLK09HRZFxDaOMFKPm5mbccccdWLZsGZzOgW9Kf9+2IAhD+rv775Nq/2z2kXPvvffC4/FIf5qbmwc9JqNBAuhunHqKtE0eQGf0QOTyQtGV1tHHA/T781WrqMzIJ7th8TdCLWNKdrSIqm61QovA8FIxIP9YtzEUIxKbQjseCwAsZhPqy8XrpZVLJRSJoTluNCjhLjSbTZJqtFcjd1qLN4BQJAabxYTauMptNpswPh4T98rmw5p0qj/S5YMgiEormUuNSkaGUWNjI9rb2zFp0iRYrVZYrVasX78ev/vd72C1WiUFp79i097eLn1WU1ODUCiErq6uQfdpa2s76fePHz+etE//3+nq6kI4HD5JSSI4HA6UlJQk/cknUmU8GDmArj8V8SykDgMF29LicHyhG1WRWGyIYdTeo43RIAgC9scXp1KXMiXXiLvwWPfALSH0gj8UxbG4S1AJowFIjI9Dncp1Nh+Mw50+xASg0G6RxidtiDr50saDmoQXHIobt/VlBUlZd8SdphXEGB5ZXkA9sJ81MjKMLr/8cmzfvh3btm2T/px33nmYN28etm3bhlNPPRU1NTVYu3at9G9CoRDWr1+PqVPFOiGTJk2CzWZL2qelpQVNTU3SPlOmTIHH48Enn3wi7bNlyxZ4PJ6kfZqamtDSkoiXWbNmDRwOByZNmpTFpcgftHjbYIGKeDBxJ1eMACRizjbv75AC0nsCESnmzGUTpwetFKOj3X4EIqLbs9btGmLv7KiTFCP9G0afxQuXlrisKFPojX6UxgHYkhttGP2sO8KYeJzdxq87NJkrD0ovKeK1Js+p/OWAPKNqxob2Py4jk9FrWHFxMRoaGpK2FRYWoqKiQtq+aNEiPPTQQxg7dizGjh2Lhx56CAUFBZg7V+zI63a7cdNNN2Hx4sWoqKhAeXk57r77bkycOFEK5j7jjDNw5ZVXYsGCBXj22WcBADfffDNmzZqF8ePFHjfTp0/HhAkTMH/+fDz66KPo7OzE3XffjQULFuSdEpQp5EGa2VBj6AC6/shdaem4d41OqpizJf9I1By7aqJY4l9tw4gUuWs8lFCVv2rtkd6eaRaZJK60owYwjLbHW7cQ94sSjIrHFfVPJ1eLRKq+crE/YzSIK5JzsCPZHcpKbOjh+HGN5IZR5vziF7+A3+/HLbfcgq6uLkyePBlr1qxBcXEisPGJJ56A1WrF9ddfD7/fj8svvxwvvvgiLBaLtM/y5ctx++23S9lrs2fPxtNPPy19brFYsGrVKtxyyy248MIL4XK5MHfuXPz2t7+lfUqGoy1evOzHF402vPtMDnGlhSIx9AYjKHYaoxdctpAWCzuOefDLN8SJVl7lutXjx6rtraoHX6u5EBDFyAhZaUT1IuekBKPii3XjoS60ewOqzx+kv6MSL3TEII/K6lNo0SdQihOLuy3Jc7qtuRv/8TexGvZJTW5VgASEjyo3fsP1nA2jdevWJf2/yWTCkiVLsGTJkgH/jdPpxNKlS7F06dIB9ykvL8eyZcsG/e2RI0di5cqVmRxu3iMIghQzkk9qEQAU2K1SZkdnXyjvDSNSqZbUtAISMWdAorlmuzeoqsJGFoK3Pj+C5zccBKDcQkDUlRaPH7GYALNZXyqivOP8jrjRYDObpQWd9mJOFuuOvhDaNDCM9kkxZ/SfXVaUmUP9XFbkOY3ISiTIn1O1OMxdaRyj4g1EpHT1quL8UYsI5YV2HO32o6MvlBRonM8MFHNVGc9QC0Zi6AlGUKKSIUkWgn9uT8QPKrUQVJc4YTYB4aiAE71B3SmoqRbzNTvbsGanmLxCezEfXuqCCYAAoMunfqwecXkOL6OvihGDPBSNYs7vNwEAfn31BJx/SjkAdV4kYzFBcheSGluEIocl1T9RhWhMQHMXN4w4BuV4XC0qcVrhsmv3oGlFRZFoGHX28gBsAsnSO7O2JGnyd9ktKHZY0ROM4HhPUDXDiKDGwmuzmFFd4kSLJ4Cj3X7dGUZkMQeAm17ciraeIH5y0Whce85wAPQWc7kyVVpgQ5cvjI/3dUjV0ZV0M5Hf9oei6PKJSQIef5i6KkYMckEQYDEBUUGsI6SmMtPWE0AoKipD5n4KbaFDXK5NSPT5U4vtR7sRjgqwmpVLhGAJbhjlGSS+SG8LAC0SAdj5mZmXClLX6eLxw04aF8NKHOg5HkG7N4jTVA5KJUoWaYugFHWlLrR4Anjuw/1YMvtMXT0bZDEHgHBMVIKVUNdSKVPPfrgfz364H4CybqZUv/3A2zulv9P+bZPJBKfNgr5QFH5ZbzA1OHgike3Xv0EuMYwEAO4CdQ2jpqOJemIWnbmbs4EbRnlGWzwjrbokv+KLCCRlnxd5TECuRUWKFO9hRQ7sP96nSfXrrj5RHbjuvHpFjRUSZ/TPplbc8u0xujKM5PQEIgDEAny0kStTd72+DXvaenHdpBG4IV4sVknDlfz23rZe3Pn6NgDKBx8XOqzoC0VRYFNniSSq2MZ9J6Rt/QO/5cVX+4IROG3qKf4kOaFGwYxHluCGUZ5B5PDqPIwvAhKZadyVlqAzrp5VpJDntax+TVS9MoXfjocrmMWlFoFwFOG4C+bUYfRj5+TKVGWRA3vaelFZZFfFzUR+2yNr/qx08HGJy4b2niDsVrqNiwci3cBvkjzSF4yiQmEBV+4+3X60GwBgtygX2M8S3DDKM4hiNCxPFSPeFuRkOuJGIokXkUMC9LUwjEg8iVLtB+QTP0GL9GwaEKPBYjYp0kNMDlEq/Cr3HJQbRkpTGI+/9IUiqvweUcVe+Pgg3vjsCIDUqlihwwp/OIreoPLHlcpY27S/E7OWbgBg7N6a3DDKM9q9ea4YccPoJAZ1pWnUFiQaE9DtIwabMoYRK+nZNOiOG5GlLpviZRXKCsQgfLVjTbxxw2h0RYHiGWIFdnFp7AupE2NEVDGnLaFQpVLFihwWnOgF+lQw2OTu0ztf34a9KrpPtYYbRnkGWeCUasrJOpIrjQdfAxDTg7uIYcSQK83rD4OUbSktUCYbjkz8jYe68Ot4xW8tCufRgBiRboWulRxSxkHtEFxvQDSMvjGyTHElrzCeGu9TQZmRQ+LEBoIEYKuhGMndp8QGHltVrHr9JC3ghlGekchK08+kTxPiLuIxRiLeQFgqHJdKmSGG0c5jXlUrHXfGF/oSpxU2izJxHmTil2ceaVE4jwak151bgcKH/SFqik/ljC2PBueolmJEIMbfFWdUpTTMC8lxqWyw+YLidSjUsJaSmqgTWcZhAnnV63x3pZ2I90vLd4gbrdhhhcN68qRHJueOvpCqDTVJqr5SbjQ5LhWze5TCI3OlKU2BXRs1xesXf69/4UMlIMqM2gYIUYz+z6QRKV9CiGGi9nGRosBKFNZkEW4Y5RFJVa/zVDGS90tT+22QRaTA6wEKxg2TvbVGouoF2xLDSKku8XJIoVO7xaQr95mcbr94vUpVqG9TQNxMKj8/RDEqUcH4I8HXasTyyOmJK0YDtStKuNLUvfZEVc2XbgHclZZHtHsTVa/VrIHBEgV2K5w2MwLhGDp7Q4rUfNETUqp+PwOEZGzFYoLUAuKTg52KdLhPRdcgAeG0IQpITNBv4VN13UzaGEbEzaSGYVQQnxd8KhsgRDEqHkAVK9JAyYrGBCmmKV/my/w4Sw4AYHdbDwB1FhuWqSh04Gi3Hyf6ghiZB31/BqOjL3WqfqqMrYf++ZX0d6UztkiMkdI1jICEKy0SExCOxhSLaVISKStNheBrKcZIZTVFUoxUaE2jnWJEDKPBFSM1j0v+WwMZbEYjP86SAwDYf1xsTuh25blhFO+X9sKGAxgxy6VblYAGxJXW31iWp+r+4I+b0RuM4I7Lx0rblHY5dfaqGGMk6xnoC0XhdunQMPJrEGOktmKkpiqmgWIkV2YGiqPSIvaJGGs2iwkOlQpeak1+nCUHANDRK04sZYXqNgNlDbLYvv1li6oBxSzSOUCqflWJU8rQIvL5iHKXtE1pY1JSjFQwjOwWs5SO7Ndp3BkJvlYjXT+hGKntSosbDS7l3+dJJ3s1lZnegFyZSX0fpeNS0WDrlalYStfIYgWuGBkceXXffe2iKy0mIC/Kug+EGiqEXjgR74E22DUhb4khFSsdkxijchVcaSaTCQV2K3qDEdWbhtJCCr5WQQ3WSjHSJF1fRWWGxFA5rOYBW5GoWceIkAgIzx9zIX/ONE9JFSuyfs9xrN9zHIC+qvvmCjES5Wn6em0BQQuiGFUWDewaK4xPiPKqvErTqXA7kP647Bb0BiOqx83QoltFxahQgxijQDiKUEQ0zNXJSlNfFRsqvgjQJvi6J88CrwFuGBkeeazIz//6BXa19mDOOcPx44tGA9BXdd9cMVILCFqkUy+IxDs4VMxk7FIxXR9IBGAHdKoYqVnHiMRk+cNRxGICzCq0BiHxRWYTUGRXftkq0MCV1iNl3Q18floUeBwqU86I5M+Z5inysu62uDx76rBCXVb3zRViJP5v4xG8uPEgAP22gKDFid6B24EQiNGg5tuzmgUeAe3cQzSIRGPSW70adYxIkUFBAAKRqOR2UhKvrL6PGoaYpBipGMuTjmKkpSutyJE/sancMMojSPyEESr9ZgMxEhsPdUnb9NoCggaxmIAuH8lKG9goJAqBWmpKMJLoHq5GjBGQ6BivR8PIKwvaVaMqtNOanMWnhmGUKO6ozpJVqIFiJNVpGuQeJlxp6gdfqzG2WIFnpeURkbiPvqY0v+Jo+qNmrAzLePxhRON90gbLVCRGg1oZWyRexmI2qSbfF6hs/NGENJAtdlilApxKYjabEiqiSgs0aQeiRuA1kFCMAuGYahXf03FZadEShBxXETeMOEYkGDeM6svyu6ghWehHlLny0n1GIMUd7RaTFKOSCrIIqpWxJbUDKbCr4jYB9O1KkxrIqhB4TZC6z4fVWaATaoo651gga5aqVrNcKftrEJdVkazAo1q9Hol6m08xRtwwyiNIbzA1pG+WIYbRsDzMQpPTEU/VD0WFQes5aWUYlatYb0ttVYwmHhWrXhOIe1Utl46aqfqAWNvKGjfK1VLFetKo00RijGKCes+jNw9jjLhhlEeQ9NpCR37GGBGcUgaSenV5WIQYIEMhxRipZDTIFSO1KLCra/zRRM0aRgTialLLkPSq2A4EILWt1I0z8qYRfF1gt4DUWFQrALuXZ6VxjEooEkM4Kkqv+a4YEQUkqMNFkAakntN2WQ2nweo5uVQ2Gg539gFIGCtq4NKxYqRmDSOCS2WjwaOBu7DIYYU3EFEvjiqNQoomkwmF8WKkfcEoUKz8cfF0fY5hkRdjU3PBYRESfK1HdYAGmdZzSrjS1FHYjnb5AahbN8mlUZsLGqjtZgK0UIzUz4wqULlhazrp+oCo+IuGkUqKUR7GGOXPmeY5JL7IbjXrsns4TfRezC9XSD2n5ZsP4S9bmwEMXs9JbTUl0SxUxUVQUsX0V/m6W8XijgStFCM1ql4TCu3qZoCl23pDjDMKquZK65HVkMoXuGGUJ/jiD1FhnqtFgCzQNk8NI1LPqVi2yAxWz8mlgtEg7+nXHFeMegMR1Xr66dmVRowGNYOvyTyimrEcUF8Vk/qlqXSOUvD1EAaI2m1BenlLEI5RIYM73+OLgOTga0EQ8qZjdH/S7XWlRsZWKvfequ2tWLW9FYDy7Vpcek7X96kffK2261HtdH1AVpKANcXIrm71ay+PMeIYFTKB5ZPVPxDyAo/BSExa+PMNMiYuHFMxaD0nNWKM5D397ljxOb4+3ocfnF+Pf7tgFADl27WoXZKAJprUMcoHV5pDXcUoEUc1VIyRetWvg5FE897B6isZDb5K5glEdi3I81R9AEmGUCAczVvDiChAM86sGdRNpUZLEHlPP6tFVPBOG1akWruWApVdQzQh9ajUKvgHqH+9EpWv1Yw7I/3SlDf+wtGYZJQPpcwUqVj9ulfWboZXvuYYDqIOFHJXGmyy4m16VAhoQcbEUL3z1I6/CcaVKTVbt+jZlUYKPIZjKhpGKqoWsZiQcKVpEHzdq4IqJjdA0gu+VseVRuKeCuwWWFSqQs8C3DDKE4jkne+p+gRe5DFh6LiGGBNqB6uTBb7WrV5Vcr1mKgqCgB6STq2im1zNLL7eUAREDFMzxogYf2rUMZIbIEP1u1Mz+DofU/UB7krLG8jDXchjjACIi31vMKJL1wktSJ+roYxltatCh+MxDbWlLlV+D5C5TXQyHkgWX18wAiIUNXf6VM/iU0MxIoqY3WpW1e2tZhxVOsUdCYUq1lfy5mGqPsANo7yBK0bJEDdNIKKPhVAJJMXINvg0QBbBUCSGaExQXFL3a9DTz2XXV9HPVFl8v/r7DunvSmfxkcVZjRcLLVL1gcQ5qqEYZWKAJFxpyh8XcfHlW9JOfp1tHiPFGOXZAB8IvbpOaJIwQIaIMbInB6srPYaIcTJU7BNNXCpXcs4VksXX3OnDvy//DMDgRTppo2aBRxJ4HYnG0O4NqNb4maTrq3GOmbTdULPwZD62AwG4YZQ39EoFHvktB+QxRvpYCJXAF07PMHJYEzEPvpCyhlE4GkMk7hsaKvaJJgVEFYvGEInGhozz0Bp5Fh9hsCKdtFGzJQhJ1e/yhdHeE1TNMFLTvZpucUdA3eDrfI0xYvvp51BDqnzN0/UByBWj/A2+9qUZfG0ymVRT2OSLkLqKUeK39OJOA7SLiVKz8zxxM6kNMf7UUWbSjzFSM/haOq48qmEEcMUob+jTIG6DZRykkaxOXCe0icYEqXBbOmPCZbfAH44qbjQQw8tqNsFuVe+9zWE1w2QCBEEcE3oJNiX3o7LIrrj7TE6BCuUNSID57lavtI0ElwPKB5gXaOJKS18xUsUwIu1A8kwxyq+zzWNI+weuGIlICkieBl/L24GkE5CvVi2jdGsr0YaoYr6Q8sYfTcj9GFVRqJqLCUh2MynVVidVgPk9b26X/q50gHmRmsHXpLJ3Wllp4rPR3hNUPOaKxxhxDA1Jq+WKkYga/b9Yhpy3yZQcQzQQJItPaaOBHJdTg+zJArtoGOklZR9IKGxqG5JETYnGBISiMTis9H+fBJi/vOkgXv/0CAB1A8zVdBe2e8Xq5enYl5LBFooqHnPVw7PSOEZGUox4uj6AxEISjORnjJFcmUnnbd+lUi0jf5q1lZRArXOkCTlWtdvaFMh+zxeMKmIYkQDzIll8ixYB5oGw8mUqOnzBtPeVJz/EFK523qtB814W4IZRniApRnlm+Q+EM89jjPxpZqQRJNejwtfLH4ol/Z6aqN36hAbpVi+njdViht1qRigSgy8cRZmCv6WVoSrvK9kXiihqHPiCQz+PJOYqKHP/f3a4C+a4waZEzBV3pXEMTR9XjJIgrpp8TddPNyONINX5UTwrLRL/PS0UI33VMgLkNZ/UTzAusFsQisTgV9jVFIyf40VjKlQNMLfHeypGYgJ8wSh1w4gYOgBwPN4I+ERvaMDq5alirpa8vVP6uxIxV92+EAAgEssvZZ0bRnkCbwmSjNOa38HXUnHHIapeE1xqxRhpFDMj/qZ4jj4dGctaVAknFNqt6PaFFW8LQsbEjDNrVA0wN5lMcNkt6AlEcLizDzWUe/elMnRe3nQIL286BOBkQ4fEXAHAnN9/jFBUwM9njMMl46oAKBNz5YkX1wxF1WtQzAJ8lcwDQpEYQlHR4ucFHkUSwdf59SZEyFSZUcvNlG41biUokBQj5YNtaaFVjBGQGDtKB6uTc3RocI4Oqxk9AI52BYDRdL9bbuj86M+foLMvhH+/5FRcdVYdgJMNHXlRT6fNglA0glMqChWNuSLzRIEG115L+CqZB8gXMy1cFCziyvNeaRnHGNlVMowYWOj16UrTJosPSC79oARaZd4Bsgr5CswTydXLRUVmfE1JWoYOqfEVUiB5hLj4BEGQjN7mLvUaFLMAN4zyABJfZI8HTHJkE56OFkGa+DJUZiSFTaXK15pkpcXPUU+utIAUK6ZNjBGghmKkbkC+PPaHsLvVq6hhEIqIhpEjzVgxYsQrERqRysX30D+/kv6udP0oFuCGUR4gyaG8uKMEmVjyVTFKBF+nG2OkjmGkpTpAFno9GcvaKkakno46wddqqYipDIMXNx7CixtTx/7QgGSa1ZW60tqfhEQo4QEgLj6vP4y5f9oCAHjw2gacXV8KQPn6USzADaM8gARH8viiBKTuip7cJjQhcTTpZjOp3SstXYONJpJipKMxQY5VC9ejeoqRuqqYPPbnrte3YU9bL66bNAI3TD0FAH3DIBYTEI4HN49I0zBySM8jfVcacfG1ePzStrPrS1WrH8UCfKXMA0hPHS3cE6wiKUZ52kQ2EWOUpmKkcoyRJllpdv250jK9jzRRzTCKf78SRSRTIY/9qSi0AwCGFTsUMwzkRWbTNXCd8ZCIoIKKd77OjQDAA07yANJAlqfqJyATC69jxFaMEQsxM3pypQVUVlPkEGNs3e52tHsDiv1O4hzVN5alIOeockaCfA5K1zBSUjEiyN3a+eA+k8MNozyAN5A9GVeeF3hM1DFKb0wQo8Gv8Fskd6Vlhp8BV9rWg10nBSvTJKBy8LUcUtTRZlFuqSRxjnaLOe22I2ooRuQlqKLIbvgstP5wwygP4A1kT0YtBYRVMq58rVZLEE1daepU96aJltdLDQWaNKkFtDH+yuKuNCUNI8lVmEH1cjUVIy2uu9bwlTIP4A1kT8alwsTCMom0+PSmAKcUf6NsBpKWBR712CtNCzcTSWcn7SIASKnsAN10drmiq2Udo6CCxjKZgzIxQNRQjILSceWffsINozyAN5A9GYeswKMgCGl1mDcSmXaxV63yNQPp+npSjCTlT8XrlSqd/Z43t0t/p5nOLr8XDg1qsDlUiEUkrrRMDBCnmoqRSkHvLMFXyjyAK0YnQyYWQRCzQvJNLs7alaZ4jJGWTWTVqeRMC0EQZKns6l0vks7+/ldteHytaCA9MmeilLVFM1A3kZFmlrrIq4mkGClQYZqQjQHiUCMrLaJd0LvWcMMoDyCVr3mMUQL5G3YwnH+GUaYuK5dKaoqWgbZ6c6UFIzEI8d6eal4vks5+uNMnbWsY7lYknT2o8eKshmJEXFaZnGPCxaekwSZ+t1plElgiI23ymWeewVlnnYWSkhKUlJRgypQpeOedd6TPb7zxRphMpqQ/F1xwQdJ3BINBLFy4EJWVlSgsLMTs2bNx5MiRpH26urowf/58uN1uuN1uzJ8/H93d3Un7HD58GFdffTUKCwtRWVmJ22+/HaFQCJyTkQo88qw0CZssA0RPrhNaZOqyUstokKq0a9JEVl+utGzSvGmihmuLNHnWwlAGEkHOSipGfkYVo0TGY/7FGGV0xiNGjMAjjzyCTz/9FJ9++ikuu+wyXHPNNdixY4e0z5VXXomWlhbpzz//+c+k71i0aBHeeustrFixAhs2bEBvby9mzZqFaDRxg+fOnYtt27Zh9erVWL16NbZt24b58+dLn0ejUVx11VXo6+vDhg0bsGLFCrzxxhtYvHhxttfB0JACj7yOUTJqVXNmkVzqGAlEplAALZvIkt/0+sOK1uWhBblWNotJ0aypgSDXq6LQrlidGy3HA6BOvTPy3ZlkpakSYxTR9tprSUYr5dVXX530/w8++CCeeeYZbN68GWeeeSYAwOFwoKamJuW/93g8eP755/HKK6/giiuuAAAsW7YM9fX1eO+99zBjxgzs2rULq1evxubNmzF58mQAwHPPPYcpU6Zg9+7dGD9+PNasWYOdO3eiubkZdXV1AIDHHnsMN954Ix588EGUlJRkdhUMDlkEeUuQZJw2M3qD+lEIaOLPMCtNbkApFZMViwnSRK+lYhQVgFZPgPnaLVrWMBJ/V1zIi5xWxa6V1injaihG2WSlSckjqmTLccUobaLRKFasWIG+vj5MmTJF2r5u3TpUVVVh3LhxWLBgAdrb26XPGhsbEQ6HMX36dGlbXV0dGhoasHHjRgDApk2b4Ha7JaMIAC644AK43e6kfRoaGiSjCABmzJiBYDCIxsbGbE/JsPRp6J5gGWeeKkaCIGTsspK7MpRyp8kb+moZfA0ouxDSQouMNDkk9kTJOJeEy1ebxVlNxSizdH3lDbaghhmiWpOxhLB9+3ZMmTIFgUAARUVFeOuttzBhwgQAwMyZM3Hddddh1KhROHDgAH71q1/hsssuQ2NjIxwOB1pbW2G321FWVpb0ndXV1WhtbQUAtLa2oqqq6qTfraqqStqnuro66fOysjLY7XZpn1QEg0EEg4kKrV6vN9PT1yVeXxiAsmXt9Ui+FnkMRmKIkaDdNA0Qi9kEu9WMUCQGfziKsqH/ScbIK06rmSJM6vLEYgkX4bbmbuna0KzLQxOyoGr1wuOUlbxQClYUIzVcVpkYf+ooRtyVljbjx4/Htm3b0N3djTfeeAM33HAD1q9fjwkTJuD73/++tF9DQwPOO+88jBo1CqtWrcKcOXMG/M7+dWRS1ZTJZp/+PPzww3jggQeGPEej0ROPMco3ZWQoXCpkdrCIXPFJtyUIIF6vUCSmWMsMebCnmqnZqeryPPjPXdLfadbloYnW8TdEMVJjcdZKtVClWWsWLlGHCoqR1uNLSzI2jOx2O8aMGQMAOO+887B161Y89dRTePbZZ0/at7a2FqNGjcLeveKkU1NTg1AohK6uriTVqL29HVOnTpX2aWtrO+m7jh8/LqlENTU12LJlS9LnXV1dCIfDJylJcu69917cdddd0v97vV7U19ene+q6RevJhVWcKrx1sQjpHm+3mGHNIGjXZbPA4w8rdr20GqekLg8AXPfsJvhDUdw1bSwuO13cxmoDTX+GAfS0IaqFWDZAmSKpWsdRqaMYsR1jpEVhTa3J+YwFQUhyT8np6OhAc3MzamtrAQCTJk2CzWbD2rVrpX1aWlrQ1NQkGUZTpkyBx+PBJ598Iu2zZcsWeDyepH2amprQ0tIi7bNmzRo4HA5MmjRpwGN1OBxSqQHyx6i0ewNoOupB01EP+uKTy+FOn7RND1k3SpOvrjR/lkUUla5llGmbElpUlTilOjzEnTGyvFDaxqIbDdC2SjiQUC0EQTk3fTZGA02cMuNPKRIFHjPISlNBMeKutDS57777MHPmTNTX16OnpwcrVqzAunXrsHr1avT29mLJkiX43ve+h9raWhw8eBD33XcfKisr8d3vfhcA4Ha7cdNNN2Hx4sWoqKhAeXk57r77bkycOFHKUjvjjDNw5ZVXYsGCBZIKdfPNN2PWrFkYP348AGD69OmYMGEC5s+fj0cffRSdnZ24++67sWDBAkMbO5mQyj3w36t3479X7wbArntATdRIeWURUhsm09gUyZBUypUWTrjStMJutQAIIxxl31jWWgmW36dgJKZIIcCEKqZV8LUavdJIuj5jilFE2xpSWpKRYdTW1ob58+ejpaUFbrcbZ511FlavXo1p06bB7/dj+/btePnll9Hd3Y3a2lp8+9vfxmuvvYbi4mLpO5544glYrVZcf/318Pv9uPzyy/Hiiy/CYklc/OXLl+P222+Xstdmz56Np59+WvrcYrFg1apVuOWWW3DhhRfC5XJh7ty5+O1vf5vr9TAMxD0QCEfxf/6wCQDwn9eciXNHii5MVt0DapKvipHUdiPDCY+80LZ6lFEbMy0hoAQF8QVHD1XiM61FRRu7xQyTSVSMAuEoSpw26r+hdb8uhyoB5pkbIFwxUpaMnv7nn39+wM9cLhfefffdIb/D6XRi6dKlWLp06YD7lJeXY9myZYN+z8iRI7Fy5cohfy9fIWX7O/sS1cDPHlGqSNl+veLK8xijTBdUczyGpL1HIcOIgVi4Qoe4uOvBMNL6eplMJjisZgTCMcUSGAJZjlVaEAMkHBUQjQlStXyaZBPkrEZ8ZJABBVcr8u+M8wz5g6PEQ61n8rWOUaZ90ghSGwKFFkGtFRBAXwH5ASauF1EulHavaqsYAcqdYyALA0TVViVcMeIYDfLQ2S0m7j7rR762BEkYIEM//qTGD5CQ/A929KHpqAcA3Ro/WisggDpp0LRg43oRQ1KZ6+XPoio0TeQuvGA4hgI7/d8IZnGOJFA7FIkhFhMUKW+Rz5WvuWFkcMjgLnHZmc2u0QpHnsYYkay0dGoYpQrif/vLFrz9pZgRSjOI389AhXY9KUYsvNErrRhpHWBuNptgt5gRisYUizNK9CTLXDECxIxAp5n+9ZGCwjWK79ISbhgZnGAWD12+4MrTrDRfBq40eY2f/1q1E5v3d+Ky06twV9wYoqlCkmw5p4aGka4UI9J5XtPrpaxilIgx0m7+cljjhpHC55iNYkT+vRLGsdbxXVrCDSODk02DwnxBT+oATfwZTHgkiB8AauL/LS2wKRLE7wunr2QphUOFSse08IdZUNgUjjEiBR41VC0cNgt6ghGm4qisFjMsZhOissbLtNG6hpSWcBnB4GQj0+YL+RpjlG3wtT1uNIQVUlNYCCZWo9IxLbSuCg0kDBblFuf4ORpaFYsbIBkaf0q2K4nFBISIYcQrX3OMRjCP/cRDka8FHrPtyl4WjzxVKrvRx8BCry/FiIHga5uy18uf5ViliVT9WuFWOJm+vCppxMvjqbhixDEc+ZxZMBT5WuCxI17bKtMuDhVFomFkVqAnFpC4D1q6hqSFXgfGsj+LwoC0cSitGDEQCiC9QCmklGaTlQYoqxjJ7yc3jDiGQ+vKsSxDjMXDHX151TvO4xcNo0gss4k+sUAYWB2wKnuONGHD9ahsnJ7WWWmA3JVG/xyjMUHqM5fpOSqqGMkaTedj/TtuGBmcfC7rPhRkIjreG5Jq9eQDid5MGUr3Chd4zCQoXCn0pRhp/2wr3ZqCBXdhIsBcOQNE/jvpoqTbN9s5wijwrDSDQx7mfB3gg5FPxqK8UCNxpZ3oCWZUqFHpVHYmFkGrsm4TmmRSdkEplFSMBEHIOv6GJkoqRvLvdGQY5KxkjCQLLkwt4YaRwcn3AZ4KYiQ0d/mkbcRAAOhWc2aFVIUaX/2kGa9+0gwgvUKNSpc3YKGJrEPhQFuasOBmUlIxCkVjiAnx32GiJIESQc7id9qt5oyrVyupGPkZMEi1hBtGBkdKd+UxRhKpjIR73twu/Z1mNWdWkBdqvOnFrWjrCeInF43GtecMB5BeoUalFaOeoFiXJxCvz6MFeinwKAgCE65HJY3lQEgWAKxlHSOrcsZyIgY0cwNEScUomOexqdwwMjj57itOBTESTvQGceMLWwEAj8yZKBUtNGJPOXmhRlM8q2x8TVFGhRqVDrTtixtGvpB2Rolein6Sbu+A1uUNlFRTxHtgMZtgs2gXAKxks+lcYkAVjTGKaG90awk3jAxOtsXDjAwxErp9IWnb6TXFilRzZpFQVJz0bJZMgz2VVVNCYe3j4fSiGMlLTLBQ40cJo0GepWhSqEREOqgRfJ2NAaJKjFGerhvcMDI4wTz3FQ+GvOhlOCpoeCTqQs611p1ZHJUSb6gk3ksQBPjj33uooy+joHCaJM6RbcOILKhaqylKZiqyEueibPB19gaIGkHh+epp4IaRwQnmcb+boZBngRQ78+dRIKX+h5e5Mvp3Sryhpor3euifX0l/VzveS1IHGHelSRlpzKgpbLmZaOJQQTHKxvhTVsnK73Ujf1aDPIWFdFdWMZtNsFvEztklLpvWh6MKgiAkSjhk+JaqhGJE4r16gxH84I+bAQD/75ozcc7IMgDqx3vpRTGS+qRpHAOSiDtTTjHS0lUIqKMYOXKJMVLCjcmIUaoV3DAyOIkmsvk5wIfCYRMNI9aDbWkhX/AzNZblipEgCFSUChLv1d6TqDz+jfpSzeK9lAy0pQkrRkMiXZ/+9cq2VQZtlI3lyX5+ViP2KR8byAK88rXhkd5I8nSAD4Vegm1pEcyhB5I83iCUaaO1IZAfl5auIb0oRizUMAKUNRqYMf4UbJSbOMfM52cllaxgDkHhRoCvlgYnEUSXnwN8KPSyENIiOQU6u5YgAP3rJY1Tq1nTcglKd4unBTOuNCWLDDJzjnmoGOV5bCo3jAwObyI7OHqpW0OLXCRyu8UMIubQvl5kci8rsGtadZw8J/I6QSxClIaOnqCmDZAVbWQaYcOdo6RiJCXHZJOVpmRxTe5K4xiZRHYBv9WpyDdXWi7BniaTSbH0bFaSBOTuQpZVI6KmHOn2a9oAWUl3jlTHKC8Uoyyy0hScu8i1z1dPA18tDQ5P1x8crhhlhlLp2aykB8sz9ZSozUMLPyPjVZXih4zEGDFX+VrJ48rzdYNnpRmcYJ6nXQ5FvilGuRrKCYVAoRgjjccpKZgYjgqSK4clSEHMAyf6pG1aNkBWpfih5oaR+PshJZSZnFqCGN8o1QpuGBmcRLo+FwdToXT/L9bI1QBRajIm45SF7EmH1YJwNMKkYsRaA2S5YkSrhAOBlVo6rBp/6ihZ2j+PWsANIwMTjQlS+4dMi/nlC0r66Vkk1wlPCkSlPBmzog6Ix2BGbxBMKkakIOYLHx/EG58dAaBtA2SnLTlTkeb9Yyddn83K10oqRqzUkNIKbhgZGPmbRL5a/kPhUGihZ5WAVPU6u/GgmGLEUBaMdI4MKkakIKa8hU3DcLdmBTGTYrIoG0asqBZ5qRjluachP886T0gyjLhilJL8VYyyGw9KTcas9MUC9FHbipWMOZvFBHPce0b75aLbFwIARGLa3gepiKUSykwOBoiS2XJSDak8XTe4YWRgyMRut5hhNmtXTZhl8k0xyqVuCqCcYpQICtd+SkrU5mF3TJDF8FtjKjUtiCmWcFBmgfb6wwC0V+6IoRyNCYhQrvgulSTIQTFSpIFvJLdYRL2j/SzEUYxEoC2/zQOh5NsgiwRzdE8oVemYpexJPShG5Nmedma1pgUxAeUW6GAkHh/JSIwRQH+eyMUAIf9GCcORGLlax3dpBY8xMjAsBbSyipIdqlkkd1eaMuoAS3VTlHwTpwVLFe1FxShMZUyQcgRAwpXW5g1IJQnULkcA9GuFE46iyEFv2ZTm6CzuI4nHC0VjiMUEql4BVuK7tIIbRgaGpRRoVtGDOkCTXJsKK6UYsRh8rUTsBi0SFcy1v140DclU5Qhe3nQIL286BED9cgSA6C60W80IRWL0FaNcstJsyYHvNCuE86w0jmFhKaCVVZw6iCehSa5jQqneWKwUeASUbYxKi0TWkPbXi6aKSMoRAMANf/4EHX0h/OySUzHrrDoA6pcjIDjjhhFLZSqcSU2do9QMo2hMQCjKDSOOQQnyPmlDkm+KETnP7As8KqUY5aZk0UQpdyFNWHKT0xwTpByBnPHVJZqVIyA4bBYgEFHshSCbWB6rxQyr2YRITKB6XLzMCw++NjQsxSGwih4ykGiSa+xAIotPKZeC9mNVD4pRkCXXo0KGZDBKjGXtM2qlMhWUx4Q/FAEA9AYjWf17JcYqL/PCDSNDwxvIDk2+KUaBHNP1yb+jvUCwFHytlPFHExYNSdovF+H4GKstdVH93mxwKlD0MxKNId6YAD2BcFbfoYS6SZ5FuzV/y7xww8jA5HtmQTrka4xRtkG7ShkNuZYRoIlSxh9NWHrpUaJlhiAIUrr+8DLtDSOHAoqRPJDbzlAyBEuJEFrBY4wMDEsBraySd4pRju7VhNGgULo+A9K9vhQj7RcvJRQj+fPIhPFHUTEiJQlIOQIA2NPWK2VDZlKSQBHFiCE1Uiu4YWRgcu2LlQ8o2YiRRXJVGpSqFM5SgcdEmxh2FSOWXI9KKEZyA4QpY1mhkgT3vrld+nsmJQnsChil5LsC4SjavQHNC4hqATeMDAy3/IdGyUaMLJJ75WuFm8iyoIAwrhiFozFEY6KbiQWjQYlniLiszCaxH5vWSEophXMkJQmaO/vw78s/BwA8MmeilHmXSUkCJYxSoj55AxG09wS5YcQxFrlUVc0X8k0xyjXNW7kmskTd1H6ssj4m5NeehQKPSlwv+UudycSAYUTRAElVkqBhuDurkgRKuDHz5SVxMLhhZGBYegtnlXxTjHKthq6YYpRDl3HasD4m5PEkLLjJFVGMGKrTBLBrgBCb8Xi8jUoukNinPW290jbSigXQph2LVnDDyMCwlLnCKg4FpGiWyb1XmlKKETtuX70oRg6rmQk1xaFATBZrmVFKNGwlxl9FoT37it7xdP8TvbkbRqlin+7JMvZJ73DDyMCwlALNKlIjxgj9RowskjCWc1OMQpRTs1nq/cV6gccgQ+1AAFmvNANnRkmKEcUx4Y+fY315QdZKDAm+Ji08coHEPv2zqQW//+BrANnHPukdbhgZGJb6KbGKvJRBKBqD02zsa5VQG3JtCUJvEZRP6iyMVdZbggQYa/XjUKDuUyDH1jW0UTYtPrP7SFxeAOALid/R3OmT3F7ZurxI7NPm/R3Stmxjn/QON4wMDEv9p1hFfm2C4RgTC7NSyJWZ7F1p9AtiBlhLzWZcMWJNTVFWMWJj7iJj4pMDHdRS2LO9j6lcXu/uaMO7O9oA5O7yYtWFrCbcMDIwrE2gLGKzmGExmxCNCQhEonDDpvUhKYZ8wsu68rUCihFx+bKSmq1U7y9asJZtKhnLisQYsXWO2496qaWwZ1vUlLi8AOC/V3+Fj/aewMVjK/GLK08HkLvLi1z7s0e488p9JocbRgYmV7dJvuCwmuELRZmtW0MLGkXzlFSMWEnN1o9ixJaaQvP5CTLmLlTiOLKNAZWn+9e6xf+6XTZqLi8yvi44tSJvstD6ww0jA5NroG2+4LRZ4AtFme6NRYMghaJ5ZBGMxAREojFYLbmPrVxLCNBGcg0x6lIIMhZ/41BCMWIkPpLE85zoTbTvoJXC7o/HB7ns2Z+jEgpuIhGCjfGlBdwwMjDclZYeSrzxsggNZUbuggvRMowYG6cOilWOlYC960VKOBgvK03JFPbEC0H251hWYAcAWChm07KmSGoBN4wMDGtF0liFddcJLWgoM/JJPBCOIT4v5wRr49QhU4wEQWDCvSdHUlOYUdiUqGPEhtpN4nk+2nsC/736KwD0UthpjPthCsQAkTICLkaeRy3ghpGBCTLmomAV1tOzaUHjLdxiNsFmMSEcFagthPKChSxAjD9BAMJRAXYrY4YRa4akgoqR1vGRJJ6nzRuQttFKYaehzCihbrI2vrSAjZmIowh8gKdH3ihGlMZDoqEmnYWQtQrt8oWKxbgz1lwdkmJk4MVZieOgcY4OBeLhggy159GK/D3zPIC1CZRVWE/PpgUtBTExGdNVjFgZp3aLWepBxWLcWZARNYVAFvbeYATtMmUlF1jqnQcknhm3y0othZ1G2xNlFCO2SiVoARujjkOdSDSGSExspJPPAzwduGKUGVJvLEpGAyuBtgSTyaRI01BaBBjLNiXXKiYgyeWUC6yNCXIcLpuVWgo7OcdcstKUyKBkTa3TAjaeLA515A9KPg/wdMi3GCNaihEtoyHbQndKwnIjWVaNBoBOzy5AVseImbgz+i9PNEoSKKEY+RkbX1rAg68NivxBYSWolVXyRzGiM+HRNhok1xAjCgjA9phgxTAiNX4iMmPoi+ZuaXzkUuOHlXMkKNMrjbRsYk0xYsuNqQXcMDIo5C3cbjUbvmN8rrCsDtCElgvGSVsxYjCmgWUVkZUeiKlq/Pznyl3S32nU+GHFMJLH1dEq4UDDAFHSYGPl2mtBRnfkmWeewVlnnYWSkhKUlJRgypQpeOedd6TPBUHAkiVLUFdXB5fLhUsvvRQ7duxI+o5gMIiFCxeisrIShYWFmD17No4cOZK0T1dXF+bPnw+32w2324358+eju7s7aZ/Dhw/j6quvRmFhISorK3H77bcjFAqBI8JaCjTL0F7oWSVITTGi+5bKSs0aOVwxGpp5k0di5cKLsHLhRbDHK6n/fMY4adu8ySOz/m7WxgR5eYrFSzjQgIbLSolxSmue0DMZjboRI0bgkUcewaeffopPP/0Ul112Ga655hrJ+PnNb36Dxx9/HE8//TS2bt2KmpoaTJs2DT09PdJ3LFq0CG+99RZWrFiBDRs2oLe3F7NmzUI0mrixc+fOxbZt27B69WqsXr0a27Ztw/z586XPo9EorrrqKvT19WHDhg1YsWIF3njjDSxevDjX62EYWJk89UC+KEZBSrE8tK8Xi2NViTRoWrBS3qCqxCnV9CHHckpFobQtlyBl6cWOkTGhRAkHEkeVSyHFRKkEiooRYxmBWpCRK+3qq69O+v8HH3wQzzzzDDZv3owJEybgySefxP333485c+YAAF566SVUV1fj1VdfxU9/+lN4PB48//zzeOWVV3DFFVcAAJYtW4b6+nq89957mDFjBnbt2oXVq1dj8+bNmDx5MgDgueeew5QpU7B7926MHz8ea9aswc6dO9Hc3Iy6ujoAwGOPPYYbb7wRDz74IEpKSnK+MHqHvHEFw1G0ewN52wwwHfJFMQpQiuWhfb1Y6/0FJIxHmrV5aMFiDIg9rlyEaBvLjLhXSQkHQYgbIRSmUxovBEQxCkVjiMWEnMMmItGYpIixcu21IOsnKxqNYsWKFejr68OUKVNw4MABtLa2Yvr06dI+DocDl1xyCTZu3AgAaGxsRDgcTtqnrq4ODQ0N0j6bNm2C2+2WjCIAuOCCC+B2u5P2aWhokIwiAJgxYwaCwSAaGxsHPOZgMAiv15v0x6gQadUbiKC9J6jx0bBNvihGrAZfs7jQs6wYsZjFR1LOCx10wlZZc6UpUcKBZowRQGesBmTfkUsZAb2T8R3Zvn07ioqK4HA48LOf/QxvvfUWJkyYgNbWVgBAdXV10v7V1dXSZ62trbDb7SgrKxt0n6qqqpN+t6qqKmmf/r9TVlYGu90u7ZOKhx9+WIpbcrvdqK+vz/Ds9QOLhelYJX8UIzop0NSDrxlc6Ml7N62ChTRhMQak0C4aRLQW0yBjwdcA3RcCQRCoxhgBdJ5Hns0skrF5P378eGzbtg3d3d144403cMMNN2D9+vXS5/2j9dOJ4O+/T6r9s9mnP/feey/uuusu6f+9Xq/hjCOSQrunLRHX1XTUI/09lxRao0I7mJhVpMrXzCpG7CyCJLy2o4+9hA42FTa62VEsZkY5bWZ4/HQMkHBUQLz+bk4vBFaLGVazCZGYQEcxkiXtsNY8WU0yNozsdjvGjBkDADjvvPOwdetWPPXUU/jlL38JQFRzamtrpf3b29sldaempgahUAhdXV1JqlF7ezumTp0q7dPW1nbS7x4/fjzpe7Zs2ZL0eVdXF8Lh8ElKkhyHwwGHg343YpZIlUJ7z5vbpb/nkkJrVBwKBDCyCL3K18q0BGHpDdVuoRszQxMa9W9o41RoTLBk/EmBzhTOUR7A7bTnWHDVakYkFKWkGLFnkGpBzqNOEAQEg0GMHj0aNTU1WLt2rfRZKBTC+vXrJaNn0qRJsNlsSfu0tLSgqalJ2mfKlCnweDz45JNPpH22bNkCj8eTtE9TUxNaWlqkfdasWQOHw4FJkyblekq6hqTQ3vbtMdK2R+ZMpJJCa1SclHt/sQotA4R2JkyQkcm43RtA01EPmo560BeMAACaO/3SNlbcaixmDdFUjFhtZyS9EFA4R/IsmkwJIzxbEgYbveNiaWxpQUaK0X333YeZM2eivr4ePT09WLFiBdatW4fVq1fDZDJh0aJFeOihhzB27FiMHTsWDz30EAoKCjB37lwAgNvtxk033YTFixejoqIC5eXluPvuuzFx4kQpS+2MM87AlVdeiQULFuDZZ58FANx8882YNWsWxo8fDwCYPn06JkyYgPnz5+PRRx9FZ2cn7r77bixYsCDvM9KqSpyoKnHikwOd0jaSPstJDe3eX6wSoJTmTV0xYmShT6W2rt3VhrW7RAWbFbWVRdcjTcUowGg7I6mYIoVzTLQ8seTssqIZFC71b2PoumtBRoZRW1sb5s+fj5aWFrjdbpx11llYvXo1pk2bBgD4xS9+Ab/fj1tuuQVdXV2YPHky1qxZg+LiYuk7nnjiCVitVlx//fXw+/24/PLL8eKLL8JiSdyI5cuX4/bbb5ey12bPno2nn35a+txisWDVqlW45ZZbcOGFF8LlcmHu3Ln47W9/m9PFMBK0am3kA1IwscGvGa23QdrVdllZ6OdNHolpE0RX/G/e/Qof7jmBi8ZU4p6ZpwMAta7quSAIQsKVxtBbPc0xwWoAME3FyE9RmaGrGLGh3mpNRobR888/P+jnJpMJS5YswZIlSwbcx+l0YunSpVi6dOmA+5SXl2PZsmWD/tbIkSOxcuXKQffJZ8gAP2u4m4kJnWXyRTGiVuCRsusxSKlVSa4QtRUAhrtdAIBil5UptZXV5tA0VURiGLHWzoimYkTzZSDhxqR3XCzVFNMCdsxxDlXIAJ98ajnPQhuCfFGMaLcE2XXMSyXuJhH7xM5kbI8fC2vB13LjnaX4G7qKEZ2yErRJdLKnd440XFY0s2oltzZj115t8vvsDQwr7gk9kC+KEb3K1+L1OtDho1I8lEX5vqLIBiBRz4gVyMJlNgE2CztHl3AzsaWm0ERSShlTZmjWFWPxWdQCbhgZFFYnFxZhuWEoTQJhSq40ym+TLGbCVBYRlZUd4wNIzuBjqc4MzTgXFos7AonnJsBY9hfNumI8+FqETv12DnNwyz99aAcTs0qu2V+keGiLJ+E+y7V4qCAkCtOx5EpjtYRDgFGjgW5mFBsxZ/1JKEYUg68pjHm6ihF7LylawA0jg0Iz68HoyBWjdCq165Vc6wUpUTw0OZiYnbGqRNdyGiSaq7JzrQClaumwZfwlFCOK6fqMKkasXXu14YaRQeGSaPoQP39MEEv1263GM4wEQZAm9GxjjEg6+65WL37+1y8BiMVDSdZWNtmP8rdcliZjVgPyWVWCFYlzYUhBBGQqIo3g6/i4otFbjscY0YcbRgaFlWrCekAeMxOMRGFn7G2cBqFoDEK8N5PXH0FV8eD7p4Kks5tlilquxUPJRGwxm2DLsQIwTSR1gLHGwqymUyuhWrBUpwmQZaXRTNenYPwlkkdoBoWzde3VJr/P3sBwV1r6JBtGbLlOaCGPn/IGcmuMSnPSDDKaHuyQ3sLZGg8s9pUD5NeLXh8x1l7qlFBmaGal0U3XZ+vaqw1bTxeHGtxXnD4mk4lq8CiLyIOIbWY66fpmU+7VoFmV7h2sKkaMFMPsD83rxe6YoGeA0HxxVeLa03Dx6RnuSgOASB8QMdZACITFJphOc0g8P86g2CwmBCPAsY4ujCgWtD4carT3BNHeE0KrJ1FvaMeR4zDFxMyyqmJ7xsaN0yQqTjEBqHBGchpfgUCv+J1WE1Pj1GkWr1cwEmXquAIBHwDAaQVTx+U0i2MiGM5tPABAIOgXv9MSY+scLeKcGgzlPqcGgoH4d+Z+jk5LlNpx+YPiuHeac7+PiqPg8XHDCADerAMKtD4Iuvh7XgFQBuf7FwGuA1ofDvPYIssAlKLl3R8CZR9pfTjUWN46F0+1z03ads/f9kh/v6PqVdxZ82pG3+mMOgH8LwAg9HolXObsizwGes8E8N/o621H+/J6VNm6sv4umjhDwwC8gECgD3i9SOvDkQie+A6AW+BsfRt4farWhyPh6J0I4GEEOncBr1+a03cFW+cB+CGch/4EvP4HGodHBUfXpQDuRvDIWuD1KTl9V+DIrQBmwrX7IaB7RU7f5Tx+LYCfIPD1q8Drj+X0XcFDvwIwGc5ttwPNa3L6LsXxKffV3DAyKMGYHUDizZczOHaT+DYYEmwaHwld5lW8g2klW7A3UI87j9wNAHhk+O/Q4PoaAFBl68z4O4k6AACBmD03w0gQ1aruqBvt4XJ2DCOigAgOCALASgUHcr3k94AFJIUtlvvzEyBzl4m1cxSPJxDLvfdkMEbuY+7zs8NExqo95+8KCGTdYOvaqw03jABgzjGgpETro6BKYMd6AAJcs78E3LxXWiqImwkAhAPbgZ4Q9ox6HE1nix3Ws3EzsUZV/I/vYDfwp20AgIZrXkJDXRZpaXEsAGw71yMcFRC46kBO4yuw8zhwYIf4P9M3ADkcF00cgQiwcwMAIDjHw0y8S+CDg0DLQThPmwt89wGtD0fC2doLPP0pAo564PrenL4r8PYe4MQxOBvuBK74HaUjzB3n7g7gle0IlE7O/Rz/sgPoPg7npEeAC17J6bscjS3AW7sRqL4auP7+3I7rj58BvV44L3oBOHNYTt+lOF4vsKBOka/mhhEAWAvFPwYhEo0hHBXjZJzOYsCa+5uEEVn+6dGTChY+9/ERPPfxEQDZFSxkFX9MpjtbXDmPd6fVgnA0goDgzOq7SBXtvSfC0ram1hAQj+PIpoo2TZyuRIBtQHDCycgzFIiJBprT4WBqznI4xPkmGBFyPq5AVAxIdjqyG1tK4XCIsU/BKHI+Lr84zOF05P4sOhyu+HGZKFz7+HE5C5i69imxKpcYwQ0jAxJIqibMxpsui5CChQBw6/LPcKjTh3+bPBI/+OZIALlnXLEEyVipKXFQOS+HzYyeYPaZMEpU0aaJzWKGxWxCNCYwlbIflNK82cpKo1kpXEplZ64kAb3WQQGK9zHR0ih3Q8Ef4tnMADeMDIn8AWFtcmEJUrAQAMoK7DjU6UN1iTOngoWsQsbEqcOKqCgxuaYIE6N05ZfH8If1+wHkXkWbNk6rGX2hKFP90litM0PmmVA0hmhMgMWcfVAWq6VGaDablipfUzhHmmUEWC2VoDbcMDIg8iJw5hwmqHyCtAEJGbbAI90WMc4cCyASo/TjfSekbblW0aaN02ZBXyjKlGLE6sIlP55QJJZTHZxErSY2z5GmYkTjHGkqRsEcG00bhfw+e4PC6hsXyxS7xGwaI/ZJA+hL5ImmoblNxiwZHf1hsegnq93P5cp0rteL1XOkWfk6SHGOToxTigYbY4qk2rA18jhUkKqXcsMobUpdYnCtzaATAu23cFpvz6QC8DfqS5lwn8mh+SZOC1YVI6vFDGtcnc7VpROk2EeMJvJ+cIKQWxFYmpWvEy8p9PrU5Xvla24YGRBW37hYhubbIIskFCM6YyLRn4mOOnDhmApNs9BSIQXbMuRe7QmIWXw0GobShpYhyarxJ392cjVCaKr6UoxRjtc9HI0hEotnMzNmlKoNXzkNiJ+70jKGZvwAi9AM9gTo9WeiHftEE8n4Y8gIIYYRS8YagVYQcIDROBeHzFjI3TCip+rTUoySknYYu/Zqk99nb1Bodm7OF4yuGAWoxxjRiWtgOR6OvDWzZISEIuIbvYPBWDh6ihGbY8JmMYHksuRiLAuCIBl/NAyQ/hmB2UKeZZOJZzPzrDQDkngLz+/BnQlOK51gYlah3TXbSUkxYlndZMVYJsUwAcAbV4yOdQXQdNQDQPtimARaweoJVxpb85fJZILTZoEvx0zFUDQGEqJEMysNyC0jUJ7NbGKlB45GcMPIgLD6xsUyRnel+WWTHg1oFbtjNZ4EkAXbamwYpSqG+dyGA3hug9gcWutimAQHZZeOg8E4F4fVDF+Ota0CIVkBXgrn2D8jMFvDKJGqz951VxtuGBmQAKNZHSzDijqgFLSzTWgFX/t1EGOktbEsr9D+gz9uRm8wgjsuHyttYyWbj4ZiJAiCZFixuECLxxTOaUwQN5rZJLrncoVkBEZiQk5GKc9mTsANIwNC222SD5C3Xb9RDSOy2FAylmkpbIl6Lmy5TQB6tZpyRV6hPRaPIZlQV8JUMUxAbixnPybk/7YnEMYwRow+Ao3q13JFn5bLymmzoDcYycko5Z6GBOzNRpyc4en6mcNizRqakOBr6jFGhlaM2HOvkgWZxeBYGs+Q/N96/eFB9tQGGmNCCWWGRkYgbXe7nuFXwID4GfbRs4qTYvVYFqGdAu2g5HqUxiqDhhGtc6RFOBpDNB60O6K0QNuDSQGNxVn+/Fkt7C1PDorGH01lho5Ryq4LU224K82AcFda5hhdMaLeEkQqKsdOPRfaOCipYrSQu3lHlLs0PJLU5PIMkcy7Y91+aRvJugPYy7yjosxQVPTpGKXc00DghpEBYbUDN8vQLKvPIgHKGSfUatZQrshNE1aCrwnkWrNaZyaXxTlV5t09b26X/s5K5h1NdyHN+ZmmksXiS4racMPIgLC82LCK0bPS/CG6ygy1arukIjeD6qbTypaxHJDdQxbrzEhjIotniGTefdXqxd1//RIA8MiciVKAOWuZdzTchTTnZxoZgbT7KeoZbhgZENrqQD5gdFcazW7e4vfkPhFHojGE40EzLL6lsjYmWC6GCcgW5yyMBpJ5RwpYAkDDcDeDmXe5j4mgAi8DNDICaVfH1zNcUjAgLMdtsEqikjMb6gBtaGd/JRqs5v6GCrA5GbOmIrLu6shFMSKwcq0HImH85X6Ox7r8aPcGKB0XzaBwbhbwK2BAAgoE9xkdaRGMRCEI2fcbYpGkrtm0stIoZPGRgHD597FEovI1G8ayn/GFi0YqO3H51pU6mXGfyUk0Fs593B/o8EmtXqgdVy6KkVQKgk3DW03YfMI4OcG65M4iRAERBLGXkZGQv0WyFHwtf0NlM2Ymd3WAJpLqx2A8FkC3+OHYqmImstD6Q6N+lxJNiWmm67M6vtSExxgZEO5Kyxz5W3ggHDPUW5MSXbNpuB714hpixb0TVCCbiSY0+uexXPATSKjw2ShGpCTB4Y4+aRutkgRU0/UZHV9qwg0jA0I70DYfsFvMMJlExSgYjgIum9aHRA35hEevBQFZIIxbUI6Ge4ImelGMaMTfMOsulDIVMz9HJUsS0Ijv6vKJge8Rgynm2cANIwPCeiwCi5hMJjitFvjDUcMFYCux2NBI12deHaAQ0EoTEn/DriGZe0yWn3LrGto4cqhtRUoSPLv+a7z9ZQsAeiUJaChGpAWL0UIJsoEbRgaENwPMDqfNLBpGjMSU0EKJmDPyXaFoDNGYAIs5cyUqkSTA5jhltcAjq881DcWI9fjIXBoLk5IEBfbEskurJAHNMgIsJkKoDTeMDAiPMcoOcXIJM6MQ0EKJ8SBXn4KRaNJkny4JxYjNiZg5xYjx60VFMWJcRaQRW+dTYDxlqxiRuCcA6OwLidt6glLsEyutWNSGG0YGQxAERXrx5AMsdlOngRKNWuXB6YFwDAX2zL+DdQVE7i4UBEHzzDnmg9Upxhixeo5S8HUuqljcXXj56VXUShJkqxilintasbUZK7Y2A2CnFYvacMPIYAQZL5rHMjTK6rNIQAGlwWI2wWYxIRwVsr5erC+CyapYTPPniXVD0pEPMUYUszGvPruOmhqTbV0xEvcEAD95+VO0egK46aJT8N1zRgBgpxWL2nDDyGDIJyVWFxxWYS09mxZKLahOqwXhaCTr6+VnvAWB/LiCYe0NI/bjbyioKYyfo4NCNXQlzpEYpV+1etHuDaRtcJG4JwAgYYLjq4uZa8WiNtzXYjCIjC2+0fPbmwmJgn7GcqUppcw4ZK6mbGC9aaXNYpaCylkIyJcaARtYTfEzHh9Jo7GwEqoYUYwO5lBNm7xU23kdI24YGQ3pLZxnFmSMURUjpZSZXHuJJRYIdscqS+5VqTk0o882DcUowLgrjUb/PCVeVGg82yRNv640/4Kt+8NdaQYjoEDn5nxBehtkYBGkiVLKTK7B6omFnt2x6rRZ4AuxUduKdaOBKEbhqJB1CQfWs9IcNBQjiudIsspauv3StmyraZNzGlFWkPNx6R1uGBkMMoEbqaWFWrBWt4YWCcWIrtKQa90a1hd6IKHO5KKC0IL1+BuaJRxYP0ePL5RRLI+cRAXz3J9HWtW0ozEBoQjbbkw14YaRwVBqEcwHjOpKk1REhRSjbBU21luCAGyVcGA+K41CCQfms9KkwqYC2nuC2RlGFF3bJKtsb1sP7nz9CwDZVdOWz3msXns14YaRwZDcE4xOniwjLYIMqAM0CSgeY5Sd0cC6OgDIG6NqPyZYD0yWl3DIVmFjvoSDLL4rFhMy/vexmCC5rGicI8kqk1erzqaatl82vnnla24YGY4g4xMLy+TSB4llpMrXlN8EnTlWhma9YSjAWPA1401kAXkJhyzjzhidv0gsjy+UGAfbjnTDHI+jSjeWR/7SRfM+5vpyISl1NnqNpvUMN4wMhh7ewlkl14WeVQIK9UDKtZEs64G2AFslHCRDkuH4QYfNjJ5gds+QvGq/k7FMxVSxPP/f33dIf083lscvM6xo3ke5kTWsKHMfJrnuBQwb3WrCDSODkYjbYGti0QMsxZPQRKm4jVyL3bEeMwPkHkdFE5pBu0qRS9ZWKBoD8U6xNibkFaKvefpjRAUB98w8HReNqQSQfiyPX6aSmrPI2hsI+cuFO4vgLtaLraoNN4wMhh4WG1ZJqAPaL4I0kdL1KSsNOafrMx4zA8hURAYUIz0sXrkYy4EQu1X75RWinTYz+kJRjKooyDyWJ6SMSiofE/5QNOMx4teBm1ZN2H314GSFHjJ9WIUldYAmSqXF55qur4dmx1LRQo3HhDxol+Vn2xKPT2nzBjL+t2Q8WBmv2i81ks3ihUAp97HFbII9fs38WYxVPbi11YTd0cfJCr8OAlpZxah1jBKZisrEGBm1iSwgb3OhrWEkd02xfL2IPdPuzbwthV4WZ1KfqTCLFw1J9VNAmSHPdzaGUUAhJUuv8NXTYPCstOwxavC1Yi1BcuyNpYssK0aMZflix7JiZLOQOj9ZqCkKGg00KXKIhlE2x6mk8UeeI3mAd7okgt7ZvvZqwWOMDEZnn/imFs2ixka+Y9g6RgrVtsrVzSS5fRnOsmKl6Cf5fbussS0rkFR2AAjFx9r+E71Sa4p0U9n1ohjlYoAoqZK6chiriWvPtRKAG0aGo9sXBgBEuGGUMUatYyR1ZVeq8nWu6foMv6U6cjxHWrDsIk+Vyv5G41G80XgUQPqp7HpwrQKJ48splkcRV1oOx8VdaUlww8hgkAncZmHrrVIPsKIO0CYYVlYxyuZ6haMxSdVkWzFio8Ajy60y5Knsv/p7Ez4/3I2ZDTW49dtjAGSQyq4TV1pOykxIuQB6KkoW49deLTJ6/Xj44Ydx/vnno7i4GFVVVbj22muxe/fupH1uvPFGmEympD8XXHBB0j7BYBALFy5EZWUlCgsLMXv2bBw5ciRpn66uLsyfPx9utxtutxvz589Hd3d30j6HDx/G1VdfjcLCQlRWVuL2229HKBTK5JQMQbs3gKajHjQd9eBEryhpd/SFpG3tWWSI5CO5xsywilIuCikwOQvXY1LMjA7q8midrh9kuNVPVYlTakNRE3eZlRXYpG3p9hPTizvHSSGWR0lXWjaKkU8HpSDUJCPFaP369bj11ltx/vnnIxKJ4P7778f06dOxc+dOFBYWSvtdeeWVeOGFF6T/t9uTC04tWrQIb7/9NlasWIGKigosXrwYs2bNQmNjIyzx4L25c+fiyJEjWL16NQDg5ptvxvz58/H2228DAKLRKK666ioMGzYMGzZsQEdHB2644QYIgoClS5dmdzV0Siop+2+fH8PfPj8GIH0pO99hJTWbJuFoTHKr0s9Ky971SN5QTSZIacYswo5ixH7NJ0BewoGdVHbaJAyQ7Mc9uzFGbF97tcjIMCJGCuGFF15AVVUVGhsbcfHFF0vbHQ4HampqUn6Hx+PB888/j1deeQVXXHEFAGDZsmWor6/He++9hxkzZmDXrl1YvXo1Nm/ejMmTJwMAnnvuOUyZMgW7d+/G+PHjsWbNGuzcuRPNzc2oq6sDADz22GO48cYb8eCDD6KkpCSTU9M1cin7tlc/w8EOH+ZNHokffnMkgPSl7HzHiMHX8kmS9ttgLg1WA7KFnuXeTERF3N3qRbs3kFU3dRropdVPeaH4EpxNfLhe3Dk5xRgp6BIlSlYuLyrcMBLJ6VXN4xGzDsrLy5O2r1u3DlVVVRg3bhwWLFiA9vZ26bPGxkaEw2FMnz5d2lZXV4eGhgZs3LgRALBp0ya43W7JKAKACy64AG63O2mfhoYGySgCgBkzZiAYDKKxsTHl8QaDQXi93qQ/RkAuZZOMlTFVRRlL2fkOWXTCUcEwWX3ySZJ6r7QcyhvoZaEnx3e40y9lXmmBHhruAkBl/CXMhMwtIz1U9gYSRg1r455Vg02PZP2UCYKAu+66CxdddBEaGhqk7TNnzsTy5cvx/vvv47HHHsPWrVtx2WWXIRgUJ5XW1lbY7XaUlZUlfV91dTVaW1ulfaqqqk76zaqqqqR9qqurkz4vKyuD3W6X9unPww8/LMUsud1u1NfXZ3v6zMJbgmSPfNHR2nVCC/mCSluZkVyPWbhN9PKGyoohohdXB5WMLcbPUcr+yiHGSIlmrS4Kx8UNI5Gss9Juu+02fPnll9iwYUPS9u9///vS3xsaGnDeeedh1KhRWLVqFebMmTPg9wmCkDRxp5rEs9lHzr333ou77rpL+n+v12s44ygSFZWOWjdXiTJFnh0VCEdR6NB/0qaSBkguvdJYbwdCavO0eBKJC6QuD5B+bR5a6M3NlJV7VQe98wBKyoyCWWnZKVn6uPZqkdXMv3DhQvzjH//Ahx9+iBEjRgy6b21tLUaNGoW9e8Xg4JqaGoRCIXR1dSWpRu3t7Zg6daq0T1tb20nfdfz4cUklqqmpwZYtW5I+7+rqQjgcPklJIjgcDjgcxo63IRVnh5e6ND4S/WGO9xsKRWOaZyHRQknpPpfecqwrRqkSGu55c7v0d7UTGiQ3E8OlDYDE4uwzcMq4K4fWG8q2BMneYOMtQZLJ6HVNEATcdtttePPNN/H+++9j9OjRQ/6bjo4ONDc3o7a2FgAwadIk2Gw2rF27VtqnpaUFTU1NkmE0ZcoUeDwefPLJJ9I+W7ZsgcfjSdqnqakJLS0t0j5r1qyBw+HApEmTMjktQ+HjvuKcyKU7OIso+RaeSxNZ1l2+8yaPxMqFF+F3PzhH2vbInIlYufAirFx4EeZNHqnq8UhVwhl/rmmoKayOCYKkzDCWri/1SuMtQXImI8Xo1ltvxauvvoq///3vKC4ulmJ53G43XC4Xent7sWTJEnzve99DbW0tDh48iPvuuw+VlZX47ne/K+170003YfHixaioqEB5eTnuvvtuTJw4UcpSO+OMM3DllVdiwYIFePbZZwGI6fqzZs3C+PHjAQDTp0/HhAkTMH/+fDz66KPo7OzE3XffjQULFuRVRpoceQdubvlnh9NmQU8gYhjDKOGyUu4NlQSrZ9KqgnW3SVWJE1UlTqkvFgApmUEL9BJ/Q6VfF+PnmFOFaUbrGOllfKlFRorRM888A4/Hg0svvRS1tbXSn9deew0AYLFYsH37dlxzzTUYN24cbrjhBowbNw6bNm1CcXGx9D1PPPEErr32Wlx//fW48MILUVBQgLfffluqYQQAy5cvx8SJEzF9+nRMnz4dZ511Fl555RXpc4vFglWrVsHpdOLCCy/E9ddfj2uvvRa//e1vc70mukX+QHDFKDtYaRpKi4TLin4sTy7B6npZBOVBsoKgXaaiXrLS8qGWTi4GSMJdSP8+5laRWx/XXi0yUoyGmhhcLhfefffdIb/H6XRi6dKlgxZiLC8vx7Jlywb9npEjR2LlypVD/l6+kFRNmPFYBFYh180oRR6VdFnJx1hzpw+n16av1OploZe7FtwFNs2Og/WYLAKdGCO2x0ROqpiC7kLpuBjr4aZH2B6BnIxIPHRmmBnrwK0XjFbkkSw2Ld1+6q1hzGYTrPFxJs/eSge9qAMFsuMrdmhnGOlFYWM1Y4smrKpiOZUR0Mm1VwtuGBkIvSw2LGM0VxqZ8A50+BQpUGi3klpGmU3GUjAx42PVajFLLUt8GqqIugtMZqz4IU1yyv5SUJnJtlWJIAi6ufZqof9CLRwJMnkW2PltzRZnDm+DLKJE2QFS4wcAzPGaYTuPeTGirABAejV+9JKaDYjHGPLHsnoTp0VAJ0kV5PjCUQHhaAy2DPrg6eXFjoYrTck6RpmGAcgLtOrheVQDvoIaCL9O4jZYRuqmrnPFiBgvh070SdtoFShMVePnd+/vw+/e3wcgvRo/UowR5TYlSlBgt8DjD2trGOmkDIf8+PzhaEaGkW7OMcvCpnJlhqWsNPm4Zt0oVQtuGBkI3u8md1jppp4rShYolDct/slLW9HqDeLHF56COeeKxV7TaVrc2RcCAER00JMuEVAc0ewY9PLSY7eYYTYBMUE0dEqc6cdl6UYxih9fKBpDJBqDNU3jLxSNgQx3lgo8kv3tVnNGJTeMDDeMDITUh8fGb2u2GCX4mhgvz6zbh1XbxXpjj8yZKNXhScd4GQhS4wcAygrsaPUGUVPiyqjGj8cXBgCEo+wrc2Qh1DLGiPWCmASTyQSXzYK+UDTrBZr1c5S/eAYiMRSlaRgFQjKXlZJZaRkqm3oxSNWE7dcPTkYoWW4+XyBv5Ot2H6eexaUmVSVONAx3w2U/uUBhw3A3tT5fCUMyMzWFxDU4dFBWoiCHmBJa6GnxyiZtPBYTEkU/GZ+/HDL3byZjglwPm8WUkYsxXcjYCEZiiGWgxPKMtJPh0oKB8EmKER/g2UJq83xyoBPtPUFVG4UqQTaZM5lQ4hSnkHQmennQNnGlHe8JSLFPajdmTRdiXGZTm4cWegtWBzK7XkkBwIzPX0QV84ejGbnciStWKUVMft0CkWjaSTh6GltqwQ0jA6GX4EWWYV3GzxTyNnjFGVU5uc8GorxI/E6reWjDKFXc02ufHsFrnx4BoH5j1nQpyCE9mxZSeQMdKGxScHIWagqgj2fQZRcNo0zGhNKqX38lK13DSC8uTDXhhpGB4AM8e4ia4fGHpG20sri0hBhGs78xXJHjJ0Z4XxqByUlB2y9/ilZPIOOgbS1IuNK0Cb5OymbSwUtPNtlRAZ0FAEvnmIHxp7QyYzab4LCaEYzEMrr2UuNxxgP71YQbRgbCJ9UxYn/yZA0ls7i0ROm31MIM4m/kQdtk6RtfU6xZY9Z0yaXNBQ1Ik15AHy895BgzuV56iqECZJ3sM1GMQsrXonLZLQhGYhm5+Lgr7WS4YWQg9NJPiUWImrG6qRVPfyDW46GVxaUlfoWNZRJ/k45iJIeMVT0EX2ejDtBEniHpDYTgdmnXmiQdCrIIvpa3M9ID2QSYq6Hou2wWdCMsGWHpwIOvT4YbRgaCBPdxyz9ziJrx9fFeaRvJ4NIzSk/GBVmqKaF4mv7wUvbdk9meIy3ksTrdfWHUl2lyGGmTTVsQvb3U5RJHpahilIUbk4dgnIw+zHNOWpAeOXqZXFik0GDtVJR2rxJXmi+YYRuC+FgdUV5A/Zhoo3VWmnyRM5nYj7/Jppmp3hbnbIopqpEck01LI725MdXAWKtAnsMrX+dOgUO8duUFNt26z+Qo/SYuGQ0ZTMShSEyqeK2HYqQFWSggNCAJAQc76Ld1URJXNjFGOpu7clFmlI4xkv9WOvBs5pNhf1bipI0/HHelccs/a4hi5LJbmVx0MkEQBMm9qrRilEnGVlJvJh1Mxlq1BNFrQkA2hqTeVItsqkyrFWMEGPvaqwE3jAyE3t66WKQwrhj1BrXri0ULpXszAbJ0/QxcaWQitppNsOukiSygviuNJAR80dyN+//WBEAfCQG5pOu3dPvR7g0w/1KSlQEizc/Kjflc3Jh83UjADSMDwWOMcqfQQeJJ9G8YqdE1mxSRy6xuir6UzWy7lucKSQhok7Wm0UNCgDMbNSW+74EOny4qzmcVY8SoK02NMgJ6g/3XNU7a+HlWWs6QhT4cFRCKsN/gdDCU7s0EJNSUvgwUNp/OlE2t6xhp2YokG7Jpukte6vRCwpWWQVq8KllpmddX4nWMToYrRgaC+4pzRx6L4wtFYLfaNTya3PCFlI9pyKbBKhmneilEKqliWmWlxX/3lIoCZt1ncqQYozSuFwkwP6TTAPOsKkwrmPmaTRkBpXu46RFuGBkIHmOUOzaLGXarGaFIDH2hKErZzyYfEKWLOwIy12M4CkEQ0kon96uwQNAkm4KFNCEL15l1biaNhP5k4mbSa4B5bkHOCsYY5VB4kr9QJ9DHzMRJC729ibNKod2CUCQGn84DsNVMD47GBAQjsbTeOvXWmymRfq7NeJBiB3XyXGeippAA8//5YB/eaWoFoI8A82ziqFSpY2TNxjDiMUb94YaRQQhHYwhHxRQkPsBzo8BuRZcvjD6dxXb0Rw1lpkA21vyhaFqGESkrkW73b61JpJ/HEIsJMKvc5NSvt2D1LPrnyc9NDwHm2bjSPP4wACCoYOxiNrFPvI7RyejjlY0zJPIHlPuKc4Ok7BtHMVLuMbfGXY9A+v3SpCwYnUzE8uPUwp2mt+bQ2bge9Rpgnsk59gTjhpGCgea5uPj4upGAG0YGgVj9ZhPg0EFtGJYpkBqj6muy7k8ixkhZZSbTAGy9pes7ZY1utVjA9VZnJptaOiSDbdqEambdZ3JILaJMDBBiECnZKJcXeKSDPrRszpDIB7ce+imxTFE8oDiTFHQWUetNsNBuRbcvnLbRoEZQOE3MZhNcNgv84ajqbUEA/V2vrNplxI3l754zXF8B5kOMeZJ1BwA9AfEcj3b7pcw72ll32QRfc1fayXDDyCDorTYMy0i1eXRe5FEtF4wrw+vl05kCAojX0B+OaqIYJYLV9XG9smmXoTd3YbrGX6qsuz+s348/rN8PgH7WXXZlBMTnVu8vgjThhpFB0JvczjJSCnqGHeNZQ41Ku0DmrjS9KSBA/Lnq0yYzLWFI6mO6Jo2BIzEB4WgsreKiarl9aeGyp+eyIll3APC9ZzYiGInh7unjcOn4KgD0s+5cGboxw9EY4jk76A1ww4igj1HIGZKAzt4qWcY4ipE6ldAT1yszw0hPYzWbQpa0COjMkHTKeoH5w9G0DKM+hZsd0yYRyzN4IDXJuhOERCX9iSOUy7rLNPZJriw5dFI+Qw24YWQQ9Ca3s0yiX5q+FSO1sr8SlaEzdaXpZ/pJ1DLSwJUW1lerH7vFDLMJiAmiUVfitA35b/QWCiB3WaVT2DQYiSEuzCQF89Mm3eKaJPapoy8obfuqtUcyYlmtOK4W+pmZOIPCXWn0yKb/F4tI9YJUcqWlH3ytL3UAyK45Jy309tJjMonB6n2h9GOy9OZeJUHO0ZiAcFSA3Tq4YSS/DiPLlSunn64rLVXs0706qDiuFtwwMgg85ZIehXajKEbqGMsZG0Y6rNCuZb80vRkNgKgG9oWiaRmSoUgMkZiop5D4JNaRz7P+cFSq5TUQxK3tsJpRW+pS7rjs6bn4SOzTvvZeLHptGwB9VBxXC32MQs6Q8D5p9ChwGEMxUss9USAZkmm60lRobksbl2T8qT8m9GhIkliXdAwjubGpl/nLZjHDajYhEhMQCEfhdg3uLlQtQzT+TIWiMUSiMVgHiO8isU/ylxk9VBxXCx5tZRASihG3dXNFqmOk8+BrtVTEhOvRmG4TIOGO9GnpStNhTFY6ChuJobJZTEMqLyyR0TmqlHUnf9lo7vIPub/e5zil0M8o5AxKYvLktzRXpMrXBknXV9oAybzytQ4NI42y0qKxRDaTntzk2RgNejo/ILNiiqS9kNJjXt714Einb8j9SUmSulJn3rvP5PBV1CAkFkH9vFWySqGGbhOaqOWyklxpGaYI60nddGYYR0UL+RjUkyGZSbA6WZz1NndlUkxRehlwKHuOJpNJMo7SaVZLFKPx1cV5nYXWH32NRM6A+HUYt8EqBQ5jKEZqu9LSbbqrx3g4EhSsdlYa+T2TznogZmY06C9LEQBsZjETraXbD4wsG3RfqU6TQs+ivPWIJX5cO455UOMWjZ2B0u8TShY3BeTwq2EQ9CpHs4hRFCO1qgm7MlBTBEHQ5UKolStNuoc664GYSVsQPbaIAQCzRbwfbd7AkPuS61DoUOYcU6XfP/HeXjzxnrhtoPT7Ph26tdWAG0YGQa14knxAUoz0nq4vLTjKKg2FGWSlBSMxxDOzdbUQapWVprfCh4R0Cw0C+gzGBwBnRi4rZQPo5a1Hbn75UxzzBPB/LzwF3zt3BICB0+8TBhs3BeTwq2EQeB0jehDFKBSJpd3riUXUymbKpI6RvFWBnsZqprWaaKFXwygThU1PWXdylxUJiv/6eC+ajnoADOyyIkVNCxW6jyT9HgAqihw45gmgssgxZPq93lqxqAX7I5GTFuRN1skHeM7IXU++UBRul/4MIzWzmQoyaKFC9rFZTLoyOLVypUlKsI4C1QF5L7F0FCN1KrTTIJXL6n8bj+J/G48CGNplpYaBW5RBHTYS+M4Vo2T41TAI/nilUz1MLqxjt5pht5gRisbgC0WGLN7GInIXhlrp+um4mfQaC0dcQ1wxSo9MesslMrbYP0e5y+o/396JTw52YtoZ1bjjirEA0nBZqaCKVRSln3bPFaPUcMPIIAR0OoGySoHDgpAvptvq12QiViObKZNFUK9lJcjxptu1nBbE2NSdIRmfhz491Il2b2DQVHA91bWSu6xGlLvwyUExoHool5V0H1U4x+r48ZFYvsHwqWiw6Qn9aNmcQSHVY3m6Ph0KdV7k0S9TZpTOZiIyfDASQ3SI2VivCohWMUZ6DUwmyvWulh4pJmcgElmK+lqcSYX83jRentTM/ipxigq3NxAecl/y4qcHtU5NuGFkEPyhuCtNZxMoq0htLnSasq9mML58zA3lTtOrAqJVVppfp6nsmRyvXt2rtfEaQZHo0FlparrSip3ib/QE0ndt83UjGX2Z6JwB6QuKbwfpFtnjDI4UUKxXxUjFBdVhNcNsEqV7XyiKYufAMVm6VUAyqORME70tXCRr67hMJSIZW0DqrC29jokRZQUAgEA66fpB9VxpJfGYSK9/aMVIr2qd0vCrYQAEQUAgHnytV4WDNQp1rhipqcyYTCYU2K3oDUaGdDXpVQEhWWHhqKBqCQe/ztSUVFlb97y5Xfp7qqwtvRl/hIQBMvQcQca9UgUe5ZTEFaN0XGk8xig1/GoYgFA0BhLZYbfqa3JhFan/l06LPKpd8NNlt8QNo6Fcafpa6AlOWZHMw50+nDasSJXfTRiS+piqSdbWrlYvfv7XLwEAj8yZKAUnp8ra8unsHAnEAPGkocxIipEKZRcyUYx4jFFq9DUSOUkQ2bpH9mbwdXuvFBQ4ULExztAUZlALhEXUaiBLKLRbcBxDG5J6dZvYLQl34ZEu9QwjvakpJGtLrgg2DHcPmrWldPFDpSBlPNJRZpRuCSInEXw9+NwltufhilEq+NXQMalk6/v/1iT9faBiY5yhKcygaCGLqG2AuNJU2PRU5ViOyWSC02qBLxyV3NZq4NdpnRl57S+jZioSZaYnEEE0JkjNW1OhalaaK+5KG0IxCkVjiMTvDVeMktHX7MRJgsjWBzv6cNurnwMYWrbmpIfeY4zUjuWRGu8OobD5ddbTL2XX8qMeDC91AVBelVVb+aOF3DAaym2qVrNj2pTIkgx6AxG4C9JJOlAjK008jmAkhmAkCscA4RXyxBJeGDgZfY1EThJEtg5GEgN8KNmakx4FUh0jnRpGUiyPOo94Ip19KFeavtL1U6myv3t/H373/j4AyquyejMkCTaLGYV2C/pCUdiGKDCq1+rLdqsZLpsF/nAUHn94QMMoHI0hFFWvnEqxwwqTCRAEUc1yFKX+TXLd7VYzrDpqz6MG3DAyAOnUq+BkBokF0Gu6fsI9oc6ERyb8lV8ew7fGVg6ooujNbSJvAXHr8s9wqNOHf5s8Cj/4Zj0A5VVZvcZkAUBpgR19If+Qwcl6GxNy3C4b/OHooHFG8pcFNRQjs9mEIocVPYEIvP4wKgdoEZKoraS/66403DAyAKQ6c53byd1nlJAUI5260gIqFngEEsGbH+w+jvae4MCGkc4UEHkLiKoSBw51+lBeaFNNldVrTBYgxuAc7faj2xcadD89G38lLitavYPH85BMTavZBLvC7Xmk43LaRMNokJfmPp26MNWA62cGoDde3PH02hKehUYJSTHSafC12gtqum/7AZ2m6wNAkVQfRj1jWc0K5rRxu4ZOZw9FZAHAKrl9aUJiqQY7Ry0yC9NJ2SfxgGpkyukN/Y1Ezkn0xhUjkqbPyR3dxxiptKCS4GS/zIAcrNKxnt0m1cXieQyVZUUTPasppS47gMEXZ/m40eOYSKcvmRbB5ekUeeSK0cDwK2IAegPE8ue3kxbENXSowzdkd3AWUWtBzbTSccKVpr+xSjLRIjH10vXV7MpOG6KmdPsGUS3iza9tFvXcTDRJRzHSoogiyUwbrCo3GVtcMToZ/c1OnJMgcTCkeSAnd8hk0dEXGjRmhlXUUoxIcPI/m1rw+w++BjB4yQi91uUBgNKCoRd62ug1Kw2AlKWVjptJj65CIL22IFrE1Um1jAZTjIL6fUlRGn5FDADJSuPVS+mhd/XNE1+8Q2l0/s4FEpx8uNMnbRusZARZ6PVWlwcA3AWia0gtwygcjSEcFd12ejQc0oq/0fniXJLJOaoYQyW5+NIICudZaSeTkXb58MMP4/zzz0dxcTGqqqpw7bXXYvfu3Un7CIKAJUuWoK6uDi6XC5deeil27NiRtE8wGMTChQtRWVmJwsJCzJ49G0eOHEnap6urC/Pnz4fb7Ybb7cb8+fPR3d2dtM/hw4dx9dVXo7CwEJWVlbj99tsRCg2eAWFEeuNSbRFXjHKm3RtA01EPmmULfdNRj/Sn3RvQ8OjSxxsPyA+q1A2+dJDidnL0HTMTV4zS6EFFA39Y3/E37jSul0/HCiKQXiyPdI4quqzkVbkHgihGesx4VJqMDKP169fj1ltvxebNm7F27VpEIhFMnz4dfX190j6/+c1v8Pjjj+Ppp5/G1q1bUVNTg2nTpqGnp0faZ9GiRXjrrbewYsUKbNiwAb29vZg1axai0cREMHfuXGzbtg2rV6/G6tWrsW3bNsyfP1/6PBqN4qqrrkJfXx82bNiAFStW4I033sDixYtzuR66hPiwi7ivOGeWbzmMWUs34KaXPpW23fPmdsxaugGzlm7A8i2HNTy69AnF21aopcyUxdUUl808aMkIMlb9OiyDkHClqfPyRYxIi9kEuw4L8KWlGKlcoZ02aSlGWmSlpWOwhbliNBAZmYqrV69O+v8XXngBVVVVaGxsxMUXXwxBEPDkk0/i/vvvx5w5cwAAL730Eqqrq/Hqq6/ipz/9KTweD55//nm88soruOKKKwAAy5YtQ319Pd577z3MmDEDu3btwurVq7F582ZMnjwZAPDcc89hypQp2L17N8aPH481a9Zg586daG5uRl1dHQDgsccew4033ogHH3wQJSUlOV8cvUCCr4sc6b21cwaGxMzEYgKu+Z+PIQC47zunY+pplQDYbrMib19BJsQj3X4pS0zJ9hXEMApFBQwb4BoJggB/3GDr1WG2H8myUsuVJi2oNgtMpoH7cLEKMSQ9g1wvPSuIgKyRbFqGkYqutLTS9ePHpfOwASXI6TXE4xEn3PLycgDAgQMH0NraiunTp0v7OBwOXHLJJdi4cSMAoLGxEeFwOGmfuro6NDQ0SPts2rQJbrdbMooA4IILLoDb7U7ap6GhQTKKAGDGjBkIBoNobGxMebzBYBBerzfpjxHgrjR6VJU40TDcjbPqS6W3rrpSlxQ3w3IQNlG7Zi3dgK74YvTMuq9VUbvIIhiNCQPW+QlGEvFOA/VvYhkSTOwPR6UCmkpCXDBOnRsN6akp+py7SCzP4OeovruwJI2aW308xmhAsh6NgiDgrrvuwkUXXYSGhgYAQGtrKwCguro6ad/q6mocOnRI2sdut6OsrOykfci/b21tRVVV1Um/WVVVlbRP/98pKyuD3W6X9unPww8/jAceeCDTU2WeXu5KU4RipxWeQGTQjBOW0FLtctosUt+obl8oqYkoUbLki8fXx/ukAHelG7HSosRphcVsEo0/f1hxN2VAxxlpQEJhG8xo0HOWIiBTjAYxQDRRjNIJvuaK0YBkfUVuu+02fPnll9iwYcNJn/WXfQVBGFIK7r9Pqv2z2UfOvffei7vuukv6f6/Xi/r6+kGPSw8kDCPuSqNJRZEDR7oD0IsXg2SIeQNhkBKEk0aVqda+oqzABr8nii5fGKMqEttT1Tq6762Bax2xislkgttlQ2dfCN3+sOLGnN5T2YnR4A9HB+zyrueCn0AiLZ45xcg1dOFJrhgNTFaG0cKFC/GPf/wDH374IUaMGCFtr6mpASCqObW1tdL29vZ2Sd2pqalBKBRCV1dXkmrU3t6OqVOnSvu0tbWd9LvHjx9P+p4tW7Ykfd7V1YVwOHySkkRwOBxwONiNEcmWXl7aXRGqS5wAPKpWOqaB/C1RTZdVaYEdxzwBdPULTiZK1t62Htz5+hcABq91xDKlxDBSIc5Ii6BdmhQ7E13ePf4wqooHNoz0eo7E+AtFYgiEoylVRG2Cr9Mp8KhvN6aSZBRjJAgCbrvtNrz55pt4//33MXr06KTPR48ejZqaGqxdu1baFgqFsH79esnomTRpEmw2W9I+LS0taGpqkvaZMmUKPB4PPvnkE2mfLVu2wOPxJO3T1NSElpYWaZ81a9bA4XBg0qRJmZyWrglFYgjFYzeKuWJElfJC0RXQ1aevEhDk7bXAblHV6CgrTJ21ReK2KmXHQmK2WI/b6g+JM+pv/ClBQOcZW2azaUiXTkJN0efiXGi3whxXlAc6Ry0KKRIlyx+OIjxALTOpIrdOx5eSZHSnbr31Vrz66qv4+9//juLiYimWx+12w+VywWQyYdGiRXjooYcwduxYjB07Fg899BAKCgowd+5cad+bbroJixcvRkVFBcrLy3H33Xdj4sSJUpbaGWecgSuvvBILFizAs88+CwC4+eabMWvWLIwfPx4AMH36dEyYMAHz58/Ho48+is7OTtx9991YsGBBXmWkyXt5ccWILmVxw6hTpfRsWpC3xLpSl6pGR2kBMSRTLxBqVoxWClLLaLBMK1q0esSaWWboxJebArfLBo8/POC917u70Gw2ocRlQ7cvDG8gtXvVH1Zf0Zf3zewJRKSXvOTjiqp+XHohI8PomWeeAQBceumlSdtfeOEF3HjjjQCAX/ziF/D7/bjlllvQ1dWFyZMnY82aNSguLpb2f+KJJ2C1WnH99dfD7/fj8ssvx4svvgiLJXGDli9fjttvv13KXps9ezaefvpp6XOLxYJVq1bhlltuwYUXXgiXy4W5c+fit7/9bUYXQO8QN5rTZoZVh7VOWKa8QJ+KEYkrKFE5S7FsiDo/RMk6tbJQV+4zOcT46/YrPyaO94qlF/QS45aKoTLT9J6uD4huq25fGJ4B3FZSIUUVjT+rxYxCuwV9oSi8/nBKw4i3BBmYjK6IIAwda2EymbBkyRIsWbJkwH2cTieWLl2KpUuXDrhPeXk5li1bNuhvjRw5EitXrhzymIwMD7xWDqIYdelM6SCLUIlL3TFBahkNdL3IcZ13Spmu3Gdy0mmMSougjtunEIbqLyfFueg4M2qoWkbE+FO7zVCJyyYaRgMEYCdaguj32isFvyI6h6fqK0eZivEkNCETtFtlw4j83kDXy6PRcdGkTFKMlDGM5EU6j3T5AYjPuBpFOpVgqMrQUoNVHRt/QzVsJRWm1Y4VK3Ha0OIJpAzAjsUEmVGq32uvFNww0jlS1Wte3JE6UoyR7lxp4pggga9qQYyGgRZB4mIj7ig9kk4151xIVdpg49cdmLVULIuil9IGhNIhDCNPfEwMFCCsB4ZyF5J6QWorM8Rge/WTQxhXXZRkUMv78HHF6GT4FdE5Uqo+H9zU0W2MkeRKUznGqDA9xUhtFx9NShVWEUlpA0Cs9fTlEQ9mnVWLn11yGgB9lTYAhjYaSJNTNSqJK8XQmXfaxFGR4/rn9lbccumYJMOI1DAymcT4VE4yfDXVOcQwKuaKEXWIYtQXig5Yo4RFJMNIZcUo3ay0Uh0bRkrHGJEinUAiG21cdZFqRTppM5RhFIzoP46KGPrvf9WO68+rTzJAYjFBUmdUd6UN8pxJVa912odPafhqqnP6pBgjfitpI28B0e0Lo8atj8mbxDqoHcsjxd8YOMaodAh3IU08AW0MXJpIrkfZ9ZLHUZFMrqMqNTtWAjKePzvcjfaeoOYuK3J9w5HEb5NrC4jX1whB70rCr4rOIVK02hkP+YDJZEJZgR0neoPo7Auhxq2PyVq7rDTx9/pCUYQiMdityRI9OS6yWOqRUkkxUt69Sl56TqksVPy3lMKd4nqliqNa+v4+LH1/HwD9xVENVhaDuKwAwOsPwWV3KX48qa7vPW8mt+D51lixfyJvB5IavprqHEkx4q40RSgvtOFEb1BXmWkkC0VtpaHEaYPZBMQEcSHs/9ZvDMVocOOPFoIgSNdrTFWRIr+hBqmy0kgclccfxrw/iW2dHry2AWfXlwLQTxxVqubI/ZUZuWJ0vDeEarfyhhG5vu80teJ/PhCNzf4teHa19gAQQzHavQFdKXRqwFdTnSOl6/Pga0UgrhM9ZaZp5Uozm8Umq12+MLp8yVWAQ5GYJN+Trut6pMRpS+r/NUyhRdwXiiIYb/WTqjifXiD3+li3X1qAyZ89bT3SfmfXl+oujiodZWbGmTVqH5Z0fdu8AWkbab9DaDzUBQA40Rs6yf3H4YaR7unhipGilA8RN8MiHo2y0gAxzkg0jJKvFzkmk0nfiQLE+Ov2hdHtCylmGBFD3GE167ZdBpDoLecPx9DWT5k4Ho8z0itEmTnc0YdbXv0cQEKZEe+fgO1Hu6X9+6tJShsjVcUDf39fSL9ZgGqg3xmKAyDhSuMxRsqQqGWkj+rX4WhCmdEiaLd0gLYgnngLjRKnDWazvrNgSolhpGAANjEsywvtus4akmcgEgWMcCLe8mREqUs37jM5RJmpLy+Qto2NZxA+sXbPkGqS0nFU1SWJa1oRn8eI+29fe0KtU9tg0wN8NdU5pMBjMTeMFKF8iNo8rEGC8QFtlJmB2oIYIb6I4C6wAx0+vLzxIEaVFyiykBDFqEynxTDJAiwIAiwmICoAWw92Smn5VcUOSTE6d5R+W8QAYvC1zWJCOCpIpSqImvS3bUfxp48OADg5zkdpKoocUsyfJf4yko77T0+B70rBV1Od08tdaYpSprMYI2KAFDmsmjQVlmoZ9TMkpRpGOs5IIxAV5O0vW/DTS05TZFGXK0Z6JNUC/N+rd+O/V+8GIC7AgXg6eWWR/tQiOSaTCVXFThzt9kv9RIma9PdtR6X9+sf5KI3FbEJlkQPtPUG0ecU4ImKw/c8H+/BOUysA9Q02PcBXU53Ty11pilJemHqhZ5VEcUdtxkPZAE1DjaQYqWHcEddtmU4NI3kF71uXf4ZDnT7MmzwSP/zmSADiAkyMpMpifZ6jnLpS0TAKRZMbrbd6tY2jqioRDaP2ngAAt2SwySuNq22w6QG+muocqfI1N4wUQW/90khGmlZtN4jRsGHvcbR7R0tqCjGU9GwYEfdQLJZY/JSKzyBtaMp1qrDJK3jXlxfgUKcPLrslaQE+Ho8xGqZzxQiAdK7yTDAAaPWIjYBnNtRoosZUFzvRBC/a+hloR7v9qh+LnuCrqY4RBIEHXyuM3vqlad2PjLjSdrb0JKUBG6G4o5rxGZ1xhVKvipGciiLxHDp6kxfnE/EYo0oDuG+q4xlgbT39DKO4ofSTb43WJI6K/Ga77LgEQcDRLtEwmn/BKO4+SwFfTXVMMBJDOC7d8hgjZZBijHTjStOmuCNhoGBhI7jSiHvo/a/a8Pha0UBSKj5DUowMYBidUiFmbfUGk1PETxhIMSIZYO0yZUYQBLR5gvHPtQkuJ2NSrhh5AxEpXf++75yheg83PcBXUx1D1CJAvT48+QbpGB8Ix+APRZmfRLQq7kjcTPI0fbmbibgY9FzckbiH/OEoEDeMlIrP6NB5VpqcsdXFAJJLOMRignSOStWCUpPqFK60zr4QQtEYTKbBawqpcVzHZYoRUYvKC+3Mz2dawVdTHUPiiwrsFikdk0OXIocVVjMQiQF723tw1ohSrQ9pULQq7jiUm4moBnpWjAgjZXVrItHYIHtmD1GMKgygGNXEF+cWT2Jx7vKFEI3HahlBFasqIcpM4hzJ+VYUOhRrHTPkcaVQjI7F44vqSvVbIkFpuGGkY6RUfR5fpBgmkwnFTrHNxf7jfcwbRomsNHUNEOJm6g1G8IM/bgYALJl9Js4bVQYAuPfNLwEkKiHrmWFFDqluTUwYev9s6DJQjBFpvtzuFQPXzWaTFHhdXmiHTYOyErQhyozclUaMpFoNm09Xp4gxOhYPCB9eqnzfNr3CV1QdQ4o7hiIx3ghQQUj/r54A+9WvvfExobYyI89CKnZa0ROIoKLQLrmZSEyDERQjs9mE+vIC7D/el9QklBaxmCAVyDSEmlLshMkEhKIxdPpCqCxy4ESPaPhVFun//ICEAdITjKAvGEGhwyopRlrFF4m/LSpGx3uCiMYEWMwmyZVWxw2jAdG/qZ7HEMWo2x9Gu877DrFGuzeApqMeNB31wBxvyUD+v+moB+390nJZQeusNCCxELTKXCdeA2SlyakvE91pzZ0+6t/dE4hIbiYjXC+71YyKQnGBJmOCBF7rvbgjochhRWE8XofMxSwoRvLq1yQrkKTqc8VoYLhhpGN6ZcHXHLos33IYs5ZuwKylG7D/RB8A4LVPj0jblm85rPERpkbrAo8AMErKQhKPRRAEQ9QxklNfLi4qzV30DSOSAVnksMJhNUZwLDEOiGFE2oEYIfCa0D8AmyhGNRoaRqT6NZAw2I5xw2hIuCtNh5AMoN1tvBGgUsgr9/7po/3427ZjGFddhMev/wYAdkvna13gEQDGVRfjX7vaJWPIF4oiQhQQHWelyUkoRvQL5Ul90gqNYUQConGw/agHLV5jKkaAGIC9/0SfZBiR/9ZoPBeT6tdt3gAahrslxYi70gaGG0Y6hDcCVB55zMxFYyvxt23H0O4NMl8638tAvSCStXU47mYiXejtFjOcNmOI1OQclVCMElWvjWFEAgnjoI0oRgY0jPoHYLOgGAGJ6tftPUExHjWuHA0v44bRQHDDSIcQNePBVbuwaX8HAN4IUElOqSgEQGK5AprVJBkKQRASBR41NIyImkIMIw9xoxXYYDIZo6xEfblyMUYJxchAhpE7OWU/H1xpbYwYRvJSAm3eAASBxH0ZZ3zRhhtGOoSoGfLy87wRoHKMLC9AWYGYmbbzmBdV49k0jIKRGELxujpBBbKl0oWoKUe6/IjFBHT7xYU+EjVO9iQx/k70huALRVBAscAqiTEykmIkxRh5RTfOiV5jZaUBsppBPUH0BiPoiceAau5Ki7/IvberDePixTaHl7oM85KiBMbQtfOQYCSKQx3031Y5J1NV4sRFY4cBAHa2eDU+moEhGWlAclV0taktdcJiNiEYieF4b1By73X5jJM96S6woTge4H6ki26cUZcRFaN+mYpETTFSYVqiGH12qBM74jGfxU6r5n0syXE1HfXi88NdAIzRhkVJuGGkUw6c6EM0JqDQbsEdl4/h7jOFmVBbAgDYeYxdw8grM4y0fBu0WcxSVd3DnT4pCNtoKJWyT4JjtaqWrARyV1o0JkgFLAVBoQqZGkAMkKPdATQeEg2QSgaMW/naQIx4t8qV8fUGvzo6ZU9bLwBgfE0x7pw2XuOjMT4T6tg1jEiW4ueHu6VtWmcp1pcVoLnTj437TqBZpqhofVw0qS93YWeLFy9vOoiJw93UzoXUyLIYyNVBDCNfKIrPD3eBmENaNTtWAlJMEQCaO8USH6UaukPJvOALJdzqH+87AUBU6ozi1lYCbhjplH3xVH3iM+YoC1GM9p/ow29Wf4Ubp57CzKTCYpbiyPICbPy6A0+8x9Zx0YTEUq3fcwLtPUFq40EquWAgo6HAboXLZoY/HMPfPj8qbf+qtQfWeEsQvRrKxAAJyOL63tt1HABgs2hngKSaF0hl/NU72lBWYMe8C0bp9rorCTeMdApRjMZUFWl8JPnBsGIHqorFeiC/X/c1vjOxlpnJhGQp/uJ/v8DOFtFg1jpLkWRtjSovwKFOH6wWEyJRQfPjokm9rJlsrpDFFUgEJnf0BSWFzQiLl90iGkbLZMVRjWAopzJASDmCTw524Ym1ezQxQMi8sHzLIfzlk+aTPv/L1mb8ZWuzbq+7knDDSKfsaeeKkdpMqCtB+27xTbCzL4Qn1u7BjDOr8e6ONsybPFKzhauqxIkipxV723ulbVpnKRI15VA8/uaC0RXYsO+E5sdFA2LERGUdZDfuO4HlWw5hZkMtKovsGY+JVIvrsx/ux7Mf7gegX6NBbvBVFNnhCZDG1xb0BqO47zunY+pplQD0ayizaoCQ7OU7rxiHyaMrsOi1bZh/wSi8svkQHp4zERMN8oKiBNww0iHyjDRuGCkPmdzlmRybvj6BZ9bvh9VswlP/2itVyV6+5bAmxtKnB7sQjgqoLLJLioOW9FdTLh5biQ3x+Aa9k8qIeeidrwAAf/mkGT88vx5/2dqMSaPK0h4PZHF9/dNmvLzpEADtVT8apLpWANAbFN1OB4734eaLT1P7sKiSygBZeNkYLH1/HxP3sKrEKXkWJo0qwyubD2GiAV5QlIQbRjrk00NdUkaaPOCPowypJvdn1otv8o+t3SNta+8J4ql/7cXoykI89a+90sI4b/JI6XvkiyTZRsOAIoU+vzm6AmOrijRfSEfKDCOn1YwrJ9agLxTV/LhoIG8X87t/7cWanW3SZ/9x1RkYW1WEv2xtRmdfKGk8pDKe5eNhWJEdf9+WiL8xgromv1ZbD3TigZU78Z/XnIkSpw2LXtuGmRNrND5CesgNkNOGif9l5R5WFTtwx+VjUW6gNjNKwg0jhWj3BgacAIGBJ8f+n6XaRor41ZfzIl1qQCb3zr4Qlm85hHd3tJ20z/1vbce5I8sAAN54QUOyMJKFIdUiKTegsh0jM86sxpufHQEAXHZ6Ff7PpBHKXpBBIOqaIAhwWM0IRmI4o7YEXn9EOme9QxSCdm8A35lYm2QY/deqXSiK1615p6kFQHI6f3/jWT4evjjSDY8/Il03IyBvrUM4d2SZtFCfXlOi0ZEpA6sGSFWJE3dOG4d2bwB3XD7WEC8oSsINIwCI9AERul2s27t7xImv3Jr032njxYkg3c9SbZt+RgUAYGSZUzx2jqJUFQBVBVY88a/mlEYRAHxxxIMvjoiBsv+1ahcA4Ol/7QYA/OOzg2gYHnd5xuIFDqOJFPbOnp6cxkhNkQlt8f5MU0a5NB0TyzcdwFMfHEra9nlzN2Yt3QAAuOPbo3Dn5aO1ODTqpDpXAOiNF9ckY4Woive/+QVGlIkL0uHj3eLOsvHw7nZRLZoyuhRnjyhGVUHUWM83GfNRP6oKrLjz28MBGOscqwqAO789HO09Qdzx7VHM3UNyfIa47goePzeMAODNOoBeggnaw2XY7j0fwO3Y+cH/A/B/0Lz+HgA3oHf1NBSYAwCeBDb9GMDPE/9dc1H8G55KuY18x5d7dwGogu3Ym2h6cR4AoMrWiSpbF72T4JzEvHAZRo84C4uO/BzfL12N17qvxDjHQewJnpK0XygqBuXuOyEuBH/8+Ij02f/3xicAinHbc3+DwxwGcCr+/PZbAE7HilV/AfAN/OP1e1Fk8QH4EQ6s/w8A89Dz8W0AbkV0zbdghgD5GNn+0ZMAvoMa63EMX1Op7EUYgnnhMkwbUw4A+LDnHPym7UY8Mvx3aHB9DQCoau0EXjfGOJ0XLsOkU0bhHc+FGGbtxO+Oz8Mk1w40+s9Muf8XR3vwxVExaeLx9w8CAH7x188BOHHjs2vRES0BYMXozj9jmvAB2psBGOi5rgqX4Y6qmaj6YD5gkHMaiCoAdwLAOxofiJFRsPGDSTBS6dEM8Xq9cLvd8DwHlFAwjNrDZWgPl+OvnZfhpc5rBtkzBsAMK8KIwAYHAgjCiSKTmFXUKxSh1NyN7lgpRliPwWqK4mC4ftDfvqPqVdxZ82ruJ8EZlPZwGZZ3zMSkgp340cH/wgO1v8evW27BA7W/x/FIGZ4+/kMVjyYKIKF0TnDuwz01L6Lc2sOEodzkOw2z9j2FlWPuQEPB15oei9KQc335lF+hM1KCRUd+jutLV+P17isx0nYMh8N1WX0vf645nNR4fYB7AeDxeFBSQtclyxUjAJhzDKBwYZf/K7W0fjJiQbMIRD90EKIPvldI1CTqjpUCAI5EBp9Qf3heDeZ9cziqiqcAxX/M/KA5GUHeBJuO9QC/b4T7oqXAX3dh0nefBwA8/ftGLL7iFDz23kH8eMpw/HnTUfx4ynB4/BG8sa0NZ9YWYkdLH6qKbGjvzbVVRrL7d2dgDH508L8AMOKyOtYD7GsEpm8A6gyePRk/1/Lv/BPlAPD7Rkyddide/+su3DTjYvx65T48MGsMTvSGsHTdYVw6tgzr9nZhYl0hth/rw4WnlsJhM+P93Z2478pTMfVUMV6NP9cczgB4vcCC7F44hoIbRgBgLRT/5Mi8KWMwraEenX0hbD3QiaUf7MO3xw/DB7uP48Ix5fh4XyeuOqsG4YiANTvbcE59KT5v7sZZw0vw5VEvppxWDgjApv2dOLOuGDuO9eD0mmJEYwL2tvfijJpi7GrtwfXnjcDrnx7Bk9//BqaeVqH7wm96pKrUgjsuH4txtRViMGNpqVSvpb6iFABw1shhwKajmHOeaKC8sa0NCy4ei0WvbcNvrz8HnX0hLHptG75//gi8tvUIZjbU4J2mVsw+uxYA8I8vWnDhmAp8vK8DU08rx8avOzHzzGrEIMavnHdKKT492C2NsYWXjcH5p5ShvFAsRgmrxl2949eoqrRU82NRmqRzhVh3qLxYfNFxF8ZTpUeLGVhL1x3GteeOwrq9XbjpW+J4uPeqBgDA+7s3YOrYOiYymTgcprFGh94nS4zTpZABqkqcaBjuxsXjhmFGgzgJXvON4QCA6yaJ2UT/fskY3H75WADADVNPAQD8+KJTAQD3f2cC7r9qAgBgwbfE2h6/ve5sPPH9bwAAfnqJuI0URBtTVcSNIo0gWR4T6ty4c9o4MfsmnpEyrrpoyMyU8kK7lNo75VTxfs44UxwzN198mlTb5bpJogv1+vPE8XPrZWOx8DJx/Pzb5FMAJMbYjDNrcPG4KjRQ7NuVC+QasXAsSiM/V/L302tKksYDzwTicPQBV4x0SHmhnU+0DEIWRACYUOc+KTU21SLJYmovhw79xwNBPg5SjQf+XHM42sKDr91uRYK3lKxjpGX7CQ59+o+VbOoY8XHB4XDyCSXXb24YKXRhORwOh8PhKIOS6zePMeJwOBwOh8OJww0jDofD4XA4nDjcMOJwOBwOh8OJww0jDofD4XA4nDjcMOJwOBwOh8OJww0jDofD4XA4nDjcMOJwOBwOh8OJww0jDofD4XA4nDjcMOJwOBwOh8OJww0jDofD4XA4nDh53USWdEPxer0aHwmHw+FwOJx0Ieu2El3N8tow6unpAQDU19drfCQcDofD4XAypaenB263m+p35nUT2VgshmPHjqG4uBgmk4nqd3u9XtTX16O5udnwDWr5uRoTfq7GhJ+rMcnHc925cyfGjx8Ps5luVFBeK0ZmsxkjRoxQ9DdKSkoMP0gJ/FyNCT9XY8LP1Zjk07kOHz6culEE8OBrDofD4XA4HAluGHE4HA6Hw+HE4YaRQjgcDvz617+Gw+HQ+lAUh5+rMeHnakz4uRoTfq70yOvgaw6Hw+FwOBw5XDHicDgcDofDicMNIw6Hw+FwOJw43DDicDgcDofDicMNIw6Hw+FwOJw43DBSgN///vcYPXo0nE4nJk2ahI8++kjrQ8qZhx9+GOeffz6Ki4tRVVWFa6+9Frt3707a58Ybb4TJZEr6c8EFF2h0xNmzZMmSk86jpqZG+lwQBCxZsgR1dXVwuVy49NJLsWPHDg2POHtOOeWUk87VZDLh1ltvBaDve/rhhx/i6quvRl1dHUwmE/72t78lfZ7OfQwGg1i4cCEqKytRWFiI2bNn48iRIyqeRXoMdq7hcBi//OUvMXHiRBQWFqKurg4/+tGPcOzYsaTvuPTSS0+61z/4wQ9UPpOhGeq+pjNmjXBfAaR8dk0mEx599FFpHz3c13TWFzWfV24YUea1117DokWLcP/99+Pzzz/Ht771LcycOROHDx/W+tByYv369bj11luxefNmrF27FpFIBNOnT0dfX1/SfldeeSVaWlqkP//85z81OuLcOPPMM5POY/v27dJnv/nNb/D444/j6aefxtatW1FTU4Np06ZJvff0xNatW5POc+3atQCA6667TtpHr/e0r68PZ599Np5++umUn6dzHxctWoS33noLK1aswIYNG9Db24tZs2YhGo2qdRppMdi5+nw+fPbZZ/jVr36Fzz77DG+++Sb27NmD2bNnn7TvggULku71s88+q8bhZ8RQ9xUYeswa4b4CSDrHlpYW/PnPf4bJZML3vve9pP1Yv6/prC+qPq8Chyrf/OY3hZ/97GdJ204//XThnnvu0eiIlKG9vV0AIKxfv17adsMNNwjXXHONdgdFiV//+tfC2WefnfKzWCwm1NTUCI888oi0LRAICG63W/jDH/6g0hEqxx133CGcdtppQiwWEwTBOPcUgPDWW29J/5/Ofezu7hZsNpuwYsUKaZ+jR48KZrNZWL16tWrHnin9zzUVn3zyiQBAOHTokLTtkksuEe644w5lD44yqc51qDFr5Pt6zTXXCJdddlnSNj3e1/7ri9rPK1eMKBIKhdDY2Ijp06cnbZ8+fTo2btyo0VEpg8fjAQCUl5cnbV+3bh2qqqowbtw4LFiwAO3t7VocXs7s3bsXdXV1GD16NH7wgx9g//79AIADBw6gtbU16R47HA5ccsklur/HoVAIy5Ytw49//OOkpspGuady0rmPjY2NCIfDSfvU1dWhoaFB9/fa4/HAZDKhtLQ0afvy5ctRWVmJM888E3fffbcuVVBg8DFr1Pva1taGVatW4aabbjrpM73d1/7ri9rPa143kaXNiRMnEI1GUV1dnbS9uroara2tGh0VfQRBwF133YWLLroIDQ0N0vaZM2fiuuuuw6hRo3DgwAH86le/wmWXXYbGxkZdVWOdPHkyXn75ZYwbNw5tbW34r//6L0ydOhU7duyQ7mOqe3zo0CEtDpcaf/vb39Dd3Y0bb7xR2maUe9qfdO5ja2sr7HY7ysrKTtpHz89zIBDAPffcg7lz5yY1G503bx5Gjx6NmpoaNDU14d5778UXX3whuVf1wlBj1qj39aWXXkJxcTHmzJmTtF1v9zXV+qL288oNIwWQv20D4o3uv03P3Hbbbfjyyy+xYcOGpO3f//73pb83NDTgvPPOw6hRo7Bq1aqTHlaWmTlzpvT3iRMnYsqUKTjttNPw0ksvSUGcRrzHzz//PGbOnIm6ujppm1Hu6UBkcx/1fK/D4TB+8IMfIBaL4fe//33SZwsWLJD+3tDQgLFjx+K8887DZ599hnPPPVftQ82abMesnu8rAPz5z3/GvHnz4HQ6k7br7b4OtL4A6j2v3JVGkcrKSlgslpOs0/b29pMsXb2ycOFC/OMf/8AHH3yAESNGDLpvbW0tRo0ahb1796p0dMpQWFiIiRMnYu/evVJ2mtHu8aFDh/Dee+/hJz/5yaD7GeWepnMfa2pqEAqF0NXVNeA+eiIcDuP666/HgQMHsHbt2iS1KBXnnnsubDab7u91/zFrtPsKAB999BF279495PMLsH1fB1pf1H5euWFEEbvdjkmTJp0kUa5duxZTp07V6KjoIAgCbrvtNrz55pt4//33MXr06CH/TUdHB5qbm1FbW6vCESpHMBjErl27UFtbK0nS8nscCoWwfv16Xd/jF154AVVVVbjqqqsG3c8o9zSd+zhp0iTYbLakfVpaWtDU1KS7e02Mor179+K9995DRUXFkP9mx44dCIfDur/X/ceske4r4fnnn8ekSZNw9tlnD7kvi/d1qPVF9ec126hxTmpWrFgh2Gw24fnnnxd27twpLFq0SCgsLBQOHjyo9aHlxL//+78LbrdbWLdundDS0iL98fl8giAIQk9Pj7B48WJh48aNwoEDB4QPPvhAmDJlijB8+HDB6/VqfPSZsXjxYmHdunXC/v37hc2bNwuzZs0SiouLpXv4yCOPCG63W3jzzTeF7du3Cz/84Q+F2tpa3Z0nIRqNCiNHjhR++ctfJm3X+z3t6ekRPv/8c+Hzzz8XAAiPP/648Pnnn0uZWOncx5/97GfCiBEjhPfee0/47LPPhMsuu0w4++yzhUgkotVppWSwcw2Hw8Ls2bOFESNGCNu2bUt6foPBoCAIgrBv3z7hgQceELZu3SocOHBAWLVqlXD66acL55xzjq7ONd0xa4T7SvB4PEJBQYHwzDPPnPTv9XJfh1pfBEHd55UbRgrwP//zP8KoUaMEu90unHvuuUkp7XoFQMo/L7zwgiAIguDz+YTp06cLw4YNE2w2mzBy5EjhhhtuEA4fPqztgWfB97//faG2tlaw2WxCXV2dMGfOHGHHjh3S57FYTPj1r38t1NTUCA6HQ7j44ouF7du3a3jEufHuu+8KAITdu3cnbdf7Pf3ggw9SjtkbbrhBEIT07qPf7xduu+02oby8XHC5XMKsWbOYPP/BzvXAgQMDPr8ffPCBIAiCcPjwYeHiiy8WysvLBbvdLpx22mnC7bffLnR0dGh7YikY7FzTHbNGuK+EZ599VnC5XEJ3d/dJ/14v93Wo9UUQ1H1eTfGD4nA4HA6Hw8l7eIwRh8PhcDgcThxuGHE4HA6Hw+HE4YYRh8PhcDgcThxuGHE4HA6Hw+HE4YYRh8PhcDgcThxuGHE4HA6Hw+HE4YYRh8PhcDgcThxuGHE4HA6Hw+HE4YYRh8PhcDgcThxuGHE4HA6Hw+HE4YYRh8PhcDgcThxuGHE4HA6Hw+HE+f8BEjRxXNUfuaIAAAAASUVORK5CYII=", + "text/plain": [ + "<Figure size 640x480 with 1 Axes>" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "d_s = d.copy()\n", + "d_s.sort()\n", + "frac = 0.1\n", + "bottom = d_s[int(len(d_s)*frac)].mean()\n", + "top = d_s[int(len(d_s)*(1-frac))].mean()\n", + "middle = (top + bottom)/2\n", + "\n", + "fig, ax = plt.subplots()\n", + "ax.axhline(top, color='orange')\n", + "ax.axhline(bottom, color='orange')\n", + "ax.axhline(middle, color='orange')\n", + "ax.plot(d, '-+')" + ] + }, + { + "cell_type": "code", + "execution_count": 19, + "id": "eb350503-090c-4203-a73a-422c281479ed", + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "thr_bot=26379.8875 thr_top=31163.1125\n", + "--------------0+\n", + "++++++++++++++++++++++++++++++0-\n", + "----------------------0+\n", + "++++++0-\n", + "------0+\n", + "++++++++++++++0-\n", + "--------------0+\n", + "++++++++++++++0-\n", + "------0+\n", + "++++++++++++++0-\n", + "------0+\n", + "+++++++-\n", + "------0+\n", + "++++++++" + ] + }, + { + "data": { + "image/png": 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xSj0O2OIPZ5+OC+FRXxBdoSgcNguGV9INACduouNd5jGM9h+XjMjhlYWwKFdXCoytlVRDvQ1Jco4jKulnlo6qll4U97R2DrCnuhw4nly8cGytNFe/btLnuMhzNBhJrNHkGWrG52hWhlFXVxdmz56N5557DmVlCRlTFEU8+eSTeOCBBzBz5kw0NDTgpZdeQk9PD159VapZ4PP58Pzzz+Oxxx7D5ZdfjrPPPhuLFy/G1q1b8d577wEAdu7ciRUrVuDPf/4zJk6ciIkTJ+K5557D22+/jV27pCj9lStXYseOHVi8eDHOPvtsXH755Xjsscfw3HPPwe/35zoupsYfjOBwu5SeOqqKoUqqKlPikRQCvd94WYSoRYNLPShy2WG1WlBeKC06ejrbSXzRiMpCOCirAw3xANGukIDOoDnmxL64mnIKZSMSAIZXSMXeDp7oof7dmbAvbjRMHltNfUEmz0OiUurFgfgYXzJmEKqKXTgtrmTtbNZ3bdP72mtFVk+a2267DVdeeSUuv/zypO379+9Hc3MzpkyZIm9zuVy46KKLsG7dOgDA5s2bEYlEkvapq6tDQ0ODvM/69evh9XoxYcIEeZ/zzjsPXq83aZ+GhgbU1dXJ+0ydOhWhUAibN29OedyhUAh+vz/pTz5BeqQt/6pJ3na4PSD3TWOtFw9t6rzSQ5S0kuAkIAYIeWMGgNpSabzkkv46sEc+LvoGfJHLjhK3lH/SpJOLgjYk8HqECobR0Lhh1Njeo+ucUPMcSWjBvmPdiOr4nDh4QjrH/3v+CFSVuHF63DDa1dyp63EdapMMo+vOGWKoYOpMyTgrbenSpfj888+xadOmkz5rbpai1aurq5O2V1dX4+DBg/I+TqczSWki+5B/39zcjKqqkyuwVlVVJe3T+3fKysrgdDrlfXrz8MMP4ze/+U06p2lKUmU86J1xpCX15dKDPRjhhlFviGt1cGniDXxQkfTgO6ajq4lkyo1SKRaurtQDf3MnjnYEMFoF40tr1DQaar0eOG1WhIUYjnYE5PtJa9Q8x8GlHjkz7VBbD04ZpH0MZiwm4mDcACHnOKy8QD6u37y1HfMuHaW5+yoYEeRs1V9ecRoqisxrGGWkGDU2NuLOO+/E4sWL4Xb3fVF6+7ZFURzQ3917n1T7Z7OPkvvuuw8+n0/+09jY2O8xmQ0SQHfTpOHyNmUAndkDkcsLJVfaiW4eoN+br5slZUb5sBsUfyPUM6Zke5Ok6lartAgMLpUC8o92mEMxIrEptOOxAMBmtaC+XBovvVwq4WgMjXGjQQ13odVqkVWjPTq505r8QYSjMThsFtTGVW6r1YIx8Zi4VzYc0qVT/eH2HoiipLSSZ6lZycgw2rx5M1pbWzF+/HjY7XbY7XasWbMGv//972G322UFp7di09raKn9WU1ODcDiM9vb2fvdpaWk56fePHTuWtE/v32lvb0ckEjlJSSK4XC6UlJQk/cknUmU8mDmArjcV8SykEyYKtqXFofhCN6wisdgQw6i1Ux+jQRRF7IsvTqUedUquEXfh0Y6+W0IYhUBYwNG4S1ANowFIzI+Dbep1Nu+PQ209iIlAodMmz0/aEHXypXUHdAkvOBg3buvLCpKy7og7TS+IMTy0vIB6YD9rZGQYXXbZZdi6dSu2bNki/znnnHMwe/ZsbNmyBaeccgpqamqwatUq+d+Ew2GsWbMGkyZJdULGjx8Ph8ORtE9TUxO2bdsm7zNx4kT4fD58+umn8j4bN26Ez+dL2mfbtm1oakrEy6xcuRIulwvjx4/PYijyBz3eNligIh5M3MYVIwCJmLMN+07IAemdwagcc+ZxSI8HvRSjIx0BBKOS27PW6xlg7+yokxUj4xtGn8cLl5Z47ChT6Y1+mM4B2LIbbRD9rDvCyHic3bpvTujyrDwgv6RIY03uU+XLAblHtYwN7X1cZiaj17Di4mI0NDQkbSssLERFRYW8ff78+XjooYcwatQojBo1Cg899BAKCgowa5bUkdfr9eLmm2/GggULUFFRgfLyctxzzz0YN26cHMx9+umn44orrsDcuXPx7LPPAgBuueUWTJ8+HWPGSD1upkyZgrFjx2LOnDl49NFH0dbWhnvuuQdz587NOyUoU8iNNK2hxtQBdL1RutLSce+anVQxZwvfTNQcu3KcVOJfa8OIFLnbfDChKn/d3Cm/PdMsMklcaUdMYBhtjbduIe4XNRgWjyvqnU6uFYlUffVif0bqEFek5MCJZHcoK7Ghh+LHNZQbRpnzi1/8AoFAALfeeiva29sxYcIErFy5EsXFicDGJ554Ana7Hddddx0CgQAuu+wyvPjii7DZbPI+S5YswR133CFnr82YMQNPP/20/LnNZsPy5ctx66234vzzz4fH48GsWbPwu9/9jvYpmY6WePGyH18wwvTuMyXElRaOxtAViqLYbY5ecNlCWixsP+rDL5dJD1plletmXwDLtzZrHnyt5UJAFCMzZKUR1YuckxoMiy/Wmw+2o9Uf1Pz5Qfo7qvFCRwxyQVGfQo8+gXKcWNxtSe7TLY0d+I9/SNWwT2pyqwEkIHxYufkbrudsGK1evTrp/y0WCxYuXIiFCxf2+W/cbjcWLVqERYsW9blPeXk5Fi9e3O9vDx06FG+//XYmh5v3iKIox4zkk1oEAAVOu5zZ0dYdznvDiFSqJTWtgETMGZBortnqD2mqsJGF4I0vDuP5tQcAqLcQEHWlyRdALCbCajWWiqjsOL89bjQ4rFZ5Qae9mJPF+kR3GC06GEZ75Zgz+vcuK8rMwV4uK3KfRhUlEpT3qVYc4q40jlnxB6NyunpVcf6oRYTyQieOdARwojucFGicz/QVc1UZz1ALRWPoDEVRopEhSRaCf21NxA+qtRBUl7hhtQARQcTxrpDhFNRUi/nKHS1YuUNKXqG9mA8u9cACQATQ3qN9rB5xeQ4uo6+KEYM8LAiY+cf1AIBfXzUW5w4vB6DNi2QsJsruQlJji1DksqX6J5ogxEQ0tnPDiGNSjsXVohK3HR6nfjeaXlQUSYZRWxcPwCaQLL0zakuSHv4epw3FLjs6Q1Ec6wxpZhgRtFh4HTYrqkvcaPIFcaQjYDjDiCzmAHDzi5vQ0hnCTy4YgWvOHgyA3mKuVKZKCxxo74ngk70n5OroarqZyG8HwgLae6QkAV8gQl0VIwa5KIqwWQBBlOoIaanMtHQGERYkZcjaS6EtdEnLtQWJPn9asfVIByKCCLtVvUQIluCGUZ5B4ouMtgDQIhGAnZ+ZeakgdZ0uHDPopHkxqMSFzmNRtPpDOFXjoFSiZJG2CGpRV+pBky+I5z7ah4UzzjDUvUEWcwCIxCQlWA11LZUy9exH+/DsR/sAqOtmSvXbv3lrh/x32r9tsVjgdtjQHRYQUPQG04IDxxPZfr0b5BLDSATgLdDWMNp2JFFPzGYwd3M2cMMoz2iJZ6RVl+RXfBGBpOzzIo8JyFhUpEjxHlTkwr5j3bpUv27vltSBa8+pV9VYIXFG/9rWjFsvGWkow0hJZzAKQCrARxulMnX337Zgd0sXrh0/BDfGi8WqabiS397T0oW7/rYFgPrBx4UuO7rDAgoc2iyRRBVbt/e4vK134Ley+Gp3KAq3QzvFnyQn1KiY8cgS3DDKM4gcXp2H8UVAIjONu9IStMXVs4oU8rye1a+Jqlem8tvxYBWzuLQiGBEQibtgThlEP3ZOqUxVFrmwu6ULlUVOTdxM5Ld9iubPagcfl3gcaO0MwWmn27i4L9IN/CbJI90hARUqC7hK9+nWIx0AAKdNvcB+luCGUZ5BFKNBeaoY8bYgJ3MibiSSeBElJEBfD8OIxJOo1X5A+eAn6JGeTQNiNNisFlV6iCkhSkVA456DSsNIbQrj8Zc94agmv0dUsRc+OYBlnx8GkFoVK3TZEYgI6Aqpf1ypjLX1+9owfdFaAOburckNozyj1Z/nihE3jE6iX1eaTm1BhJiIjh5isKljGLGSnk2DjrgRWepxqF5WoaxACsLXOtbEHzeMRlQUqJ4hVuCUlsbusDYxRkQVczsSClUqVazIZcPxLqBbA4NN6T69629bsEdD96necMMozyALnFpNOVlHdqXx4GsAUnpwOzGMGHKl+QMRkLItpQXqZMORB//mg+34dbzitx6F82hAjEivSmOlhJRx0DoE1x+UDKNvDS1TXckrjKfG92igzCghcWJ9QQKwtVCMlO5TYgOPqirWvH6SHnDDKM9IZKUZ56FPE+Iu4jFGEv5gRC4cl0qZIYbRjqN+TSsdt8UX+hK3HQ6bOnEe5MGvzDzSo3AeDUivO68KhQ97Q9SUHo0ztnw6nKNWihGBGH+Xn16V0jAvJMelscHWE5LGoVDHWkpaok1kGYcJlFWv892VdjzeLy3fIW60YpcdLvvJDz3ycD7RHda0oSZJ1VfLjabEo2F2j1r4FK40tSlw6qOm+APS7/UufKgGRJnR2gAhitH/GT8k5UsIMUy0Pi5SFFiNwposwg2jPCKp6nWeKkbKfmlavw2yiBx43UfBuEGKt9aooF2wLTGM1OoSr4QUOnXaLIZynynpCEjjVapBfZsC4mbS+P4hilGJBsYfCb7WIpZHSWdcMeqrXVHClabt2BNVNV+6BXBXWh7R6k9UvdayBgZLFDjtcDusCEZiaOsKq1LzxUjIqfq9DBCSsRWLiXILiE8PtKnS4T4V7f0EhNOGKCAx0biFT7V1M+ljGBE3kxaGUUH8udCjsQFCFKPiPlSxIh2ULCEmyjFN+fK8zI+z5AAAdrV0AtBmsWGZikIXjnQEcLw7hKF50PenP050p07VT5Wx9dC/vpb/rnbGFokxUruGEZBwpUVjIiJCTLWYJjWRs9I0CL6WY4w0VlNkxUiD1jT6KUbEMOpfMdLyuJS/1ZfBZjby4yw5AIB9x6TmhF5PnhtG8X5pL6zdjyHTPYZVCWhAXGm9jWVlqu4Nf9qArlAUd142St6mtsuprUvDGCNFz8CesACvx4CGUUCHGCOtFSMtVTEdFCOlMtNXHJUesU/EWHPYLHBpVPBSb/LjLDkAgBNd0oOlrFDbZqCsQRbbt75q0jSgmEXa+kjVrypxyxlaRD4fUu6Rt6ltTMqKkQaGkdNmldORAwaNOyPB11qk6ycUI61daXGjwaP++zzpZK+lMtMVVCozqa+jfFwaGmxdChVL7RpZrMAVI5OjrO67t1VypcVE5EVZ977QQoUwCsfjPdD6GxPylhjWsNIxiTEq18CVZrFYUOC0oysU1bxpKC3k4GsN1GC9FCNd0vU1VGZIDJXLbu2zFYmWdYwIiYDw/DEX8udM85RUsSJrdh/Dmt3HABirum+uECNRmaZv1BYQtCCKUWVR366xwvgDUVmVV23aVG4H0huP04auUFTzuBladGioGBXqEGMUjAgIRyXDXJusNO1VsYHiiwB9gq878yzwGuCGkelRxor8/O9fYmdzJ2aePRg/vmAEAGNV980VM7WAoEU69YJIvINLw0zGdg3T9YFEAHbQoIqRlnWMSExWICIgFhNh1aA1CIkvslqAIqf6y1aBDq60Tjnrru/z06PA40CZcmYkf840T1GWdXfE5dlTBhUasrpvrhAj8f9tPowX1x0AYNwWELQ43tV3OxACMRq0fHvWssAjoJ97iAZRISa/1WtRx4gUGRRFIBgVZLeTmvgV9X20MMRkxUjDWJ50FCM9XWlFrvyJTeWGUR5B4ifMUOk3G4iRuPlgu7zNqC0gaBCLiWjvIVlpfRuFRCHQSk0JRRPdw7WIMQISHeONaBj5FUG7WlSFdtuTs/i0MIwSxR21WbIKdVCM5DpN/VzDhCtN++BrLeYWK/CstDwiGvfR15TmVxxNb7SMlWEZXyACId4nrb9MRWI0aJWxReJlbFaLZvJ9gcbGH01IA9lil10uwKkmVqsloSJqtECTdiBaBF4DCcUoGIlpVvE9HZeVHi1ByHEVccOIY0ZCccOoviy/ixqShX5ImScv3WcEUtzRabPIMSqpIIugVhlbcjuQAqcmbhPA2K40uYGsBoHXBLn7fESbBTqhpmhzjgWKZqlaNcuVs7/6cVkVKQo8atXrkai3+RRjxA2jPIL0BtNC+mYZYhgNysMsNCUn4qn6YUHst56TXoZRuYb1trRWxWji07DqNYG4V7Vy6WiZqg9Ita3scaNcK1WsM406TSTGKCZqdz/68zDGiBtGeQRJry105WeMEcEtZyBpV5eHRYgBMhByjJFGRoNSMdKKAqe2xh9NtKxhRCCuJq0MSb+G7UAAUttK2zgjfxrB1wVOG0iNRa0CsLt4VhrHrISjMUQESXrNd8WIKCAhAy6CNCD1nLYqajj1V8/Jo7HRcKitG0DCWNECj4EVIy1rGBE8GhsNPh3chUUuO/zBqHZxVGkUUrRYLCiMFyPtDglAsfrHxdP1OaZFWYxNywWHRUjwtRHVARpkWs8p4UrTRmE70h4AoG3dJI9ObS5ooLWbCdBDMdI+M6pA44at6aTrA5LiLxlGGilGeRhjlD9nmueQ+CKn3WrI7uE0MXoxv1wh9ZyWbDiIv25qBNB/PSet1ZREs1ANF0FZFTNe5esODYs7EvRSjLSoek0odGqbAZZu6w0pziikmSutU1FDKl/ghlGe0BO/iQrzXC0CFIG2eWoYkXpOxYpFpr96Th4NjAZlT7/GuGLUFYxq1tPPyK40YjRoGXxNniOaGctB7VUxuV+aRucoB18PYIBo3Raki7cE4ZgVMrnzPb4ISA6+FkUxbzpG9ybdXldaZGylcu8t39qM5VubAajfrsVj5HT9Hu2Dr7V2PWqdrg8oShKwphg5ta1+7ecxRhyzQh5g+WT194WywGMoGpMX/nyDzInzR1b0W89JixgjZU+/O5d+gW+OdeOGc+vxb+cNA6B+uxatSxLQRJc6RvngSnNpqxgl4qgGijHSrvp1KJpo3ttffSWzwVfJPIHIrgV5nqoPIMkQCkaEvDWMiAI09Yyaft1UWrQEUfb0s9skBe/UQUWatWsp0Ng1RBNSj0qrgn+A9uOVqHytZdwZ6ZemvvEXEWKyUT6QMlOkYfXrLkW7GV75mmM6iDpQyF1pcCiKtxlRIaAFmRMD9c7TOv4mFFemtGzdYmRXGinwGIlpaBhpqFrEYmLClaZD8HWXBqqY0gBJL/haG1caiXsqcNpg06gKPQtwwyhPIJJ3vqfqE3iRx4Sh4xlgTmgdrE4W+FqvdlXJjZqpKIoiOkk6tYZuci2z+LrCURAxTMsYI2L8aVHHSGmADNTvTsvg63xM1Qe4Ky1vIDd3IY8xAiAt9l2hqCFdJ7Qgfa4GMpa1rgodicc01JZ6NPk9QOE2Mch8IFl83aEoiFDU2NajeRafFooRUcScdqumbm8t46jSKe5IKNSwvpI/D1P1AW4Y5Q1cMUqGuGmCUWMshGogK0aO/h8DZBEMR2MQYqLqknpAh55+Hqexin6myuL71T+3y39XO4uPLM5avFjokaoPJM5RC8UoEwMk4UpT/7iIiy/fknby62zzGDnGKM8meF8Y1XVCk4QBMkCMkTM5WF3tOUSMk4Fin2ji0biSc66QLL7Gth78+5LPAfRfpJM2WhZ4JIHXUSGGVn9Qs8bPJF1fi3PMpO2GloUn87EdCMANo7yhSy7wyC85oIwxMsZCqAY9kfQMI5c9EfPQE1bXMIoIMUTjvqGBYp9oUkBUMSGGqBAbMM5Db5RZfIT+inTSRsuWICRVv70ngtbOkGaGkZbu1XSLOwLaBl/na4wR23c/hxpy5Wuerg9AqRjlb/B1T5rB1xaLRTOFTbkIaasYJX7LKO40QL+YKC07zxM3k9YQ408bZSb9GCMtg6/l48qjGkYAV4zyhm4d4jZYxkUayRrEdUIbISbKhdvSmRMepw2BiKC60UAML7vVAqddu/c2l90KiwUQRWlOGCXYlFyPyiKn6u4zJQUalDcgAea7mv3yNhJcDqgfYF6giystfcVIE8OItAPJM8Uov842jyHtH7hiJCErIHkafK1sB5JOQL5WtYzSra1EG6KK9YTVN/5oQq7HsIpCzVxMQLKbSa22OqkCzO99fav8d7UDzIu0DL4mlb3TykqT7o3WzpDqMVc8xohjakhaLVeMJLTo/8Uy5LwtluQYor4gWXxqGw3kuNw6ZE8WOCXDyCgp+0BCYdPakCRqihATERZicNnp/z4JMH95/QH87bPDALQNMNfSXdjql6qXp2NfygZbWFA95qqTZ6VxzIysGPF0fQCJhSQUzc8YI6Uyk87bvkejWkaBNGsrqYFW50gTcqxat7UpUPxeT0hQxTAiAeZFivgWPQLMgxH1y1Sc6Amlva8y+SGmcrXzLh2a97IAN4zyBFkxyjPLvy/ceR5jFEgzI40gux5VHq9AOJb0e1qidesTGqRbvZw2dpsVTrsV4WgMPREBZSr+ll6GqrKvZHc4qqpx0BMa+H4kMVchhfv/80PtsMYNNjVirrgrjWNqurlilARx1eRrun66GWkEuc6P6llp0fjv6aEYGauWEaCs+aR9gnGB04ZwNIaAyq6mUPwcLxhZoWmAuTPeUzEaE9ETEqgbRsTQAYBj8UbAx7vCfVYvTxVztfCtHfLf1Yi56ugJAwCisfxS1rlhlCfwliDJuO35HXwtF3ccoOo1waNVjJFOMTPSb0rn2GMgY1mPKuGEQqcdHT0R1duCkDkx9YwaTQPMLRYLPE4bOoNRHGrrRg3l3n2pDJ2X1x/Ey+sPAjjZ0CExVwAw84+fICyI+PnU0bhodBUAdWKufPHimmFBuwbFLMBXyTwgHI0hLEgWPy/wKJEIvs6vNyFCpsqMVm6mdKtxq0GBrBipH2xLC71ijIDE3FE7WJ2co0uHc3TZregEcKQ9CIyg+91KQ+dHf/kUbd1h/PtFp+DKM+sAnGzoKIt6uh02hIUohlcUqhpzRZ4TBTqMvZ7wVTIPUC5mergoWMST573SMo4xcmpkGDGw0BvTlaZPFh+QXPpBDfTKvAMUFfJVeE4kVy+XFJkxNSVpGTqkxldYheQR4uITRVE2ehvbtWtQzALcMMoDSHyRMx4wyVE88Ay0CNKkJ0NlRlbYNKp8rUtWWvwcjeRKC8qxYvrEGAFaKEbaBuQrY38Iu5r9qhoG4ahkGLnSjBUjRrwaoRGpXHwP/etr+e9q149iAW4Y5QGyHMqLO8qQB0u+KkaJ4Ot0Y4y0MYz0VAfIQm8kY1lfxYjU09Em+ForFTGVYfDiuoN4cV3q2B8akEyzulJPWvuTkAg1PADExecPRDDrzxsBAA9e04Cz6ksBqF8/igW4YZQHkOBIHl+UgNRdMZLbhCYkjibdbCate6Wla7DRRFaMDDQnyLHq4XrUTjHSVhVTxv7c/bct2N3ShWvHD8GNk4YDoG8YxGIiIvHg5iFpGkYu+X6k70ojLr4mX0DedlZ9qWb1o1iAr5R5AOmpo4d7glVkxShPm8gmYozSVIw0jjHSJSvNaTxXWqbXkSaaGUbx71ejiGQqlLE/FYVOAMCgYpdqhoGyyGy6Bq47HhIRUlHxztdnIwDwgJM8gDSQ5an6CciDhdcxYivGiIWYGSO50oIaqylKiDG2elcrWv1B1X4ncY7aG8tykLOgnpGgfAalaxipqRgRlG7tfHCfKeGGUR7AG8iejCfPCzwm6hilNyeI0RBQ+S2Su9IyI8CAK23TgfaTgpVpEtQ4+FoJKerosKm3VJI4R6fNmnbbES0UI/ISVFHkNH0WWm+4YZQH8AayJ6OVAsIqGVe+1qoliK6uNG2qe9NEz/HSQoEmTWoBfYy/srgrTU3DSHYVZlC9XEvFSI9x1xu+UuYBvIHsyXg0eLCwTCItPr1HgFuOv1E3A0nPAo9G7JWmh5uJpLOTdhEA5FR2gG46u1LR1bOOUUhFY5k8gzIxQLRQjELyceWffsINozyAN5A9GZeiwKMoiml1mDcTmXax16zyNQPp+kZSjGTlT8PxSpXOfu/rW+W/00xnV14Llw412FwaxCISV1omBohbS8VIo6B3luArZR7AFaOTIQ8WUZSyQvJNLs7alaZ6jJGeTWS1qeRMC1EUFans2o0XSWf/4OsWPL5KMpAemTlOztqiGaibyEizyl3ktURWjFSoME3IxgBxaZGVFtUv6F1vuGGUB5DK1zzGKIHyDTsUyT/DKFOXlUcjNUXPQFujudJC0RjEeG9PLceLpLMfauuRtzUM9qqSzh7SeXHWQjEiLqtMzjHh4lPTYJO+W6syCSyRkTb5zDPP4Mwzz0RJSQlKSkowceJEvPPOO/LnN910EywWS9Kf8847L+k7QqEQ5s2bh8rKShQWFmLGjBk4fPhw0j7t7e2YM2cOvF4vvF4v5syZg46OjqR9Dh06hKuuugqFhYWorKzEHXfcgXA4DM7JyAUeeVaajEORAWIk1wktMnVZaWU0yFXadWkiayxXWjZp3jTRwrVFmjzrYSgDiSBnNRWjAKOKUSLjMf9ijDI64yFDhuCRRx7BZ599hs8++wyXXnoprr76amzfvl3e54orrkBTU5P851//+lfSd8yfPx9vvPEGli5dirVr16KrqwvTp0+HICQu8KxZs7BlyxasWLECK1aswJYtWzBnzhz5c0EQcOWVV6K7uxtr167F0qVLsWzZMixYsCDbcTA1pMAjr2OUjFbVnFkklzpGIpEpVEDPJrLkN/2BiKp1eWhBxsphs6iaNdUXZLwqCp2q1bnRcz4A2tQ7I9+dSVaaJjFGUX3HXk8yWimvuuqqpP9/8MEH8cwzz2DDhg0444wzAAAulws1NTUp/73P58Pzzz+PV155BZdffjkAYPHixaivr8d7772HqVOnYufOnVixYgU2bNiACRMmAACee+45TJw4Ebt27cKYMWOwcuVK7NixA42NjairqwMAPPbYY7jpppvw4IMPoqSkJLNRMDlkEeQtQZJxO6zoChlHIaBJIMOsNKUBpVZMViwmyg96PRUjQQSafUHma7foWcNI+l1pIS9y21UbK71TxrVQjLLJSpOTRzTJluOKUdoIgoClS5eiu7sbEydOlLevXr0aVVVVGD16NObOnYvW1lb5s82bNyMSiWDKlCnytrq6OjQ0NGDdunUAgPXr18Pr9cpGEQCcd9558Hq9Sfs0NDTIRhEATJ06FaFQCJs3b872lExLt47uCZZx56liJIpixi4rpStDLXeasqGvnsHXgLoLIS30yEhTQmJP1IxzSbh89VmctVSMMkvXV99gC+mYIao3GUsIW7duxcSJExEMBlFUVIQ33ngDY8eOBQBMmzYN1157LYYNG4b9+/fjV7/6FS699FJs3rwZLpcLzc3NcDqdKCsrS/rO6upqNDc3AwCam5tRVVV10u9WVVUl7VNdXZ30eVlZGZxOp7xPKkKhEEKhRIVWv9+f6ekbEn9PBIC6Ze2NSL4WeQxFY4iRoN00DRCb1QKn3YpwNIZAREDZwP8kY5QVp7VMESZ1eWKxhItwS2OHPDY06/LQhCyoer3wuBUlL9SCFcVIC5dVJsafNooRd6WlzZgxY7BlyxZ0dHRg2bJluPHGG7FmzRqMHTsW119/vbxfQ0MDzjnnHAwbNgzLly/HzJkz+/zO3nVkUtWUyWaf3jz88MP4zW9+M+A5mo3OeIxRvikjA+HRILODRZSKT7otQQBpvMLRmGotM5TBnlqmZqeqy/Pgv3bKf6dZl4cmesffEMVIi8VZL9VCk2atWbhEXRooRnrPLz3J2DByOp0YOXIkAOCcc87Bpk2b8NRTT+HZZ589ad/a2loMGzYMe/ZID52amhqEw2G0t7cnqUatra2YNGmSvE9LS8tJ33Xs2DFZJaqpqcHGjRuTPm9vb0ckEjlJSVJy33334e6775b/3+/3o76+Pt1TNyx6P1xYxa3BWxeLkO7xTpsV9gyCdj0OG3yBiGrjpdc8JXV5AODaZ9cjEBZw9+RRuPQ0aRurDTQDGQbQ04aoFlLZAHWKpOodR6WNYsR2jJEehTX1JuczFkUxyT2l5MSJE2hsbERtbS0AYPz48XA4HFi1apW8T1NTE7Zt2yYbRhMnToTP58Onn34q77Nx40b4fL6kfbZt24ampiZ5n5UrV8LlcmH8+PF9HqvL5ZJLDZA/ZqXVH8S2Iz5sO+JDd/zhcqitR95mhKwbtclXV1ogyyKKatcyyrRNCS2qStxyHR7izhhaXihvY9GNBuhbJRxIqBaiqJ6bPhujgSZuhfGnFokCjxlkpWmgGHFXWprcf//9mDZtGurr69HZ2YmlS5di9erVWLFiBbq6urBw4UL84Ac/QG1tLQ4cOID7778flZWV+P73vw8A8Hq9uPnmm7FgwQJUVFSgvLwc99xzD8aNGydnqZ1++um44oorMHfuXFmFuuWWWzB9+nSMGTMGADBlyhSMHTsWc+bMwaOPPoq2tjbcc889mDt3rqmNnUxI5R74nxW78D8rdgFg1z2gJVqkvLIIqQ2TaWyKbEiq5UqLJFxpeuG02wBEEBHYN5b1VoKV1ykUjalSCDChiukVfK1FrzSSrs+YYhTVt4aUnmRkGLW0tGDOnDloamqC1+vFmWeeiRUrVmDy5MkIBALYunUrXn75ZXR0dKC2thaXXHIJXnvtNRQXF8vf8cQTT8But+O6665DIBDAZZddhhdffBE2W2LwlyxZgjvuuEPOXpsxYwaefvpp+XObzYbly5fj1ltvxfnnnw+Px4NZs2bhd7/7Xa7jYRqIeyAYEfB//nc9AOA/rz4D3x4quTBZdQ9oSb4qRnLbjQwfeOSFttmnjtqYaQkBNSiILzhGqBKfaS0q2jhtVlgskmIUjAgocTuo/4be/bpcmgSYZ26AcMVIXTK6+59//vk+P/N4PHj33XcH/A63241FixZh0aJFfe5TXl6OxYsX9/s9Q4cOxdtvvz3g7+UrpGx/W3eiGvhZQ0pVKdtvVDx5HmOU6YJqjceQtHaqZBgxEAtX6JIWdyMYRnqPl8VigctuRTASUy2BIZjlXKUFMUAiggghJsrV8mmSTZCzFvGRIQYUXL3IvzPOM5Q3jho3tZHJ1zpGmfZJI8htCFRaBPVWQABjBeQHmRgvolyo7V7VVzEC1DvHYBYGiKatSrhixDEb5KZz2izcfdaLfG0JkjBABr79SY0fICH5HzjRjW1HfADo1vjRWwEBtEmDpgUb40UMSXXGK5BFVWiaKF14oUgMBU76vxHK4hxJoHY4GkMsJqpS3iKfK19zw8jkkMld4nEym12jF648jTEiWWnp1DBKFcT/1ldNeOsrKSOUZhB/gIEK7UZSjFh4o1dbMdI7wNxqtcBpsyIsxFSLM0r0JMtcMQKkjEC3lf74yEHhOsV36Qk3jExOKIubLl/w5GlWWk8GrjRljZ//Xr4DG/a14dLTqnB33BiiqUKSbDm3joaRoRQj0nle1/FSVzFKxBjp9/xy2eOGkcrnmI1iRP69Gsax3vFdesINI5OTTYPCfMFI6gBNAhk88EgQPwDUxP9bWuBQJYi/J5K+kqUWLg0qHdMiEGFBYVM5xogUeNRRtXA5bOgMRZmKo7LbrLBZLRAUjZdpo3cNKT3hMoLJyUamzRfyNcYo2+BrZ9xoiKikprAQTKxFpWNa6F0VGkgYLOotzvFzNLUqFjdAMjT+1GxXEouJCBPDiFe+5piNUB77iQciXws8ZtuVvSweeapWdmMPAwu9sRQjBoKvHeqOVyDLuUoTufq1yq1wMn15VdOIV8ZTccWIYzryObNgIPK1wOOJeG2rTLs4VBRJhpFVhZ5YQOI66Okakhd6AxjLgSwKA9LGpbZixEAogPwCpZJSmk1WGqCuYqS8ntww4pgOvSvHsgwxFg+d6M6r3nG+gGQYRWOZPegTC4SJ1QG7uudIEzZcj+rG6emdlQYoXWn0z1GIiXKfuUzPUVXFSNFoOh/r33HDyOTkc1n3gSAPomNdYblWTz6Q6M2UoXSvcoHHTILC1cJYipH+97barSlYcBcmAszVM0CUv5Muarp9s31GmAWelWZyyM2crxO8P/LJWFQWaiSutOOdoYwKNaqdys7EImhX121Ck0zKLqiFmoqRKIpZx9/QRE3FSPmdrgyDnNWMkWTBhakn3DAyOfk+wVNBjITG9h55GzEQALrVnFkhVaHGVz9txKufNgJIr1Cj2uUNWGgi61I50JYmLLiZ1FSMwkIMMTH+O0yUJFAjyFn6TqfdmnH1ajUVowADBqmecMPI5MjprjzGSCaVkXDv61vlv9Os5swKykKNN7+4CS2dIfzkghG45uzBANIr1Ki2YtQZkuryBOP1efTAKAUeRVFkwvWoprEcDCsCgPWsY2RXz1hOxIBmboCoqRiF8jw2lRtGJifffcWpIEbC8a4QbnphEwDgkZnj5KKFZuwppyzUaIlnlY2pKcqoUKPagbbdccOoJ6yfUWKUop+k2zugd3kDNdUU6RrYrBY4bPoFAKvZbDqXGFBVY4yi+hvdesINI5OTbfEwM0OMhI6esLzttJpiVao5s0hYkB56DlumwZ7qqinhiP7xcEZRjJQlJlio8aOG0aDMUrSoVCIiHbQIvs7GANEkxihP1w1uGJmcUJ77ivtDWfQyIog6Hom2kHOt9WYWR6XGGyqJ9xJFEYH49x480Z1RUDhNEufItmFEFlS91RQ1MxVZiXNRN/g6ewNEi6DwfPU0cMPI5ITyuN/NQCizQIrd+XMrkFL/g8s8Gf07Nd5QU8V7PfSvr+W/ax3vJasDjLvS5Iw0ZtQUttxMNHFpoBhlY/ypq2Tl97qRP6tBnsJCuiurWK0WOG1S5+wSj0Pvw9EEURQTJRwyfEtVQzEi8V5doShu+NMGAMB/XX0Gzh5aBkD7eC+jKEZynzSdY0AScWfqKUZ6ugoBbRQjVy4xRmq4MRkxSvWCG0YmJ9FENj8n+EC4HJJhxHqwLS2UC36mxrJSMRJFkYpSQeK9WjsTlce/VV+qW7yXmoG2NGHFaEik69Mfr2xbZdBG3Vie7J/PWsQ+5WMDWYBXvjY98htJnk7wgTBKsC0tQjn0QFLGG4QzbbQ2AMrj0tM1ZBTFiIUaRoC6RgMzxp+KjXIT55j581lNJSuUQ1C4GeCrpclJBNHl5wQfCKMshLRIToHOriUIQH+85Hlqt+paLkHtbvG0YMaVpmaRQWbOMQ8VozyPTeWGkcnhTWT7xyh1a2iRi0TutFlBxBza40Ue7mUFTl2rjpP7RFkniEWI0nCiM6RrA2RVG5lG2XDnqKkYyckx2WSlqVlck7vSOGYmkV3AL3Uq8s2Vlkuwp8ViUS09m5UkAaW7kGXViKgphzsCujZAVtOdI9cxygvFKIusNBWfXWTs89XTwFdLk8PT9fuHK0aZoVZ6NivpwcpMPTVq89AiwMh81aT4ISMxRsxVvlbzuPJ83eBZaSYnlOdplwORb4pRroZyQiFQKcZI53lKCiZGBFF25bAEKYi5/3i3vE3PBsiaFD/U3TCSfj+shjKTU0sQ8xulesENI5OTSNfn4mAq1O7/xRq5GiBqPYzJPGUhe9JltyEiRJlUjFhrgKxUjGiVcCCwUkuHVeNPGyVL//tRD7hhZGKEmCi3f8i0mF++oKafnkVyfeDJgaiUH8asqAPSMVjRFQKTihEpiPnCJwew7PPDAPRtgOx2JGcq0rx+7KTrs1n5Wk3FiJUaUnrBDSMTo3yTyFfLfyBcKi30rBKUq15nNx9UU4wYyoKRz5FBxYgUxFS2sGkY7NWtIGZSTBZlw4gV1SIvFaM89zTk51nnCUmGEVeMUpK/ilF280GthzErfbEAY9S2YiVjzmGzwBr3ntF+uejoCQMAojF9r4NcxFINZSYHA0TNbDm5hlSerhvcMDIx5MHutFlhtepXTZhl8k0xyqVuCqCeYpQICtf/kZSozcPunCCL4XdHVupaEFMq4aDOAu0PRADor9wRQ1mIiYhSrvgulyTIQTFSpYFvNLdYRKOj/1OIoxqJQFt+mftCzbdBFgnl6J5Qq9IxS9mTRlCMyL09+YxqXQtiAuot0KFoPD6SkRgjgP5zIhcDhPwbNQxHYuTqHd+lFzzGyMSwFNDKKmp2qGaR3F1p6qgDLNVNUfNNnBYsVbSXFKMIlTlByhEACVdaiz8olyTQuhwB0KsVTkRAkYvesik/o7O4jiQeLyzEEIuJVL0CrMR36QU3jEwMSynQrGIEdYAmuTYVVksxYjH4Wo3YDVokKpjrP140DclU5QheXn8QL68/CED7cgSA5C502q0IR2P0FaNcstIcyYHvNCuE86w0jmlhKaCVVdwGiCehSa5zQq3eWKwUeATUbYxKi0TWkP7jRVNFJOUIAODGv3yKE91h/OyiUzD9zDoA2pcjILjjhhFLZSrcSU2dBWqGkRATERa4YcQxKSHeJ21A8k0xIueZfYFHtRSj3JQsmqjlLqQJS25ymnOClCNQMqa6RLdyBASXwwYEo6q9EGQTy2O3WWG3WhCNiVSPi5d54cHXpoalOARWMUIGEk1yjR1IZPGp5VLQf64aQTEKseR6VMmQDAnEWNY/o1YuU0F5TgTCUQBAVyia1b9XY67yMi/cMDI1vIHswOSbYhTMMV2f/DvaCwRLwddqGX80YdGQpP1yEYnPsdpSD9XvzQa3CkU/o0IM8cYE6AxGsvoONdRNci867flb5oUbRiYm3zML0iFfY4yyDdpVy2jItYwATdQy/mjC0kuPGi0zRFGU0/UHl+lvGLlUUIyUgdxOhpIhWEqE0AseY2RiWApoZZW8U4xydK8mjAaV0vUZkO6NpRjpv3ipoRgp70cmjD+KihEpSUDKEQDA7pYuORsyk5IEqihGDKmResENIxOTa1+sfEDNRowskqvSoFalcJYKPCbaxLCrGLHkelRDMVIaIEwZyyqVJLjv9a3y3zMpSeBUwSgl3xWMCGj1B3UvIKoH3DAyMdzyHxg1GzGySO6Vr1VuIsuCAsK4YhQRYhBikpuJBaNBjXuIuKysFqkfm97ISimFcyQlCRrbuvHvS74AADwyc5yceZdJSQI1jFKiPvmDUbR2hrhhxDEXuVRVzRfyTTHKNc1bvSayRN3Uf66yPieUY89CgUc1xkv5UmexMGAYUTRAUpUkaBjszaokgRpuzHx5SewPbhiZGJbewlkl3xSjXKuhq6YY5dBlnDaszwllPAkLbnJVFCOG6jQB7BogxGY8Fm+jkgsk9ml3S5e8jbRiAfRpx6IX3DAyMSxlrrCKSwUpmmVy75WmlmLEjtvXKIqRy25lQk1xqRCTxVpmlBoNW4nxV1HozL6idzzd/3hX7oZRqtine7OMfTI63DAyMSylQLOK3IgxSr8RI4skjOXcFKMw5dRslnp/sV7gMcRQOxBA0SvNxJlRsmJEcU4E4udYX16QtRJDgq9JC49cILFP/9rWhD9++A2A7GOfjA43jEwMS/2UWEVZyiAsxOC2mnusEmpDri1B6C2Cyoc6C3OV9ZYgQcZa/bhUqPsUzLF1DW3UTYvP7DoSlxcA9ISl72hs65HdXtm6vEjs04Z9J+Rt2cY+GR1uGJkYlvpPsYpybEKRGBMLs1oolZnsXWn0C2IGWUvNZlwxYk1NUVcxYuPZRebEp/tPUEthz/Y6pnJ5vbu9Be9ubwGQu8uLVReylnDDyMSw9gBlEYfNCpvVAiEmIhgV4IVD70NSDeUDL+vK1yooRsTly0pqtlq9v2jBWrapbCyrEmPE1jluPeKnlsKebVFT4vICgP9Z8TU+3nMcF46qxC+uOA1A7i4vMvZnDfHmlftMCTeMTEyubpN8wWW3oicsMFu3hhY0iuapqRixkpptHMWILTWF5v0TYsxdqMZxZBsDqkz3r/VK//V6HNRcXmR+nXdKRd5kofWGG0YmJtdA23zB7bChJyww3RuLBiEKRfPIIhiNiYgKMdhtuc+tXEsI0EZ2DTHqUggxFn/jUkMxYiQ+ksTzHO9KtO+glcIeiMcHeZzZn6MaCm4iEYKN+aUH3DAyMdyVlh5qvPGyCA1lRumCC9MyjBibpy6KVY7VgL3xIiUczJeVpmYKe+KFIPtzLCtwAgBsFLNpWVMk9YAbRiaGtSJprMK664QWNJQZ5UM8GIkh/lzOCdbmqUuhGImiyIR7T4mspjCjsKlRx4gNtZvE83y85zj+Z8XXAOilsNOY94NUiAEiZQQ8jNyPesANIxMTYsxFwSqsp2fTgsZbuM1qgcNmQUQQqS2EyoKFLECMP1EEIoIIp50xw4g1Q1JFxUjv+EgSz9PiD8rbaKWw01Bm1FA3WZtfesDGk4ijCnyCp0feKEaU5kOioSadhZC1Cu3KhYrFuDPWXB2yYmTixVmN46Bxji4V4uFCDLXn0Yv8PfM8gLUHKKuwnp5NC1oKYuJhTFcxYmWeOm1WuQcVi3FnIUbUFAJZ2LtCUbQqlJVcYKl3HpC4Z7weO7UUdhptT9RRjNgqlaAHbMw6DnWiQgzRmNRIJ58neDpwxSgz5N5YlIwGVgJtCRaLRZWmobQIMpZtSsYqJiLJ5ZQLrM0Jchweh51aCjs5x1yy0tTIoGRNrdMDNu4sDnWUN0o+T/B0yLcYI1qKES2jIdtCd2rCciNZVo0GgE7PLkBRx4iZuDP6L080ShKooRgFGJtfesCDr02K8kZhJaiVVfJHMaLzwKNtNMiuIUYUEIDtOcGKYURq/EQVxtCXjR3y/Milxg8r50hQp1caadnEmmLElhtTD7hhZFLIW7jTbjV9x/hcYVkdoAktF4ybtmLEYEwDyyoiKz0QU9X4+c+3d8p/p1HjhxXDSBlXR6uEAw0DRE2DjZWx14OMrsgzzzyDM888EyUlJSgpKcHEiRPxzjvvyJ+LooiFCxeirq4OHo8HF198MbZv3570HaFQCPPmzUNlZSUKCwsxY8YMHD58OGmf9vZ2zJkzB16vF16vF3PmzEFHR0fSPocOHcJVV12FwsJCVFZW4o477kA4HAZHgrUUaJahvdCzSoiaYkT3LZWVmjVKuGI0MLMnDMXb8y7A2/MugDNeSf3nU0fL22ZPGJr1d7M2J8jLUyxewoEGNFxWasxTWs8JI5PRrBsyZAgeeeQRfPbZZ/jss89w6aWX4uqrr5aNn9/+9rd4/PHH8fTTT2PTpk2oqanB5MmT0dnZKX/H/Pnz8cYbb2Dp0qVYu3Yturq6MH36dAhC4sLOmjULW7ZswYoVK7BixQps2bIFc+bMkT8XBAFXXnkluru7sXbtWixduhTLli3DggULch0P08DKw9MI5ItiFKIUy0N7vFicq2qkQdOClfIGVSVuuaYPOZbhFYXytlyClOUXO0bmhBolHEgcVS6FFBOlEigqRoxlBOpBRq60q666Kun/H3zwQTzzzDPYsGEDxo4diyeffBIPPPAAZs6cCQB46aWXUF1djVdffRU//elP4fP58Pzzz+OVV17B5ZdfDgBYvHgx6uvr8d5772Hq1KnYuXMnVqxYgQ0bNmDChAkAgOeeew4TJ07Erl27MGbMGKxcuRI7duxAY2Mj6urqAACPPfYYbrrpJjz44IMoKSnJeWCMDnnjCkUEtPqDedsMMB3yRTEKUorloT1erPX+AhLGI83aPLRgMQbEGVcuwrSNZUbcq6SEgyjGjRAKj1MaLwREMQoLMcRiYs5hE1EhJitirIy9HmR9ZwmCgKVLl6K7uxsTJ07E/v370dzcjClTpsj7uFwuXHTRRVi3bh0AYPPmzYhEIkn71NXVoaGhQd5n/fr18Hq9slEEAOeddx68Xm/SPg0NDbJRBABTp05FKBTC5s2b+zzmUCgEv9+f9MesEGnVH4yitTOk89GwTb4oRqwGX7O40LOsGLGYxUdSzgtddMJWWXOlqVHCgWaMEUBnrgYV35FLGQGjk/EV2bp1K4qKiuByufCzn/0Mb7zxBsaOHYvm5mYAQHV1ddL+1dXV8mfNzc1wOp0oKyvrd5+qqqqTfreqqippn96/U1ZWBqfTKe+TiocffliOW/J6vaivr8/w7I0Di4XpWCV/FCM6KdDUg68ZXOjJezetgoU0YTEGpNApGUS0FtMQY8HXAN0XAlEUqcYYAXTuR57NLJGxeT9mzBhs2bIFHR0dWLZsGW688UasWbNG/rx3tH46Efy990m1fzb79Oa+++7D3XffLf+/3+83nXFEUmh3tyTiurYd8cl/zyWF1qzQDiZmFbnyNbOKETuLIAmvPdHNXkIHmwob3ewoFjOj3A4rfAE6BkhEEBGvv5vTC4HdZoXdakE0JtJRjBRJO6w1T9aSjA0jp9OJkSNHAgDOOeccbNq0CU899RR++ctfApDUnNraWnn/1tZWWd2pqalBOBxGe3t7kmrU2tqKSZMmyfu0tLSc9LvHjh1L+p6NGzcmfd7e3o5IJHKSkqTE5XLB5aLfjZglUqXQ3vv6VvnvuaTQmhWXCgGMLEKv8rU6LUFYekN12ujGzNCERv0b2rhVmhMsGX9yoDOFc1QGcLudORZctVsRDQuUFCP2DFI9yHnWiaKIUCiEESNGoKamBqtWrZI/C4fDWLNmjWz0jB8/Hg6HI2mfpqYmbNu2Td5n4sSJ8Pl8+PTTT+V9Nm7cCJ/Pl7TPtm3b0NTUJO+zcuVKuFwujB8/PtdTMjQkhfb2S0bK2x6ZOY5KCq1ZcVPu/cUqtAwQ2pkwIUYexq3+ILYd8WHbER+6Q1EAQGNbQN7GiluNxawhmooRq+2M5BcCCudI7kWLJWGEZ0vCYKN3XCzNLT3ISDG6//77MW3aNNTX16OzsxNLly7F6tWrsWLFClgsFsyfPx8PPfQQRo0ahVGjRuGhhx5CQUEBZs2aBQDwer24+eabsWDBAlRUVKC8vBz33HMPxo0bJ2epnX766bjiiiswd+5cPPvsswCAW265BdOnT8eYMWMAAFOmTMHYsWMxZ84cPProo2hra8M999yDuXPn5n1GWlWJG1Ulbny6v03eRtJnOamh3fuLVYKU0rypK0aMLPSp1NZVO1uwaqekYLOitrLoeqSpGAUZbWckF1OkcI6Jlie2nF1WNIPC5f5tDI27HmRkGLW0tGDOnDloamqC1+vFmWeeiRUrVmDy5MkAgF/84hcIBAK49dZb0d7ejgkTJmDlypUoLi6Wv+OJJ56A3W7Hddddh0AggMsuuwwvvvgibLbEhViyZAnuuOMOOXttxowZePrpp+XPbTYbli9fjltvvRXnn38+PB4PZs2ahd/97nc5DYaZoFVrIx+Qg4lNPma03gZpV9tlZaGfPWEoJo+VXPG/ffdrfLT7OC4YWYl7p50GANS6queCKIoJVxpDb/U05wSrAcA0FaMARWWGrmLEhnqrNxkZRs8//3y/n1ssFixcuBALFy7scx+3241FixZh0aJFfe5TXl6OxYsX9/tbQ4cOxdtvv93vPvkMmeBnDvYy8UBnmXxRjKgVeKTsegxRalWSK0RtBYDBXg8AoNhjZ0ptZbU5NE0VkRhGrLUzoqkY0XwZSLgx6R0XSzXF9IAdc5xDFTLBJ5xSzrPQBiBfFCPaLUF2HvVTibtJxD6x8zB2xo+FteBrpfHOUvwNXcWITlkJ2iQ62dM7RxouK5pZtbJbm7Gx15r8PnsTw4p7wgjki2JEr/K1NF77T/RQKR7KonxfUeQAkKhnxApk4bJaAIeNnaNLuJnYUlNoIiuljCkzNOuKsXgv6gE3jEwKqw8XFmG5YShNghFKrjTKb5MsZsJUFhGVlR3jA0jO4GOpzgzNOBcWizsCifsmyFj2F826Yjz4WoJO/XYOc3DLP31oBxOzSq7ZX6R4aJMv4T7LtXioKCYK07HkSmO1hEOQUaOBbmYUGzFnvUkoRhSDrynMebqKEXsvKXrADSOTQjPrwewoFaN0KrUblVzrBalRPDQ5mJiduapG13IaJJqrsjNWgFq1dNgy/hKKEcV0fUYVI9bGXmu4YWRSuCSaPsTPHxOlUv1Ou/kMI1EU5Qd6tjFGJJ19Z7MfP//7VwCk4qEkayub7EflWy5LD2NWA/JZVYJViXNhSEEEFCoijeDr+Lyi0VuOxxjRhxtGJkQQgMbtReje68TuLR4IZwG2/J7n/eKyiDjv0Feo6mpH9AMXnJddYroBC4RjCBwsh9Dlxqr3RNwwI/NTJOns1lhMHq8J40WMGD8t6/HqDsYQPFQOsduNTz624rvfZWPo3RbgvENf4cwjAaAhChYOTBCA9Wut6N5Rh66hNgiC7ockIQgY8uWnmLHjMwzGKYDwrawPTBCAz9bb0b2jDu2Ci6lzPGX7Z5ix4yvUFrYA3xuT0zl++akD3TvqcMxZnPM5krk6fOXXgGV81nNVEICdn7vQvaMOR8qKIFzJyNjrgZjH+Hw+EYDo8/n0PhRqLFsmikOGiCKQ+DNkiLSdk4Jly8SYyQds2TJRrBsco3OKy5aJkbrBVMZr2TJRrK0T2Bv6ZcvEUG0dU3OC2fua4oHxc8zu2HyV1Tl/IbNj3w9qrt/cMDKRYbRsmShaLMmTG5C2WSxsT3JdyIMBS5xiLPdTjH9ZjMJ4UT0umlA8R8qHxN40pXhg/ByzOEdKc5XZsR8ANddviyiKor6alX74/X54vV74Thw1fI81QQCGj/Tg8GELUqUYWywihgwWsX9vIH/lUSWCAIwcCxw+kvpziwUYPBjYu92werIgAPWnuNF01Iq+5kRtXQyHvgkOfIoUx4vZucrgnMiHseLnmMU5Ujo2Zsc+Dfx+P7wVdfD5fNTXbx5jBACv1wEFeh9Ebny84yIcPry6z89F0YLGwxZ8/F9X4uKxa7Q7MFbZAeBwP5+LInD4MPBfXmCsVgdFl493XISmo6v7/FwULTh6xJbenKA4XszOVQbnRD6MFT/HLM6R0rExO/bp0KPeV7OV88nJmqaOWqr7mZ4OyvsxCNU50ZHmj6axH7NztYPyfhTIh7Hi55j5frSOjdmx1xmuGAHAzKOAwV1ptdVW4A9p7Pf9vwAX/Vn9A2Kd6o+AP3xv4P2+/y/gogvVPx4VoDonKI4Xs3OVwTmRD2PFz1GxX7rnSOnYmB37dPD7gbl1qnw1jzHyelXxUWqNIADDhwNHjkgqam8sFmDIEGD/fsOGzNBFENBZMwSFx5tTyqYxAF2DalDSdNiwA0Z1TlD8MkEA6oeKaG6SpPqTv0pEbR1w6KBF+5gSxm4iBg+J+oHxc8ziHCl9IbNjnwZqrt/clWYSbDbgqaekv1ssyTOcFHJ+8kn2Jrdu2GyIPfEELBYLxF6VrkWLRdr++BOGHjDlnECucyJ5giV/luGX2WzA1J80xR/EvZ/GIkQRmHJzk/ZDT/EcTXxIEpTnAz/HDM9R8YW9n1+ZfCGzY6831PPcDITZ0vVFMXXNmvp6dlMudSdVAQ+TDdiyZaJYUR2hc4qUxqvFFxCf+FOX6K0MJ31VTZ0gPvGnLrHFF8ji4CjB4Jxg8JD6PLBYlgdmpHPM9sCon+OyZWKgpjbnL2R27PuBp+urhJlcaUoOHu/BhDu+hCXgwV/v/BYLRXvZRhCw8OfPoG3vIZx/QQOuXzDbdAP21w2HcNfvj+C0kiosvOHU3OaEIODu2xcheuQofnr9+TjjhulZf9kzH3yD3/y5FUKXG7+dMwo/mlnExtALAm6Z+wTcx1txz00XY+jVU3WfE4IAzPqvvfjg807826VV+N28wXofkoQgIPD+avzy6XfRWlSGF55fAI/Hme1XYdp9O/HF10HcfuUQ/MdPBjFzjkfeXIn/eeFDdJcPwvPP351T5euJd36F/YcE/Me1I3D7rNKcznHDnlY8+evn0WDtwX/85LKcKl+PveUztB2z4bGbRmP21YVsjH0fqLl+8+BrExKJCXAPbYPX48DFF+t9NAbAZkPjWRPwvnMERo0fpfsCqAYhQZoTZ4xz5T4nbDbsOn08tntHYeY55+Y0XuFYDO6hbQCAcyedws7Q22zYNupsHK0K4uZzJ2EoAwdmswGDRvtRGGzCmefmtphSxWaD47JL8OYHQQBAMAZ4sv8qlJ7agUJrG8ZPrGbqHMWLL8KbG2NS0+kcDsxmA4qGt6GwqBsTLxiW8zm6XA5sGHomGks9+I8cbm6bDXAMOYHCQVFceOFodsZeB3iMkQkhjQB5A9n0KY2/4ToYa1xJi2CUbnNI8j3BHBtqBuKNL79VX5pVE1o1SZwjO41kWW3yabdZYbdKQSm5dnkPkQ7vjN2Lyi72uTpaAnIX+9yXYDIXch13QNF8nEJzWyPDDSMTEqR40+ULNDtUs0ggTHdOyJ3Gc+w+T8b7/JEVqCpx53xcNHERw4jCgkOLzmAEQMJ4YAlahiSrxp/y3snVCEk8o3M/R5c9fi/mOO4RIYZoTDL4WDNKtYavnCYkQPGmyxdoKSCsEowbMLRURPL2nPsiSPe4aCIbfwwZIcQwYslYI8gLdK5GQ5TNFzuXwljI3TCip+rTUoyU97KLsbHXmvw+e5NCbjoXg4sNq5hdMQqG6RrLifFi582ZNuStmSUjJByV3uhd9pPrP+kNPcWIzTnhsFkQ9xbmZCyLoigbfzQMEGKQhoUYhFj2Lj5yL1ssie/MV3jwtQlJvIXn9+TOBLccP2BSw4i8oVKKHXBTUoxYVjdZMZZb/UG0doYAAP64YnS0PYhtR3wAgKpiFxNuSLKY0nOlsfX8slgscDts6AkLOb0QhIWYXEyRxrxXfkc4Gsv6HifXzWW3wtK7qFGewQ0jE8LqGxfLmN2VFlA89GjgojRerMaTAIpgW50NoyUbD+Gp9/ckbXtu7X48t3Y/AODOy0bhrsmj9Ti0JFyUXTouBuNcXHYresJCTi9QwXBifGjE8ijv6WBEyNowCkX5ukHghpEJCTKa1cEyrKgDakE724RW8HXAADFGehvLsycMxeSx1QCAG/60AV2hKO68bJS8jZVsPhqKkSiKsmHF4gItHVMkpzlB3GhWi+SeyxWSERiNiTkZpTybOQE3jEwIbbdJPkDedgNmNYzIYkPJWKalsMmp2Yy5TQBlUKu+c6KqxC27ymLxGJKxdSVoGOzV87BOImEsZz8nlP+2MxjBIEaMPkIiwDwHxUih6NNyWbkdNnSFojkZpdzTkIC9pxEnZ3i6fuawWLOGJiT4mnqMkakVI/bcq2RBZjE4lsY9pPy3/kAk52OiDY05oYYyQyMjkLa73cjwETAhAYZ99KzitrPhNlEL2inQLkquR3muMmgY0TpHWkSEGIR40O6Q0gJ9DyYFNBZn5f1nt7G3PLkoGn80lRk6Rim7Lkyt4a40E8JdaZljdsUoQDtdXy4qx049F9q4KKlitFC6eYeUZ9t0Qz1yuYdI5t3RjoC8jWTdAexl3lFRZigq+nSMUu5pIHDDyITI6gBXjNKGZll9FglSzjihVrOGckVumrASfE0gY81qnZlcFudUmXf3vr5V/jsrmXc03YU0n880lSwWX1K0hhtGJoTlxYZVzJ6VFgjTVWaoVdslFbkZVDfddraM5aDiGrJYZ0aeE1ncQyTz7utmP+75+1cAgEdmjpMDzFnLvKPhLqT5fKaREUi7n6KR4YaRCaGtDuQDZnelhSjHNdAwJKNCDJF40AyLb6mszQmWi2ECisU5C6OBZN6RApYA0DDYy2DmXe5zIqTCywCNjEDa1fGNDJcUTAjLcRuskqjkzIY6QBva2V+JBqu5v6ECbD6MWVMRWXd15KIYEVgZ675IGH+5n+PR9gBa/UFKx0UzKJybBXwETEhQheA+syMvglEBoph9vyEWSeqaTSsrjUIWHwkIV34fSyQqX7NhLAcYX7hopLITl29dqZsZ95mSRGPh3Of9/hM9cqsXaseVi2Ikl4Jg0/DWEjbvME5OsC65swhRQERR6mVkJpRvkSwFXyvfUNmMmcldHaCJrPoxGI8F0C1+OKqqmIkstN7QqN+lRlNimun6rM4vLeExRiaEu9IyR/kWHozETPXWpEbXbBquR6O4hlhx74RUyGaiCY3+eSwX/AQSKnw2ihEpSXDoRLe8jVZJAqrp+ozOLy3hhpEJoR1omw84bVZYLJJiFIoIgMeh9yFRQ/nAo9eCgCwQ5i0oR8M9QROjKEY04m+YdRfKmYqZn6OaJQloxHe190iB71GTKebZwA0jE8J6LAKLWCwWuO02BCKC6QKw1VhsaKTrM68OUAhopQmJv2HXkMw9JitAuXUNbVw51LYiJQmeXfMN3vqqCQC9kgQ0FCPSgsVsoQTZwA0jE8KbAWaH22GVDCNGYkpooUbMGfmusBCDEBNhs2auRCWSBNicp6wWeGT1vqahGLEeH5lLY2FSkqDAmVh2aZUkoFlGgMVECK3hhpEJ4TFG2SE9XCLMKAS0UGM+KNWnUFRIetinS0IxYvNBzJxixPh4UVGMGFcRacTW9agwn7JVjEjcEwC0dYelbZ0hOfaJlVYsWsMNI5MhiqIqvXjyARa7qdNAjUatyuD0YCSGAmfm38G6AqJ0F4qiqHvmHPPB6hRjjFg9Rzn4OhdVLO4uvOy0KmolCbJVjFLFPS3d1IilmxoBsNOKRWu4YWQyQowXzWMZGmX1WSSogtJgs1rgsFkQEcSsx4v1RTBZFYvpfj+xbki68iHGiGI25lVn1VFTY7KtK0bingDgJy9/hmZfEDdfMBzfP3sIAHZasWgNN4xMhvKhxOqCwyqspWfTQq0F1W23ISJEsx6vAOMtCJTHFYrobxixH39DQU1h/BxdFKqhq3GOxCj9utmPVn8wbYOLxD0BAAkTHFNdzFwrFq3hvhaTQWRs6Y2eX95MSBT0M5crTS1lxqVwNWUD600rHTarHFTOQkC+3AjYxGpKgPH4SBqNhdVQxYhidCCHatrkpdrJ6xhxw8hsyG/hPLMgY8yqGKmlzOTaSyyxQLA7V1lyr8rNoRm9t2koRkHGXWk0+uep8aJC494mafp1pfkXbN0b7kozGUEVOjfnC/LbIAOLIE3UUmZyDVZPLPTszlW3w4aeMBu1rVg3GohiFBHErEs4sJ6V5qKhGFE8R5JV1tQRkLdlW02bnNOQsoKcj8vocMPIZJAHuJlaWmgFa3VraJFQjOgqDbnWrWF9oQcS6kwuKggtWI+/oVnCgfVz9PWEM4rlUZKoYJ77/UirmrYQExGOsu3G1BJuGJkMtRbBfMCsrjRZRVRJMcpWYWO9JQjAVgkH5rPSKJRwYD4rTS5sKqK1M5SdYUTRtU2yyva0dOKuv30JILtq2spnHqtjryXcMDIZsnuC0Ycny8iLIAPqAE2CqscYZWc0sK4OAMrGqPrPCdYDk5UlHLJV2Jgv4aCI74rFxIz/fSwmyi4rGudIssqU1aqzqaYdUMxvXvmaG0amI8T4g4VlcumDxDJy5WvKb4LuHCtDs94wFGAs+JrxJrKAsoRDlnFnjD6/SCxPTzgxD7Yc7oA1HkeVbiyP8qWL5nXM9eVCVuoc9BpNGxluGJkMI7yFs0quCz2rBFXqgZRrI1nWA20Btko4yIYkw/GDLocVnaHs7iFl1X43Y5mKqWJ5/r9/bpf/nm4sT0BhWNG8jkoja1BR5j5MMu4FDBvdWsINI5ORiNtg68FiBFiKJ6GJWnEbuRa7Yz1mBsg9joomNIN21SKXrK2wEAPxTrE2J5QVoq9++hMIooh7p52GC0ZWAkg/liegUEmtWWTt9YXy5cKbRXAX68VWtYYbRibDCIsNqyTUAf0XQZrI6fqUlYac0/UZj5kBFCoiA4qRERavXIzlYJjdqv3KCtFuhxXdYQHDKgoyj+UJq6OSKudEICxkPEcCBnDTagm7rx6crDBCpg+rsKQO0ESttPhc0/WN0OxYLlqo85xQBu2yfG/b4vEpLf5gxv+WzAc741X75UayWbwQqOU+tlktcMbHLJDFXDWCW1tL2J19nKwIGCCglVXMWscokamoToyRWZvIAso2F/oaRkrXFMvjReyZVn/mbSmMsjiT+kyFWbxoyKqfCsoMub+zMYyCKilZRoWvniaDZ6Vlj1mDr1VrCZJjbyxDZFkxYiwrFzuWFSOHjdT5yUJNUdFooEmRSzKMsjlONY0/ch8pA7zTJRH0zvbYawWPMTIZbd3Sm5qQRY2NfMe0dYxUqm2Vq5tJdvsynGXFStFP8vtORWNbViCp7AAQjs+1fce75NYU6aayG0UxysUAUVMl9eQwVxNjz7USgBtGpqOjJwIAiHLDKGPMWsdI7squVuXrXNP1GX5LdeV4jrRg2UWeKpV92eYjWLb5CID0U9mN4FoFEseXUyyPKq60HI6Lu9KS4IaRySAPcIeNrbdKI8CKOkCbUERdxSib8YoIMVnVZFsxYqPAI8utMpSp7L/65zZ8cagD0xpqcNslIwFkkMpuEFdaTspMWL0AeipKFuNjrxUZvX48/PDDOPfcc1FcXIyqqipcc8012LVrV9I+N910EywWS9Kf8847L2mfUCiEefPmobKyEoWFhZgxYwYOHz6ctE97ezvmzJkDr9cLr9eLOXPmoKOjI2mfQ4cO4aqrrkJhYSEqKytxxx13IBwOZ3JKpqDVH8S2Iz5sO+LD8S5J0j7RHZa3tWaRIZKP5BozwypquSjkwOQsXI9JMTMGqMujd7p+iOFWP1UlbrkNRU3cZVZW4JC3pdtPzCjuHDeFWB41XWnZKEY9BigFoSUZKUZr1qzBbbfdhnPPPRfRaBQPPPAApkyZgh07dqCwsFDe74orrsALL7wg/7/TmVxwav78+XjrrbewdOlSVFRUYMGCBZg+fTo2b94MWzx4b9asWTh8+DBWrFgBALjlllswZ84cvPXWWwAAQRBw5ZVXYtCgQVi7di1OnDiBG2+8EaIoYtGiRdmNhkFJJWX/44uj+McXRwGkL2XnO6ykZtMkIsRktyr9rLTsXY/kDdVigZxmzCLsKEbs13wClCUc2Ellp03CAMl+3rMbY8T22GtFRoYRMVIIL7zwAqqqqrB582ZceOGF8naXy4WampqU3+Hz+fD888/jlVdeweWXXw4AWLx4Merr6/Hee+9h6tSp2LlzJ1asWIENGzZgwoQJAIDnnnsOEydOxK5duzBmzBisXLkSO3bsQGNjI+rq6gAAjz32GG666SY8+OCDKCkpyeTUDI1Syr791c9x4EQPZk8Yih9+ZyiA9KXsfMeMwdfKhyTtt8FcGqwGFQs9y72ZiIq4q9mPVn8wq27qNDBKq5/yQuklOJv4cKO4c3KKMVLRJUqUrFxeVLhhJJHTq5rPJ2UdlJeXJ21fvXo1qqqqMHr0aMydOxetra3yZ5s3b0YkEsGUKVPkbXV1dWhoaMC6desAAOvXr4fX65WNIgA477zz4PV6k/ZpaGiQjSIAmDp1KkKhEDZv3pzyeEOhEPx+f9IfM6CUsknGysiqooyl7HyHLDoRQTRNVp/yIUm9V1oO5Q2MstCT4zvUFpAzr/TACA13AaAy/hJmQeaWkREqewMJo4a1ec+qwWZEsr7LRFHE3XffjQsuuAANDQ3y9mnTpmHJkiX44IMP8Nhjj2HTpk249NJLEQpJD5Xm5mY4nU6UlZUlfV91dTWam5vlfaqqqk76zaqqqqR9qqurkz4vKyuD0+mU9+nNww8/LMcseb1e1NfXZ3v6zMJbgmSPctHR23VCC+WCSluZkV2PWbhNjPKGyoohYhRXB5WMLcbPUc7+yiHGSI1mrR4Kx8UNI4mss9Juv/12fPXVV1i7dm3S9uuvv17+e0NDA8455xwMGzYMy5cvx8yZM/v8PlEUkx7cqR7i2eyj5L777sPdd98t/7/f7zedcRQVJKWj1stVokxRZkcFIwIKXcZP2lTTAMmlVxrr7UBIbZ4mXyJxgdTlAdKvzUMLo7mZsnKvGqB3HkBJmVExKy07JcsYY68VWT35582bhzfffBMfffQRhgwZ0u++tbW1GDZsGPbskYKDa2pqEA6H0d7enqQatba2YtKkSfI+LS0tJ33XsWPHZJWopqYGGzduTPq8vb0dkUjkJCWJ4HK54HKZO96GVJwdXOrR+UiMhzXebygsxHTPQqKFmtJ9Lr3lWFeMUiU03Pv6VvnvWic0yG4mhksbAInFucfEKeOeHFpvqNsSJHuDjbcESSaj1zVRFHH77bfj9ddfxwcffIARI0YM+G9OnDiBxsZG1NbWAgDGjx8Ph8OBVatWyfs0NTVh27ZtsmE0ceJE+Hw+fPrpp/I+GzduhM/nS9pn27ZtaGpqkvdZuXIlXC4Xxo8fn8lpmYoe7ivOiVy6g7OImm/huTSRZd3lO3vCULw97wL8/oaz5W2PzByHt+ddgLfnXYDZE4ZqejxylXDG72saagqrc4IgKzOMpevLvdJ4S5CcyUgxuu222/Dqq6/in//8J4qLi+VYHq/XC4/Hg66uLixcuBA/+MEPUFtbiwMHDuD+++9HZWUlvv/978v73nzzzViwYAEqKipQXl6Oe+65B+PGjZOz1E4//XRcccUVmDt3Lp599lkAUrr+9OnTMWbMGADAlClTMHbsWMyZMwePPvoo2tracM8992Du3Ll5lZGmRNmBm1v+2eF22NAZjJrGMEq4rNR7QyXB6pm0qmDdbVJV4kZViVvuiwVATmbQA6PE31Dp18X4OeZUYZrROkZGmV9akZFi9Mwzz8Dn8+Hiiy9GbW2t/Oe1114DANhsNmzduhVXX301Ro8ejRtvvBGjR4/G+vXrUVxcLH/PE088gWuuuQbXXXcdzj//fBQUFOCtt96SaxgBwJIlSzBu3DhMmTIFU6ZMwZlnnolXXnlF/txms2H58uVwu904//zzcd111+Gaa67B7373u1zHxLAobwiuGGUHK01DaZFwWdGP5cklWN0oi6AySFYU9ctUNEpWWj7U0snFAEm4C+lfx9wqchtj7LUiI8VooAeDx+PBu+++O+D3uN1uLFq0qN9CjOXl5Vi8eHG/3zN06FC8/fbbA/5evpBUTZjxWARWIeNmliKParqslHOssa0Hp9Wmr9QaZaFXuha8BQ7djoP1mCwCnRgjtudETqqYiu5C+bgY6+FmRNiegZyMSNx0VlgZ68BtFMxW5JEsNk0dAeqtYaxWC+zxeabM3koHo6gDBYrjK3bpZxgZRWFjNWOLJqyqYjmVETDI2GsFN4xMhFEWG5YxmyuNPPD2n+hRpUCh005qGWX2MJaDiRmfq3abVW5Z0qOjimi4wGTGih/SJKfsLxWVmWxblYiiaJix1wrjF2rhyJCHZ4GTX9ZscefwNsgiapQdIDV+AMAarxm246gfQ8oKAKRX48coqdmAdIzhQCyrN3FaBA2SVEGOLyKIiAgxODLog2eUFzsarjQ16xhlGgagLNBqhPtRC/gKaiICBonbYBm5m7rBFSNivBw83i1vo1WgMFWNn99/sBe//2AvgPRq/MgxRpTblKhBgdMGXyCir2FkkDIcyuMLRISMDCPDnGOWhU2VygxLWWnKec26UaoV3DAyEbzfTe6w0k09V9QsUKhsWvyTlzah2R/Cj88fjpnfloq9ptO0uK07DACIGqAnXSKgOKrbMRjlpcdps8JqAWKiZOiUuNOPyzKMYhQ/vrAQQ1SIwZ6m8RcWYiDTnaUCj2R/p92aUckNM8MNIxMh9+Fx8MuaLWYJvibGyzOr92L5Vqne2CMzx8l1eNIxXvqC1PgBgLICJ5r9IdSUeDKq8ePriQAAIgL7yhxZCPWMMWK9ICbBYrHA47ChOyxkvUCzfo7KF89gNIaiNA2jYFjhslIzKy1DZdMoBqmWsP36wckINcvN5wvkjXz1rmPUs7i0pKrEjYbBXnicJxcobBjspdbnK2FIZqamkLgGlwHKShTkEFNCCyMtXtmkjcdiYqLoJ+PPL5fC/ZvJnCDj4bBZMnIxpguZG6FoDLEMlFiekXYyXFowET2yYsQneLaQ2jyf7m9Da2dI00ahapBN5kwmlLilR0g6D3pl0DZxpR3rDMqxT1o3Zk0XYlxmU5uHFkYLVgcyG6+kAGDGn19EFQtEhIxc7sQVq5Yiphy3YFRIOwnHSHNLK7hhZCKMErzIMqzL+JlC3gYvP70qJ/dZX5QXSd9ptw5sGKWKe3rts8N47bPDALRvzJouBTmkZ9NCLm9gAIVNDk7OQk0BjHEPepySYZTJnFBb9eutZKVrGBnFhakl3DAyEXyCZw9RM3yBsLyNVhaXnhDDaMa3Bqty/MQI704jMDkpaPvlz9DsC2YctK0HCVeaPsHXSdlMBnjpySY7KmiwAGD5HDMw/tRWZqxWC1x2K0LRWEZjLzceZzywX0u4YWQieuQ6Ruw/PFlDzSwuPVH7LbUwg/gbZdA2WfrG1BTr1pg1XXJpc0ED0qQXMMZLDznGTMbLSDFUgKKTfSaKUVj9WlQepw2haCwjFx93pZ0MN4xMhFH6KbEIUTNWbGvG0x9K9XhoZXHpSUBlY5nE36SjGCkhc9UIwdfZqAM0UWZI+oNheD36tSZJh4Isgq+V7YyMQDYB5loo+h6HDR2IyEZYOvDg65PhhpGJIMF93PLPHKJmfHOsS95GMriMjNoP44Is1ZRwPE1/cCn77slsz5EWylidju4I6st0OYy0yaYtiNFe6nKJo1JVMcrCjclDME7GGOY5Jy1IjxyjPFxYpNBk7VTUdq8SV1pPKMM2BPG5OqS8gPox0UbvrDTlImexsB9/k00zU6MtztkUU9QiOSablkZGc2NqgblWgTyHV77OnQKXNHblBQ7Dus+UqP0mLhsNGTyIw9GYXPHaCMVIC7JQQGhAEgIOnKDf1kVNPNnEGBns2ZWLMqN2jJHyt9KBZzOfDPtPJU7aBCJxVxq3/LOGKEYep53JRScTRFGU3atqK0aZZGwl9WYywMNYr5YgRk0IyMaQNJpqkU2Vaa1ijABzj70WcMPIRBjtrYtFCuOKUVdIv75YtFC7NxOgSNfPwJVGHsR2qwVOgzSRBbR3pZGEgC8bO/DAP7YBMEZCQC7p+k0dAbT6g8y/lGRlgMjPZ/XmfC5uTL5uJOCGkYngMUa5U+gi8STGN4y06JpNishlVjfFWMpmtl3Lc4UkBLQoWtMYISHAnY2aEt93/4keQ1SczyrGiFFXmhZlBIwG+69rnLQJ8Ky0nCELfUQQEY6y3+C0P9TuzQQk1JTuDBS2HoMpm3rXMdKzFUk2ZNN0l7zUGYWEKy2DtHhNstIyr6/E6xidDFeMTAT3FeeOMhanJxyF0+7U8WhyoyesfkxDNg1WyTw1SiFSWRXTKyst/rvDKwqYdZ8pkWOM0hgvEmB+0KAB5llVmFYx8zWbMgJq93AzItwwMhE8xih3HDYrnHYrwtEYusMCStnPJu8TtYs7AgrXY0SAKIpppZMHNFggaJJNwUKakIXrjDovk0ZCbzJxMxk1wDy3IGcVY4xyKDzJX6gTGOPJxEkLo72Js0qh04ZwNIYegwdga5keLMREhKKxtN46jdabKZF+rs98kGMHDXJfZ6KmkADzP3y4F+9sawZgjADzbOKoNKljZM/GMOIxRr3hhpFJiAgxRAQpBYlP8NwocNrR3hNBt8FiO3qjhTJToJhrgbCQlmFEykqk2/1bbxLp5zHEYiKsGjc5DRgtWD2L/nnKczNCgHk2rjRfIAIACKkYu5hN7BOvY3Qyxnhl4wyI8gblvuLcICn75lGM1LvN7XHXI5B+vzQ5C8YgD2LlcerhTjNac+hsXI9GDTDP5Bw7Q3HDSMVA81xcfHzdSMANI5NArH6rBXAZoDYMyxTIjVGN9bDuTSLGSF1lJtMAbKOl67sVjW71WMCNVmcmm1o6JINt8thqZt1nSkgtokwMEGIQqdkolxd4pIMxtGzOgCgntxH6KbFMUTygOJMUdBbR6k2w0GlHR08kbaNBi6BwmlitFngcNgQiguZtQQDjjVdW7TLixvL3zx5srADzAeY8yboDgM6gdI5HOgJy5h3trLtsgq+5K+1kuGFkEoxWG4Zl5No8Bi/yqJULxpPhePUYTAEBpDEMRARdFKNEsLoxxiubdhlGcxema/ylyrr73zX78L9r9gGgn3WXXRkB6b41+osgTbhhZBKMJrezjJyCnmHHeNbQotIukLkrzWgKCBC/r7r1yUxLGJLGeFyTxsDRmIiIEEuruKhWbl9aeJzpuaxI1h0A/OCZdQhFY7hnymhcPKYKAP2sO0+GbsyIEEM8ZwddQW4YEYwxCzkDEjTYWyXLmEcx0qYSemK8MjOMjDRXsylkSYugwQxJt6IXWCAipGUYdavc7Jg2iVie/gOpSdadKCYq6Y8bol7WXaaxT0plyWWQ8hlawA0jk2A0uZ1lEv3SjK0YaZX9lagMnakrzTiPn0QtIx1caRFjtfpx2qywWoCYKBl1JW7HgP/GaKEASpdVOoVNQ9EY4sJMUjA/bdItrklin050h+RtXzd3ykYsqxXHtcI4TyZOv3BXGj2y6f/FInK9II1caekHXxtLHQCya85JC6O99FgsUrB6dzj9mCyjuVdJkLMQExERRDjt/RtGynEYWq5eOf10XWmpYp/uM0DFca3ghpFJ4CmX9Ch0mkUx0sZYztgwMmCFdj37pRnNaAAkNbA7LKRlSIajMURjkp5C4pNYR/mcDUQEuZZXXxC3tstuRW2pR73jcqbn4iOxT3tbuzD/tS0AjFFxXCuMMQs5A8L7pNGjwGUOxUgr90SBbEim6UrToLktbTyy8af9nDCiIUliXdIxjJTGplGeXw6bFXarBdGYiGBEgNfTv7tQswzR+D0VFmKICjHY+4jvIrFPypcZI1Qc1woebWUSEooRt3VzRa5jZPDga61UxITr0ZxuEyDhjuzR05VmwJisdBQ2EkPlsFkGVF5YIqNz1CjrTvmy0dgeGHB/oz/j1MI4s5DTL4mHJ7+kuSJXvjZJur7aBkjmla8NaBjplJUmxBLZTEZyk2djNBjp/IDMiimS9kJqz3ll14PDbT0D7k9KktSVuvPefaaEr6ImIbEIGuetklUKdXSb0EQrl5XsSsswRdhI6qY7wzgqWijnoJEMyUyC1cnibLRnVybFFOWXAZe652ixWGTjKJ1mtUQxGlNdnNdZaL0x1kzk9EnAgHEbrFLgModipLUrLd2mu0aMhyNBwVpnpZHfsxisB2JmRoPxshQBwGGVMtGaOgLA0LJ+95XrNKl0Lypbj9jix7X9qA81XsnY6Sv9PqFkcVNACR8Nk2BUOZpFzKIYaVVN2JOBmiKKoiEXQr1cafI1NFgPxEzaghixRQwAWG3S9WjxBwfcl4xDoUudc0yVfv/Ee3vwxHvStr7S77sN6NbWAm4YmQSt4knyAVkxMnq6vrzgqKs0FGaQlRaKxhDPzDbUQqhXVprRCh8S0i00CBgzGB8A3Bm5rNQNoFe2Hrnl5c9w1BfE/z1/OH7w7SEA+k6/Txhs3BRQwkfDJPA6RvQgilE4Gku71xOLaJXNlEkdI2WrAiPN1UxrNdHCqIZRJgqbkbLulC4rEhT/zbEubDviA9C3y4oUNS1U6TqS9HsAqChy4agviMoi14Dp90ZrxaIV7M9ETlqQN1k3n+A5o3Q99YQFeD3GM4y0zGYqyKCFCtnHYbMYyuDUy5UmK8EGClQHlL3E0lGMtKnQToNULqv/t/kI/t/mIwAGdllpYeAWZVCHjQS+c8UoGT4aJiEQr3RqhIcL6zjtVjhtVoSFGHrC0QGLt7GI0oWhVbp+Om4mo8bCEdcQV4zSI5PecomMLfbPUemy+s+3duDTA22YfHo17rx8FIA0XFYaqGIVRemn3XPFKDXcMDIJQYM+QFmlwGVDuCdm2OrX5EGsRTZTJougUctKkONNt2s5LYixaThDMv4c+uxgG1r9wX5TwY1U10rpshpS7sGnB6SA6oFcVvJ11OAcq+PHR2L5+qNHQ4PNSBhHy+b0C6key9P16VBo8CKPAYUyo3Y2E5HhQ9EYhAGexkZVQPSKMTJqYDJRrnc2dcoxOX2RyFI01uJMKuR3pfHypGX2V4lbUrj9wciA+5IXPyOodVrCDSOTEAjHXWkGe4CyitzmwqAp+1oG4yvn3EDuNKMqIHplpQUMmsqeyfEa1b1aG68RFBUGzkrT0pVW7JZ+ozOYvmubrxvJGMtE5/RJd0h6O0i3yB6nf+SAYqMqRhouqC67FVaLJN33hAUUu/uOyTKsApJBJWeaGG3hIllbxxQqEcnYAlJnbRl1TgwpKwAABNNJ1w9p50oricdE+gMDK0ZGVevUho+GCRBFEcF48LVRFQ7WKDS4YqSlMmOxWFDgtKMrFB3Q1WRUBYRkhUUEUdMSDgGDqSmpsrbufX2r/PdUWVtGM/4ICQNk4GcEmfdqFXhUUhJXjNJxpfEYo9Tw0TABYSEGEtnhtBvr4cIqcv8vgxZ51Lrgp8dpixtGA7nSjLXQE9yKIpmH2npw6qAiTX43YUga41FNsrZ2Nvvx879/BQB4ZOY4OTg5VdZWj8HOkUAMEF8ayoysGGlQdiETxYjHGKXGWDORkwSRrTsVbwbftHbJQYF9FRvjDExhBrVAWESrBrKEQqcNxzCwIWlUt4nTlnAXHm7XzjAymppCsraUimDDYG+/WVtqFz9UC1LGIx1lRu2WIEoSwdf9P7uk9jxcMUoFHw0Dk0q2fuAf2+S/91VsjDMwhRkULWQRrQ0QT5oKm5GqHCuxWCxw223oiQiy21oLAgatM6Os/WXWTEWizHQGoxBioty8NRWaZqV54q60ARSjsBBDNH5tuGKUjLGeTpwkiGx94EQ3bn/1CwADy9ac9DB6jJHWsTxy490BFLaAwXr6pexafsSHwaUeAOqrslorf7RQGkYDuU21anZMmxJFkkFXMApvQTpJB1pkpUnHEYrGEIoKcPURXqFMLOGFgZMx1kzkJEFk61A0McEHkq056VEg1zEyqGEkx/Joc4sn0tkHcqUZK10/lSr7+w/24vcf7AWgviprNEOS4LBZUei0oTsswDFAgVGjVl922q3wOGwIRAT4ApE+DaOIEENY0K6cSrHLDosFEEVJzXIVpf5NMu5OuxV2A7Xn0QJuGJmAdOpVcDKDxAIYNV0/4Z7Q5oFHHvhvf3UU3x1V2aeKYjS3ibIFxG1LPsfBth7824RhuOE79QDUV2WNGpMFAKUFTnSHAwMGJxttTijxehwIRIR+44yULwtaKEZWqwVFLjs6g1H4AxFU9tEiJFFbyXjjrjbcMDIBpDpzndfN3WeUkBUjg7rSghoWeAQSwZsf7jqG1s5Q34aRwRQQZQuIqhIXDrb1oLzQoZkqa9SYLECKwTnSEUBHT7jf/Yxs/JV47Gj29x/PQzI17VYLnCq355GPy+2QDKN+Xpq7DerC1AKun5mArnhxx9NqS3gWGiVkxcigwddaL6jpvu0HDZquDwBFcn0Y7YxlLSuY08brGTidPRxVBABr5PalCYml6u8c9cgsTCdln8QDapEpZzSMNxM5J9EVV4xImj4ndwwfY6TRgkqCkwMKA7K/SsdGdptUF0vnMVCWFU2MrKaUepwA+l+clfPGiHMinb5kegSXp1PkkStGfcNHxAR0BYnlzy8nLYhr6OCJngG7g7OIVgtqppWOE640481VkokWjWmXrq9lV3baEDWlo6cf1SLe/Nph087NRJN0FCM9iiiSzLT+qnKTucUVo5Mx3tOJcxIkDoY0D+TkDnlYnOgO9xszwypaKUYkOPlf25rwxw+/AdB/yQij1uUBgNKCgRd62hg1Kw2AnKWVjpvJiK5CIL22IHrE1cm1jPpTjELGfUlRGz4iJoBkpfHqpfQwuvrmiy/e4TQ6f+cCCU4+1NYjb+uvZARZ6I1WlwcAvAWSa0grwygixBARJLedEQ2HtOJvDL44l2RyjhrGUMkuvjSCwnlW2slkpF0+/PDDOPfcc1FcXIyqqipcc8012LVrV9I+oihi4cKFqKurg8fjwcUXX4zt27cn7RMKhTBv3jxUVlaisLAQM2bMwOHDh5P2aW9vx5w5c+D1euH1ejFnzhx0dHQk7XPo0CFcddVVKCwsRGVlJe644w6Ew/1nQJiRrrhUW8QVo5xp9Qex7YgPjYqFftsRn/yn1R/U8ejSxx8PyA9p1A2+tJ/idkqMHTMTV4zS6EFFg0DE2PE33jTGq8fACiKQXiyPfI4auqyUVbn7gihGRsx4VJuMDKM1a9bgtttuw4YNG7Bq1SpEo1FMmTIF3d3d8j6//e1v8fjjj+Ppp5/Gpk2bUFNTg8mTJ6Ozs1PeZ/78+XjjjTewdOlSrF27Fl1dXZg+fToEIfEgmDVrFrZs2YIVK1ZgxYoV2LJlC+bMmSN/LggCrrzySnR3d2Pt2rVYunQpli1bhgULFuQyHoaE+LCLuK84Z5ZsPITpi9bi5pc+k7fd+/pWTF+0FtMXrcWSjYd0PLr0CcfbVmilzJTF1RSPw9pvyQgyVwMGLIOQcKVp8/JFjEib1QKnAQvwpaUYaVyhnTZpKUZ6ZKWlY7BFuGLUFxmZiitWrEj6/xdeeAFVVVXYvHkzLrzwQoiiiCeffBIPPPAAZs6cCQB46aWXUF1djVdffRU//elP4fP58Pzzz+OVV17B5ZdfDgBYvHgx6uvr8d5772Hq1KnYuXMnVqxYgQ0bNmDChAkAgOeeew4TJ07Erl27MGbMGKxcuRI7duxAY2Mj6urqAACPPfYYbrrpJjz44IMoKSnJeXCMAgm+LnKl99bO6RsSMxOLibj6D59ABHD/907DpFMrAbDdZkXZvoI8EA93BOQsMTXbVxDDKCyIGNTHGImiiEDcYOsyYLYfybLSypUmL6gOGyyWvvtwsQoxJH39jJeRFURA0Ug2LcNIQ1daWun68eMyeNiAGuT0GuLzSQ/c8vJyAMD+/fvR3NyMKVOmyPu4XC5cdNFFWLduHQBg8+bNiEQiSfvU1dWhoaFB3mf9+vXwer2yUQQA5513Hrxeb9I+DQ0NslEEAFOnTkUoFMLmzZtTHm8oFILf70/6Ywa4K40eVSVuNAz24sz6Uvmtq67UI8fNsByETdSu6YvWoj2+GD2z+htN1C6yCAoxsc86P6FoIt6pr/5NLEOCiQMRQS6gqSbEBeM2uNGQnppizGcXieXp/xy1dxeWpFFzq5vHGPVJ1rNRFEXcfffduOCCC9DQ0AAAaG5uBgBUV1cn7VtdXY2DBw/K+zidTpSVlZ20D/n3zc3NqKqqOuk3q6qqkvbp/TtlZWVwOp3yPr15+OGH8Zvf/CbTU2WeLu5KU4Vitx2+YLTfjBOW0FPtcjtsct+ojp5wUhNRomQpF49vjnXLAe5qN2KlRYnbDpvVIhl/gYjqbsqggTPSgITC1p/RYOQsRUChGPVjgOiiGKUTfM0Voz7JekRuv/12fPXVV1i7du1Jn/WWfUVRHFAK7r1Pqv2z2UfJfffdh7vvvlv+f7/fj/r6+n6PywgkDCPuSqNJRZELhzuCMIoXg2SI+YMRkBKE44eVada+oqzAgYBPQHtPBMMqEttT1Tq6/42+ax2xisVigdfjQFt3GB2BiOrGnNFT2YnREIgIfXZ5N3LBTyCRFs+cYuQZuPAkV4z6JivDaN68eXjzzTfx0UcfYciQIfL2mpoaAJKaU1tbK29vbW2V1Z2amhqEw2G0t7cnqUatra2YNGmSvE9LS8tJv3vs2LGk79m4cWPS5+3t7YhEIicpSQSXywWXi90YkWzp4qXdVaG6xA3Ap2mlYxoo3xK1dFmVFjhx1BdEe6/gZKJk7WnpxF1/+xJA/7WOWKaUGEYaxBnpEbRLk2J3osu7LxBBVXHfhpFRz5EYf+FoDMGIkFJF1Cf4Op0Cj8Z2Y6pJRjFGoiji9ttvx+uvv44PPvgAI0aMSPp8xIgRqKmpwapVq+Rt4XAYa9askY2e8ePHw+FwJO3T1NSEbdu2yftMnDgRPp8Pn376qbzPxo0b4fP5kvbZtm0bmpqa5H1WrlwJl8uF8ePHZ3JahiYcjSEcj90o5ooRVcoLJVdAe7exSkCQt9cCp01To6OsMHXWFonbqlQcC4nZYj1uqzckzqi38acGQYNnbFmtlgFdOgk1xZiLc6HTDmtcUe7rHPUopEiUrEBEQKSPWmZyRW6Dzi81yehK3XbbbXj11Vfxz3/+E8XFxXIsj9frhcfjgcViwfz58/HQQw9h1KhRGDVqFB566CEUFBRg1qxZ8r4333wzFixYgIqKCpSXl+Oee+7BuHHj5Cy1008/HVdccQXmzp2LZ599FgBwyy23YPr06RgzZgwAYMqUKRg7dizmzJmDRx99FG1tbbjnnnswd+7cvMpIU/by4ooRXcrihlGbRunZtCBviXWlHk2NjtICYkimXiC0rBitFqSWUX+ZVrRo9kk1s6wwiC83BV6PA75ApM9rb3R3odVqQYnHgY6eCPzB1O7VQER7RV/ZN7MzGJVf8pKPS9D8uIxCRobRM888AwC4+OKLk7a/8MILuOmmmwAAv/jFLxAIBHDrrbeivb0dEyZMwMqVK1FcXCzv/8QTT8But+O6665DIBDAZZddhhdffBE2W+ICLVmyBHfccYecvTZjxgw8/fTT8uc2mw3Lly/HrbfeivPPPx8ejwezZs3C7373u4wGwOgQN5rbYYXdgLVOWKa8wJiKEYkrKNE4S7FsgDo/RMk6pbLQUO4zJcT46wioPyeOdUmlF4wS45aKgTLTjJ6uD0huq46eCHx9uK3kQooaGn92mxWFThu6wwL8gUhKw4i3BOmbjEZEFAeOtbBYLFi4cCEWLlzY5z5utxuLFi3CokWL+tynvLwcixcv7ve3hg4dirfffnvAYzIzPPBaPYhi1G4wpYMsQiUebecEqWXU13iR4zpneJmh3GdK0mmMSouQgdunEAbqLyfHuRg4M2qgWkbE+NO6zVCJxyEZRn0EYCdaghh37NWCj4jB4an66lGmYTwJTcgD2quxYUR+r6/x8ul0XDQpkxUjdQwjZZHOw+0BANI9rkWRTjUYqDK03GDVwMbfQA1bSYVprWPFStwONPmCKQOwYzFRYZQad+zVghtGBkeues2LO1JHjjEynCtNmhMk8FUriNHQ1yJIXGzEHWVE0qnmnAupShus++YEpi+SyqIYpbQBoXQAw8gXnxN9BQgbgYHchaRekNbKDDHYXv30IEZXFyUZ1Mo+fFwxOhk+IgZHTtXnk5s6ho0xkl1pGscYFaanGGnt4qNJqcoqIiltAEi1nr467MP0M2vxs4tOBWCs0gbAwEYDaXKqRSVxtRg4806fOCpyXP/a2oxbLx6ZZBiRGkYWixSfykmGr6YGhxhGxVwxog5RjLrDQp81SlhENow0VozSzUorNbBhpHaMESnSCSSy0UZXF2lWpJM2AxlGoajx46iIof/B16247pz6JAMkFhNldUZzV1o/95lc9dqgffjUhq+mBqdbjjHil5I2yhYQHT0R1HiN8fAmsQ5ax/LI8TcmjjEqHcBdSBNfUB8Dlyay61ExXso4KpLJdUSjZsdqQObz54c60NoZ0t1lRcY3Ek38NhlbQBpfMwS9qwkfFYNDpGitMx7yAYvFgrICJ453hdDWHUaN1xgPa/2y0qTf6w4LCEdjcNqTJXpyXGSxNCKlsmKkvnuVvPQMryxU/bfUwptivFLFUS36YC8WfbAXgPHiqPori0FcVgDgD4ThcXpUP55U43vv68kteL47SuqfyNuBpIavpgZHVoy4K00VygsdON4VMlRmGslC0VppKHE7YLUAMVFaCHu/9ZtDMerf+KOFKIryeI2sKlLlN7QgVVYaiaPyBSKY/WeprdOD1zTgrPpSAMaJo0rVHLm3MqNUjI51hVHtVd8wIuP7zrZm/OFDydjs3YJnZ3MnACkUo9UfNJRCpwV8NTU4cro+D75WBeI6MVJmml6uNKtVarLa3hNBe09yFeBwNCbL96TruhEpcTuS+n8NUmkR7wkLCMVb/aQqzmcUyLU+2hGQF2DyZ3dLp7zfWfWlhoujSkeZmXpGjdaHJY9viz8obyPtdwibD7YDAI53hU9y/3G4YWR4OrlipCrlA8TNsIhPp6w0QIozkgyj5PEix2SxGDtRgBh/HT0RdPSEVTOMiCHuslsN2y4DSPSWC0RiaOmlTByLxxkZFaLMHDrRjVtf/QJAQpmRrp+IrUc65P17q0lqGyNVxX1/f3fYuFmAWmDcJxQHQMKVxmOM1CFRy8gY1a8jQkKZ0SNot7SPtiC+eAuNErcDVquxs2BKiWGkYgA2MSzLC52GzhpSZiASBYxwPN7yZEipxzDuMyVEmakvL5C3jYpnED6xaveAapLacVTVJYkxrYg/x4j7b29rQq3T2mAzAnw1NTikwGMxN4xUoXyA2jysQYLxAX2Umb7agpghvojgLXACJ3rw8roDGFZeoMpCQhSjMoMWwyQLsCiKsFkAQQQ2HWiT0/Kril2yYvTtYcZtEQNIwdcOmwURQZRLVRA16R9bjuDPH+8HcHKcj9pUFLnkmD9b/GUkHfefkQLf1YKvpgani7vSVKXMYDFGxAApctl1aSos1zLqZUjKNYwMnJFGICrIW1814acXnarKoq5UjIxIqgX4f1bswv+s2AVAWoCD8XTyyiLjqUVKLBYLqordONIRkPuJEjXpn1uOyPv1jvNRG5vVgsoiF1o7Q2jxS3FExGD7w4d78c62ZgDaG2xGgK+mBqeLu9JUpbww9ULPKonijvrMh7I+moaaSTHSwrgjrtsygxpGygrety35HAfbejB7wlD88DtDAUgLMDGSKouNeY5K6kolwygsJDdab/brG0dVVSIZRq2dQQBe2WBTVhrX2mAzAnw1NThy5WtuGKmC0fqlkYw0vdpuEKNh7Z5jaPWPkNUUYigZ2TAi7qFYLLH4qRWfQdrQlBtUYVNW8K4vL8DBth54nLakBfhYPMZokMEVIwDyuSozwQCg2Sc1Ap7WUKOLGlNd7MY2+NHSy0A70hHQ/FiMBF9NDYwoijz4WmWM1i9N735kxJW2o6kzKQ3YDMUdtYzPaIsrlEZVjJRUFEnncKIreXE+Ho8xqjSB+6Y6ngHW0tnLMIobSj/57ghd4qjIb7YqjksURRxplwyjOecN4+6zFPDV1MCEojFE4tItjzFSBznGyDCuNH2KOxL6ChY2gyuNuIc++LoFj6+SDCS14jNkxcgEhtHwCilrqyuUnCJ+3ESKEckAa1UoM6IoosUXin+uT3A5mZNKxcgfjMrp+vd/73TNe7gZAb6aGhiiFgHa9eHJN0jH+GAkhkBYYP4holdxR+JmUqbpK91MxMVg5OKOxD0UiAhA3DBSKz7jhMGz0pSMqi4GkFzCIRYT5XNUqxaUllSncKW1dYcRFmKwWPqvKaTFcR1TKEZELSovdDL/PNMLvpoaGBJfVOC0yemYHLoUueywW4FoDNjT2okzh5TqfUj9oldxx4HcTEQ1MLJiRBiqqFsTFWL97Jk9RDGqMIFiVBNfnJt8icW5vScMIR6rZQZVrKqEKDOJcyTnW1HoUq11zIDHlUIxOhqPL6orNW6JBLXhhpGBkVP1eXyRalgsFhS7pTYX+451M28YJbLStDVAiJupKxTFDX/aAABYOOMMnDOsDABw3+tfAUhUQjYyg4pcct2amDjw/tnQbqIYI9J8udUvBa5brRY58Lq80AmHDmUlaEOUGaUrjRhJtTo2n65OEWN0NB4QPrhU/b5tRoWvqAaGFHcMR2O8EaCKkP5fnUH2q1/743NCa2VGmYVU7LajMxhFRaFTdjORmAYzKEZWqwX15QXYd6w7qUkoLWIxUS6QaQo1pdgNiwUICzG09YRRWeTC8U7J8KssMv75AQkDpDMURXcoikKXXVaM9Iovkn5bUoyOdYYgxETYrBbZlVbHDaM+Mb6pnscQxagjEEGrwfsOsUarP4htR3zYdsQHa7wlA/n/bUd8aO2VlssKemelAYmFoFnhOvGbICtNSX2Z5E5rbOuh/t2dwajsZjLDeDntVlQUSgs0mRMk8NroxR0JRS47CuPxOuRZzIJipKx+TbICSao+V4z6hhtGBqZLEXzNocuSjYcwfdFaTF+0FvuOdwMAXvvssLxtycZDOh9havQu8AgAw+QsJOlYRFE0RR0jJfXl0qLS2E7fMCIZkEUuO1x2cwTHEuOAGEakHYgZAq8JvQOwiWJUo6NhRKpfAwmD7Sg3jAaEu9IMCMkA2tXCGwGqhbJy758/3od/bDmK0dVFePy6bwFgt3S+3gUeAWB0dTHe39kqG0M9YQFRooAYOCtNSUIxol8oT+6TVmgOIxKQjIOtR3xo8ptTMQKkAOx9x7tlw4j8t0bnZzGpft3iD6JhsFdWjLgrrW+4YWRAeCNA9VHGzFwwqhL/2HIUrf4Q86Xz/QzUCyJZW4fibibShd5ps8LtMIdITc5RDcUoUfXaHEYkkDAOWohiZELDqHcANguKEZCoft3aGZLiUePK0eAybhj1BTeMDAhRMx5cvhPr950AwBsBqsnwikIAJJYrqFtNkoEQRTFR4FFHw4ioKcQw8hE3WoEDFos5ykrUl6sXY5RQjExkGHmTU/bzwZXWwohhpCwl0OIPQhRJ3Jd55hdtuGFkQIiaoSw/zxsBqsfQ8gKUFUiZaTuO+lE1hk3DKBSNIRyvqxNSIVsqXYiacrg9gFhMREdAWuijgnmyJ4nxd7wrjJ5wFAUUC6ySGCMzKUZyjJFfcuMc7zJXVhqgqBnUGUJXKIrOeAyo7q60+IvceztbMDpebHNwqcc0LylqYA5dOw8JRQUcPEH/bZVzMlUlblwwahAAYEeTX+ej6RuSkQYkV0XXmtpSN2xWC0LRGI51hWT3XnuPebInvQUOFMcD3A+3040zajejYtQrU5GoKWYqTEsUo88PtmF7POaz2G3XvY8lOa5tR/z44lA7AHO0YVETbhgZlP3HuyHERBQ6bbjzspHcfaYyY2tLAAA7jrJrGPkVhpGeb4MOm1WuqnuorUcOwjYbaqXsk+BYvaolq4HSlSbERLmApSiqVCFTB4gBcqQjiM0HJQOkkgHjVrk2ECPeq3FlfKPBR8eg7G7pAgCMqSnGXZPH6Hw05mdsHbuGEclS/OJQh7xN7yzF+rICNLYFsG7vcTQqFBW9j4sm9eUe7Gjy4+X1BzBusJfauZAaWTYTuTqIYdQTFvDFoXYQc0ivZsdqQIopAkBjm1Tio1RHdyh5LvSEE271T/YeByApdWZxa6sBN4wMyt54qj7xGXPUhShG+45347crvsZNk4Yz81BhMUtxaHkB1n1zAk+8x9Zx0YTEUq3ZfRytnSFq80EuuWAio6HAaYfHYUUgEsM/vjgib/+6uRP2eEsQoxrKxAAJKuL63tt5DADgsOlngKR6LpDK+Cu2t6CswInZ5w0z7LirCTeMDApRjEZWFel8JPnBoGIXqoqleiB/XP0NvjeulpmHCclS/MX/+xI7miSDWe8sRZK1Nay8AAfbemC3WRAVRN2Piyb1imayuUIWVyARmHyiOyQrbGZYvJw2yTBarCiOagZDOZUBQsoRfHqgHU+s2q2LAUKeC0s2HsRfP2086fO/bmrEXzc1Gnbc1YQbRgZldytXjLRmbF0JWndJb4Jt3WE8sWo3pp5RjXe3t2D2hKG6LVxVJW4Uue3Y09olb9M7S5GoKQfj8TfnjajA2r3HdT8uGhAjRlB0kF239ziWbDyIaQ21qCxyZjwnUi2uz360D89+tA+AcY0GpcFXUeSEL0gaX9vQFRJw//dOw6RTKwEY11Bm1QAh2ct3XT4aE0ZUYP5rWzDnvGF4ZcNBPDxzHMaZ5AVFDbhhZECUGWncMFIf8nBXZnKs/+Y4nlmzD3arBU+9v0eukr1k4yFdjKXPDrQjIoioLHLKioOe9FZTLhxVibXx+Aajk8qIeeidrwEAf/20ET88tx5/3dSI8cPK0p4PZHH922eNeHn9QQD6q340SDVWANAVktxO+49145YLT9X6sKiSygCZd+lILPpgLxPXsKrELXsWxg8rwysbDmKcCV5Q1IQbRgbks4PtckaaMuCPow6pHu7PrJHe5B9btVve1toZwlPv78GIykI89f4eeWGcPWGo/D3KRZJso2FAkUKf3xlRgVFVRbovpEMVhpHbbsUV42rQHRZ0Py4aKNvF/P79PVi5o0X+7D+uPB2jqorw102NaOsOJ82HVMazcj4MKnLin1sS8TdmUNeUY7Vpfxt+8/YO/OfVZ6DE7cD817Zg2rganY+QHkoD5NRB0n9ZuYZVxS7cedkolJuozYyacMNIJVr9wT4fgEDfD8fen6XaRor41ZfzIl1aQB7ubd1hLNl4EO9ubzlpnwfe2IpvDy0DAPjjBQ3JwkgWhlSLpNKAynaOTD2jGq9/fhgAcOlpVfg/44eoOyD9QNQ1URThslsRisZwem0J/IGofM5GhygErf4gvjeuNskw+u/lO1EUr1vzzrYmAMnp/L2NZ+V8+PJwB3yBqDxuZkDZWofw7aFl8kJ9Wk2JTkemDqwaIFUlbtw1eTRa/UHcedkoU7ygqAk3jAAg2g1E6Xaxbu3olB585fak/04eIz0I0v0s1bYpp1cAAIaWuaVj56hKVQFQVWDHE+83pjSKAODLwz58eVgKlP3v5TsBAE+/vwsA8ObnB9AwOO7yjMULHAqJFPa2zs6c5khNkQUt8f5ME4d5dJ0TS9bvx1MfHkza9kVjB6YvWgsAuPOSYbjrshF6HBp1Up0rAHTFi2uSuUJUxQde/xJDyqQF6dCxDmlnxXx4d6ukFk0cUYqzhhSjqkAw1/1N5rwQQFWBHXddMhiAuc6xqgC465LBaO0M4c5LhjF3DcnxmWLcVTx+bhgBwOt1AL0EE7RGyrDVfy6AO7Djw/8C8H/QuOZeADeia8VkFFiDAJ4E1v8YwM8T/115Qfwbnkq5jXzHV3t2AqiC4+jr2PbibABAlaMNVY52eifBOYnZkTKMGHIm5h/+Oa4vXYHXOq7AaNcB7A4NT9ovLEhBuXuPSwvBnz45LH/2/y37FEAxbn/uH3BZIwBOwV/eegPAaVi6/K8AvoU3/3Yfimw9AH6E/Wv+A8BsdH5yO4DbIKz8LqwQoZwjWz9+EsD3UGM/hsErK9UdhAGYHSnD5JHlAICPOs/Gb1tuwiODf48GzzcAgKrmNuBv5pinsyNlGD98GN7xnY9B9jb8/thsjPdsx+bAGSn3//JIJ748IiVNPP7BAQDAL/7+BQA3bnp2FU4IJQDsGNH2F0wWP0RrIwAT3ddVkTLcWTUNVR/OAUxyTn1RBeAuAHhH5wMxMyo2frCIZio9miF+vx9erxe+54ASCoZRa6QMrZFy/L3tUrzUdnU/e8YAWGFHBFE44EIQIbhRZJGyirrEIpRaO9ARK8UQ+1HYLQIOROr7/e07q17FXTWv5n4SnH5pjZRhyYlpGF+wAz868N/4Te0f8eumW/Gb2j/iWLQMTx/7oYZHIwBIKJ1j3Xtxb82LKLd3MmEob+s5FdP3PoW3R96JhoJvdD0WtSHn+vLwX6EtWoL5h3+O60pX4G8dV2Co4ygOReqy+l5+X3M4qfH3AN65gM/nQ0kJXZcsV4wAYOZRgMLALnk/tbR+MlJBsygkP3QIkg++S0zUJOqIlQIADkf7f6D+8JwazP7OYFQVTwSK/5T5QXMygrwJbjvaCfxxM7wXLAL+vhPjv/88AODpP27GgsuH47H3DuDHEwfjL+uP4McTB8MXiGLZlhacUVuI7U3dqCpyoLUr11YZye7fHcGR+NGB/wbAiMvqaCewdzMwZS1QZ/Lsyfi5ln/vXygHgD9uxqTJd+Fvf9+Jm6deiF+/vRe/mT4Sx7vCWLT6EC4eVYbVe9oxrq4QW4924/xTSuFyWPHBrjbcf8UpmHSKFK/G72sOpw/8fmBudi8cA8ENIwCwF0p/cmT2xJGY3FCPtu4wNu1vw6IP9+KSMYPw4a5jOH9kOT7Z24Yrz6xBJCpi5Y4WnF1fii8aO3Dm4BJ8dcSPiaeWAyKwfl8bzqgrxvajnTitphhCTMSe1i6cXlOMnc2duO6cIfjbZ4fx5PXfwqRTKwxf+M2IVJXacOdlozC6tkIKZiwtleu11FeUAgDOHDoIWH8EM8+RDJRlW1ow98JRmP/aFvzuurPR1h3G/Ne24Ppzh+C1TYcxraEG72xrxoyzagEAb37ZhPNHVuCTvScw6dRyrPumDdPOqEYMUvzKOcNL8dmBDnmOzbt0JM4dXobyQqkYJew6d/WOj1FVaanux6I2SecKqe5QebH0ouMtjKdKj5AysBatPoRrvj0Mq/e04+bvSvPhvisbAAAf7FqLSaPqmMhk4nCYxi4MvE+WmKdLIQNUlbjRMNiLC0cPwtQG6SF49bcGAwCuHS9lE/37RSNxx2WjAAA3ThoOAPjxBacAAB743lg8cOVYAMDc70q1PX537Vl44vpvAQB+epG0jRREG1lVxI0inSBZHmPrvLhr8mgp+yaekTK6umjAzJTyQqec2jvxFOl6Tj1DmjO3XHiqXNvl2vGSC/W6c6T5c9ulozDvUmn+/NuE4QASc2zqGTW4cHQVGij27coFMkYsHIvaKM+V/P20mpKk+cAzgTgcY8AVIwNSXujkD1oGIQsiAIyt856UGptqkWQxtZdDh97zgaCcB6nmA7+vORx94cHXXq8qwVtq1jHSs/0Ehz6950o2dYz4vOBwOPmEmus3N4xUGlgOh8PhcDjqoOb6zWOMOBwOh8PhcOJww4jD4XA4HA4nDjeMOBwOh8PhcOJww4jD4XA4HA4nDjeMOBwOh8PhcOJww4jD4XA4HA4nDjeMOBwOh8PhcOJww4jD4XA4HA4nDjeMOBwOh8PhcOJww4jD4XA4HA4nTl43kSXdUPx+v85HwuFwOBwOJ13Iuq1GV7O8Now6OzsBAPX19TofCYfD4XA4nEzp7OyE1+ul+p153UQ2Fovh6NGjKC4uhsViofrdfr8f9fX1aGxsNH2DWn6u5oSfqznh52pO8vFcd+zYgTFjxsBqpRsVlNeKkdVqxZAhQ1T9jZKSEtNPUgI/V3PCz9Wc8HM1J/l0roMHD6ZuFAE8+JrD4XA4HA5HhhtGHA6Hw+FwOHG4YaQSLpcLv/71r+FyufQ+FNXh52pO+LmaE36u5oSfKz3yOviaw+FwOBwORwlXjDgcDofD4XDicMOIw+FwOBwOJw43jDgcDofD4XDicMOIw+FwOBwOJw43jFTgj3/8I0aMGAG3243x48fj448/1vuQcubhhx/Gueeei+LiYlRVVeGaa67Brl27kva56aabYLFYkv6cd955Oh1x9ixcuPCk86ipqZE/F0URCxcuRF1dHTweDy6++GJs375dxyPOnuHDh590rhaLBbfddhsAY1/Tjz76CFdddRXq6upgsVjwj3/8I+nzdK5jKBTCvHnzUFlZicLCQsyYMQOHDx/W8CzSo79zjUQi+OUvf4lx48ahsLAQdXV1+NGPfoSjR48mfcfFF1980rW+4YYbND6TgRnouqYzZ81wXQGkvHctFgseffRReR8jXNd01hct71duGFHmtddew/z58/HAAw/giy++wHe/+11MmzYNhw4d0vvQcmLNmjW47bbbsGHDBqxatQrRaBRTpkxBd3d30n5XXHEFmpqa5D//+te/dDri3DjjjDOSzmPr1q3yZ7/97W/x+OOP4+mnn8amTZtQU1ODyZMny733jMSmTZuSznPVqlUAgGuvvVbex6jXtLu7G2eddRaefvrplJ+ncx3nz5+PN954A0uXLsXatWvR1dWF6dOnQxAErU4jLfo7156eHnz++ef41a9+hc8//xyvv/46du/ejRkzZpy079y5c5Ou9bPPPqvF4WfEQNcVGHjOmuG6Akg6x6amJvzlL3+BxWLBD37wg6T9WL+u6awvmt6vIocq3/nOd8Sf/exnSdtOO+008d5779XpiNShtbVVBCCuWbNG3nbjjTeKV199tX4HRYlf//rX4llnnZXys1gsJtbU1IiPPPKIvC0YDIper1f83//9X42OUD3uvPNO8dRTTxVjsZgoiua5pgDEN954Q/7/dK5jR0eH6HA4xKVLl8r7HDlyRLRareKKFSs0O/ZM6X2uqfj0009FAOLBgwflbRdddJF45513qntwlEl1rgPNWTNf16uvvlq89NJLk7YZ8br2Xl+0vl+5YkSRcDiMzZs3Y8qUKUnbp0yZgnXr1ul0VOrg8/kAAOXl5UnbV69ejaqqKowePRpz585Fa2urHoeXM3v27EFdXR1GjBiBG264Afv27QMA7N+/H83NzUnX2OVy4aKLLjL8NQ6Hw1i8eDF+/OMfJzVVNss1VZLOddy8eTMikUjSPnV1dWhoaDD8tfb5fLBYLCgtLU3avmTJElRWVuKMM87APffcY0gVFOh/zpr1ura0tGD58uW4+eabT/rMaNe19/qi9f2a101kaXP8+HEIgoDq6uqk7dXV1WhubtbpqOgjiiLuvvtuXHDBBWhoaJC3T5s2Dddeey2GDRuG/fv341e/+hUuvfRSbN682VDVWCdMmICXX34Zo0ePRktLC/77v/8bkyZNwvbt2+XrmOoaHzx4UI/DpcY//vEPdHR04KabbpK3meWa9iad69jc3Ayn04mysrKT9jHy/RwMBnHvvfdi1qxZSc1GZ8+ejREjRqCmpgbbtm3Dfffdhy+//FJ2rxqFgeasWa/rSy+9hOLiYsycOTNpu9Gua6r1Rev7lRtGKqB82wakC917m5G5/fbb8dVXX2Ht2rVJ26+//nr57w0NDTjnnHMwbNgwLF++/KSblWWmTZsm/33cuHGYOHEiTj31VLz00ktyEKcZr/Hzzz+PadOmoa6uTt5mlmvaF9lcRyNf60gkghtuuAGxWAx//OMfkz6bO3eu/PeGhgaMGjUK55xzDj7//HN8+9vf1vpQsybbOWvk6woAf/nLXzB79my43e6k7Ua7rn2tL4B29yt3pVGksrISNpvtJOu0tbX1JEvXqMybNw9vvvkmPvzwQwwZMqTffWtrazFs2DDs2bNHo6NTh8LCQowbNw579uyRs9PMdo0PHjyI9957Dz/5yU/63c8s1zSd61hTU4NwOIz29vY+9zESkUgE1113Hfbv349Vq1YlqUWp+Pa3vw2Hw2H4a917zprtugLAxx9/jF27dg14/wJsX9e+1het71duGFHE6XRi/PjxJ0mUq1atwqRJk3Q6KjqIoojbb78dr7/+Oj744AOMGDFiwH9z4sQJNDY2ora2VoMjVI9QKISdO3eitrZWlqSV1zgcDmPNmjWGvsYvvPACqqqqcOWVV/a7n1muaTrXcfz48XA4HEn7NDU1Ydu2bYa71sQo2rNnD9577z1UVFQM+G+2b9+OSCRi+Gvde86a6boSnn/+eYwfPx5nnXXWgPuyeF0HWl80v1+zjRrnpGbp0qWiw+EQn3/+eXHHjh3i/PnzxcLCQvHAgQN6H1pO/Pu//7vo9XrF1atXi01NTfKfnp4eURRFsbOzU1ywYIG4bt06cf/+/eKHH34oTpw4URw8eLDo9/t1PvrMWLBggbh69Wpx37594oYNG8Tp06eLxcXF8jV85JFHRK/XK77++uvi1q1bxR/+8IdibW2t4c6TIAiCOHToUPGXv/xl0najX9POzk7xiy++EL/44gsRgPj444+LX3zxhZyJlc51/NnPfiYOGTJEfO+998TPP/9cvPTSS8WzzjpLjEajep1WSvo710gkIs6YMUMcMmSIuGXLlqT7NxQKiaIoinv37hV/85vfiJs2bRL3798vLl++XDzttNPEs88+21Dnmu6cNcN1Jfh8PrGgoEB85plnTvr3RrmuA60voqjt/coNIxX4wx/+IA4bNkx0Op3it7/97aSUdqMCIOWfF154QRRFUezp6RGnTJkiDho0SHQ4HOLQoUPFG2+8UTx06JC+B54F119/vVhbWys6HA6xrq5OnDlzprh9+3b581gsJv76178Wa2pqRJfLJV544YXi1q1bdTzi3Hj33XdFAOKuXbuSthv9mn744Ycp5+yNN94oimJ61zEQCIi33367WF5eLno8HnH69OlMnn9/57p///4+798PP/xQFEVRPHTokHjhhReK5eXlotPpFE899VTxjjvuEE+cOKHviaWgv3NNd86a4boSnn32WdHj8YgdHR0n/XujXNeB1hdR1PZ+tcQPisPhcDgcDifv4TFGHA6Hw+FwOHG4YcThcDgcDocThxtGHA6Hw+FwOHG4YcThcDgcDocThxtGHA6Hw+FwOHG4YcThcDgcDocThxtGHA6Hw+FwOHG4YcThcDgcDocThxtGHA6Hw+FwOHG4YcThcDgcDocThxtGHA6Hw+FwOHG4YcThcDgcDocT5/8HpywAUq7VhJYAAAAASUVORK5CYII=", + "text/plain": [ + "<Figure size 640x480 with 1 Axes>" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "fig, ax = plt.subplots()\n", + "ax.axhline(top, color='orange')\n", + "ax.axhline(bottom, color='orange')\n", + "ax.axhline(middle, color='orange')\n", + "ax.plot(d, '-+')\n", + "\n", + "thr_top = middle + (top - bottom) * 0.1\n", + "thr_bot = middle - (top - bottom) * 0.1\n", + "print(f'{thr_bot=} {thr_top=}')\n", + "\n", + "state = -1\n", + "run_length = 0\n", + "indices = []\n", + "for i in range(len(d)):\n", + " old_run_length = run_length\n", + " if d[i] < thr_bot:\n", + " next_state = -1\n", + " run_length = 1\n", + " print('-', end='')\n", + " elif d[i] > thr_top:\n", + " next_state = 1\n", + " run_length = 1\n", + " print('+', end='')\n", + " else:\n", + " next_state = state\n", + " run_length += 1\n", + " print('0', end='')\n", + "\n", + " if next_state != state:\n", + " color = 'red' if state == 1 else 'blue'\n", + " #ax.axvline(i - run_length/2, color=color)\n", + " slope = d[i-1] - d[i-1-old_run_length]\n", + " intersect_x = i-1 - (d[i-1] - middle) / slope\n", + " indices.append(intersect_x)\n", + " print()\n", + " ax.plot(intersect_x, middle, 'o', color=color)\n", + " state = next_state\n", + "\n", + "indices = np.array(indices)\n", + "indices = indices[1:] - indices[:-1]" + ] + }, + { + "cell_type": "code", + "execution_count": 21, + "id": "6834328b-6324-4c12-b3a5-eae619186bd9", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "(array([1., 4., 1., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,\n", + " 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,\n", + " 0., 0., 0., 0., 0., 0., 0., 0., 0., 4., 0., 0., 0., 0., 0., 0., 0.,\n", + " 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,\n", + " 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,\n", + " 1., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,\n", + " 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.,\n", + " 0., 0., 0., 0., 0., 0., 0., 0., 1.]),\n", + " array([ 7.77950663, 7.96952698, 8.15954733, 8.34956768, 8.53958803,\n", + " 8.72960838, 8.91962873, 9.10964909, 9.29966944, 9.48968979,\n", + " 9.67971014, 9.86973049, 10.05975084, 10.24977119, 10.43979154,\n", + " 10.62981189, 10.81983225, 11.0098526 , 11.19987295, 11.3898933 ,\n", + " 11.57991365, 11.769934 , 11.95995435, 12.1499747 , 12.33999506,\n", + " 12.53001541, 12.72003576, 12.91005611, 13.10007646, 13.29009681,\n", + " 13.48011716, 13.67013751, 13.86015787, 14.05017822, 14.24019857,\n", + " 14.43021892, 14.62023927, 14.81025962, 15.00027997, 15.19030032,\n", + " 15.38032067, 15.57034103, 15.76036138, 15.95038173, 16.14040208,\n", + " 16.33042243, 16.52044278, 16.71046313, 16.90048348, 17.09050384,\n", + " 17.28052419, 17.47054454, 17.66056489, 17.85058524, 18.04060559,\n", + " 18.23062594, 18.42064629, 18.61066664, 18.800687 , 18.99070735,\n", + " 19.1807277 , 19.37074805, 19.5607684 , 19.75078875, 19.9408091 ,\n", + " 20.13082945, 20.32084981, 20.51087016, 20.70089051, 20.89091086,\n", + " 21.08093121, 21.27095156, 21.46097191, 21.65099226, 21.84101262,\n", + " 22.03103297, 22.22105332, 22.41107367, 22.60109402, 22.79111437,\n", + " 22.98113472, 23.17115507, 23.36117542, 23.55119578, 23.74121613,\n", + " 23.93123648, 24.12125683, 24.31127718, 24.50129753, 24.69131788,\n", + " 24.88133823, 25.07135859, 25.26137894, 25.45139929, 25.64141964,\n", + " 25.83143999, 26.02146034, 26.21148069, 26.40150104, 26.59152139,\n", + " 26.78154175, 26.9715621 , 27.16158245, 27.3516028 , 27.54162315,\n", + " 27.7316435 , 27.92166385, 28.1116842 , 28.30170456, 28.49172491,\n", + " 28.68174526, 28.87176561, 29.06178596, 29.25180631, 29.44182666,\n", + " 29.63184701, 29.82186737, 30.01188772, 30.20190807, 30.39192842,\n", + " 30.58194877, 30.77196912, 30.96198947, 31.15200982, 31.34203017,\n", + " 31.53205053, 31.72207088, 31.91209123, 32.10211158]),\n", + " <BarContainer object of 128 artists>)" + ] + }, + "execution_count": 21, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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m5o47LxAIKDU1NWIsNTVVIyMjGhgYGPOY6upqJScnhze32z3ZZQIAgFvcpGNk48aN+uKLL/T+++9fc67D4YjYtyxrzPGrKisrNTg4GN56e3snu0wAAHCLs3XPyFWbNm3S4cOH1dbWpvnz5084Ny0tTYFAIGKsv79fcXFxmjt37pjHOJ1OOZ3OySwNAABEGVvvjFiWpY0bN+rgwYP65JNPlJmZec1jPB6PmpqaIsaOHTum/Px8zZw5095qAQBAzLEVI+Xl5dq/f7/ee+89JSYmKhAIKBAI6L///W94TmVlpdavXx/eLysr04ULF+T1enX27Fnt2bNHu3fvVkVFxdS9CgAAELVsxUhdXZ0GBwe1evVquVyu8PbBBx+E5/j9fvX09IT3MzMz1djYqJaWFt1777169dVXtWPHDn6sFwAASLJ5z8jVG08n0tDQMGps1apVOn36tJ2nAgAAtwm+mwYAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhlO0ba2tq0du1apaeny+Fw6MMPP5xwfktLixwOx6jt3Llzk10zAACIIXF2DxgaGtLSpUv11FNPqaSk5LqP6+rqUlJSUnh/3rx5dp8aAADEINsxUlRUpKKiIttPlJKSotmzZ9s+DgAAxLabds/IsmXL5HK5VFBQoObm5gnnhkIhBYPBiA0AAMSmaY8Rl8ulXbt2yefz6eDBg8rKylJBQYHa2trGPaa6ulrJycnhze12T/cyAQCAIbY/prErKytLWVlZ4X2Px6Pe3l7V1NRo5cqVYx5TWVkpr9cb3g8GgwQJAAAxysiP9i5fvlznz58f93Gn06mkpKSIDQAAxCYjMdLR0SGXy2XiqQEAwC3G9sc0ly5d0ldffRXe7+7uVmdnp+bMmaOMjAxVVlaqr69P+/btkyTV1tZq4cKFysnJ0fDwsPbv3y+fzyefzzd1rwIAAEQt2zHS3t6uBx98MLx/9d6O0tJSNTQ0yO/3q6enJ/z48PCwKioq1NfXp4SEBOXk5OjIkSMqLi6eguUDAIBoZztGVq9eLcuyxn28oaEhYn/btm3atm2b7YUBAIDbA99NAwAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjLIdI21tbVq7dq3S09PlcDj04YcfXvOY1tZW5eXlKT4+XosWLVJ9ff1k1goAAGKQ7RgZGhrS0qVLtXPnzuua393dreLiYq1YsUIdHR2qqqrS5s2b5fP5bC8WAADEnji7BxQVFamoqOi659fX1ysjI0O1tbWSpOzsbLW3t6umpkYlJSV2nx4AAMSYab9n5Pjx4yosLIwYW7Nmjdrb23X58uUxjwmFQgoGgxEbAACITbbfGbErEAgoNTU1Yiw1NVUjIyMaGBiQy+UadUx1dbVefvnl6V6aJGnh80eu+7Gvtz8y3csBgHH99L9J/PcIN+pWup5uyk/TOByOiH3LssYcv6qyslKDg4Phrbe3d9rXCAAAzJj2d0bS0tIUCAQixvr7+xUXF6e5c+eOeYzT6ZTT6ZzupQEAgFvAtL8z4vF41NTUFDF27Ngx5efna+bMmdP99AAA4BZnO0YuXbqkzs5OdXZ2SvrxR3c7OzvV09Mj6cePWNavXx+eX1ZWpgsXLsjr9ers2bPas2ePdu/erYqKiql5BQAAIKrZ/pimvb1dDz74YHjf6/VKkkpLS9XQ0CC/3x8OE0nKzMxUY2Ojtm7dqrfeekvp6enasWMHP9YLAAAkTSJGVq9eHb4BdSwNDQ2jxlatWqXTp0/bfSoAAHAb4LtpAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUcQIAAAwihgBAABGESMAAMAoYgQAABhFjAAAAKOIEQAAYBQxAgAAjCJGAACAUZOKkbfffluZmZmKj49XXl6ePv3003HntrS0yOFwjNrOnTs36UUDAIDYYTtGPvjgA23ZskUvvPCCOjo6tGLFChUVFamnp2fC47q6uuT3+8Pb4sWLJ71oAAAQO2zHyBtvvKFnnnlGGzZsUHZ2tmpra+V2u1VXVzfhcSkpKUpLSwtvM2bMmPSiAQBA7LAVI8PDwzp16pQKCwsjxgsLC/X5559PeOyyZcvkcrlUUFCg5ubmCeeGQiEFg8GIDQAAxCZbMTIwMKArV64oNTU1Yjw1NVWBQGDMY1wul3bt2iWfz6eDBw8qKytLBQUFamtrG/d5qqurlZycHN7cbredZQIAgCgSN5mDHA5HxL5lWaPGrsrKylJWVlZ43+PxqLe3VzU1NVq5cuWYx1RWVsrr9Yb3g8EgQQIAQIyy9c7IXXfdpRkzZox6F6S/v3/UuyUTWb58uc6fPz/u406nU0lJSREbAACITbZiZNasWcrLy1NTU1PEeFNTk+6///7r/ns6OjrkcrnsPDUAAIhRtj+m8Xq9euKJJ5Sfny+Px6Ndu3app6dHZWVlkn78iKWvr0/79u2TJNXW1mrhwoXKycnR8PCw9u/fL5/PJ5/PN7WvBAAARCXbMfLYY4/pu+++0yuvvCK/36/c3Fw1NjZqwYIFkiS/3x/xO0eGh4dVUVGhvr4+JSQkKCcnR0eOHFFxcfHUvQoAABC1JnUD63PPPafnnntuzMcaGhoi9rdt26Zt27ZN5mkAAMBtgO+mAQAARhEjAADAKGIEAAAYRYwAAACjiBEAAGAUMQIAAIwiRgAAgFHECAAAMIoYAQAARhEjAADAKGIEAAAYRYwAAACjiBEAAGAUMQIAAIwiRgAAgFHECAAAMIoYAQAARhEjAADAKGIEAAAYRYwAAACjiBEAAGAUMQIAAIwiRgAAgFHECAAAMIoYAQAARhEjAADAKGIEAAAYRYwAAACjiBEAAGAUMQIAAIwiRgAAgFHECAAAMIoYAQAARk0qRt5++21lZmYqPj5eeXl5+vTTTyec39raqry8PMXHx2vRokWqr6+f1GIBAEDssR0jH3zwgbZs2aIXXnhBHR0dWrFihYqKitTT0zPm/O7ubhUXF2vFihXq6OhQVVWVNm/eLJ/Pd8OLBwAA0c92jLzxxht65plntGHDBmVnZ6u2tlZut1t1dXVjzq+vr1dGRoZqa2uVnZ2tDRs26Omnn1ZNTc0NLx4AAES/ODuTh4eHderUKT3//PMR44WFhfr888/HPOb48eMqLCyMGFuzZo12796ty5cva+bMmaOOCYVCCoVC4f3BwUFJUjAYtLPc6/JD6D/XPXc6nh+x7afXF9cPbhTXE6bSzbierv69lmVNOM9WjAwMDOjKlStKTU2NGE9NTVUgEBjzmEAgMOb8kZERDQwMyOVyjTqmurpaL7/88qhxt9ttZ7lTLrnW6NMjynH9YCpxPWEqTff1dPHiRSUnJ4/7uK0YucrhcETsW5Y1auxa88cav6qyslJerze8/8MPP+jf//635s6dO+HzxKpgMCi3263e3l4lJSWZXk7M43zffJzzm49zfnPdrufbsixdvHhR6enpE86zFSN33XWXZsyYMepdkP7+/lHvflyVlpY25vy4uDjNnTt3zGOcTqecTmfE2OzZs+0sNSYlJSXdVhexaZzvm49zfvNxzm+u2/F8T/SOyFW2bmCdNWuW8vLy1NTUFDHe1NSk+++/f8xjPB7PqPnHjh1Tfn7+mPeLAACA24vtn6bxer169913tWfPHp09e1Zbt25VT0+PysrKJP34Ecv69evD88vKynThwgV5vV6dPXtWe/bs0e7du1VRUTF1rwIAAEQt2/eMPPbYY/ruu+/0yiuvyO/3Kzc3V42NjVqwYIEkye/3R/zOkczMTDU2Nmrr1q166623lJ6erh07dqikpGTqXkWMczqdevHFF0d9dIXpwfm++TjnNx/n/ObifE/MYV3r520AAACmEd9NAwAAjCJGAACAUcQIAAAwihgBAABGESO3iLa2Nq1du1bp6elyOBz68MMPIx63LEsvvfSS0tPTlZCQoNWrV+vLL780s9gYca1z/uSTT8rhcERsy5cvN7PYGFBdXa377rtPiYmJSklJ0aOPPqqurq6IOVznU+t6zjnX+dSqq6vTkiVLwr/czOPx6OOPPw4/zjU+NmLkFjE0NKSlS5dq586dYz7+l7/8RW+88YZ27typkydPKi0tTQ8//LAuXrx4k1caO651ziXpt7/9rfx+f3hrbGy8iSuMLa2trSovL9eJEyfU1NSkkZERFRYWamhoKDyH63xqXc85l7jOp9L8+fO1fft2tbe3q729XQ899JDWrVsXDg6u8XFYuOVIsg4dOhTe/+GHH6y0tDRr+/bt4bH//e9/VnJyslVfX29ghbHn5+fcsiyrtLTUWrdunZH13A76+/stSVZra6tlWVznN8PPz7llcZ3fDHfeeaf17rvvco1PgHdGokB3d7cCgYAKCwvDY06nU6tWrdLnn39ucGWxr6WlRSkpKfr1r3+tZ599Vv39/aaXFDMGBwclSXPmzJHEdX4z/PycX8V1Pj2uXLmiAwcOaGhoSB6Ph2t8AsRIFLj6RYM//zLC1NTUUV9CiKlTVFSkf/zjH/rkk0/017/+VSdPntRDDz2kUChkemlRz7Iseb1ePfDAA8rNzZXEdT7dxjrnEtf5dDhz5ozuuOMOOZ1OlZWV6dChQ7rnnnu4xidg+9fBwxyHwxGxb1nWqDFMncceeyz859zcXOXn52vBggU6cuSIfv/73xtcWfTbuHGjvvjiC3322WejHuM6nx7jnXOu86mXlZWlzs5Off/99/L5fCotLVVra2v4ca7x0XhnJAqkpaVJ0qhy7u/vH1XYmD4ul0sLFizQ+fPnTS8lqm3atEmHDx9Wc3Oz5s+fHx7nOp8+453zsXCd37hZs2bp7rvvVn5+vqqrq7V06VK9+eabXOMTIEaiQGZmptLS0tTU1BQeGx4eVmtrq+6//36DK7u9fPfdd+rt7ZXL5TK9lKhkWZY2btyogwcP6pNPPlFmZmbE41znU+9a53wsXOdTz7IshUIhrvEJ8DHNLeLSpUv66quvwvvd3d3q7OzUnDlzlJGRoS1btuj111/X4sWLtXjxYr3++uv65S9/qT/84Q8GVx3dJjrnc+bM0UsvvaSSkhK5XC59/fXXqqqq0l133aXf/e53BlcdvcrLy/Xee+/po48+UmJiYvj/DpOTk5WQkCCHw8F1PsWudc4vXbrEdT7FqqqqVFRUJLfbrYsXL+rAgQNqaWnR0aNHucYnYu4HefBTzc3NlqRRW2lpqWVZP/7Y44svvmilpaVZTqfTWrlypXXmzBmzi45yE53z//znP1ZhYaE1b948a+bMmVZGRoZVWlpq9fT0mF521BrrXEuy9u7dG57DdT61rnXOuc6n3tNPP20tWLDAmjVrljVv3jyroKDAOnbsWPhxrvGxOSzLsm5m/AAAAPwU94wAAACjiBEAAGAUMQIAAIwiRgAAgFHECAAAMIoYAQAARhEjAADAKGIEAAAYRYwAAACjiBEAAGAUMQIAAIwiRgAAgFH/D7S3UPMdHt9RAAAAAElFTkSuQmCC", + "text/plain": [ + "<Figure size 640x480 with 1 Axes>" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "plt.hist(indices, bins=128)" + ] + }, + { + "cell_type": "code", + "execution_count": 38, + "id": "30ca1765-2b98-430c-a0bd-92dc101140db", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "[<matplotlib.lines.Line2D at 0x7f5ce719b610>]" + ] + }, + "execution_count": 38, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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rPgh3jBssdklkhxhGiIio3/xj3zmcKGuAj0KOtNvYPUNdYxghIqJ+cbpcZZ498/zNiQhTeopcEdkrhhEiIrK6Vq0BT36ZDZ1BwLykENyZwu4ZujaGESIisrq07Xk4V9OMYB8F0m4bye4Z6hbDCBERWdWe/GpsPFQCAHjzzlHw93YXuSKydwwjRERkNbVNGvzh36cAAA9NjcaMYUEiV0SOwKIwsmbNGowcORK+vr7w9fXF5MmTsX379m7v2bt3L8aNGwcPDw/ExsZi7dq1fSqYiIjskyAI+GN6DmqbNBgWMgDP3DRc7JLIQVgURgYPHozXXnsNWVlZyMrKwo033ohbbrkFubm5XV5fXFyMBQsWYPr06cjOzsaqVavwxBNPID093SrFExGR/dhw4AJ251XBXSbF6rvHwMNNJnZJ5CAkgiAIffkB/v7+eOONN/DII49c9b1nnnkGW7ZsQV5envnckiVLcPLkSRw6dKjHr6FWq6FUKqFSqeDr69uXcomIqB+cKGvAnWsPQmcQ8JefJeGBKdFil0R2oKef370eM2IwGPDll1+iubkZkydP7vKaQ4cOITU1tdO5efPmISsrCzqd7po/W6PRQK1WdzqIiMg+NbRosfSfx6EzCFg4IgyLJ0eJXRI5GIvDSE5ODgYMGACFQoElS5bg66+/RmJiYpfXVlZWIiQkpNO5kJAQ6PV61NbWXvM10tLSoFQqzUdERISlZRIRkQ0IQvty7+UNrYgK8ELa7VxllSxncRiJj4/HiRMncPjwYfz2t7/FAw88gDNnzlzz+p/+ozT1CnX3j3XlypVQqVTmo6yszNIyiYjIBj7aX9w+TkQuxfv3joWvh5vYJZEDklt6g7u7O4YOHQoASElJwdGjR/HOO+/gH//4x1XXhoaGorKystO56upqyOVyBAQEXPM1FAoFFAqFpaUREZENHSupx1935ANo3403eZBS5IrIUfV5nRFBEKDRaLr83uTJk5GRkdHp3K5du5CSkgI3N6ZnIiJHValqw5JNx6E3Clg0Khz3TYwUuyRyYBaFkVWrVmH//v24cOECcnJy8OyzzyIzMxP33XcfgPbulcWLF5uvX7JkCUpKSrB8+XLk5eXh448/xvr167FixQrrPgUREdlMm86A33yWhZpGDeJDfPAad+OlPrKom6aqqgr3338/KioqoFQqMXLkSOzYsQNz584FAFRUVKC0tNR8fUxMDLZt24annnoK77//PsLDw/Huu+/i9ttvt+5TEBGRTQiCgJWbc3Dyogp+Xm74cHEKvBUW9/gTddLndUZsgeuMEBHZhw/3nccr2/Igk0rw2cMTMGVooNglkR3r93VGiIjItew9W4O07e2LWD6/MIFBhKyGYYSIiK6rsKoRj39+HEYBuDslgiusklUxjBARUbcqVW144OMjULfpkRI1EC/emsQBq2RVDCNERHRNqlYdHtxwBJdUbYgN8saHi1OgkHMDPLIuhhEiIuqSRt8+hTe/shFBPgp8+tAEDPR2F7ssckIMI0REdBWjUcDyf53E4fP1GKCQ45OHxiPC30vssshJMYwQEVEngiDgL//NxdZTFXCTSfCP+8chKZxLvVP/YRghIiIzQRDw4rdn8OmhEgDAG3eMwlRO4aV+xjBCREQA2oPIK1vzsOHABQDAa7eNwK1jBolbFLkEhhEiIoIgCEjbno+Pvi8GALz68xG4ZwI3vyPbYBghInJxgiDgrzsKsG7feQDAy7cm417uwks2xN2NiIhcmMEo4IUtp7HpcPsmpy/dkoRfTooSuSpyNQwjREQuqk1nwBNfZGPXmSpIJMCLtyTjfgYREgHDCBGRC7rcrMUjnx7F8dIGuMuleOfu0Zg/IkzssshFMYwQEbmYsvoWPLDhCM7XNMPXQ471D47H+Gh/scsiF8YwQkTkQi43a3HvR4dRVt+KcKUHPn14AuJCfMQui1wcwwgRkYvQGYz43T+Po6y+FRH+nvi/30xBqNJD7LKIOLWXiMhVvPTtGRw6Xwdvdxk+WjyeQYTsBsMIEZEL+OJIKTZ2LPH+9t2jER/KrhmyHwwjRERO7khxPf70n9MAgN/PHYbUpFCRKyLqjGGEiMiJVara8NtNx6AzCFg4IgyP3ThU7JKIrsIwQkTkxF7fkY+6Zi0Sw3zxxp0jIZFIxC6J6CoMI0RETurMJTW+PlEOAHjt9hHwcucESrJPDCNERE7qtR35EATg5pFhGDnYT+xyiK6JYYSIyAkdKKrFvrM1cJNJ8Id58WKXQ9QthhEiIidjNApI254HALhvYhSiArxFroioewwjRERO5r+nLuF0uRoDFHI8ztkz5AAYRoiInIhGb8CbuwoAAL+ZEYuAAQqRKyK6PoYRIiIn8vkPpSirb0WwjwKPTI8RuxyiHmEYISJyEqoWHd79rhAAsGzOME7lJYfBMEJE5CTe+a4Ql1t0GBYyAHelDBa7HKIeYxghInICRdVN2HjoAgDg+ZsTIZfx7Z0cB/+1EhE5gZe3noHeKGBOQjCmxwWJXQ6RRRhGiIgc3J6CamQWtC9w9uzCRLHLIbKYRWEkLS0N48ePh4+PD4KDg3HrrbeioKCg23syMzMhkUiuOvLz8/tUOBERATqDES9/ewYA8OCUaMQEcoEzcjwWhZG9e/di6dKlOHz4MDIyMqDX65Gamorm5ubr3ltQUICKigrzERcX1+uiiYio3WeHSnCuphkB3u54fDbfV8kxWTTva8eOHZ2+3rBhA4KDg3Hs2DHMmDGj23uDg4Ph5+dncYFERNS1+mYtVu8+CwBYMS8evh5uIldE1Dt9GjOiUqkAAP7+/te9dsyYMQgLC8Ps2bOxZ8+ebq/VaDRQq9WdDiIi6uyNnflQt+mREOaLu1IixC6HqNd6HUYEQcDy5csxbdo0JCcnX/O6sLAwrFu3Dunp6di8eTPi4+Mxe/Zs7Nu375r3pKWlQalUmo+ICP5HRkR0pWMl9fjiSBkA4C8/S4JMKhG5IqLekwiCIPTmxqVLl2Lr1q34/vvvMXiwZYvrLFq0CBKJBFu2bOny+xqNBhqNxvy1Wq1GREQEVCoVfH19e1MuEZHT0BmMWPT375Ff2Yg7xw3GG3eOErskoi6p1Woolcrrfn73qmXk8ccfx5YtW7Bnzx6LgwgATJo0CYWFhdf8vkKhgK+vb6eDiIjafXLgAvIrG+Hn5YaVCxLELoeozywawCoIAh5//HF8/fXXyMzMRExM7zZhys7ORlhYWK/uJSJyZZcaWvF2x6DVVfMT4O/tLnJFRH1nURhZunQpPv/8c/znP/+Bj48PKisrAQBKpRKenp4AgJUrV6K8vBwbN24EAKxevRrR0dFISkqCVqvFpk2bkJ6ejvT0dCs/ChGR8/vLf3PRojUgJWog7hjH/WfIOVgURtasWQMAmDVrVqfzGzZswIMPPggAqKioQGlpqfl7Wq0WK1asQHl5OTw9PZGUlIStW7diwYIFfauciMjFfJdXhZ25VZBLJXj558mQctAqOYleD2C1pZ4OgCEiclbNGj1S396H8oZW/GZGLMeKkEPo1wGsRERkW69tz0d5QysG+XniyTlcaZWcC8MIEZGdO1hUi88OlwAAXr9jJLzcLephJ7J7DCNERHasWaPH0+mnAAD3TozE1KGBIldEZH0MI0REduy17fm4eLm9e2YVx4mQk2IYISKyUz/tnhmgYPcMOSeGESIiO3Rl98x97J4hJ8cwQkRkh17eesbcPcNpvOTsGEaIiOzMt6cu4YsjZZBIgDfuZPcMOT+GESIiO1JW34KV6TkAgN/NGoIpQ9g9Q86PYYSIyE7oDEY8/kU2GjV6jIsaiGVzholdEpFNMIwQEdmJtzLO4kRZA3w95HjnntFwk/EtmlwD/6UTEdmB/YU1WJN5DgDw19tHYvBAL5ErIrIdhhEiIpE1afR46quTANqn8c4fESZyRUS2xTBCRCSy7/KqUNukweCBnnj+5kSxyyGyOYYRIiKR7cqtAgAsGhUODzeZyNUQ2R7DCBGRiNp0BmQWVAMA5iWFilwNkTgYRoiIRHSgqBbNWgNCfT0wcpBS7HKIRMEwQkQkop25lQCA1KQQSKUSkashEgfDCFE3mjR6qNt0YpdBTkpvMGJ3HrtoiBhGiK5B1arDvLf3YdYbmbhQ2yx2OeSEskouo75ZC6WnGybE+ItdDpFoGEaIruHtjLMob2hFfbMWv/nsGFq0erFLIidj6qKZnRDM1VbJpfFfP1EX8irU2HjoAgDAx0OOgqpGPP3vUxAEQdzCyGkIgmCe0ssuGnJ1DCNEPyEIAv70n9MwCsCCEaH4+MHxkEsl+PZUBdZ/Xyx2eeQkci+pUd7QCg83KWbEBYldDpGoGEaIfuI/Jy7h6IXL8HST4dmFiRgf7Y8/LWpfFTNtez4OnqsVuUJyBqYumpnDguDpzoXOyLUxjBBdobFNh1e25QEAHrtxKAb5eQIA7p8UhdvGDoLBKOCxz7NR3tAqZpnkBExhhF00RAwjRJ28s7sQNY0axAR649HpMebzEokEr/58BJLCfVHfrMXv/nkcWr1RxErJkRXXNuNsVRPkUglmDw8Ruxwi0TGMEHU4W9WIDQcvAABeWJQIhbxz07mHmwxrfzkOSk83nCxrwKsdLShEljK1ikyKDYDSy03kaojExzBChPZBq89/cxoGo4DUxBDMig/u8roIfy+8ffcoAMAnBy/g21OXbFkmOYkfu2jYKkIEMIwQAWgftPpDcT083KTX3cL9xuEh+O2sIQCAZ/59CudqmmxRIjmJKnUbsksbAACpHC9CBIBhhAjqKwatPn5jHCL8va57z+/nDsPEGH80aw343abjaNUa+rtMchK7OlpFxkT6IcTXQ+RqiOwDwwi5vLczzqKmUYPYnwxa7Y5cJsXffzEGgQMUKKhqxLPf5HBBNOqRnVzojOgqDCPk0s5cUuPTjkGrf7kl6apBq90J9vXA338xBlIJsPl4Od7YWcBAQt1Stehw+HwdAIYRoisxjJDLMhoFPN+x0urCEWGY3otVMCcPCcBffpYEAPgg8xze3l1o7TLJiXyXXwW9UcCwkAGICfQWuxwiu8EwQi7r38cv4ljJZXi5y/DczQm9/jn3T442D3p997tCvPsdAwl1jQudEXXNojCSlpaG8ePHw8fHB8HBwbj11ltRUFBw3fv27t2LcePGwcPDA7GxsVi7dm2vCyayhmp1G17bng8AWDYnDmFKzz79vEemxWDVguEAgLcyzuL9PUV9rpGcS6vWgL1nawAwjBD9lEVhZO/evVi6dCkOHz6MjIwM6PV6pKamorm5+Zr3FBcXY8GCBZg+fTqys7OxatUqPPHEE0hPT+9z8US9odUb8bt/Hkd9sxbDQ33w0NSeDVq9nl/PGIKnb4oHALyxswBv7MyH3sBVWqndvsIatOmMGOTniaRwX7HLIbIrcksu3rFjR6evN2zYgODgYBw7dgwzZszo8p61a9ciMjISq1evBgAkJCQgKysLb775Jm6//fbeVU3UB69uy0NWyWX4KOT44L6xcJNZr7fyd7OGwmAQ8LeMs3h/zzl8X1SH1XeP5vgAMnfRpCaFQCKRiFwNkX3p07uwSqUCAPj7+1/zmkOHDiE1NbXTuXnz5iErKws6na7LezQaDdRqdaeDyBq+zr6ITzpmz7x192jEBg2w+ms8PjsO79wzGj4ecpwsa8CCd/bj8x9KOdPGhekMRnyXVw2AXTREXel1GBEEAcuXL8e0adOQnJx8zesqKysREtJ5yeOQkBDo9XrU1na9FXtaWhqUSqX5iIiI6G2ZRGZnLqmxcnMOAODxG4dibmL/LcV9y+hB2LlsBibHBqBVZ8Cqr3Pw0CdHcfBcLYxGhhJXc6S4HqpWHfy93TE++tq/vBG5ql6HkcceewynTp3CF198cd1rf9okafoN8VpNlStXroRKpTIfZWVlvS2TCADQ0KLFbzZloU1nxMxhQVg2Z1i/v2a4nyf++ehEPLsgAe4yKTILanDvhz9g+ut78MbOfC4j70JMXTRzEoIhk7KLhuinLBozYvL4449jy5Yt2LdvHwYPHtzttaGhoaisrOx0rrq6GnK5HAEBAV3eo1AooFAoelMa0VWq1W341cYslNW3IsLfE+/cM9pmHwhSqQS/mhGLmfFB2HCgGN+eqkB5Qyve33MO7+85h5tHhuGtu0bDXc5Z9s7KaBSwi6uuEnXLondAQRDw2GOPYfPmzfjf//6HmJjrz0KYPHkyMjIyOp3btWsXUlJS4ObGrbMdTXbpZfx20zG8v6fIIbobzlxS49b3D+DkRRX8vNyw9pfj4OflbvM6hoX4IO22kTj67By8f+9YzB7e/hvyt6cq8NtNx6DRc28bZ3WqXIVKdRu83WWYOjRQ7HKI7JJFYWTp0qXYtGkTPv/8c/j4+KCyshKVlZVobW01X7Ny5UosXrzY/PWSJUtQUlKC5cuXIy8vDx9//DHWr1+PFStWWO8pqN+dq2nCbzcdw88/OIjtpyvxxs4CPP5FNtp0/fsheqmhFSfLGno1+PO7vCrcufYgLqnaEBvojW9+NxVJ4cp+qLLnPNxkWDgyDOsfHI9PH5oAhVyK7/KrseSzY/3+Z0niMHXRzIoPhodbz7cbIHIlFoWRNWvWQKVSYdasWQgLCzMfX331lfmaiooKlJaWmr+OiYnBtm3bkJmZidGjR+Oll17Cu+++y2m9DqKuSYNVX+cg9e192H66ElIJMCchBG4yCbbmVODeDw+jrklj9ddt0xnwdsZZzHozE7e8fwD3ffQDTpY19Oherd6IdfvO4Vcbs9CsNWDKkAB8/bupiLaz6bXT4gKx4cHx8HCTYk9BDX7DQOKUrpzSS0RdkwgOMN9QrVZDqVRCpVLB15eLBdmK0Sjg52sOmkPAnIRg/GHecMSH+uDQuTr85rMsqNv0iPT3wscPjsfQYOtMk91TUI0/b8lFSV0LAEAiAUz/Sucnh+L3qfFdvtb5miZ8ebQM6ccuoq5ZCwD4xYQIvHhLslXXErG2Q+fq8PAnR9GqM2B6XCA+XJzC36CdRFF1I+a8tQ9uMgmOPT8Xvh7smibX0tPPb4YRuqYtJy/hiS+y4e0uw8cPjsfE2M4Djouqm/DQJ0dQVt8KpacbVs4fjjtTIno9OLRK3YYX/pOLHR2/SYb4KvD8zYkYHeGHtzMKsTn7IgQBkEqAmEBv+Hm5w8/TDUovN1y83IojxfXmnxXso8BjNw7F/ZOiHGKBqR/O1+GhT46iRWvAfRMj8crPR4hdElnB+3uK8MbOAswcFoRPH54gdjlENscwQn2i1Rsx5629KK1vwfK5w/DE7Lgur6tt0uBXG7OQXdoAABgWMgB/nD8cN8QHWxQCtuVUYNXXOWho0UEmleDhqdF4cs4wDFD8OOGroLIRb+4qQMaZqi5/hlQC3BAfjHsmROKG+CDI7bg1pCv7ztZg8cdHAAAfLk7p13VQyDZ+9t73OHVRhVd/PgL3TowUuxwim2MYoT755EAx/vzfMwjyUWDvH2bBy/3as8A1egM+O1SCv/+vCKrW9lV1J8X64/ep8UiJGthtKFG36fDn/+Ric3Y5ACB5kC/evHMUhode+++5pK4ZlxraoGrVoqFFB1Vre4BZODKszxveie2VrWfw4f5i+Hu7Y8eT0xHs6yF2SdRLlxpaMeW1/0EiAY6smoMgHy5XQK6np5/fvVpnhJxbY5sO7/6vfdfZZXPiug0iAKCQy/Do9FjcOS4CH+wtwoYDF3D4fD3uXHsIsUHeuGPcYNw+djBCOj5Y9QYjSupbcLpchdd3FKC8oRVSSfu+Lk/MjrvumhtRAd6ICrCvwajWsmJePA4U1eFMhRq//7+T+PShCZBykSyHtKuju3Fc5EAGEaLrYBihq6zbdx71zVrEBnrjrpSeL8Wv9HLDyvkJWDw5Gu/sPostJy/hfE0zXt9RgDd3FiAlyh+qVh3O1zZBZ/ixQS7S3wtv3z0K46K4TLZCLsO7vxiNhe9+j/2Ftfjk4AU8PM06uwqTbe3sWOjspmQudEZ0PY7VqU79rlrdho/2FwMAnr4pvlezUAb5eeL1O0bh6LNz8NfbR2B89EAYBeDIhXoUVDVCZxDg6SbDiEFK/HpGLLY9OZ1B5ApDg33w3M2JAIDXduQjv5IbRTqay81aHLnQPqCaq64SXR9bRqiT1d8VolVnwJhIvz6/ifp4uOHu8ZG4e3wkimubcfh8HUKVHogLHoBwpSe7H7rxy4mRyMyvxnf51Xjs82yk/3YKlJ6cFuoodudVwWAUkBDmiwh/L7HLIbJ7bBkhs6LqJnx1tH1TwpXzE6w6JTYm0Bu/mBCJG+KDMXigF4PIdUgkEvz1jpEI8VWgqLoJv96YxSXjHchO8140nBFF1BMMIwSgfd+h5785DYNRwJyEEEyIYbeJ2AIHKLDhwQkYoJDjh+J6LP/XSYfYD8jVtWj12F9YA4BdNEQ9xTBCAIBvTpTj0Pk6eLhJ8cKiRLHLoQ6J4b74x/3j2pffP1WBV7bliV0SXcfeghpo9EZE+ntheKiP2OUQOQSGEYKqRYeXv23/kHtidhz7uO3M1KGBePPOUQCA9d8X46P950WuiLpj2otmXlKIQ6z+S2QPGEYIf92Zj7pmLeKCB+DRabFil0NduGX0IKycPxwA8PLWPOw4XSFyRdQVrd6I7/KrAbCLhsgSDCMu7ljJZXz+Q/suyy/fmnzdBcdIPL+eEYsHJkcBAP7w71Moq28RuSL6qcPn69DYpkfgAAXGRg4Uuxwih8FPHhemMxjx7Nc5AIA7xw2+aiM8si8SiQTP3ZyIsZF+aGzT4/EvsqEzGMUui65g6qKZmxjCGWNEFmAYcWEbDhQjv7IRfl5uWLkgQexyqAfcZFK8c88Y+HrIcaKsAW/uKhC7JOpgNArmTRw5pZfIMgwjLupAUS3e2Nn+QbZqfgL8vd1Froh6KsLfC6/fMRIA8I+955FZUC1yRQQA2WUNqG7UwEchx5QhgWKXQ+RQGEZcUO4lFX7z2THoDAJuHhmGO8YNFrskstBNyWG4f1L7+JHf/+skqtRtIldEpo3xbhgezLFXRBbifzEupqy+BQ9uOIomjR6TYv3xt7tGsW/bQT27MAHDQ31Q16zF8n+dgCBwQTSxCIJwxZRezqIhshTDiAu53KzFAxuOoKZRg+GhPli3OAUKuUzssqiXPNxkeO/esXCXS3GgqA5nKrihnljOVjXhQl0L3OVSzIoPErscIofDMOIiKlVteOTTozhf04xwpQc+eWgCfD248ZqjGxo8ALOGtX/4mfZDIdvbcbq9VWRGXCC8Fdx/lMhSDCNOrE1nwJaTl7D44yOY8tp3OF7aAF8POT59eAJClR5il0dWYuoWMI1ZINszddGksouGqFcY4Z2QIAhYvbsQHx8oRmOb3nx+fPRAPLcwEXEh3C/DmcxOCIZMKkF+ZSNK6poRFeAtdkkupay+BWcq1JBKgDkJnNJL1BsMI07og8xzeOe7QgDAID9P3D52EG4bOxjRgfyQckZ+Xu6YFOuPA0V12JlbiV/PGCJ2SS7F1CoyIcafU+SJeolhxMlsPVVhXj/k+ZsT8dCUaM6WcQHzkkI7wkgVw4iN7co1LXTGLhqi3uKYESdyoqwBy/91AgDw0NRoPDIthkHERaQmtn8QHi+9jOpGrjliK7VNGhwtqQfA8SJEfcEw4iTKG1rx6KdZ0OiNuHF4MJ5bmCh2SWRDoUoPjIrwgyDAvCQ59b/dZ6ogCMCIQUoM8vMUuxwih8Uw4gQa23R45JOjqG1qXz/k3V+MgYwtIi7HtB8Kp/jazo8LnXHgKlFfMIw4OEEQ8Ez6KeRXNiJwgALrHxyPAVznwCWZxiwcOlcLVatO5GqcX2ObDgeK6gBwvAhRXzGMOLh//lCKbTmVkEslWLd4HJuKXdiQoAGICx4AnUHAnnxuntffMgtqoDUYERvojaHBA8Quh8ihMYw4sLwKNV789gwA4JmbhmNs5ECRKyKxmX5D38kF0PrdDlMXTXIoJBJ2ixL1BcOIg2rR6vHY58eh1RtxQ3wQHpkWI3ZJZAdMYSSzoAZtOoPI1TivNp0BmR2tT+yiIeo7hhEH9cJ/cnGuphkhvgr87a7RnMJLAIDkQb4Y5OeJVp0B+wtrxS7HaR08V4tmrQGhvh4YOUgpdjlEDo9hxE4IgoCaRg2OldSjplHT7bXfZJfj/45dhFQCvHPPGK76SGYSiQRzE02zathV0192nm6fsZSaFMJfBIisgNMuRHSyrAGfHS7BuZomnKtugrpjHxl3mRR3pAzGb2cOQYS/l/n6/Eo11u09jy0nLwEAnpgdh0mxAaLUTvZrXlIoPjl4Ad/lVUFvMEIu4+8c1mQwCtidx1VXiazJ4nepffv2YdGiRQgPD4dEIsE333zT7fWZmZmQSCRXHfn5+b2t2Wk8/e9T+Pexi8gubYC6TQ+JBAgcoIDWYMTnP5Ri1puZWP7VCWzLqcADHx/BTav3Y3N2OfRGAQtHhOHxG+PEfgSyQ+OjB2Kglxsut+hw5EK92OU4nawL9ahr1kLp6YYJMf5il0PkFCxuGWlubsaoUaPw0EMP4fbbb+/xfQUFBfD19TV/HRQUZOlLO5ULtc0oqGqETCrB23ePxrCQAYgO8IaHmww/nK/D+5nnsO9sDTZnl2NzdjkAQCoB5ieH4dczYjEqwk/cByC7JZdJMSchBP937CJ25VZhypBAsUtyKqZF5WYnBMONrU5EVmFxGJk/fz7mz59v8QsFBwfDz8/P4vuclWnJ7kmx/vjZqPBO35sYG4CJsQE4dbEB7+8pwqmLKsxNDMEj02K4PTz1yE3Jofi/YxexM7cSLyxK5NRTKxEE4YpVV9lFQ2QtNhszMmbMGLS1tSExMRHPPfccbrjhhmteq9FooNH8OIhTrVbbokSb2nWm/Q3NtMFZV0YO9sM/7k+xVUnkRKYODYS3uwwVqjacuqhiS5qV5F5So7yhFZ5uMsyIc+3WXSJr6vc2xrCwMKxbtw7p6enYvHkz4uPjMXv2bOzbt++a96SlpUGpVJqPiIiI/i7TpmqbNMgquQwA5pkPRNbk4SbDrPhgAJxVY02mP8uZw4Lg6S4TuRoi59HvYSQ+Ph6/+tWvMHbsWEyePBkffPABFi5ciDfffPOa96xcuRIqlcp8lJWV9XeZNvW/vGoIQvuaEOFcvp36SWoSp/ham7mLJpm/RBBZkyijryZNmoTCwsJrfl+hUMDX17fT4Ux60kVD1Fc3DA+Gm0yCczXNKKpuErsch1dc24yzVU2QSyW4MZ5hhMiaRAkj2dnZCAsLE+OlRdei1ZtXxkzltuPUj3w93Mwzadg60nemP8PJQwKg9HITuRoi52LxANampiYUFRWZvy4uLsaJEyfg7++PyMhIrFy5EuXl5di4cSMAYPXq1YiOjkZSUhK0Wi02bdqE9PR0pKenW+8pHMi+s7XQ6I2I8PdEfIiP2OWQk5uXFIq9Z2uwK7cSS28YKnY5Ds0URlI5i4bI6iwOI1lZWZ1mwixfvhwA8MADD+CTTz5BRUUFSktLzd/XarVYsWIFysvL4enpiaSkJGzduhULFiywQvmO58ouGk63pP42NzEEz36Tg5MXVbjU0MoxSr1UpW5DdmkDACCVg86JrM7iMDJr1iwIgnDN73/yySedvn766afx9NNPW1yYM9IbjPhfx06ffEMjWwjyUSAlaiCOXriMXbmVeHAqd3fujV0d6wKNjfRDiK+HyNUQOR8uH2hDRy9cRkOLDv7e7hgXNVDscshFmBbnMq0cSpbbeZoLnRH1J4YRGzJ10dw4PJibl5HNmD5Aj1yox+VmrcjVOB5Viw6Hz9cBYBgh6i/8RLQRQRDMS8Czi4ZsKcLfCwlhvp12m6We+y6/CnqjgPgQH0QHcjsGov7AMGIjZyrUuHi5FR5uUkznMtJkY/PMC6AxjFjqx71o+EsEUX9hGLGRTYdLALR30XAZabK1m5Lbuxf2F9agWaMXuRrH0ao1YO/ZGgCc0kvUnxhGbKCuSYP04+UAgIc4m4FEEB/ig6gAL2j0RvOHK13fvsIatOmMGOTniaRw51oJmsieMIzYwGeHS6DVGzEqwg8pnEVDIpBIJFfMquFqrD1l+rO6KZnrAhH1J4aRftamM+CzQ+1dNI9Oi+EbGonGNObhf/nV0OqNIldj/3QGI3Z3DDrnLBqi/sUw0s++zi5HXbMWg/w8MT+Zb2gknjERAxHko0Bjmx6HOqaq0rX9cL4e6jY9ArguEFG/YxjpR0ajgI/2nwcAPDQ1mmuLkKikUol5Wjm7aq7P9Gc0NzEEMilbNIn6Ez8d+9HeszU4V9MMH4Ucd4+PELscInN3w67cKhiM197WwdUZjYJ5kUJ20RD1P4aRfvRhR6vILyZGwseDW46T+CbFBsDHQ47aJg2ySy+LXY7dOnmxAVVqDQYo5JgyNEDscoicHsNIP8m9pMLBc3WQSSV4YEq02OUQAQDc5VLMHh4MgF013dnR8Wdzw/BgKORcF4iovzGM9JP1+4sBAAtHhGEQt20nO3Llxnnd7cDtqgRBwK5c0ywarrpKZAsMI/2gtkmD/566BAB4dDoXOSP7MjM+CAq5FKX1LcivbBS7HLtTWN2E4tpmuMulmBUfLHY5RC6BYaQffHW0DDqDgDGRfhg52E/scog68XKXY8aw9v2RdpxmV81P7ez4M5k2NBADFHKRqyFyDQwjVmYwCvj8h1IAwP2TokSuhqhrXI312kzjRW7iLBoim2EYsbI9+dUob2jFQC83LBgRJnY5RF2akxAMmVSC/MpGlNa1iF2O3Sirb0HuJTWkEmB2ArtoiGyFYcTKPuvYnfeulAh4uHEUPtknPy93TIzxB8DWkSvt6lj+fXy0PwIGKESuhsh1MIxYUUldM/aerYFEAtw7MVLscoi6dVPH9gQ7GEbMTMGMC50R2RbDiBX9s2OsyMxhQYgK8Ba5GqLupSa2f+AeL72M6sY2kasRX22TBlkX6gEA87iPFJFNMYxYSZvOgH9llQHgwFVyDKFKD4yK8IMgABkd3ROubPeZKhgFYMQgJdcGIrIxhhEr+fZUBRpadBjk58m1CchhmBb12pnLMPJjFw0XOiOyNYYRK9nUMXD1vkmR3OGTHIZp+urBolqoWnUiVyOexjYdDhTVAeB4ESIxMIxYwelyFU6UNcBdJsVdKdydlxxHbNAAxAUPgN4oYE9+tdjliCazoAZagxGxgd4YGjxA7HKIXA7DiBXs6mjenZsUgkBOByQHwwXQfpxRNC85FBIJWzaJbI1hxAqyStq3Yp86JFDkSogsZwojmQU1aNMZRK7G9tp0BmR2tAqxi4ZIHAwjfaQ3GHGirAEAkBI9UNxiiHoheZAvBvl5olVnwL6zNWKXY3MHz9WiWWtAqK8HRg5Sil0OkUtiGOmj/MpGtGgN8PWQY2gQ+5rJ8UgkEqS68Kwa02aB85JCIOXgcyJRMIz00bGOLpqxUQP5RkYOy9Q98V1+FXQGo8jV2I7eYMTuPHbREImNYaSPTONFxkWyi4Yc1/hof/h7u6OhRYcjxfVil2MzWSWXUd+shZ+XGyZ07NVDRLbHMNJHx01hhONFyIHJpBLMTTB11bjOrBpTF82chBDIZXw7JBIL/+vrgwpVK8obWiGTSjA6wk/scoj6ZF5yexjZlVsFo1EQuZr+JwiCeRl8dtEQiYthpA9M40USw3zh5S4XuRqivpkyJBADFHJUqttw8mKD2OX0u9PlapQ3tMLLXYbpcZyWTyQmi8PIvn37sGjRIoSHh0MikeCbb7657j179+7FuHHj4OHhgdjYWKxdu7Y3tdqdrAsdXTRR7KIhx+fhJsOs+CAArjGrZkduBQBgVnwQPNxkIldD5NosDiPNzc0YNWoU3nvvvR5dX1xcjAULFmD69OnIzs7GqlWr8MQTTyA9Pd3iYu2NqWWEYYScxZWrsQqCc3fVmAIXu2iIxGdx38L8+fMxf/78Hl+/du1aREZGYvXq1QCAhIQEZGVl4c0338Ttt99u6cvbjRatHmcq1AAYRsh53DA8GO4yKYprm1FY3YRhIT5il9QviqqbUFTdBDeZBDcM5y7bRGLr9zEjhw4dQmpqaqdz8+bNQ1ZWFnS6rncJ1Wg0UKvVnQ57c6KsAQajgHClB8L9PMUuh8gqBijkmNYxfmLnaeedVWOaMTRlSCB8PdxEroaI+j2MVFZWIiQkpNO5kJAQ6PV61NbWdnlPWloalEql+YiIsL+dcH+c0su1Cci5zOtYjXWHE0/xNW1uyS4aIvtgk9k0P90F09QXfa3dMVeuXAmVSmU+ysrK+r1GS/242JmfuIUQWdmchBBIJUDuJTXK6lvELsfqLjW04uRFFSQSYG5iyPVvIKJ+1+9hJDQ0FJWVnX/Dqq6uhlwuR0BAQJf3KBQK+Pr6djrsidEomFtGUtgyQk4mYIAC4zv+Xe8643yzakytIilRAxHkoxC5GiICbBBGJk+ejIyMjE7ndu3ahZSUFLi5OWZfbVFNE9Rteni5yzA81DkH+JFruym5Y1aNE44b4SwaIvtjcRhpamrCiRMncOLECQDtU3dPnDiB0tJSAO1dLIsXLzZfv2TJEpSUlGD58uXIy8vDxx9/jPXr12PFihXWeQIRmKb0jo7w4xLS5JRSOz6oj5bUo7ZJI3I11lPfrMUPxXUAGEaI7InFn6RZWVkYM2YMxowZAwBYvnw5xowZgz/96U8AgIqKCnMwAYCYmBhs27YNmZmZGD16NF566SW8++67Dj2tl4udkbMb5OeJEYOUEARgtxN11ezOq4JRaF81OcLfS+xyiKiDxeuMzJo1q9vFkD755JOrzs2cORPHjx+39KXs1vFShhFyfjclhyKnXIUduZW4Z0Kk2OVYhanbydQNRUT2gX0MFmrS6FFc2wwA3ByPnJppiu/Bojqo27peE8iRNGn02F/UvpwAu2iI7AvDiIXOVTcBAIJ8FPDzche5GqL+MzTYB0OCvKE1GLEnv1rscvoss6AaWr0RMYHeGBYyQOxyiOgKDCMWKuoII0OD+GZGzs/UgrDLCTbOM82iSU0KueYaR0QkDoYRCxXVdISRYIYRcn6msRV7CqrRpjOIXE3vafQGc+sOu2iI7A/DiIXMLSMMI+QCRgxSIlzpgRatAd8Xdr19gyM4WFSHJo0eIb4KjB7sJ3Y5RPQTDCMWMo0ZGcJuGnIBEonEvOaII+9VY9oYLzUxFFIpu2iI7A3DiAW0eiNKOvbqYMsIuQpTt8buvCroDUaRq7GcwSggo2OtFE7pJbJPDCMWKKlrhsEoYIBCjhBf7mlBrmF89ED4e7ujoUWHI8X1YpdjsawL9ahr1kLp6YYJMdxLisgeMYxYwDReZEjwAI7GJ5chl0kxN6F9zRFH7Kox1TwnIQRu3L6ByC7xv0wLcFovuap5ye1hZFduFYzGa6/AbG8EQTBPS2YXDZH9YhixAKf1kquaMiQQAxRyVKrbcPJig9jl9NjpcjXKG1rh5S7D9LhAscshomtgGLGAuZsmyFvkSohsy8NNhlnxQQB+XDzMEezIrQAAzIoPgoebTORqiOhaGEZ6yGgUcI4tI+TCTN0cO3Mru90s057s6NgYjwudEdk3hpEeKm9oRZvOCHeZFJHcepxc0Kz4YLjLpSiubUZhRyuhPSuqbsS5mma4y6S4cXiw2OUQUTcYRnrINF4kOtALco7IJxc0QCHH9KHt4y6259j/rBpTd9KUoQHw8XATuRoi6g4/VXvoHJeBJ8K8K7pq7J2pi+YmdtEQ2T2GkR4yjxfhtF5yYXMSQiCTSnCmQo3Suhaxy7mmi5dbkFOuglQCzEkMEbscIroOhpEeunLBMyJX5e/tjokdq5jac+uIaW2RlGh/BA7gaslE9o5hpIeKuEEeEYAfZ9XY82qsptrYRUPkGBhGeqCuSYPLLTpIJAwjRKmJ7R/wx0ouo1rdJnI1V6tp1ODohfY9dOZx1VUih8Aw0gOmVpFBfp7wdOfCSeTaQpUeGB3hBwDYdcb+FkDbnVcFQQBGDlZikJ+n2OUQUQ8wjPQAl4En6uwmO55VY6qJC50ROQ6GkR7gBnlEnZk+6A+dq0NDi1bkan6katXhQFEtAIYRIkfCMNIDnElD1FlMoDeGh/pAbxTwXV612OWY7cmvhs4gYGjwALZkEjkQhpEe4IJnRFcztTzY06wa00Jn8zlwlcihMIxcR7NGj0uq9hkD7KYh+pFp3Mi+szVo1uhFrgZo1RqQeba9lYZdNESOhWHkOs7XNAMAArzdMdDbXeRqiOzH8FAfRPp7QaM3Yu/ZGrHLwd6zNWjTGTF4oCeSwn3FLoeILMAwch1FNY0AOF6E6KckEsmPC6CdFr+rZucVC51JJBKRqyEiSzCMXEcRx4sQXZOpO+R/+dXQ6A2i1aHVG7E7r33Nk5s4XoTI4TCMXAen9RJd25gIP4T4KtCk0Zun1Irh4LlaNLbpEeSjwNjIgaLVQUS9wzByHYUdYSQuhGGE6KekUsmPs2pE7KoxddGkJoZAKmUXDZGjYRjphkZvQEnHNulxwT4iV0Nkn0yb0WWcqYLeYLT56xuMgnmX3vnJYTZ/fSLqO4aRblyobYHBKMBHIUeIL7chJ+rKhBh/DPRyw+UWHY4U19v89bMu1KOuWQulpxsmxvrb/PWJqO8YRrpx5cqrHJ1P1DW5TIq5iSEAgO0idNWYXnNOQgjcZHxLI3JEvfov94MPPkBMTAw8PDwwbtw47N+//5rXZmZmQiKRXHXk5+f3umhbKaxun9Ybx5k0RN0ydY/szK2E0SjY7HUFQfhxSi9n0RA5LIvDyFdffYVly5bh2WefRXZ2NqZPn4758+ejtLS02/sKCgpQUVFhPuLi4npdtK1w8CpRz0wZGgAfhRzVjRpkl1222eueuqhChaoNXu4yTI8LtNnrEpF1WRxG3nrrLTzyyCN49NFHkZCQgNWrVyMiIgJr1qzp9r7g4GCEhoaaD5lM1uuibcW0Jw0HrxJ1TyGX4caEYAC2nVVj6qK5IT4YHm72/55CRF2zKIxotVocO3YMqampnc6npqbi4MGD3d47ZswYhIWFYfbs2dizZ0+312o0GqjV6k6HrekNRvNS8FzwjOj6TJvTbT9dCUHo/64aQRCw/XRF+2uPYBcNkSOzKIzU1tbCYDAgJCSk0/mQkBBUVnb921BYWBjWrVuH9PR0bN68GfHx8Zg9ezb27dt3zddJS0uDUqk0HxEREZaUaRWl9S3QGozwcJNikJ+nzV+fyNHMGBYEDzcpLl5uRe6l/v8FIq+iESV1LVDIpbghPrjfX4+I+o+8Nzf9dGaJIAjXnG0SHx+P+Ph489eTJ09GWVkZ3nzzTcyYMaPLe1auXInly5ebv1ar1TYPJIVXLAPPRZSIrs/LXY5Zw4KxI7cSO05XInmQsl9fb0dHq8iMYUHwVvTqrYyI7IRFLSOBgYGQyWRXtYJUV1df1VrSnUmTJqGwsPCa31coFPD19e102FoRx4sQWcy8cV5u/48bMY0XWcAuGiKHZ1EYcXd3x7hx45CRkdHpfEZGBqZMmdLjn5OdnY2wMPteKZEb5BFZ7saEYLjJJCiqbkJRx9T4/lBU3YjC6ia4ySS4cXjPfxEiIvtkcdvm8uXLcf/99yMlJQWTJ0/GunXrUFpaiiVLlgBo72IpLy/Hxo0bAQCrV69GdHQ0kpKSoNVqsWnTJqSnpyM9Pd26T2JlpjVGGEaIes7Xww1ThwYis6AG23Mq8fjs/mlZ3J7T3ioydWgglJ5u/fIaRGQ7FoeRu+++G3V1dXjxxRdRUVGB5ORkbNu2DVFRUQCAioqKTmuOaLVarFixAuXl5fD09ERSUhK2bt2KBQsWWO8prMxoFK7opmEYIbLEguQwZBbUYNvpSjw+u3/WEzJ10cznQmdETkEi2GIOXh+p1WoolUqoVCqbjB8pq2/B9Nf3wF0mxZkX50HOJaaJeuxysxYpr+yGwShgz4pZiAn0turPL6lrxsw3MiGTSnD02Tnw93a36s8nIuvp6ec3P2W7YGoViQn0ZhAhstBAb3dMGRIAANiWU2H1n29qFZkU688gQuQk+EnbBfN4ES4DT9QrC0a0D1A3LUpmTaYwclOyfQ+CJ6KeYxjpAseLEPXNvKRQyKQSnC5Xo7SuxWo/91JDK06WNUAiAeYlcRYNkbNgGOlCIdcYIeoTf293TIr1BwBss2LriGnfm/FR/gj28bDazyUicTGM/IQgCCiq4hojRH1l6qqx5rgRU7fPTZxFQ+RUGEZ+okqtQaNGD5lUguhAL7HLIXJYqYmhkEqAUxdVKKvve1dNpaoNRy9cBsCN8YicDcPIT5jGi0QFeEEh55bkRL0V5KPAhJj2rhpT90pfbO1oYUmJGogwJTevJHImDCM/YZpJw8GrRH23sKOrZqsVumq+PXUJAHDzSM6iIXI2DCM/Ucg9aYisZl5yKCQS4ERZA8obWnv9cy5ebkF2afssGtNYFCJyHgwjP8HdeomsJ9jHA+Oj27tqtvehdWTrqfZ7J8b4I9iXs2iInA3DyE9wt14i61rQMfNlex/GjXzbEUZuHhlulZqIyL4wjFyhWt2G+mYtJBJgSBDDCJE1zB8RBokEOFZyuVddNSV1zcgpV0Eq4cZ4RM6KYeQKB87VAgCSwn3h6c6ZNETWEOLrgYkds2r+c6Lc4vtNrSJThgQiYIDCqrURkX1gGLnC/rPtYWR6XJDIlRA5l9vGDAYAfH28HJZuFP5jFw0HrhI5K4aRDoIgYH+RKYwEilwNkXO5aUQoFHIpCqubkHtJ3eP7ztU0Ia9CDblUwlVXiZwYw0iHgqpG1DRq4Okmw7iogWKXQ+RUfD3cMCexfWO7r7N73lXz7cn2VpFpcYHw83Lvl9qISHwMIx1MXTQTY/258ipRP/j56EEAgC0nL0FvMPbonh8XOuMsGiJnxjDSwdRFM20ou2iI+sPM+CAM9HJDTaMGB87VXff6gspGFFY3wV0mxdyOVhUick4MIwDadAb8cL79zXHGMA5eJeoPbjIpFo1qb+H4pgddNZ//UAKgPcQoPd36tTYiEhfDCNrXP9DojQjxVXBPGqJ+9PMx7V01O05Xolmjv+Z1qhYd/pV1EQDw4JRoW5RGRCJiGAGwr7AGADBtaBAkEonI1RA5r9ERfogO8EKrzoBdZ669IuvnR0rRqjNgeKgPpgwJsGGFRCQGhhFcub4Ix4sQ9SeJRIJbO1pHNh/vuqtGqzfik4PFAIBHp8fyFwQiF+DyYaS2SYMzFe3rHkzl4FWifmfqqjlQVItqddtV39+WU4EqtQZBPgosGsWFzohcgcuHkQMds2gSw3wR5MOlpon6W1SAN8ZG+sEoABsPlXT6niAI+Oj78wCAByZHcZo9kYtw+TCyv5BdNES2du/EKADAe3uKsHbvOfP5H4rrcbpcDQ83qfkaInJ+Lh1GBEHA/o7Bq9yPhsh2bh87CI/fOBQA8Nr2fLy1q6C9VWR/ccf3B8PfmyuuErkKudgFiKmwuglVag0UcilSorkEPJGtSCQS/D41Hl7ucvx1Rz7e/V8Ryi634rv8KgDAw9NiRK6QiGzJpVtGTF00E2L84eHGvmkiW/vtrCF48ZYkAO171ggCMCchGEOCuN4PkStx8TBi6qLheBEisSyeHI037hgJaccM3kemxYpbEBHZnEt30yyZOQTxoT64cTj3vSAS050pERg80AtV6jZM5iJnRC7HpcPIpNgATIrlGx+RPWAIIXJdLt1NQ0REROJjGCEiIiJRMYwQERGRqHoVRj744APExMTAw8MD48aNw/79+7u9fu/evRg3bhw8PDwQGxuLtWvX9qpYIiIicj4Wh5GvvvoKy5Ytw7PPPovs7GxMnz4d8+fPR2lpaZfXFxcXY8GCBZg+fTqys7OxatUqPPHEE0hPT+9z8UREROT4JIIgCJbcMHHiRIwdOxZr1qwxn0tISMCtt96KtLS0q65/5plnsGXLFuTl5ZnPLVmyBCdPnsShQ4d69JpqtRpKpRIqlQq+vr6WlEtEREQi6ennt0UtI1qtFseOHUNqamqn86mpqTh48GCX9xw6dOiq6+fNm4esrCzodLou79FoNFCr1Z0OIiIick4WhZHa2loYDAaEhHReJCwkJASVlZVd3lNZWdnl9Xq9HrW1tV3ek5aWBqVSaT4iIiIsKZOIiIgcSK8GsEokkk5fC4Jw1bnrXd/VeZOVK1dCpVKZj7Kyst6USURERA7AohVYAwMDIZPJrmoFqa6uvqr1wyQ0NLTL6+VyOQICul5xUaFQQKFQWFIaEREROSiLWkbc3d0xbtw4ZGRkdDqfkZGBKVOmdHnP5MmTr7p+165dSElJgZubm4XlEhERkbOxuJtm+fLl+Oijj/Dxxx8jLy8PTz31FEpLS7FkyRIA7V0sixcvNl+/ZMkSlJSUYPny5cjLy8PHH3+M9evXY8WKFdZ7CiIiInJYFm+Ud/fdd6Ourg4vvvgiKioqkJycjG3btiEqKgoAUFFR0WnNkZiYGGzbtg1PPfUU3n//fYSHh+Pdd9/F7bffbr2nICIiIodl8TojYlCpVPDz80NZWRnXGSEiInIQarUaERERaGhogFKpvOZ1FreMiKGxsREAOMWXiIjIATU2NnYbRhyiZcRoNOLSpUvw8fHpdgqxpUyJzZlbXJz9Gfl8js/Zn9HZnw9w/mfk8/WeIAhobGxEeHg4pNJrD1N1iJYRqVSKwYMH99vP9/X1dcp/YFdy9mfk8zk+Z39GZ38+wPmfkc/XO921iJj0atEzIiIiImthGCEiIiJRuXQYUSgUeOGFF5x6tVdnf0Y+n+Nz9md09ucDnP8Z+Xz9zyEGsBIREZHzcumWESIiIhIfwwgRERGJimGEiIiIRMUwQkRERKJiGAGQlpYGiUSCZcuWiV2KVfz5z3+GRCLpdISGhopdltWVl5fjl7/8JQICAuDl5YXRo0fj2LFjYpdlFdHR0Vf9HUokEixdulTs0qxCr9fjueeeQ0xMDDw9PREbG4sXX3wRRqNR7NKsqrGxEcuWLUNUVBQ8PT0xZcoUHD16VOyyemXfvn1YtGgRwsPDIZFI8M0333T6viAI+POf/4zw8HB4enpi1qxZyM3NFafYXrreM27evBnz5s1DYGAgJBIJTpw4IUqdvdXd8+l0OjzzzDMYMWIEvL29ER4ejsWLF+PSpUs2qc3lw8jRo0exbt06jBw5UuxSrCopKQkVFRXmIycnR+ySrOry5cuYOnUq3NzcsH37dpw5cwZ/+9vf4OfnJ3ZpVnH06NFOf38ZGRkAgDvvvFPkyqzjr3/9K9auXYv33nsPeXl5eP311/HGG2/g73//u9ilWdWjjz6KjIwMfPbZZ8jJyUFqairmzJmD8vJysUuzWHNzM0aNGoX33nuvy++//vrreOutt/Dee+/h6NGjCA0Nxdy5c817izmC6z1jc3Mzpk6ditdee83GlVlHd8/X0tKC48eP4/nnn8fx48exefNmnD17Fj/72c9sU5zgwhobG4W4uDghIyNDmDlzpvDkk0+KXZJVvPDCC8KoUaPELqNfPfPMM8K0adPELsNmnnzySWHIkCGC0WgUuxSrWLhwofDwww93OnfbbbcJv/zlL0WqyPpaWloEmUwmfPvtt53Ojxo1Snj22WdFqso6AAhff/21+Wuj0SiEhoYKr732mvlcW1uboFQqhbVr14pQYd/99BmvVFxcLAAQsrOzbVqTNXX3fCZHjhwRAAglJSX9Xo9Lt4wsXboUCxcuxJw5c8QuxeoKCwsRHh6OmJgY3HPPPTh//rzYJVnVli1bkJKSgjvvvBPBwcEYM2YMPvzwQ7HL6hdarRabNm3Cww8/bNWNIsU0bdo0fPfddzh79iwA4OTJk/j++++xYMECkSuzHr1eD4PBAA8Pj07nPT098f3334tUVf8oLi5GZWUlUlNTzecUCgVmzpyJgwcPilgZ9YVKpYJEIrFJi7NDbJTXH7788kscP37cYftvuzNx4kRs3LgRw4YNQ1VVFV5++WVMmTIFubm5CAgIELs8qzh//jzWrFmD5cuXY9WqVThy5AieeOIJKBQKLF68WOzyrOqbb75BQ0MDHnzwQbFLsZpnnnkGKpUKw4cPh0wmg8FgwCuvvIJf/OIXYpdmNT4+Ppg8eTJeeuklJCQkICQkBF988QV++OEHxMXFiV2eVVVWVgIAQkJCOp0PCQlBSUmJGCVRH7W1teGPf/wj7r33XptsDuiSYaSsrAxPPvkkdu3addVvLc5g/vz55v8/YsQITJ48GUOGDMGnn36K5cuXi1iZ9RiNRqSkpODVV18FAIwZMwa5ublYs2aN04WR9evXY/78+QgPDxe7FKv56quvsGnTJnz++edISkrCiRMnsGzZMoSHh+OBBx4Quzyr+eyzz/Dwww9j0KBBkMlkGDt2LO69914cP35c7NL6xU9b7gRBcJrWPFei0+lwzz33wGg04oMPPrDJa7pkN82xY8dQXV2NcePGQS6XQy6XY+/evXj33Xchl8thMBjELtGqvL29MWLECBQWFopditWEhYUhMTGx07mEhASUlpaKVFH/KCkpwe7du/Hoo4+KXYpV/eEPf8Af//hH3HPPPRgxYgTuv/9+PPXUU0hLSxO7NKsaMmQI9u7di6amJpSVleHIkSPQ6XSIiYkRuzSrMs3WM7WQmFRXV1/VWkL2TafT4a677kJxcTEyMjJs0ioCuGgYmT17NnJycnDixAnzkZKSgvvuuw8nTpyATCYTu0Sr0mg0yMvLQ1hYmNilWM3UqVNRUFDQ6dzZs2cRFRUlUkX9Y8OGDQgODsbChQvFLsWqWlpaIJV2fvuRyWRON7XXxNvbG2FhYbh8+TJ27tyJW265ReySrComJgahoaHmWV9A+1invXv3YsqUKSJWRpYwBZHCwkLs3r3bpt36LtlN4+Pjg+Tk5E7nvL29ERAQcNV5R7RixQosWrQIkZGRqK6uxssvvwy1Wu1Uzd9PPfUUpkyZgldffRV33XUXjhw5gnXr1mHdunVil2Y1RqMRGzZswAMPPAC53Ln+U120aBFeeeUVREZGIikpCdnZ2Xjrrbfw8MMPi12aVe3cuROCICA+Ph5FRUX4wx/+gPj4eDz00ENil2axpqYmFBUVmb8uLi7GiRMn4O/vj8jISCxbtgyvvvoq4uLiEBcXh1dffRVeXl649957RazaMtd7xvr6epSWlprX3jD9QhQaGuoQazl193zh4eG44447cPz4cXz77bcwGAzmli5/f3+4u7v3b3H9Pl/HQTjT1N67775bCAsLE9zc3ITw8HDhtttuE3Jzc8Uuy+r++9//CsnJyYJCoRCGDx8urFu3TuySrGrnzp0CAKGgoEDsUqxOrVYLTz75pBAZGSl4eHgIsbGxwrPPPitoNBqxS7Oqr776SoiNjRXc3d2F0NBQYenSpUJDQ4PYZfXKnj17BABXHQ888IAgCO3Te1944QUhNDRUUCgUwowZM4ScnBxxi7bQ9Z5xw4YNXX7/hRdeELXunuru+UzTlbs69uzZ0++1SQRBEPo37hARERFdm0uOGSEiIiL7wTBCREREomIYISIiIlExjBAREZGoGEaIiIhIVAwjREREJCqGESIiIhIVwwgRERGJimGEiIiIRMUwQkRERKJiGCEiIiJRMYwQERGRqP4f5ApR5eeumSQAAAAASUVORK5CYII=", + "text/plain": [ + "<Figure size 640x480 with 1 Axes>" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "intervals = np.linspace(4, 12, 100)\n", + "error = np.array([np.sqrt((((indices + ivl/2) % ivl - ivl/2)**2).mean()) for ivl in intervals])\n", + "plt.plot(intervals, error)" + ] + }, + { + "cell_type": "code", + "execution_count": 43, + "id": "73f1bfdb-8da5-4d6f-b4db-99d8fa5933c5", + "metadata": {}, + "outputs": [ + { + "data": { + "text/plain": [ + "[<matplotlib.lines.Line2D at 0x7f5ce70d4a10>]" + ] + }, + "execution_count": 43, + "metadata": {}, + "output_type": "execute_result" + }, + { + "data": { + "image/png": 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WEE6Ujj2U5oVe0ieGcsZPW4PVnqGplomv3TP+fp/3qp6ngWHktVDaflbcsUVO5eVZ03JzjQyjsVihNPIYEWXySd5jNK+5cBIxndFHrnlm8gK60zwzLHw14pJhdLognCidaZGcNyWdNTEySRdxXWCpwS22AopNCniMmPelY5r6/bS8Jr5mXkRZHiN2MKNQ2ljIY0RUDAulzZ1eaBixomRMROg0LOXydM9MfU3OMBqOu2QYMYONPEZlUxP0IZTvpO6FcBo3jOotw2iazWPklldsvHGpSmsjM4z01xgNJ9I4Oph79rI8Rh1RMozGYyhuaWbJY0SUzXihNCDXQgBwLxRweALPDNNBDSfc8TRMNC6ieAzD4Dojt+v8iICFf9g7A1geo2Qmy5MInMQ0TZwczj3b6RoYRjPqc14tL4TSWBhtel2Iz3PR2LPS3G6RpBIH8zX5mmr1TI4hw0gRuMeoudDlyw2QpEtangk8M26H0k4vIUCUh1dS9k3TxIm8AWLvRVYb8nOvmBvhtIFYCun8hskaMKsM8xidGE4io/lGf2TAqqMji/ZoDXxGzvA+MaK/MSmKQxrriwAyjJQgkc6gJ19k73SPUV0oZ4CMKmaA1HOPkfPjiqcy/ESr64unClGPpOwPxtNI5mtq2UNWhmEUhNOchhlrDeEAz+pUmel1IRhGriilW5mwomBzulmStwgAgn4f2hpzXjaqZWRxUGN9EUCGkRIc6ovBNHOn29NPlXXcM+N8GGAkkeabycShNOcNI9b3KhL086wjojymecRjxHQ84xkgbgqwxxOEq0zA7+NrkO7htP5Y7vNmJRtkwVP2XW72rRLMY6RjDSOADCMlsMJoY0un14Vzi/yIC6E05i1qrAmgoabQAKln43LBMLKn6utWal41vBJK4/qicQwQ5jFyoy0I0xfZdU+qM4PXMtLbA8I+bzbHZUFFHsfCNEa6JseQYaQArMnh6WE0wO4xct4AsTLSxo6rPuxeHSMq7igOLr7W3DBinpkZ4wic3WwLwsY1vU4PjxHgnZR95u1ucspjRIYRhzRGRMUcyFvX88bpo8Q0Rm7UmZks84t5slwxjKi4ozC84jE6wT1GYzdBN9uCnByeeFyq4pUijwM8lCbbY0RFHk+Hha1naBJCPp2KDKMNGzbAMAysWbOGf800Taxfvx4dHR2IRCK44oorsGfPnoKfSyQSuPvuu9HS0oK6ujqsXLkShw4dKrimr68PXV1diEajiEaj6OrqQn9/f8E1Bw4cwI033oi6ujq0tLTgnnvuQTKpn2CQnWTHO+3WuRiymqxWkJtZaWxc5DGqHK+Ir0/wkNV4oTT3NEbHWaq+hh4j3Q0jZgjLNoxa8+Jr5h0kgMFYbl9orNFTA1q2YfT222/jH/7hH3DBBRcUfP0HP/gBHnroITzyyCN4++230d7ejmuuuQZDQ1az0TVr1uCFF17Apk2bsG3bNgwPD2PFihXIZCyvyKpVq7Bz5050d3eju7sbO3fuRFdXF/9+JpPBDTfcgJGREWzbtg2bNm3Cc889h7Vr15Z7S64xlDcuWNFEOyyUNprMOF4ng3lmxjOM3BRfH5pkXERpTPNIvzSrhtF4oTT3ajWd1Ex8DdhDaXprjFh4WLb4mnn1Yx6oHi+CZDqLWCr3LBoj+tUwAso0jIaHh/G1r30Njz/+OJqamvjXTdPEj3/8Y3z3u9/FTTfdhM7OTjz11FMYHR3Fs88+CwAYGBjAE088gQcffBBXX301PvWpT2Hjxo3YtWsXXn75ZQDABx98gO7ubvzjP/4jli1bhmXLluHxxx/Hiy++iH379gEANm/ejL1792Ljxo341Kc+hauvvhoPPvggHn/8cQwODlb6XByFVY8erxAWe+kAYDTl7It3eBLPDDPiUhkTibTD46LijsJgHiOWwaMrk1WXtjxGbqTr58elQQ0jBhNf6+4xGsgbwtMki68jodw26kYBURUZilvvmY7FHYEyDaM777wTN9xwA66++uqCr+/fvx+9vb1Yvnw5/1o4HMbll1+O119/HQCwY8cOpFKpgms6OjrQ2dnJr3njjTcQjUaxdOlSfs3FF1+MaDRacE1nZyc6Ojr4Nddeey0SiQR27NhRzm25xvAkHqOaoA++fOKV07WMWB2T8U67doPNybYgmayJ3nzNJ9IYVU403y9Nd48RF1+PM1fdFF+fnOQdUhWrLYjehpHlMZJsGAXzHiOHD66qMpTfD+pCfgT8esqYSzbnNm3ahHfffRdvv/32mO/19vYCANra2gq+3tbWhk8++YRfEwqFCjxN7Br28729vWhtbR3z+1tbWwuuOf3vNDU1IRQK8WtOJ5FIIJGwXnZVPEvMMGoYx7o2DAN1oQCGEmkMJ9IY+1Qkjis/wRvGMdj8PgORoB+xVAYjiQymy2lFNIaBWIpX5B1Pk0WUhvc0RuOIr11M12eicB2qXjN4KG0wAdM0tSyJkUhnuAeHNUuWRW0opwOlUFqOwbzHqFGyp04mJZlzBw8exDe/+U1s3LgRNTUTd4o+/UUq5uU6/Zrxri/nGjsbNmzgYu5oNIo5c+ZMOianYBb2eB4joFBn5CRc+zSBO5Q3knXQk8XE3jVBn7anEZVgp+nBeFrbFhCmaeJ4UaE0Zz1GsWSGZ5Pq5DFiXrdYKuNKNqwImKHvM8Y/2IkkkjeMRpNp1xoVq4TuwmugRMNox44dOHbsGJYsWYJAIIBAIICtW7fif/yP/4FAIMA9OKd7bI4dO8a/197ejmQyib6+vkmvOXr06Ji/f/z48YJrTv87fX19SKVSYzxJjHvvvRcDAwP838GDB0u5fWkMJ3Iv8UQGSK0LqfGJdAbJdK7FQkN4/AnuRluQ4SmMNaI07MXv7NoAnRiMp/lcHT+UlrvHoXga6XzbECdg4b1QwDeuN1hVakMB/n4dG9RTgM3CaNFIED6fXI8XM4yyJnhbmmqGeYxkG6QyKckwuuqqq7Br1y7s3LmT/7vooovwta99DTt37sSZZ56J9vZ2bNmyhf9MMpnE1q1bcckllwAAlixZgmAwWHBNT08Pdu/eza9ZtmwZBgYG8NZbb/Fr3nzzTQwMDBRcs3v3bvT09PBrNm/ejHA4jCVLlow7/nA4jMbGxoJ/bpPKZBFPFWeAOJkab29BMrEny/lSAuxv1Wm00ahM0O/joQA3eomJYLJ2IECh8edkIUuuL6oLaReOmp4PSeraL43NZdkZaUCuNRGDwmnWAUvnUFpJu0tDQwM6OzsLvlZXV4fp06fzr69Zswb3338/FixYgAULFuD+++9HbW0tVq1aBQCIRqO47bbbsHbtWkyfPh3Nzc1Yt24dFi9ezMXc5513Hq677jqsXr0ajz32GADg9ttvx4oVK7Bw4UIAwPLly7Fo0SJ0dXXhgQcewKlTp7Bu3TqsXr1aCYOnWOzCZWZonI4bRR7Z5K4N+eGf4MTlhseIhffs4m+iMqZFghhNZrQVYJ+YpB0IkOv/1VgTwGA8jf7R5LjhNjfGpTK1Ib0FxSxsKlt4DeQOF0G/gVTGxGgyg2l6FnsWhhVK03eNFj7yb3/724jFYrjjjjvQ19eHpUuXYvPmzWhoaODX/OhHP0IgEMDNN9+MWCyGq666Cj/96U/h91uGwTPPPIN77rmHZ6+tXLkSjzzyCP++3+/HSy+9hDvuuAOXXnopIpEIVq1ahR/+8Ieib0kqzKiIBCdW8LvhmRmapIQAww3DaGSSDD6iPBojQRwZiOtrGBXRj2xabQiD8bSjAuyTI/oJrxmRYG4t0tUDwjRGslP1GZGgH6lMWltDUiReEF9XvLu89tprBf9vGAbWr1+P9evXT/gzNTU1ePjhh/Hwww9PeE1zczM2btw46d+eO3cuXnzxxVKGqxxTCa8Bd/qlTVZCgOHGuEZIYyScaZr3SzueL0Q4mSeoqTaIA6eAPgdDQ5NV41YdppvRdaPv5+1AnDFKa0M5j6SuhqRIBmNVpjEixDNZqj6DubXtuh/ZWKn6E1v97oivc8+ANEbi0L1fGjNAJuvLxDZIJ40/3kBWR8MoqHcKet+oMzWMGFZmmp7PSyTssF81WWmEeHhG2iTWdX3YSgd1iqH8uCYz2Lhh5GCBR8tjNL4eiygdq5aRnkLbyapeM9xoC1JMiE9VmIhdW48RD6U58+wjmj8vkXghlEaGkcsUo+VhHiNHPTNFjIuH0hw02EZIfC0c5k3R12M0tWHkRluQk0WMS1V03+gHYs6JrwF7kUfne0eqRtXVMSLEU0xdnnoXCjxO1tiWYYXSHAzxUbq+cHi/NE3T9a0GshN7B9xoC1KMwaYqLDQU1zQ01E+hNNeoujpGhHiGixBfu1HgsRiPkRVKc25DpQKP4tFdY8R0Q9MnM4zq8m1BRpz0GOWMsMnGpSq6e4z6HKxjBOj/vETCNUYUSiPKpRjxteUxcj4rbbJaFFZWmnOLAaXri0d3w4jNv9pJwqtO1+VJZ7I4NUpZaW7B9HJOpetTvzQLlpWmcx0jMoxcpph0fUtj5GSBxyJCaS70SqNQmnh0N4zYgWEy3VkNq8vj0EY/GE+Dtc1qciicIxIrK03PFhfMi0ihNGfJZE0uw5gso1l1yDByGSs0NPEkcrfA42Tp+s6H+Jh3gLLSxME2Dx0No2zW5JtR7SRzgm30CYcMI92bHXONkYYeo0Q6w+eEc6E0vSuFi8K+F5DGiCibYjRGPJTmqGdm6jICbhZ4pKw0cegsvo6nrY2IhTPGw2kNCDfWNJ2nLF3fyfC9KFjVa58xuURBJBRKy8HCaOGAb9y+hbpAhpHLlFLg0Y2Q1WRWvzsFHimUJhpmGMVSGaQ06w7OPIiGAdQEJl6Iw44bRlarHx3RWUzMwmjRSBC+Cfo8isYKpelnSIrECzWMADKMXGeoxHR9kwkXZI8rXrwoPJHOOrahUksQ8dhPdrpthHYDZLJNkG308ZQz85R5DiZqDK06lmGkl6EMWJ7PJofCaIDez0skrIaRzmE0gAwj12Gp7sWk66ezJhJpZ168YkJ8dq+NE+G0bNbECN9w9H7xVCIc8MHI2xS6aUqKDVkx8bVTdXnYuCKahtJ0rmPUl89IizooeqcCjzmGmMdIY+E1QIaR6xRTl8eup3Eq66EYT1bQ70M4kJtCToTT7BW2dT+RqIRhGDwMFdcsC4lnpE3hmXE6/ZzN1VpNQ2k6twQZ4O1AnNucKSstx6AHahgBZBi5jtWsdeKN3u8z+InXCc9MIp1BMu+ZapgkKw1wVmfE9CR+n8ENMkIM3EOQ1mth556ZKQwQ9v101nQk7Bvjniw9DSO9NUY5j5E7oTT9npdIvFDDCCDDyFUyttDQVJqZegf7ktkLNk5VSNHJzDQuvA75YRjOiCqrhZq8oalbVg2bq1OFVu06KifChVYJAT03iFqNQ2lMY+RsKC2frq/h8xKJ1Q6EPEZEmdiNnKkMEPbiOWGAsDhxbcgP/xRZHU72SyPhtTxqNK1bw0JpU3lm7B5GJwTYzHOgayhN58rXvB1IxEGPUSg3v6o9lGa1A9F7jSbDyEVYGC3k9yE8Saox4Gz7jaEi+qQxrH5pTniyKFVfFkxjpNtGOFpkyMowDFtmmhMeo3y2nKahtBpb6DHpUMKHKKyUcefWCSrwmMMKpZHHiCiT4RL6ftWFnKt+XdK4HKzKTTWM5GFVOtZrEyymHQjDybYgVv82PQ2jiMYlHOIu6LuowGMOqmNEVEwpnpk6B0XOliB86sldn7/GkXFRKE0aPJ1ds02QGyBF1Aty0mMU07ysRNBv8DC6bnPCjVIJ9gKPTtWaUxEeSiPxNVEupWz0zDPjRAx7KN8OpJhy+k72SyONkTycNBpEwrU8xXiMHDzVj6aKy5ZTFXvoUTcvSMyFZ88Mo6wJJDWrHi+SQapjRFRKMUUUGXUOtgUZLsWT5aAofLjIDCSidJxumSEKNu+KCZs4qaOKFSkKVxldaxm5USqhIPSomSEpElb5msTXRNkMl+CZqeNtQRzISitBY8SucdZjpO9moyq8wKN2GqO8sVyEx8hJHRUL8ekqvgasTCvdDKPRlPPC96Dfh6A/F3qs5sw08hgRFTNUiseIi5zlv3SleIycLPBI4mt5sE1Qt1BaKdlfjmalpYo32FSlNp9ppVsto1i+ervTYcxqL/JomqbVY5MMI6JcStMYOV9IsRgBnZPjonR9eVgeI70W9dESmrU6mZXmiVCaprWM3Hr21V7kcTSZQSabE55TKI0om3I0Rk5Uvi7Fk+XkKYndO4mvxRPRtMAjM5ZZHZnJqHG0jpEHQmlB/YoWmqZpCd8dfvbV3i+NhdECPkPbpAMGGUYuwjwzpWiMnC3wOLU71Erzlq/bYOMij5F4dBXaluIxctKItwpP6jtXdQwNJdJZsGx5CqU5iyW8DmrfsokMIxdhIudi4rHOFnjMWf7FeIzCDp7CKV1fHpY3RU/xdVHp+uwenUjX90AoTUcvoj2M5bRhZBV5lL9GqwjfNzywPpNh5CIlpcXzJrIOiK+5wVZ8KM0Zw6i4hrtE6TipvxFJKQYI3+glt7jIZk1uYOpsGNVoWMeIzd+Q34eA39ntrdpDaUz0rvOcZ5Bh5CKqtt7gmQVFGCBOehqsrDT9XzzV0LXAYynp+k5t9HbjkkJpzuKmtos9r6o1jPLzpEZzfRFAhpGrDJdggDialVaC+NrJVhIkvpaHk8JkUWSzphVKUygrjc1Tw7D+po7oaBi5UdyRUath6FEkvHQGGUZEJZTiMap1sHvzUAlaHifTvCldXx4RDTVGhZ4ZdeoYsc05EvRrLULlG71GHhA32oEwqj2Uxt4rCqURFTGUT28sZqO3e2ZkNilMpDNI5jUYDUVlpTmj20ikM0hlcvdNhpF4whpqjNgGZBiWgT4ZThlGXshIA/SsY1RKwU/RsJIR1WoYsQNBDRlGRCWwF6gYzwzL/pLdpNBeDqCUUFomayIlcVwsvAdYGXqEOHTUGHHhddAPn29qz4xTerhRF8M5ItFRM2P31jlN1YfSNG+cbIcMI5dIprNI56uEFiNWs082mQs782LVhvzwl7DZ5MYlb0HgvaeCfsezTaoBHdP1LaFtcZ4Zp2o1eSFVH9DTWOahNDc8RjyUVp3p+nGPHAgAMoxco1R9RNBvgNkpMheqUvuRhQPWFJK5qVKfNLnoKL5mG1CxWYpcfC3ZA+KFqteANX69Qmnubc46ethE4qa+SzRkGLkEW5wDPgPBIjwghmE4coIrVUBnGIYjmWlWRpr+L52K6OgdYF7EYrU8/B7TzoivdW4gC+hZxyju4uZc9aE0pjEiw4gol3Jcvk6EO0bLiNGzcSUkbjjkMZILM27TkrViIinVOxBxKMvKMx4jHnrUYz4ApYdXRVLtWWkxykojKqWcmg9OaCRiZSzqLCOIVT6VAaXqy8UprZhIStXykMaoNHRsCUKhNPeIu6jvEg0ZRi5RziRyImRVTpyYj0uix4j6pMklHPCBldzRRVMyUmLIyqlaTV7LSqNQWnGwkK5OhqRIKJRGVEwlISuZG1c5C4sTwl2vbDaqYhgG9/wlNAmdxCrwGMmsBWa923ob8XqKr12sYxTy5cegz/MSiZtVx0VDhpFLlBOyYsZKwoFQWilFusIOnMS9lPGgKro1kuXi6xKz0gAgIbEgaazEbDlV0dFjVM6BUxTVXuDRTW+daMgwcolyhGpOiK+Z0LIkj1FAfogv7hFBq8rolplmaXlKq2MEyM6g9MZcZfMhmckirYkg3822FJSVRoYRUSHlVGh14kRfjmfGCZEmeYzko1t6dqnh1aDfh6A/J6RyIoGhVvO5ajfsZLf8EYWbGYH2Ao8yQ7Wq4mZxTdGQYeQS5aSVOqHlKUsUzhrJygxPpLwj7FMVp/reiWK0RPE1YM+glKmHK82TpSr24q26GMsqNJHNmnJDtapCWWlExVgvcPEfgZPp+qUYIDwrTeLiyUoBeOGlUxUnsh5FwjIVSzLiuXdTfi2wYrVPquJUUVmRWAJgF+oYaVjyQiQUSiMqppwX2Nq41BI5O+rJ8sBLpyq61a1hc7UUkXPEicOFhwrd6ZaZ5mYozR6qrTYBtmmaFEojKqec0JAjWWkVeLJk1jEijZF8eEhUk02QeYzKO1zIr7mle7o+oF9mmtvrhFNFRFUjkc6Cyaq8sEaTYeQSlWSlSa1jVMaJK+yEJ6uMMgJEaXhdfA04k3nnpXouunmM3H72OjZjFoF9zSDDiCib8rLSnCukWJLGyAFPA/NG1QRoyspCV/F1aR4j+Rv9aBkhPlXRyWNkmqarBR4B56qrqwZ7n0J+HwJFNEVXHf3vQFPK6knmYCHFUjabiAOC1nKeF1EavByEBpsgYGV/lWKAONqIWfOsNMAZTZYokpkssiyc45rHKPcOyZQ7qIglDfGGSeGNu9CQ0bJEzvLrGJXVEiQgv1caia/lE3FAKyYSXvm6BC2P7I0+nckimfe46V7HCLBC1zoYyyqEc5zQW6qI1w6uZBi5RFxVfQTPLChDfC0zXZ/qGEnHic9RFNmslQVTSlo8925KusdR27vphU0iolGbGDbGoN9A0KVwjlUnqzpDabrX7mKQYeQSo6lcGKAUMbETGqPy6hg5kJXmsROJijgREhWFfaMuqcCj5Kw0Nk99RmGBRF3RqY6RCnV0wprVAhNFOfuGyuj/5mpKOW0DnBD2lVfHSH5WWryMHm5EabCNXAfvwEheX2QYpekaZIuv7dW4DcOQ8jecJKJhKM3Nw1O1htIso9QbJoU37kJDynmJnTiNlFPWPSz5VJnOZJHMkGEkG50KPNoPFqUYILI1RuVU41YZneryqBDOqdastLgCz14kZBi5hIp1jFKZLFKZXFpHaeJruRuqPX3cKxuOijjR804UTHhdauaX7Kw0L1W9BvTKSlMhlKZbWx1ReE0DSoaRS5RTL0j2acT+MpfVK03WZmNz43tBt6EqsoXJIomlWNXr0hZi2ZoZL6XqA3ppjGIu1zACqrfAo5utWGRAu4wLZLMm775cTnE6acLR/O81ShSOspchISmuHuenEZ8ndBuqwg1cDfQR5WrOZKefs825ziMbhBN1n0ShgreuWg0jHkqrRo/Ro48+igsuuACNjY1obGzEsmXL8Ktf/Yp//9Zbb4VhGAX/Lr744oLfkUgkcPfdd6OlpQV1dXVYuXIlDh06VHBNX18furq6EI1GEY1G0dXVhf7+/oJrDhw4gBtvvBF1dXVoaWnBPffcg2QyWeLtu4PdLV3Kwi779BZPWptNKQaIFUqT68kifZFcdGoJUm6LGNk1t6wQnzfmqk5FP5UIpQXkJ6KoiArCd5GUZBjNnj0b3//+9/HOO+/gnXfewZVXXonPf/7z2LNnD7/muuuuQ09PD//3y1/+suB3rFmzBi+88AI2bdqEbdu2YXh4GCtWrEAmY714q1atws6dO9Hd3Y3u7m7s3LkTXV1d/PuZTAY33HADRkZGsG3bNmzatAnPPfcc1q5dW+5zcBS7YVSKZ4YtUumsiVRG/ItXbgNG2dontxtDVgs6ZdSU0+wYkJ9lNaqA10IkYZ3mhAKbc41GCQwiKUcaojIlBcJvvPHGgv+/77778Oijj2L79u04//zzAQDhcBjt7e3j/vzAwACeeOIJPP3007j66qsBABs3bsScOXPw8ssv49prr8UHH3yA7u5ubN++HUuXLgUAPP7441i2bBn27duHhQsXYvPmzdi7dy8OHjyIjo4OAMCDDz6IW2+9Fffddx8aGxtLewoOY++T5vOV4JmxTbp4KiO8iFm5AjpmsGXyBpvwcVEDWUfQqThd2Ua87EQBBbwWItEpNOR2A1lArwQGkagQxhRJ2TtYJpPBpk2bMDIygmXLlvGvv/baa2htbcU555yD1atX49ixY/x7O3bsQCqVwvLly/nXOjo60NnZiddffx0A8MYbbyAajXKjCAAuvvhiRKPRgms6Ozu5UQQA1157LRKJBHbs2DHhmBOJBAYHBwv+uYFVXbq0SWT3Lslw1bLeU6VO7tMNNtGQx8gZuFZMg00wUaYRL7uIpfVue0N8rVNoaLTMOSESncLRIvGa3KFkw2jXrl2or69HOBzG17/+dbzwwgtYtGgRAOD666/HM888g1deeQUPPvgg3n77bVx55ZVIJBIAgN7eXoRCITQ1NRX8zra2NvT29vJrWltbx/zd1tbWgmva2toKvt/U1IRQKMSvGY8NGzZw3VI0GsWcOXNKvX0hlBsLNwxDajpoOTWMAPkGm9deOlVxohefKCjs6wzkMSoN3kRWg9CjSNih2ite/ZKPNQsXLsTOnTvR39+P5557Drfccgu2bt2KRYsW4Stf+Qq/rrOzExdddBHmzZuHl156CTfddNOEv9M0zQKx73jC33KuOZ17770X3/rWt/j/Dw4OumIcVRILjwT9iKeycjwz+RBKqScuwzAQDviQSEsaV5kGG1EabDNPSwqJioTP1ZK9m3KNP3sGpRdga0FCg9CQZRi5563TyZAUSSzlncbJQBkeo1AohLPPPhsXXXQRNmzYgAsvvBB/93d/N+61M2fOxLx58/Dhhx8CANrb25FMJtHX11dw3bFjx7gHqL29HUePHh3zu44fP15wzemeob6+PqRSqTGeJDvhcJhn1LF/blBuDRZAbvpsJaddmSn75RpsRGnIDomKpNy5Kj2z02MeI53qGKkQSqvaytcKCN9FUvGxxjRNHio7nZMnT+LgwYOYOXMmAGDJkiUIBoPYsmULv6anpwe7d+/GJZdcAgBYtmwZBgYG8NZbb/Fr3nzzTQwMDBRcs3v3bvT09PBrNm/ejHA4jCVLllR6S9KpZKOXGQqoxDCSmbLvtc1GVWSHREVSrmdGdtsTFTKjRKJTJWcVQmnV2kSWNUX3yhpdks/xO9/5Dq6//nrMmTMHQ0ND2LRpE1577TV0d3djeHgY69evx5e+9CXMnDkTH3/8Mb7zne+gpaUFX/ziFwEA0WgUt912G9auXYvp06ejubkZ69atw+LFi3mW2nnnnYfrrrsOq1evxmOPPQYAuP3227FixQosXLgQALB8+XIsWrQIXV1deOCBB3Dq1CmsW7cOq1evVj4jDShf5AzIddVWYvXLDFHEPBaeUBWmYZMVqhVJucYyM+BTGRPpTBYBweFCZlCGPbJB6FXg0f3NWaeSFyLx2oGgJMPo6NGj6OrqQk9PD6LRKC644AJ0d3fjmmuuQSwWw65du/DP//zP6O/vx8yZM/Fnf/Zn+NnPfoaGhgb+O370ox8hEAjg5ptvRiwWw1VXXYWf/vSn8PutB/rMM8/gnnvu4dlrK1euxCOPPMK/7/f78dJLL+GOO+7ApZdeikgkglWrVuGHP/xhpc/DESrxgMg8wVXS70aqwUYeI8eQqWETSblz1b5wx9NZ1EsqeeGVuRq2VUOfSsPpNipszjqVvBBJuZXoVaUkw+iJJ56Y8HuRSAS//vWvp/wdNTU1ePjhh/Hwww9PeE1zczM2btw46e+ZO3cuXnzxxSn/nopU0ldGZlPHShb1sEztE9UxcoycoZFS3kNQ7iYY8tvDhRnUh8UKdb1mGDHD0zRzAmyVdX6jCoTSeFaa4gcL0Ywq0KdOJBSbcIGKtDwsS0SiARIJlT4trHonahlsRGno0k2dFdBjJ/Ri8fkMhCTOVc9lpdmer4w1RyQqrBNcw1ZtoTQFnr1IvPH2akYlIkGZWp7KQnzyQmlee+lUJizxcxRJRXo4iUULvRb2DfoNsOL8qm/2KoXSUhkTmazp2jicJJs1rVAaeYyIchHhMVJNY8TTVCXUOym38CRROhFNijwq/w55ZK7mBPl6GMsq1TEC1H9eorAbzF45EJBh5AKWxqj0F1hqHSMBWWkyYusxjzUoVBltNkEBiQIya255ZYMA9MhMM02T1zFy89nbS16ofrgQhb39iVfmPRlGLlBuZ3DAlvUg8bSrWhkBCqU5hy6GUSVaHiuzU/xGX24PN5WRqR8UhT105eY6IVvDpiJsfQ4HfCU1RVcZMoxcoBKXLxNGy2kJUnl4Qo72yXuncFWRaTSIpJLwKhnxpVEjuSimCOzhnJoykkdEolPjXRGooO0SDRlGLlBJ+rlVYVotjVFY4oYa9+ApXFVkzi+RVGTES6rSnspkkVbAayEa/rwU7pfGxPiGUViSwQ1kV1dXDR5p8NCcJ8PIBUYrmEgyXzoxLUFkNpGl6SobmfWoRGGaZoU1t+R0QLfP/bBH0vUBPdqC2L3KbhehlKlhUxEv1pnzzturEZWkGsvcuCprCeJAgUcPnUhUpcZW6VhVkpksWCZ0Oa03ZM1VZqwZRqEIV3d00J2x+arCGlFt1a9VEL2Lxjtvr0bwhnsV1GBRrfK1zA3Vi7oNVZFZQFQUdoNGpXT9eFIdr4VIdJgTlYRWRaODh00kcQUqjouGDCMXqCSl14lQWiV1jGSk61MdI+ew9CTqLupsPvh9BoL+0g0QLo4VfI+VvD8qI7OorCjYnFAhhMm9+gq/QyLx4rx3fxZVIbFk+V2gZWl5Kq1eKis8kcpkkcp4T9CqKjqcdu3egXI8M7LmqteqXjN0EOTzzbnEFjEyiGig0xPJqELeOlGQYeQwduFoOa5Hy2Mk9qVLpCsNT8g5VdoXYy+dSFRFi7BJhf3ImP5HtHez0nGpig6CfJVaUuhwuBBJvIL9TFW89QZrQCJtCUfLSteXpOWJVWiAyOqx5VVBq6rosKhXWr5BlsbIiyEFQA9BvkrNe3UQq4uE6hgRFWN/WcpKNeYZD3IW9VDAB38Z1UtluduZ56Im4C1Bq6rUaKCPqFSML6uIZcKroTQNNnqVwpg6hB5FMurBAwEZRg7D4rFBv4FgGYXIZImvK83qkLXZWDWMvPPSqUxYg6q9lYrxZRl/Xp2rsgpiioS3pVBgc9alerwoVMoIFAUZRg5T+WlXrnC03DixrKJmXnzpVEZWSFQkLKuz3BOqtLBvheNSFVZYVUbGqShUahukQwsVkajkrRMFGUYOU2k8lk2+ZCbLmyaKoNLMAlmZGF4VtKqKDmGAijVGkrxiXm1do0N4VSmNkQYlL0TixXnv/iyqMqyMtNIbyAKFL75I70ylwlHZglavhSdURYcwgOV1LW/5kj5XFdicRaJDKE0lr4XMLgAqwu6TWoIQZTNaYXsLe50OkQLsSj1ZbENNZ02kMuIWhDiF0hxFhz5PlW6ClgeE6hgVQ7gKMhVFokNBTJHwdiweyhr2zp1ogqWZKe/R+3wGQrxyr0ADRNBmY/9dIvBqCrSq6HDaFWXEi9bMqLQ5i4Tdj8obvUrrhFULTN3nJRIv9rIkw8hh2Em8ktCQpZFQxwCx1xgSualSnzRn0aKOUf4dCpdZ5djyisnSw3lrrupgLPNwjgLPXodwtEjYAV2FZy8KMowchp8qKyhdz4wqlUJphmHYUr3FjUulirbVAJuX6ayJtMCQqEh4r8FyPUaSBOaVjktVaiRVCheJSkkaEUkaNlVJKPTsReGdO9EEEScbGToQEcJRGeMSYUgSxVMQEhXsURGFuAKPkkJpHtJaAFTgsVSqrYmsSs9eFN56gzVARBfoGl79Wh2NESDHhezFcvMqYw+JquohECa+ltVE1mNzVZZYXSQq6btqJHUnUBWVwpiiIMPIYcR4jCRojAQI6GS4kL2q21AVWeJ+kVRas4aHfNMZmKa4WmBenata6M5UKvBYZRojlcKYovDOnWhCTEBoKCxBPMpTLgWE+Eh8rTcyxP0iqThRIP9zppkrlCp6XF6bq/YDj0hDUiQiPPGi0KHkhUj4s/eQ3MH9WVRliKjQKiPmL8KTxTYckWm9vI5RiKaqU6iuKRGVrg+INeK9GFIArPc6awKpjJqGkUpGqawuACpimiY/oHsphEy7jcMkBHhm7KEAUQgx2CSWEVBhwasWVE/PrlRjFPL7YBi5/xapo/KuxshmSCrqBVHJKFX9YCESe9RChWcvCjKMHMZ6gQVkfyl22pWxIHhVt6EysgogiqLSuWoYhpQ2F15teGw3JFXd7JUSX0vqAqAidoG5l7IxvXMnmiDiBa6R4DGyPFmVGGziRbuUleY8YcWbYIowlq25KtBjJOAdUhG7ISnyMCYSlVLGZXUBUBE25wM+AwG/d+a9d+5EE0TU5QnzE734dP1KxiWjFD6vquohYZ/qqJ5VIyK8KsW76cHWCAyV+3+lMlmkszntkwpGqawuACqiUjagSNyfRVUGm0gi6hiJ1RhVHkqTka4f9/BmoyqqayTiAryIonVU2axNhOrBuarynLCPSYV1wjAMLUociMDKBnT/uYuEDCOHEZEWL9NjVJHBJkG069XwhMqEJehvRCJiTrBTvaiUavshRYXNWTQqC/KZF8swCr01blItKfterGEEkGHkOEJEzgHxL12ljTkBy6gSmq6vkKiyWlD5tJvKZHnKuJhQmpiN3v57vDhXZfRBFAU7INYE/DCYStxlZIj7VcSr6zMZRg7DG+5VcLKR4pkRkS0noTmnSmm41YLVAkK9TVBU2ES08ccOA6GAD36fGpuzSHQIpanktVBZkyWSBGmMCBGIsLB5KE1KHSN1TuG536Xeoud1VBZfiwqbiN7ovZqqz5CRcSoKFWudqWxIisSr67O37kYDeJaVgFCayI0rIaSOkdgUaLuglTxGzmGlZqu3qIsKm1gJDKJCad7cIBgyEitEoaJXOaywJkskXq0z5823WGFELKBhwWGATNbkPaNEhPhEbaheraqqOiqfdrl3oMK6VmHBRSxVqqMjAxmlOETB5oRKmVERhXV6IuFZ1h4rp0KGkYOYpikmlMbF12JOIwlBGTWiewQV6EkUyTapBnjlaxXDJoJCVqL1cF49OTNUzkqzjFJ11giVDxci8aqn1Ft3ozipjIl8HbIKCymKPY2IyqgRPi6PVlVVHZUXdVHpwaJ1VCqGc0SicqaiiplRMhJRVISt0V7zlNJu4yB27U0l9YJEe4zYyxv0GxVl1PC4uqjaMB7NeFAdlfURojZB4eJrj4fS2JqjYpaVimFMlRMYROLVAwEZRg7CXuDKM2pEe4wqbwdi/3l7Y8FK8GpVVdWR0YtPFKI2QeFGvMd7+qkdSlNvc1bZ6yoSCqURFZPgQjVfRRk1oisTW21KKj2Fiw5PePOlUx2VF3VR4mvhc9XjFdplNN0VhYr6LpVrgYlExTCmCLz5FiuKuDCAnHYGles2xFbkVnHBqwasKsfqeQdiSTHeAeHia4/39FPZWFbxACWjbZOKkGFEVEzcVoOlEqzUWdGeGVG6DUHZcgKqcROlo8cmqNZc9brGiIVXVdzoVTxAyWj0rSIqhjFFQDuOg4jyzLATfTKTRZaluVWAVURRVKaPWtonojQsz5+6m2Clqdmiva6eN4wUNpZVbEtRLR4jaiJLVIzo0y4gZvNKCDJA2MKUzppIZyofF08F9aigVVV0SM2uuI6RYK+riMrxKsPeQRU9IFYYU53tTHRldVXx6uFVnZlUBYgSOdsz2kRsXqLcofafF7EgeLWqquqo7B3gm6Ao8bUoj5HHs9JEJ3yIxPLEq/PsRXcnUBXurfPYvCfDyEEs67qyxx7w+xDI1xsS4TESJV60G2wiUvZVFFVWAzJ68YmCb4KCSktQ5eviUNmLqKLwvUZwrTlV8Wo2prfuRnFEKvhFnupF1QsyDMOW0VT5uLy+2aiK3ZtimpVr2EQiKitNdBFLrxvxKnsRmXdaJY2Rys9LJNwo9ZhX35tvsaLEBYmcAcs7I8RjlBaTLQeITdmPU1aaKzCjwTTBmwurgugEBqp8XRxqF3hU7wDF12ePG0bsffRaEV7acRwkobjHSIQBIrJwnihROFEa9nmg2kYo6h0SfaJXsS2FSFQOpfFnH1JnO1M5s1MkXm3bpM5MqgJEKvhFnnhF1qKQYbB5TdinOiG/D6wwu6h0dlGIWoitcCE1kS0GlZuiqpgZpbIhKRKvhpC9dTeKIzI0FBZ4IhE5uSMCXe5e32xUxTAMSzyqmMdI1FxlcyqZFlMLLMZ1et5cUlX2gMQEaSRFIrrRt6qoGMYUgTffYkURK74WdyJJCMr0AeyiVgEeIxa/rjCLjygdVU+8ojQNomuBeT2Uxt5BUTXKRKJiOEfV90ckmayJVCZ3qCDDiCgbkUI1oeJrkaG0/LhiAhYEFdNwqwVVxbaismBqFK0FpiqiDUmRxBUs8Khy3SdR2N8blZ69CLx1N4ojMpSmrvhapMfI25uNyqjaHVzUO2SvBSbiHkUmVqiI6KKyIlGxQr695YxqJS9EUWAYKaTvEkFJq8ujjz6KCy64AI2NjWhsbMSyZcvwq1/9in/fNE2sX78eHR0diEQiuOKKK7Bnz56C35FIJHD33XejpaUFdXV1WLlyJQ4dOlRwTV9fH7q6uhCNRhGNRtHV1YX+/v6Caw4cOIAbb7wRdXV1aGlpwT333INkMlni7TuLSHc7F18LDAOI8GSJFLV6VdinA6LT2UWREFjlWKRXzKs9oxg+n4GQX5yXWhTpTNYK5yi0ObO1NGuCj89rsDU+FPDBlz9keIWS3uLZs2fj+9//Pt555x288847uPLKK/H5z3+eGz8/+MEP8NBDD+GRRx7B22+/jfb2dlxzzTUYGhriv2PNmjV44YUXsGnTJmzbtg3Dw8NYsWIFMhlrAV61ahV27tyJ7u5udHd3Y+fOnejq6uLfz2QyuOGGGzAyMoJt27Zh06ZNeO6557B27dpKn4dUZGR/iaiToeq4Eh7XbaiM6AKIohA7V8U0kk1nskhn1ducRaNimwv7AUwlj1GBh00xr6sorLC29w4DgVIuvvHGGwv+/7777sOjjz6K7du3Y9GiRfjxj3+M7373u7jpppsAAE899RTa2trw7LPP4q/+6q8wMDCAJ554Ak8//TSuvvpqAMDGjRsxZ84cvPzyy7j22mvxwQcfoLu7G9u3b8fSpUsBAI8//jiWLVuGffv2YeHChdi8eTP27t2LgwcPoqOjAwDw4IMP4tZbb8V9992HxsbGih+MDBICy6eLLDlvtVkQNy7SbehNjaIeI7FeVzHGn31z9vJcDQf8GEJaKWPZPj9VStIIB3IlL0wzn9lZ4/aIxOPVjDSgAo1RJpPBpk2bMDIygmXLlmH//v3o7e3F8uXL+TXhcBiXX345Xn/9dQDAjh07kEqlCq7p6OhAZ2cnv+aNN95ANBrlRhEAXHzxxYhGowXXdHZ2cqMIAK699lokEgns2LFjwjEnEgkMDg4W/HMSoXWM2GlXMQNEZIFHr/bh0QEVWxoUeGaEFiOt7B5V3ZxFI8rDJpKYTXhtGOqEc0S3R1KRhILaLlGU/Bbv2rUL9fX1CIfD+PrXv44XXngBixYtQm9vLwCgra2t4Pq2tjb+vd7eXoRCITQ1NU16TWtr65i/29raWnDN6X+nqakJoVCIXzMeGzZs4LqlaDSKOXPmlHj3lSGlkKIAj5HQitwhcRsqW/TCHg5PqIroAogiEO2ZEWX8cY2eB7UWdlTMVBSpORON12sZ8f3Mg+tzyYbRwoULsXPnTmzfvh3f+MY3cMstt2Dv3r38+6db7aZpTmnJn37NeNeXc83p3HvvvRgYGOD/Dh48OOm4RGOJnMX1SlMuK42FJ4T0SlN30fM6IrViomCGMiDGMyNqo6+WeWqVCFFpTqi7OXu9llFMwTIJoij5jkKhEM4++2xcdNFF2LBhAy688EL83d/9Hdrb2wFgjMfm2LFj3LvT3t6OZDKJvr6+Sa85evTomL97/PjxgmtO/zt9fX1IpVJjPEl2wuEwz6hj/5wkLiGjRkRlYpFp8ex3sAWrEkQ23SVKQ8UWEHbPjIiwiaiNvlqaHavoMVIxVZ9heYzUeYdE4tUGsoCAOkamaSKRSGD+/Plob2/Hli1b+PeSySS2bt2KSy65BACwZMkSBIPBgmt6enqwe/dufs2yZcswMDCAt956i1/z5ptvYmBgoOCa3bt3o6enh1+zefNmhMNhLFmypNJbkoZI16OVri/QMyNgXFYIprJxZbMmklTHyDVEasVEITpsIjqU5vV5qqbHSN3q+FyTpdA7JBIVK46LoqSstO985zu4/vrrMWfOHAwNDWHTpk147bXX0N3dDcMwsGbNGtx///1YsGABFixYgPvvvx+1tbVYtWoVACAajeK2227D2rVrMX36dDQ3N2PdunVYvHgxz1I777zzcN1112H16tV47LHHAAC33347VqxYgYULFwIAli9fjkWLFqGrqwsPPPAATp06hXXr1mH16tXKZqQBYkNWYUEeI9M0pRR4rDQEY4/Le/HFUx0VxdeiPTOijD8vbxB2RHqpRaFyo2lVi6SKwst15koyjI4ePYquri709PQgGo3iggsuQHd3N6655hoAwLe//W3EYjHccccd6Ovrw9KlS7F582Y0NDTw3/GjH/0IgUAAN998M2KxGK666ir89Kc/hd9vTexnnnkG99xzD89eW7lyJR555BH+fb/fj5deegl33HEHLr30UkQiEaxatQo//OEPK3oYskmIFF8L8hilMiZYD02hBR4F6TZyv1O9Rc/rhBVc1EX3IxMVLhRZIFVlRHmDRcLD7QpqjCwdqDqGpEi87CktyTB64oknJv2+YRhYv3491q9fP+E1NTU1ePjhh/Hwww9PeE1zczM2btw46d+aO3cuXnzxxUmvUYlM1kQyI84wEtWs1b7ICRVfVzguVkk46Dfg93Cmj6qoGAYQXddKVBFLkXXAVIZrZlSaE0n1PUYqhR5FIlKCoRrefpMVIiHcABFTnp8tcoYBXvK/onGFxHgavPzS6YCVXajQJijYMyPKA1ItzY5VzLJSudaZ1xvJ8hCygkZppag3mzyK/eUQI3IWm2osKtOnRlQ14fzPez08oSoqaox4PzJBnhlh4usqyZ5UsS6P1ZZCvXVCZBFeFRFZfkY1vHdHisImUcgvpggczxCpWOQsOtMnNy57zZlyUPkkWA0o6R0QrGkQZcSLLJCqMkr2SmPhVQW9Fip6XUVihZDVe/aVQruOQ4i2rq34tRjPjKjJLSquLlpoS5SGkhlIgj0zolpcVMtcFVm8VRQxhUPuKhqSIuHFNT0478kwcgjxwlGxfZ7EbTaiTuHefel0QGSdLFGI9syIMv6qpdlxWElBPhNfq7eViWz0rSJe9up7744UJSbaABH00ole1EU35vTiS6cDKmqMhKfrC5qrMQ9rLeyoGBpSOUlDxXC0SBIe9pR6+01WiITgF1h4A0zBuo101kQ6U/4CGqsS3YaqqFj5WrwRTxmUpaCimFjlAo/VkpXmxTWaDCOHENknDbBCHZUaIKJrsNjvr5KTJc9K8/hmoyphBXulifbMiNq4vLxB2FHTY6Ru9qooDZuqiI6CqIT37khRxLczsBaCSsJpwrVPNgOrkk2VQmnuonIoTZRnRphOjzUy9fhcVXFOxBQO51iZw+oYkiLxcsV3b7/JCiE61VhVA8TnM2yl8CsYV1rdBa8asIofqrOoCw+lCfKKVU26vqCisiJR+QBVLZWvvbhGqzebPIro0JDPZ/BK1ZV5jMQv6iJOltUSnlAV9tyT6SyyrJmey4jOghGlo6oWPZyoBtEiUVnfJSpDV1W8vEaTYeQQMk42IkIBCQlNGEVsOAmFT4LVgKhQrUhEZ8GIq7lVJZWvgyp6jNRtSyHCc64yKnvrKsV7d6QoosXXgBjxqIzJLcJjVC2ncFWpERSqFYm0rDRRbXU8PldFhR5ForIAWFQRXlVR2VtXKerNJo8i41QpIutBSihNqMHmvZdOBwJ+HwL51jWqFHkUX4xUbM0tL2ot7NQo6TFSd53wcuVr0zS5/lBFb12lkGHkEKLrGAF2V62AtHihGiMB4muuyaIp6haqtQWJCfbMiKq55WWthR2VSzio+OxVbLorilTGRCavPVTx2VcK7ToOIVPkLMZjJCGUJmBcXjyN6IKVmabGRijadS+q5lbCw60R7NgPPKaphiCfGe0qeuu8XPk6ZrsnFZ99pXj7TVYIOaE0ASErKeJrNcdFlIZqlXtFv0N2b2QlmVaxpHe1FnbYfMiaOS+b22SyJpIZdb11KnrYRMHuye8zEPQbLo9GPGQYOYQc8bWiGqP8xhWrKJSmrou8WlDtxJsQ/A75fAZCvFmuACPe43PVXnFchTkRV9xroaImSxSW99YHwyDDiCgTGZkrIjQgMkNplZzCvZwKqguqVTqOSwib1FSYUp3KZG1aC2/P1QIPmwKbvf0zU1GLaM9KUyX0KIqYx6UO6s0mjyJjUefi6wo8RgkJwlERab3kMXIfEeJ+kahYjNT+c16fq4Yhpqq9KNjmHAr44POp57VQzZAUCQ8fe3TOk2HkEDJ6+gjxGEkQjooo8FgtRfNURqWWBqlMlutaVNLpsZ8zDDW9FqJRqZqzjMOmSAqKpCrwvESico86EXj/TVYEK8tKhgEiwDMjRXxNHiOdUSmUJsszYzX6rMxjFPao1uJ0ROgaRaF6uD3o98GvWC0wUciINKiEmjPKg8gwQHjWQ0Xiaxl1jMSl63v1xdMBUb3ERGAfg0jPTKVztdrmqVoeI/W9Fpbh7f7zEgl5jAgh8EJkAsVqvHeRouJrIen6Hn3xdEClFhCyPDOVGn885OvxVH2GiGr7olC5uCNDxCFRRbjGiMTXRCXEkjLE1wILKSqUrp/JmkjyOkY0Rd0irJB3QHSqPqNi8XXa29k5p8OrOSswJ3SoOK6SWF0k3Cj16PrszbtSkISUjBoRHiPx/W4qTde3n0ZVXvS8jkqVr2UJbSstYmn3ZFUDKnmMVNcYAd5tJOv1zgTqziiPISUrjXuMynvp0pksrxwrw2NUaXgi97u8+eLpgIria9GbYKUJDDp4LUSiUjV0HXQuXvUY6aDvqgQyjBzAnmosI12//DCAHAOkUm0K+7mg3+BZHYTz1Ci0CcoyQCrVgMQ08FqIRKVq6DK88KJRKRwtEh30XZVQHW+zyxRUaBW4gLLU/3IXKSagE12DRVimT5UIWlVFpbAJW4hFZk8CIryb3t4gTiesUGhIh825RqHyBiLxuqeUDCMHYC+waAOEeZ+YgVMqdneoyEyfcIWbjdfLzeuCiAKioohLEnsy47vcjSvh8ZDC6agUGtJhc1apvIFIdAhjVgIZRg4Qt2WkiTVAxHhmRE/uSKUhPjKMlEClsIksz0ylxp8Om7NIVBIT6xDGVKkgpkjiSfEFi1XCm3elGLKs60o9RrJc0ZWekmSUNiBKR6UaLFZdK9XE1+pvziJRy2OkvteCPEZ6Uh1vs8vIPu2Wb4DIyvSpzGOkg3agGlApA0lWyErUXA1XiR5OpY1eB2+dSoakSOKSNH+qQIaRA8hy+VYaspKl5an0FO7104guhKsglFZp1pAOm7NIKtVkiUQnj5EKoUeReH2NJsPIAWQZIDyUVqmWR/QpPL94prMm0pnSFwQrfu3Nl04XVGoJIsuLyE/05er00lUWSlOqf576z94qwuv+OySSmKSCq6qg7ozyELzehmB3u90zY5pmyT8vW2MElFd80uunEV1QsYmsyHIXgIBaYFU2V1VKP5dVwkEkYYUOFyKJJ+XsHapAhpEDSAtZ5X9f1gSvYF3SuCSJnO0lCcpZEEhjpAZWGMD9RV1WbauaQGXGX6LKQmkqFSzUwSi1aoG5/7xEYvUI9KYJ4c27UgxmgIhePO0LAisJUAqyDDafz6hIdBjzeCqoLlSD0FZcokB1zFW1in6qb5Sq1FZHJDHyGBGVIis0FPT7eMuMcjQSMk9clWyqOpwEqwGl6hixE6qkUFq5J/pqq3zNxdcKGMs6FNe06hi5/7xE4nW5AxlGDiBTJFhJLSOZVn8lm6rXXzpdqFRELxJZfbFE1TGqlnR9Lr5WwmOkvrcu7FGPkddDyOrOKA8h1zOT+wjLyUyT2XqjEhcyNyQpK81VKhXRi0TVUBobV7VkUKrkMdLBWxeuUMOmIulMlmtavXp4JcPIAbhnRjEDRKZnppLO7F5PBdWFSkX0IpHlHahkngK2dH3BPdxURSWPkQ41pFRKYBCF/ZDk1QNBdbzNLmMtnuInUSW1jHi9INVCaRLHRRSPz2cgpEjlXlmVdu1i4nJKXng9pHA6YYU8Rjo0m1YpgUEUdtmGyKboKuHNu1IMnhYv0WNUzkIVkxiyqqTBrQ4u8mqhRhHxqKx0fTZPsyaQyqhTC0xVVOmfl82aSLL+eQpvzpUWEFURu2ZWZFN0lVB3RnkImRqjSjxGUkNpFZyUqm2zURlV0o2tsImcJrJApUZ8dSylqvT+sn9WKq8TkQoOrqpSDVnD1fE2u4zM7Anm7akkK02OwSaijpF3XzxdUCUUkEjLmRMhvw/s0FvqXDVNs+q8m/byBuWEHkVhn48qP3s2X0eTaZdHIo5qyBomw8gBZC6eNRW4arnlL6GQooisNC+/eLqgSq8n7jESHEozDKPsTKtUxkQ2bxuovDmLhImvzTKr7YuCbc4hWy03Fam0n6WKeL24I0CGkSPItLAjlXiMpBpsambLEaXBez25qJEwTVOq0DZcpnezMJxTHUup3TB1U3emSwiTzdd4Kots1j0Pm0hYVhoZRkRFyAwNiTBA5BZ4rKRVCU1Pt1GhkWwqYyKT31TkvkOl3SPL6jSMnOeiGgj6DfjKDD2KRBevhf1w53YCgyiqQepQHW+zyyQkWtj2E0mpyGoiC1RYX0mTRa8aUEF8bfeGSi0tUaJXzB7e82p2zukYhqFEyr4szZlo7PPVKzqjapA6kGHkADJFzjUVxLBlTvBy0/WzWZMbkl5+8XQhXGEBRBGwuR3wGQhK8MyUa/zx+mSKh3NEo0IjWVmaM9HYG2p7RWekSxizErx7ZwrhTMiq9IwauS1BygvB2A0p1U+D1YAKjWRla86sflalzVV24KkNBYSPSWWUMJYldhMQjeXV94ZhVA3lVMgwcgBHmsiW+NLZdRtSQnxlnsLtYRPVT4PVgAoF/WRvgjVl1ubRoYmpDJTwGGnUiqU2yFL2vWUYedmjr/6s0hzZoaFyTyN2Q0qlAo9sXOGADz6F03CrBRXE17IX4nJDaTq0pJCBCrWtdNIhVlJrTkXiJL4mKkV2aKjcjBpWl8bvMxD0izdAyg3BxKt0s1EVq8aPm3oS2YYRE1+Xl5Xm5ZPzeKhQ/TqukQ7Ra7WMKF2fqBjZoaFyTyP2U7iMjJpyywjIzJQjSkelrDRpobRgecaf5TGqLo1RJQkfoogn9Qlj1npNY6SRt65c1J9VmsOs65Ck0FBNmRkPsgV05WpTqiF+rRNqhdLkLFfcK1aix2g0KXdcqlLL21wo4EXUwLNcQxoj7Sjpjd6wYQM+85nPoKGhAa2trfjCF76Affv2FVxz6623wjCMgn8XX3xxwTWJRAJ33303WlpaUFdXh5UrV+LQoUMF1/T19aGrqwvRaBTRaBRdXV3o7+8vuObAgQO48cYbUVdXh5aWFtxzzz1IJpOl3JJ0ZKbqAxVojHicWM6iHi5zQ62GjAedsHpjeTcrreKwb5XN1dpwzkPmpmaGHbjCGiRoeC2UJvugogIl3dnWrVtx5513Yvv27diyZQvS6TSWL1+OkZGRguuuu+469PT08H+//OUvC76/Zs0avPDCC9i0aRO2bduG4eFhrFixApmMNXFWrVqFnTt3oru7G93d3di5cye6urr49zOZDG644QaMjIxg27Zt2LRpE5577jmsXbu2nOcgDdmLZ9nZX6oKWqtA2KcT5aayi4TNIVlp8TRXS4NlWY24WLCQh9w1ePaVtG1SkUQVHF5LWmm6u7sL/v/JJ59Ea2srduzYgcsuu4x/PRwOo729fdzfMTAwgCeeeAJPP/00rr76agDAxo0bMWfOHLz88su49tpr8cEHH6C7uxvbt2/H0qVLAQCPP/44li1bhn379mHhwoXYvHkz9u7di4MHD6KjowMA8OCDD+LWW2/Ffffdh8bGxlJuTRqyi2GVmyHinMFWoig8XZ2ncFWppEmxKEYlaxrKrmNUBRvEeNQqsNFb6frqP3sVnpdIqiEbs6LdemBgAADQ3Nxc8PXXXnsNra2tOOecc7B69WocO3aMf2/Hjh1IpVJYvnw5/1pHRwc6Ozvx+uuvAwDeeOMNRKNRbhQBwMUXX4xoNFpwTWdnJzeKAODaa69FIpHAjh07xh1vIpHA4OBgwT/ZOKXlKVljlJSbWVC2oLUKhH06oZL4WlrYt8I6RtVmxDOxuasaI8lzQiQqiNVFUg1rdNmzyjRNfOtb38LnPvc5dHZ28q9ff/31eOaZZ/DKK6/gwQcfxNtvv40rr7wSiUQCANDb24tQKISmpqaC39fW1obe3l5+TWtr65i/2draWnBNW1tbwfebmpoQCoX4NaezYcMGrlmKRqOYM2dOubdfNLLd7cwTVa74WtVx6ZBtUg2oULNGfro+SxRQy+uqKkqIr9P6bM5e0xjxdiwaPPtyKTtof9ddd+H999/Htm3bCr7+la98hf93Z2cnLrroIsybNw8vvfQSbrrppgl/n2maBWnj46WQl3ONnXvvvRff+ta3+P8PDg5KN474Ri/J5cteumQ6i2zWLDrzTbrGKH+/6ayJdCaLQJE9rqr1FK4qKtSsUVV8XbUaIx4aclNjRKE0t6iGA0FZx/K7774bv/jFL/Dqq69i9uzZk147c+ZMzJs3Dx9++CEAoL29HclkEn19fQXXHTt2jHuA2tvbcfTo0TG/6/jx4wXXnO4Z6uvrQyqVGuNJYoTDYTQ2Nhb8kw3rQC1r8bT/3lJ0ILKL09lPE6WcxKuhqqpOWFlpClQ5ltYSpLxw4WiVzlUmgh9xcaPnB04Nnr3nQmlkGBVimibuuusuPP/883jllVcwf/78KX/m5MmTOHjwIGbOnAkAWLJkCYLBILZs2cKv6enpwe7du3HJJZcAAJYtW4aBgQG89dZb/Jo333wTAwMDBdfs3r0bPT09/JrNmzcjHA5jyZIlpdyWVJzyzAClnUhkLyxhWw+jUjacanjpdKIamshaerjyxNfVNldV8IDE8p9VrQbP3mtZaZYMw7tyh5JCaXfeeSeeffZZ/PznP0dDQwP32ESjUUQiEQwPD2P9+vX40pe+hJkzZ+Ljjz/Gd77zHbS0tOCLX/wiv/a2227D2rVrMX36dDQ3N2PdunVYvHgxz1I777zzcN1112H16tV47LHHAAC33347VqxYgYULFwIAli9fjkWLFqGrqwsPPPAATp06hXXr1mH16tXKZKQB8sXXPp+BUMCHZDpbkmdGdoivYFxlGEZejl/rhAria9mu+9pwXjOTKi00VA0hhfGIcI2Rm6G0dMFYVIYbkh7xGLF5r0MNqXIpyeR79NFHMTAwgCuuuAIzZ87k/372s58BAPx+P3bt2oXPf/7zOOecc3DLLbfgnHPOwRtvvIGGhgb+e370ox/hC1/4Am6++WZceumlqK2txf/+3/8bfr/1oJ955hksXrwYy5cvx/Lly3HBBRfg6aef5t/3+/146aWXUFNTg0svvRQ333wzvvCFL+CHP/xhpc9EKLLT9QGbuK8Uj5EDWR1W1/ISDDaN6pNUA+X24hOJ7ESBOpZllSgzUaDK5qoK4mudUsbLWZ9VJZs1+Vqgw7Mvl5I8RqZpTvr9SCSCX//611P+npqaGjz88MN4+OGHJ7ymubkZGzdunPT3zJ07Fy+++OKUf89NnHC31wR9GIiVdqp34rQbCfkxGE8rNy6ieKwGq5lJExtkIjs9mG30pRYslF3VXlVqFUjX1+nZe0ljZNca6vDsy8W7QUJFcEJMXE71aydCVuW0k6hW3YaqsOKHpgkkM+54jbieRJbHKFyex4ifnKtsrirhMUqyaujqP3svpevb78HLcgcyjCTjRM2Hck4kTqQaszAMC48Vg+wMJKI07CFgt8JpXE8i6R2qs3mMpvKKF4xLo3COSNxO1zdNE6MaHaCYh80LoTR2+A75ffBLaIquCmQYScZJz0xJWh6HQnwAZaXpTMjvA1v/Sq1iLgrZ7xBripo1SytLoFM4RyRcfJ3KlGRIiiKRzoL9WR2MUqbj9JLHyOsFeL19dwrgxEZfjqvWCS0P70FVSn0lMoyUwjAM1zUlsr2b9rk2kijOC5LNmlXsMcrNB7NEQ1IUds+LDusE9+h7wGNULUVNyTCSDN/oZWZ/Mc+MQnWMgAo9WR6ukaEbLHQyXKTRIBrZWh6/z+DvULHGX7WIUMejHENSJDFbOKfYivpuwgzJRL47gc4kNGrFUgnqzyrN4en6Ems+MOu9FM+ME2GAmjLaSVRDg0LdqM+HmtzYBNOZLBd9y5yrdSV6xapFhDoe5RiSIhlN6hXOsc9b3cNpvJyKx+e8HjNLY5z0zJTiqnUio4YbbKQx0hqeteXCJmgvWirTfc+KPBabss+9FgFvi1AngguKXdjo2XrCxqA69i4A2htGrLijx9dnMowk44hnpqKQlfystFJ0CPEq1W2ojJuhNLuxb99gRFNqkcdqFV4z2H276THSZY3w+QzPFHlk1c51aMVSCWQYScaJdP1yxNfOGGy+gr81FalMFqmMKX1cRGnUc4+R84aRXYwvs7hkqUUeqz1JwKpl5J7GSKdnz/ul6e4x0qh+VCWQYSQZJxbQUtPiTdN0uIxAceOKV7FuQ2VYOvtwiQUQReBU5lddicZftWakMbhh5MacYF4LjZ69VzxG1TLvyTCSjJPp+sUaIAmHdBulpusz75phyA2bEKVRz/Q3LobSZHsHuMeoxFBatRrwvISDCx4QHTdn7j3X3GM0WiUhZNp9JFLomZGZrl+am7bAMyPRALE8WcVpjOwZfG705CLGh+lvSu0lJgKn9CRWVlpx9zhaJSGFiXCz+rWOm7ObYnWRUCiNqJhkxqrQKlPFX2pWmlN1QKzO7KWNS6eTYDVQ62K6vlNaHp6VVqTHqNo1Rrz6tQuhIR2LDHovlKZHRmC5kGEkEftLINPC5qG0IrO/Yg7VASk1W67aM31UhYXSXNGTOGSAlOoxckKjpzJuNpLV0WtRE/KGYaSjt64cyDCSCJtEQb+BoETPDK8XVKLHSPaizqpXJ4rUGFVLHx7dYGEAN9P1ZTcVruXhwhLT9TXanEVSW6IhKZJRDY3S2jIyh1XEqiGlz7MvB9qBJOKUdc21PEWLnJ1Z1CmU5g3qXSzwaHmM5C5VddwrVmJWWpUa8SqE0nTanCOe8Rjl3g+vr9HV+VY7BHsJWCqwLErVGDllsEVKzPSJV4mbVjfcLPDomMaoRI9RtWuM6lzc6HUMuZeaIKMqFEojKsYp67rUl86pTJ+GmtKymapdt6EqbvZKcypkxT1Gxc5Vh0J8qhIpsbecSHQUAPMsPs0NIwqlERUz6tAkipQpcq6TvLDUh4MAgKF4qeEJb790uuFmrzSnjGXuMSq2jlGVz1U3K1/r6LXwSlaabu1YyoUMI4nwWHhQrgFSaoHHEYc8WfV5j9FwsYZRlbx0usG8Ka6Irx3LSiux5IWGOheRuJmVpqPXwisaIx3DmOVAhpFEWOhBtVCa5TGSbBjlPQ3JTLaozDR7gUdCHUptlyES5+oYlRf29foGMRHuNpHNfUY6hdy9ojGKcaNUnzBmOZBhJJGYU6G0/O/PZM2iDBAWLpAdo6+3ic6L8RrxasJhfRa8aoAtgqlMcfNLJE657kv1gFS7Ho4Zy66Ir/OSAZ08Rl7RGFEojagYpyaR3QApRs8zmspdI9tj5PcZ/G8UE4YZdUj7RJSGfZ44XeTRqfCq1SuNwr7FwNP1U24I8vVLGfeKxqha5j0ZRhJxqp+S32egIW8cDcZSU48r4VyMnumMijHY2KZEHiO1CPh9vFaW0zojpytfJ9JZpDNTJzFUe7o+97B5uBq6SLwQSktnskjm341ajZ59OZBhJBF2snEiHttQggFihazkj4t5s0oZF3mM1MOtRrJO90oDiusYr+PmLBKWUOKOxkg/r0WtB8TXdqNOp2dfDmQYScTJtNLGSC41fjBehMeIG2xOeIxy4yrG0zDi4LiI0qgLl5bOLgqu5ZE8J0J+HwI+A0BxXhCnxqUqEZtmJps1Hf3bWmelaewxYkadYQDhgLdNB2/fncs4mdJblsfICU9WmPXZKj7EJ7tSOFE6pWpwROFUerBhGNY9FuEVq5a05Ymwr2nFtiISQSqTRSqTM8R0evZe0BjxZKKgH4ZhuDwauZBhJBGnNEYA0Jj3zBSlMXLQM9NQQi0j8hipS71LKfusaKkTmyAvS1CMx6jK6xjZPw8nw2m6hnO84DHSMYRZLmQYSYRpFZwoXV9aKM25Cc41RqVkpZHHSDnquOfPnVCaE3O1WI+RaZpVrzHy+QyrlpGDc4IZpD4jF/7UhYgHxNfV1ORbn5mlITEXPDPFhNKcagkClFb9mmelVcGLpxus+rVXQ2lA8YUsk5ksmKymWjVGgC0zzcGU/ZhNBqBTOIfN32Q6i4zDmixRONXJQQXIMJKIk56ZUkJpToasLI0RZaXpjBtZadms6WghRUtHNfmpPp600vmr1WME2GoZORhKY39Lt8Ka9j1AV68Rf/ZVcBggw0giTnpmyhNfq1PHyDRNy2CjOkbKYWWlOWcYJdKWAeLEXK0LFecxYhtbwGcgqFE4RzRupKA71U1ANOGAD8zBpasA2y6+9jrV+1Y7gKPi6yI1RqZpOpqVVh/OjWsqwyieysLMe5jJY6QeVijNHaGtIx6jIksSVLu+iFEbcr6Wka7ZgIZhaJ+Z5qQ0xG3IMJLIqIOl65nHaHAKAySZsWLcTnhmeFbaFOn69hCNboteNcA2QSc9RswACQV88Pvk60nqeGhoCo9RFYUUJqO2yOclEifXVNHoLsCmUBohBCfdvsVqjOwZJE64RLn4eooN1d6mxOfAJkiUhpWu713vQLEekFhebFztBnypjXdFoLO3LlJk1qOqUCiNqBh7ITInVPzFaoxGbafwgAP6CC6+nmJcIw62TyFKp64EEb0onO5HxsKFUxpGSf26u8sg4mIoTcdnH40UnyCjIjo/+1Ihw0gS9sXCkay0IjVGow6nxBftMcobRnUkvFaSOp6x5XwozamwSbHhQicz5VSmlmtmvDsnRMIMowFNDSMKpREVw6zrgM9AyIG+Mg02A2Sy3kVOp8SzEMxU2qcRHkojj5GK8Kw0F7wDThkgRXuMNA7niMQKDTmfrq/js59Wq7dhZIXSvL9Gk2EkCadFgkxjZJrA8CQnuBGHx9WQz0pLprNITNJTiXuMquA0oiNuFHh0uuAn22yn0oDEq6g1wmSwOeFklpWODWQZzGPUP6qpYUShNKJSnEzVB3KnalYifzKdkVVbydlQGjB5GjT3GFE7ECUptiq0SFgbmYYaZ+ZEsb3SyGOUo7bIuk8i0TmcE42EAOjrMWKfs47PvlTIMJKEk7WCGI2RfNhqkhfP6UaAfp/VtXwyAfZoFWU86AgLvTopvmbzpd4hY7nYXmmkMcphedhcKPCoYTiHhdK09RjlGzpXwxpNhpEkeCjNwUnEwmmTeYxGXcj+shrJTmKwsbAJia+VhHlT4qks0pnsFFeLYZh7jIKO/L26IksSWIeL6l4+G13Isopp/Owt8XXS5ZGUBxV4JCrGjXgsL/JYhMfIyXEV00h2xGFROFEa9mzBUYcK1A07HEqrLTLzjn2/2udqkwtiYssw0u/ZT9M8K417SskwIsrF6ZAVUFzKvhuGEatlNKknizxGShPy+xDIF950SoA95HAora7IujxD+feLvW/VCgsN9Y065wEZ1Vjfpbv4mu8dGj77UiHDSBKjLmRPFFPk0ZVQWhG1jMhjpDaGYdgayTrjMWIGiGMao7ClMTLNiUteDMZy87jRIU+WqkyrzYmJ+0ec2+jjGmdGRXVP13dBN+sWZBhJIpZ03t1eTFuQkYQLoTSuMSrGYNNvwasW6rlh5IzHiBnS9U5lpeXfVdPMaakmgmnlnNI+qQoLDQ0l0kg5pDsb1bgdC/cYxVKTGt6qYhXX9L7Z4P07dAk3QmncYzTJxsXT9R1Mi2cbyKQao4Tz4yJKo9isLVGw+eKUZ8a+2U52j8wj65T2SVWitlCiU16QmMY1pJiHLZnOTmp4q8qoxvquUiHDSBJuiK+L8hi5kC1Xz/tsTaZ9Io+R6jgdSuMeo7Aznhmfz+D1vSYz4tn7Ve0ao4Dfx41Dp3QzTjcWFkldyM91erqF0zJZE8l0zpjT8dmXChlGknDDui5GY2R5jJz3ZFFWmt44Xf2ai68d9Mw01eVO9ZMJisljZNHEdEYOCbBjGle+NgzDFk7TK2U/ZstE1fHZlwoZRpJwI/urmKw0qyWIG3WMKCtNZ5jR6lgoLeFsVhpgbfQTGUamafL3q9o1RoCVsu+Ux4hXvtbUa8EF2JplpjGPvmEAYQd6f7qN9+/QJWIp50NDbKGerGGr0y1BAOvEP3m2HHmMVIeHRKdoCCwC0zQdr2MEWB6jUxNkWiXSWaQyOeFstWelAUB0CkNSJNmsiUQ+nKOr18IuwNYJewjTMAyXRyMfMowk4UYXaLZQD02qMXJevFjMhsq8EE6G+IjScDLdOJbKIJPNGSBOeoyaWW2ekfE3euYtMgwy4gFnPUb2cI6O4mtA3yKPOocwy4EMI0m40yuteI+Ro+NiWWmThtKqp0aGrjQ76B1gRrTPcHYxnjbFPbIaRg3hAHw+75+cp2Kag5oZe+HNmoCeGzRvC6JdKE3fbMByIMNIEq62BJm08jWrr+RCS5AJDKNkOotkvg4KncLVxQozyd8Eh2z6Iidd981TiK+HSF9UgGVIyt/omZeloUZfo5QXxdRMfB3XOBuwHMgwkgRvIuuC+DpXJ2P8lGo3Q2kTaYxiSf1d5NVAs4OG0TDP/HLWAJnK+KOMtEKmOSgmZoYR+5s6EtU0lFZNNYwAMoyk4YbHqD4UADtcj2eEpDNZXovCSc/MVHWMmL4o5PchVAUZD7rCMrYcMYxcyEgDLM3MRB6QQeqTVsBUWXwiYV3poxo/e137pfEWV+QxIirBjV5pPp9h886MffFGXRIvstN1PJUdt3UAL+5IwmulscJM8hd1N2oYATYd1RQeI8pIyzHNQfE19xhFQtL/liymadovLU4aI0IEbrkeGydJ2WdeLL/PcLQWhb3Nx3iZabwdSJW4aXWlqY5tgkmeMSYLpxvIMqYq8MirXpPGCIBNM+OAx4gZX17wGOlmGLkhDXGTknbHDRs24DOf+QwaGhrQ2tqKL3zhC9i3b1/BNaZpYv369ejo6EAkEsEVV1yBPXv2FFyTSCRw9913o6WlBXV1dVi5ciUOHTpUcE1fXx+6uroQjUYRjUbR1dWF/v7+gmsOHDiAG2+8EXV1dWhpacE999yDZNJ9UZs9ZOW065ELsMd58VjF4lqHa1EE/T4u2hsvxDdC7UC0gIVNsubkbWdE4EYNI6DQKzZeo0/SGBUyVehRJMyYiGqsMdLVY0ShtEnYunUr7rzzTmzfvh1btmxBOp3G8uXLMTIywq/5wQ9+gIceegiPPPII3n77bbS3t+Oaa67B0NAQv2bNmjV44YUXsGnTJmzbtg3Dw8NYsWIFMhkr1LNq1Srs3LkT3d3d6O7uxs6dO9HV1cW/n8lkcMMNN2BkZATbtm3Dpk2b8Nxzz2Ht2rWVPA8h2ENWToeH2El2PAOElxBwIWQ1jS+gYw1XnqpPDWSVJmjrjXVKsodg2CUDhM3TTNYc1+tKWWmFsLBWLJWZMOFDFF7yGOmmMaq2UFpJq053d3fB/z/55JNobW3Fjh07cNlll8E0Tfz4xz/Gd7/7Xdx0000AgKeeegptbW149tln8Vd/9VcYGBjAE088gaeffhpXX301AGDjxo2YM2cOXn75ZVx77bX44IMP0N3dje3bt2Pp0qUAgMcffxzLli3Dvn37sHDhQmzevBl79+7FwYMH0dHRAQB48MEHceutt+K+++5DY2NjxQ+nXOwhq5Df2WglE4WOa4C4UMOIMb0+hJ6BOE6OJMZ8b8SFEgJEeTTXhTAUT+c0ODPk/R23xNfhgB91IT9Gkhn0jSTHbMLMWGqMkBEP5FPnjZwXcSCWktqqY5BrjHQ2jHKG5GA8hWzW1KbsANUxKoGBgQEAQHNzMwBg//796O3txfLly/k14XAYl19+OV5//XUAwI4dO5BKpQqu6ejoQGdnJ7/mjTfeQDQa5UYRAFx88cWIRqMF13R2dnKjCACuvfZaJBIJ7NixY9zxJhIJDA4OFvyTATdAXCif3lI/ceaQmx3sp9eFAQAnh9Uy2IjScCozzapj5PwmyFP2xzlckMeoEJ/PcMwL0u+hdH3TnLxFkmpYobTqWKPLNoxM08S3vvUtfO5zn0NnZycAoLe3FwDQ1tZWcG1bWxv/Xm9vL0KhEJqamia9prW1dczfbG1tLbjm9L/T1NSEUCjErzmdDRs2cM1SNBrFnDlzSr3tonBTqDZ9UsPIvbLubFwnxxkX0z5ROxD1maoAoiiGXcpKAybvGD9IGqMxOJWyzzVGGnuMQgEfX391KvJohdKqI1+r7Lu866678P777+Nf/uVfxnzvdC+JaZpTek5Ov2a868u5xs69996LgYEB/u/gwYOTjqlc3KhhxGjOe2ZODI8NWbnpmWmpZx4jtcZFlIblMZLrHbA8My4YRpM0kqWstLE4lbLPDNWoxun6gJ790gZ5lmh1zPuyDKO7774bv/jFL/Dqq69i9uzZ/Ovt7e0AMMZjc+zYMe7daW9vRzKZRF9f36TXHD16dMzfPX78eME1p/+dvr4+pFKpMZ4kRjgcRmNjY8E/GbhZJZSF0sYLWcVcDaVNPC7SGOlDc93EGjaR8Kw0FwT5kzWSpay0sTiVsj+Q71Ons8cIsHSgOgmwT+TXbba/eJ2SDCPTNHHXXXfh+eefxyuvvIL58+cXfH/+/Plob2/Hli1b+NeSySS2bt2KSy65BACwZMkSBIPBgmt6enqwe/dufs2yZcswMDCAt956i1/z5ptvYmBgoOCa3bt3o6enh1+zefNmhMNhLFmypJTbEo6rIau8x2i8UJob7UAY0/MeoxPjhfgoK00bnOqX5laBR8Da6MfTGFHl67FMcyBl3zRNXvlaZ40RoGfKPotAsHXc65S06tx555149tln8fOf/xwNDQ3cYxONRhGJRGAYBtasWYP7778fCxYswIIFC3D//fejtrYWq1at4tfedtttWLt2LaZPn47m5masW7cOixcv5llq5513Hq677jqsXr0ajz32GADg9ttvx4oVK7Bw4UIAwPLly7Fo0SJ0dXXhgQcewKlTp7Bu3TqsXr3a1Yw0AIil3PPMMA3IeNlfzGBzo5Ci5TGabFzkMVKdqSpDi8KtrDTAeodO94Bks6Zr9ZVUhqXsy9TMxFIZpDK5ulK6e4y4WF0jw4h5+meQYTSWRx99FABwxRVXFHz9ySefxK233goA+Pa3v41YLIY77rgDfX19WLp0KTZv3oyGhgZ+/Y9+9CMEAgHcfPPNiMViuOqqq/DTn/4Ufr+1MT7zzDO45557ePbaypUr8cgjj/Dv+/1+vPTSS7jjjjtw6aWXIhKJYNWqVfjhD39Y0gOQwaiLnYjtWWmnp4OOJlwMpRWTLUceI+WZLGNLJG4aIBN5xUaSabCaj6QxsmBFHvsl6s5Y2CnoN7QvBMsMyQEHqoWLYDSZRiyflTa9SkJpJa0641WCPR3DMLB+/XqsX79+wmtqamrw8MMP4+GHH57wmubmZmzcuHHSvzV37ly8+OKLU47Jac6b2YivX34Wzm6td/xvs0U9a+ZOJOz0C9j7t7lRx8hK1z9dID9CHiNt4FlpEj1GpmlaWWkuiD0tr1jhRs8y0kJ+n6MtdVSHi68leozsGWlOl0ARTdTB/nIiYN6imqBPe6O0WOiILoFPz23Cp+c2TX2hBIJ+H6KRIAZiKZwcThQYRmxxcUO3wUJpyUwWQ4l0wYnb8mTRdFQdJ+oYxVNZpPO92FzxGE1Qpd2eKaf75iySaTxdX77HSPcwGmCFo44NjZUVqMhxpi+qC1fNvKdjjweZqGZQT38MANARrXF8TDVBP9eLnJ6Zxj1GVMdIeZihPRhPI5XJSvkbQ4ncJmgY7oR9J2okSxlp48OM5QGJhpEXahgxZk7Lrb89AzGXR1IcbL1uaagOfRFAhpEnaZmgyvSR/jgAoGNaxPExATaD7TQBNqsNU0caI+XJhTJy/y0rFGCF0dzxzNgbyWazlnyA1zDywOYsksn6IIrCykjTX+PC1l+2HqsOW69b6vR/9sVChpEHGS8zLZXJ4uhQ7kVkJxanYeG0EzaDLZnO8pPT7CZ3DDaiePw+gxeok7URulnDCChsJGtv20Aeo/GxF3gsRodaDl7yGHVEc+tc72Acmayc5yUSFnmoFuE1QIaRJ5k+TpHHo4NxmGZOOMo8Sk7DqnLbDbZDfaPImrmQSbWkgupOs+RaRm62AwGsRrJAofHHNEaUkVZIs00/OBiT0//LUxqjhjACPgOZrIljQ+p7jY4PVVcNI4AMI0/CM8BsBghz286cVuNaR2deSsBmsH1yahQAMLe5tmqEfbojOzNtiKfqu7cJjleWgPqkjU9tKIDWvP5k/8kRKX/DSx4jv89AW2POa69DOI15jFrIMCJ0Zrz2G0e48Nq9cNV4ovBPTuQW0rnNta6MiSgdJrYdryGwCOwaI7doGqeQ5SDPStN/cxbN/JY6AMDHJ+QYRqwYou5Vrxkd05hhpL4Am2uMKJRG6Mx4Bsjh/Avolr4IsNqV2BvcMo/RvOlkGOmCdI9R3L2yEoymurEp6CxMRKG0sTDD6CNJhtGghzxGgCXA1iEzjR2wp7skwXADMow8yPS6sZ3s2Qs4y6WMNGB87dOBk/lQ2vQ6V8ZElI7s6tdui68Bq5HsKVs42l7HiChEusdo1Fseo5lRfTLTrD5p5DEiNGY8j5HbqfqAFaO2a5+Yx+gM8hhpg+x+aUMu9kljzMy/J5/kDXfAykqjdP2xnJE3jPZLMoy8pDECgFmahNIyWZMfgEhjRGjNdN4EM4V0vggf1xgp5DHKZk0cYKG0ZvIY6YLlMZJcx8hFz8w5bbl2Ph8eG+ZfGySP0YScafMYyUjZZw19oxFveC24x0jxUFrfaBKmmSu22uQRb10xkGHkQabVhsASz5i1f8TFqtcMFuI7NZpEJmvi6FAcyXQWAZ/BxYiE+jTX5RbI0wt1ioIJbd0UOS9ozTW9/vDoEN/oqY7RxMxproVh5Lx9J4bFehIzWZN7Eb3iMeIaI8VDaewQ21QbQsBfPeZC9dxpFeH3GVbm0HASQ/EUTzWe6aLHiJ04TDN3AmRhillNkap66XRnfkvem3J0GPF8Y2KR/DHvpXEzvHp2az0MIye+PjGcM+R7B3KbWDWFFIqlJujn+sWPBafsD8VTYE4o7xhGuYPgyZGklHdIFCd5nzRveOqKhXYjj8LCVqdGkujJL+jRSNBV3UbA7+PG0cmRpCW8plR9rThjei1mNISRzGSx82C/0N+dymTxx+M5w+ictgahv7sUaoJ+Pi8/PDaEPxwbxnAijbqQH2fNqHdtXCrDBNj7j4s1jJi+qDbkRyjgjS0rGgkiEswVEWXrs4ocr0LhNUCGkWexp8YfVkBfxGDFJ08MJ/DJqdwCSqn6emEYBpbObwYAvLX/lNDfvf/ECFIZE3Uhv+stYqxw2jDeO9AHALhg9jT4XSqQqjrcMBLsMeIZaR7xFgG5d4h5jXoUFmDzBrJV5iUlw8ijNNuEziyOPUsBHY+9+CQLpZHwWj+YYfTm/pNCf+++3iEAwDntDa5XQmcC7N8fHcJ7B/oBAJ+aO829ASnOGdPleoy8lg3IDqqHVTaMRlhxx+oyjEhF6FFaxulnNdPFqteMFpvHiGWkzSWPkXYsPXM6AGDHJ31IprPCQhzMMDq33b0wGoOF8j48Ooz+fHf3T81tcnNISjN/Rj4zTbTHyGNVrxmsC4HKoTSruGN1hdLIMPIo9n5piVQuZV+FUNqsfHjkH3+zn6fgUihNP86eUY+m2iD6RlPYdXgAS+aJMRh+lzeMFrqoL2IsyHuM9vYMYiSZS174kznTXByR2syfbtUyymZNYT0ZvVbDiDFTg1pGVnHH6vIYUSjNozCx3PuHBngtFhVS4v/y0vk4Y3otDvfHMJLMZWOQ+Fo/fD4Dn5WgM/r9USuU5jZnzaiHz8hV4jZNYE5zBDMaqmuDKIXZTREEfAYS6Sx6B8V5QXYfGsj/fm+tE+ygekRhj9EJrjGqLo8RGUYe5bNnNMPvM7DnyCB2Hc4tLG62A2G0R2vwv75xCc7vaAQAtDWGURsix6WOfHZ+LpwmSmc0kkjz8Oq57Y1Cfmcl2DPTAOBTcyiMNhkBv48/r48E6YxM08Sr+44BAC4/Z4aQ36kKLJR2uG90iivdg2mMyGNEeIIFbQ34f/9qGRa0WqnFqpy4WurD2HT7xfjLS+fjezee7/ZwiDJhAux3Pu5DKl9hvRKYt2hGQ5g3qnWbBbaQHgmvp2Zh3tO34Vcf8FB5Jew5MohjQwnUhvxYemZzxb9PJZgm64/HR/D3r/3B5dGMz0nyGBFeY8m8Jrx4z+fw3T8/D9/98/PQ7mLV69NpqAni/75xEf588Uy3h0KUyXkzGxGNBDGcSGPlI/+BNz86ieNDCRzqGy3LUGKGkQr6IgbLTANIX1QMa5cvREt9CHuODKLribfwyckRZLLltwh59Xc5b9GlZ7cgHPCLGqYSzJoWwZqrFwAAftC9D9//1e94o2IV2PHJKYwmMwj5fWhtUGfvcAKKYXiccMCP1Zed6fYwCA/i9xn4f750Af76uffxQc8gvvIP2/n32htr8F+vXYgvfmpW0SJcLrxWQF/EYJlpIb8PizrcD++pztmt9XjmP1+MVY9vx67DA7j8gdcQ9BvonBXFNy4/C9csaiupDMMr+TDalee2yhqyq6y5+hzUBP34/q9+h59s/SP+8Tcf4aIzmjC/pR7NdUF0dkRxzaI2VzoDPLb1IwDAFz81C5GQt4zSqSDDiCCIsrmusx2fnd+MH3T/Dv9rxyGksyb8PgO9g3Gs/dff4qEtv0dN0IesmQtF/XnnTMyfUYdTI0mkMybOn9WIxnxPtH0KGkYXnzkdjTUBXHluq+c8FrJY2N6AZ1Yvxbf/V85gTmVMvHegH7c/vQNnt+ayGRPpLKbXhTC/pR7nzWzAn53bOqZWzsnhBK+sfsVCb+mL7Hz98rMwvS6ER7f+ER8dH8H2j05h+0dWQsOsaRF8+aLZCPp9SKSzWDq/GZecNV1qna8/HBvGlg+OAkBVHqwNU0YrZE0YHBxENBrFwMAAGhvpNEgQlZDOZOHPZyU9+R8f43+++gcM55t/ToRh5FL/w0Efft87jGQmi5/feSkuVChslcmaMABh6efVRCZr4kh/DP/y1gE89frHPBP1dHwGsHj2NADAwGgSZ7c2YG5zLf7pP/bjvJmN+NU3/9TBUbvHxydGsP2jkzg6mMDRoTh+vbsXJ0fGarUWz4ripk/PwrTaIMIBP4biKQzEUpheF8aCtnqc3VrPk1pM08SBU6P45OQoegfiGE2mMaupFrObIqgLBRAO+tBUGyqoRfY3z72PTW8fxDWL2vD4f7rIsfsvBZn7NxlGZBgRhBT6RpLYc2QQAb+BZDqLV/cdw+Y9RzEYS6G5PoRM1sShvsIaLs11Ibz+N1eiJkjeGa/RN5LEf/zxBHyGgZDfh6NDcXx0fARv7j+J3YcHJ/y5O//sLPzXa891cKTqEE9l8G/vHcb2j04iHPAjlcnil7t7EE9NreGb3RRBRzSC3x8b4m1VJiIU8GHxrCgWtjfANE08t+Mwkpks/tfXl+GiM9QUvZNhJAkyjAjCXY4PJbD78ABgAHWhABa01qNJkYw0wjkO98fwzsenEAn6UR8OYPPeo/jXdw4imcniF3d9DufNpPWZcXI4gWfePIA9RwYwksggnsqgoSaAhpogjg3F8eHR4TFeplDAh/nT6zBzWg1qAn4c6h/Fkf44YskMEukMxtPHL5nXhOe+cYlDd1U6ZBhJggwjgiAINRlOpDGSSKOtsboyokRwcjiBPxwbxpGBGM6aUY9z2xsnbNtjmib2nxjBewf68cnJEQT9PkRCftxwwUwl2khNhMz9m8TXBEEQhHLUhwOoD9MWVQ7T68NFF2U0DANnzqjHmTPqp764SqA6RgRBEARBEHnIMCIIgiAIgshDhhFBEARBEEQeMowIgiAIgiDykGFEEARBEASRhwwjgiAIgiCIPGQYEQRBEARB5CHDiCAIgiAIIg8ZRgRBEARBEHnIMCIIgiAIgshDhhFBEARBEEQeMowIgiAIgiDykGFEEARBEASRp6pbF5umCQAYHBx0eSQEQRAEQRQL27fZPi6SqjaMhoaGAABz5sxxeSQEQRAEQZTK0NAQotGo0N9pmDLMLU3IZrM4cuQIGhoaYBiG0N89ODiIOXPm4ODBg2hsbBT6u1WD7tWb0L16E7pXb1KN97p3714sXLgQPp9YVVBVe4x8Ph9mz54t9W80NjZ6fpIy6F69Cd2rN6F79SbVdK+zZs0SbhQBJL4mCIIgCILgkGFEEARBEASRhwwjSYTDYXzve99DOBx2eyjSoXv1JnSv3oTu1ZvQvYqjqsXXBEEQBEEQdshjRBAEQRAEkYcMI4IgCIIgiDxkGBEEQRAEQeQhw4ggCIIgCCIPGUYS+Pu//3vMnz8fNTU1WLJkCX7zm9+4PaSK2bBhAz7zmc+goaEBra2t+MIXvoB9+/YVXHPrrbfCMIyCfxdffLFLIy6f9evXj7mP9vZ2/n3TNLF+/Xp0dHQgEongiiuuwJ49e1wccfmcccYZY+7VMAzceeedAPT+TP/93/8dN954Izo6OmAYBv7t3/6t4PvFfI6JRAJ33303WlpaUFdXh5UrV+LQoUMO3kVxTHavqVQKf/3Xf43Fixejrq4OHR0d+E//6T/hyJEjBb/jiiuuGPNZf/WrX3X4TqZmqs+1mDnrhc8VwLjvrmEYeOCBB/g1OnyuxewvTr6vZBgJ5mc/+xnWrFmD7373u3jvvffwp3/6p7j++utx4MABt4dWEVu3bsWdd96J7du3Y8uWLUin01i+fDlGRkYKrrvuuuvQ09PD//3yl790acSVcf755xfcx65du/j3fvCDH+Chhx7CI488grfffhvt7e245ppreO89nXj77bcL7nPLli0AgC9/+cv8Gl0/05GREVx44YV45JFHxv1+MZ/jmjVr8MILL2DTpk3Ytm0bhoeHsWLFCmQyGaduoygmu9fR0VG8++67+Nu//Vu8++67eP755/H73/8eK1euHHPt6tWrCz7rxx57zInhl8RUnysw9Zz1wucKoOAee3p68E//9E8wDANf+tKXCq5T/XMtZn9x9H01CaF89rOfNb/+9a8XfO3cc881/+Zv/salEcnh2LFjJgBz69at/Gu33HKL+fnPf969QQnie9/7nnnhhReO+71sNmu2t7eb3//+9/nX4vG4GY1GzZ/85CcOjVAe3/zmN82zzjrLzGazpml65zMFYL7wwgv8/4v5HPv7+81gMGhu2rSJX3P48GHT5/OZ3d3djo29VE6/1/F46623TADmJ598wr92+eWXm9/85jflDk4w493rVHPWy5/r5z//efPKK68s+JqOn+vp+4vT7yt5jASSTCaxY8cOLF++vODry5cvx+uvv+7SqOQwMDAAAGhubi74+muvvYbW1lacc845WL16NY4dO+bG8Crmww8/REdHB+bPn4+vfvWr+OijjwAA+/fvR29vb8FnHA6Hcfnll2v/GSeTSWzcuBF/+Zd/WdBU2SufqZ1iPscdO3YglUoVXNPR0YHOzk7tP+uBgQEYhoFp06YVfP2ZZ55BS0sLzj//fKxbt05LLygw+Zz16ud69OhRvPTSS7jtttvGfE+3z/X0/cXp97Wqm8iK5sSJE8hkMmhrayv4eltbG3p7e10alXhM08S3vvUtfO5zn0NnZyf/+vXXX48vf/nLmDdvHvbv34+//du/xZVXXokdO3ZoVY116dKl+Od//mecc845OHr0KP77f//vuOSSS7Bnzx7+OY73GX/yySduDFcY//Zv/4b+/n7ceuut/Gte+UxPp5jPsbe3F6FQCE1NTWOu0fl9jsfj+Ju/+RusWrWqoNno1772NcyfPx/t7e3YvXs37r33Xvz2t7/l4VVdmGrOevVzfeqpp9DQ0ICbbrqp4Ou6fa7j7S9Ov69kGEnAftoGch/06V/Tmbvuugvvv/8+tm3bVvD1r3zlK/y/Ozs7cdFFF2HevHl46aWXxrysKnP99dfz/168eDGWLVuGs846C0899RQXcXrxM37iiSdw/fXXo6Ojg3/NK5/pRJTzOer8WadSKXz1q19FNpvF3//93xd8b/Xq1fy/Ozs7sWDBAlx00UV499138elPf9rpoZZNuXNW588VAP7pn/4JX/va11BTU1Pwdd0+14n2F8C595VCaQJpaWmB3+8fY50eO3ZsjKWrK3fffTd+8Ytf4NVXX8Xs2bMnvXbmzJmYN28ePvzwQ4dGJ4e6ujosXrwYH374Ic9O89pn/Mknn+Dll1/Gf/7P/3nS67zymRbzOba3tyOZTKKvr2/Ca3QilUrh5ptvxv79+7Fly5YCb9F4fPrTn0YwGNT+sz59znrtcwWA3/zmN9i3b9+U7y+g9uc60f7i9PtKhpFAQqEQlixZMsZFuWXLFlxyySUujUoMpmnirrvuwvPPP49XXnkF8+fPn/JnTp48iYMHD2LmzJkOjFAeiUQCH3zwAWbOnMld0vbPOJlMYuvWrVp/xk8++SRaW1txww03THqdVz7TYj7HJUuWIBgMFlzT09OD3bt3a/dZM6Poww8/xMsvv4zp06dP+TN79uxBKpXS/rM+fc566XNlPPHEE1iyZAkuvPDCKa9V8XOdan9x/H0tVzVOjM+mTZvMYDBoPvHEE+bevXvNNWvWmHV1debHH3/s9tAq4hvf+IYZjUbN1157zezp6eH/RkdHTdM0zaGhIXPt2rXm66+/bu7fv9989dVXzWXLlpmzZs0yBwcHXR59aaxdu9Z87bXXzI8++sjcvn27uWLFCrOhoYF/ht///vfNaDRqPv/88+auXbvMv/iLvzBnzpyp3X0yMpmMOXfuXPOv//qvC76u+2c6NDRkvvfee+Z7771nAjAfeugh87333uOZWMV8jl//+tfN2bNnmy+//LL57rvvmldeeaV54YUXmul02q3bGpfJ7jWVSpkrV640Z8+ebe7cubPg/U0kEqZpmuYf/vAH87/9t/9mvv322+b+/fvNl156yTz33HPNT33qU1rda7Fz1gufK2NgYMCsra01H3300TE/r8vnOtX+YprOvq9kGEngf/7P/2nOmzfPDIVC5qc//emClHZdATDuvyeffNI0TdMcHR01ly9fbs6YMcMMBoPm3LlzzVtuucU8cOCAuwMvg6985SvmzJkzzWAwaHZ0dJg33XSTuWfPHv79bDZrfu973zPb29vNcDhsXnbZZeauXbtcHHFl/PrXvzYBmPv27Sv4uu6f6auvvjrunL3llltM0yzuc4zFYuZdd91lNjc3m5FIxFyxYoWS9z/Zve7fv3/C9/fVV181TdM0Dxw4YF522WVmc3OzGQqFzLPOOsu85557zJMnT7p7Y+Mw2b0WO2e98LkyHnvsMTMSiZj9/f1jfl6Xz3Wq/cU0nX1fjfygCIIgCIIgqh7SGBEEQRAEQeQhw4ggCIIgCCIPGUYEQRAEQRB5yDAiCIIgCILIQ4YRQRAEQRBEHjKMCIIgCIIg8pBhRBAEQRAEkYcMI4IgCIIgiDxkGBEEQRAEQeQhw4ggCIIgCCIPGUYEQRAEQRB5yDAiCIIgCILI8/8DemHSSss6tZ4AAAAASUVORK5CYII=", + "text/plain": [ + "<Figure size 640x480 with 1 Axes>" + ] + }, + "metadata": {}, + "output_type": "display_data" + } + ], + "source": [ + "plt.plot([\n", + " 19602, 23581, 28123, 33002, 37204, 40346, 41606, 41964, 40862, 37354, 32660, 27543, 22969, 20134, 18101, 17990, 19469, 23313, 27740, \n", + " 32654, 37020, 40117, 41531, 41936, 41110, 37806, 32992, 28003, 23344, 20233, 18218, 18060, 19314, 22997, 27422, 32234, 36686, 40038, \n", + " 41453, 41947, 41931, 41911, 42013, 41942, 41923, 41937, 41914, 41941, 41954, 41977, 41891, 42022, 41957, 41972, 41989, 41930, 41922, \n", + " 41962, 41991, 41926, 41952, 41952, 41876, 41933, 41965, 41971, 41934, 41951, 41968, 41948, 41967, 41962, 41370, 38841, 34180, 29275, \n", + " 24324, 20824, 18625, 17920, 17817, 17823, 17726, 17731, 17675, 17689, 17650, 17658, 18644, 21753, 26111, 30930, 35441, 39223, 41119, \n", + " 41990, 41519, 39197, 34636, 29800, 24763, 21073, 18840, 17810, 18598, 21463, 25809, 30608, 35147, 39067, 41021, 41933, 41965, 41967, \n", + " 41959, 41982, 41990, 41944, 41952, 41949, 41963, 41937, 41917, 41958, 41968, 41919, 41915, 41942, 41584, 39799, 35447, 30608, 25481, \n", + " 21547, 19177, 18003, 17829, 17806, 17720, 17726, 17700, 17646, 17659, 17584, 18173, 20689, 24879, 29546, 34203, 38350, 40758, 41895, \n", + " 42014, 41969, 41966, 42047, 42036, 41962, 41967, 41981, 41767, 40315, 36186, 31388, 26284, 22006, 19499, 18003, 17839, 17789, 17775, \n", + " 17698, 17706, 17626, 17617, 17629, 17600, 17572, 17609, 17628, 17606, 17601, 17563, 17568, 17942, 19923, 24061, 28585, 33359, 37618, \n", + " 40417, 41767])" + ] + }, + { + "cell_type": "code", + "execution_count": null, + "id": "5d16c10a-e7a9-4bdc-a58d-d89426eaf3cf", + "metadata": {}, + "outputs": [], + "source": [] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3 (ipykernel)", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.11.5" + } + }, + "nbformat": 4, + "nbformat_minor": 5 +} diff --git a/center_fw/memory_map.ldi b/center_fw/memory_map.ldi new file mode 100644 index 0000000..445789e --- /dev/null +++ b/center_fw/memory_map.ldi @@ -0,0 +1,2 @@ +RAM (xrw): ORIGIN = 0x20000000, LENGTH = 8K +FLASH (rx ): ORIGIN = 0x08000000, LENGTH = 32K diff --git a/center_fw/openocd.cfg b/center_fw/openocd.cfg deleted file mode 100644 index f77e29a..0000000 --- a/center_fw/openocd.cfg +++ /dev/null @@ -1,17 +0,0 @@ -telnet_port 4445 -gdb_port 3334 -tcl_port 6667 - -source [find interface/stlink-v2.cfg] -#interface jlink -#interface stlink-v2 -#adapter_khz 10000 -#transport select swd - -#source /usr/share/openocd/scripts/target/stm32f0x.cfg -source [find target/stm32f0x.cfg] - -init -arm semihosting enable - -#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME diff --git a/center_fw/8seg_protocol.c b/center_fw/src/8seg_protocol.c index ef90800..ef90800 100644 --- a/center_fw/8seg_protocol.c +++ b/center_fw/src/8seg_protocol.c diff --git a/center_fw/8seg_protocol.h b/center_fw/src/8seg_protocol.h index 2da42c4..2da42c4 100644 --- a/center_fw/8seg_protocol.h +++ b/center_fw/src/8seg_protocol.h diff --git a/center_fw/adc.c b/center_fw/src/adc.c index 0cf70d1..0cf70d1 100644 --- a/center_fw/adc.c +++ b/center_fw/src/adc.c diff --git a/center_fw/adc.h b/center_fw/src/adc.h index 906cb7f..906cb7f 100644 --- a/center_fw/adc.h +++ b/center_fw/src/adc.h diff --git a/center_fw/base.c b/center_fw/src/base.c index 8e7c03b..8e7c03b 100644 --- a/center_fw/base.c +++ b/center_fw/src/base.c diff --git a/center_fw/cmsis_exports.c b/center_fw/src/cmsis_exports.c index 39874b5..39874b5 100644 --- a/center_fw/cmsis_exports.c +++ b/center_fw/src/cmsis_exports.c diff --git a/center_fw/src/main.c b/center_fw/src/main.c new file mode 100644 index 0000000..a521acb --- /dev/null +++ b/center_fw/src/main.c @@ -0,0 +1,196 @@ +/* Megumin LED display firmware + * Copyright (C) 2018 Sebastian Götte <code@jaseg.net> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "global.h" + +uint16_t adc_data[192]; +bool sync_running = false; + +static void quicksort(uint16_t *head, uint16_t *tail); + +int main(void) { + /* Configure clocks for 64 MHz system clock. + * + * HSI @ 16 MHz --[PLL x16 /4]--> PLL "R" clock @ 64 MHz + */ + /* Enable peripherals */ + RCC->APBENR1 |= RCC_APBENR1_PWREN; + /* Increase flash wait states to 2 required for operation above 48 MHz */ + FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<<FLASH_ACR_LATENCY_Pos); + while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (2<<FLASH_ACR_LATENCY_Pos)) { + /* wait for flash controller to acknowledge change. */ + } + /* Configure PLL with multiplier 16, divisor 2 for "R" output, and enable "R" (sysclk) output */ + RCC->PLLCFGR = (16<<RCC_PLLCFGR_PLLN_Pos) | (2<<RCC_PLLCFGR_PLLSRC_Pos) | (3<<RCC_PLLCFGR_PLLR_Pos) | RCC_PLLCFGR_PLLREN; + RCC->CR |= RCC_CR_PLLON; + while (!(RCC->CR & RCC_CR_PLLRDY)) { + /* wait for PLL to stabilize. */ + } + /* Switch SYSCLK to PLL source. */ + RCC->CFGR |= (2<<RCC_CFGR_SW_Pos); + while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != (2<<RCC_CFGR_SWS_Pos)) { + /* wait for RCC to switch over. */ + } + + RCC->AHBENR |= RCC_AHBENR_DMA1EN; + RCC->APBENR1 |= RCC_APBENR1_TIM3EN | RCC_APBENR1_DBGEN; + RCC->APBENR2 |= RCC_APBENR2_TIM1EN | RCC_APBENR2_ADCEN; + RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIOCEN; + + TIM1->PSC = 1; + TIM1->ARR = 32767; + TIM1->DIER = TIM_DIER_UIE | TIM_DIER_CC1IE; + TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN; + TIM1->CCR1 = 3000; + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 0); + NVIC_EnableIRQ(TIM1_CC_IRQn); + NVIC_SetPriority(TIM1_CC_IRQn, 0); + + TIM3->CR2 = (2<<TIM_CR2_MMS_Pos); /* Update event on TRGO */ + TIM3->PSC = 0; + /* We sample 32 times per 1 kHz AC cycle, and use 16 times oversampling. */ + TIM3->ARR = 124; /* Output 64 MHz / 125 = 512 kHz signal */ + TIM3->CR1 = TIM_CR1_CEN; + + DMAMUX1[0].CCR = 5; /* ADC */ + DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR; + DMA1_Channel1->CMAR = (uint32_t)(void *)adc_data; + + NVIC_EnableIRQ(DMA1_Channel1_IRQn); + NVIC_SetPriority(DMA1_Channel1_IRQn, 64); + + ADC1->ISR = ADC_ISR_CCRDY | ADC_ISR_ADRDY; /* Clear CCRDY */ + ADC1->CR = ADC_CR_ADVREGEN; + delay_us(20); + ADC1->CR = ADC_CR_ADCAL; + while (ADC1->CR & ADC_CR_ADCAL) { + /* wait. */ + } + ADC1->CFGR1 = (1<<ADC_CFGR1_EXTEN_Pos) | (3<<ADC_CFGR1_EXTSEL_Pos) | ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* TIM3 TRGO */ + ADC1->CFGR2 = (1<<ADC_CFGR2_CKMODE_Pos) | (4<<ADC_CFGR2_OVSR_Pos) | (1<<ADC_CFGR2_OVSS_Pos) | ADC_CFGR2_TOVS | ADC_CFGR2_OVSE; /* Oversample by 16 */ + ADC1->CHSELR = (1<<4); /* Enable input 4 -> PA4 (Vdiff)*/ + while (!(ADC1->ISR & ADC_ISR_CCRDY)) { + /* wait. */ + } + ADC1->ISR = ADC_ISR_CCRDY; /* Clear CCRDY */ + ADC->CCR = ADC_CCR_TSEN | ADC_CCR_VREFEN; + ADC1->CR = ADC_CR_ADVREGEN | ADC_CR_ADEN; + while (!(ADC1->ISR & ADC_ISR_ADRDY)) { + /* wait. */ + } + ADC1->CR |= ADC_CR_ADSTART; + + GPIOA->MODER = OUT(0) | IN(1) | OUT(2) | OUT(3) | ANALOG(4) | OUT(5) | OUT(6) | IN(7) | ANALOG(9) | ANALOG(10) | OUT(11) | ANALOG(12)| AF(13) | AF(14); + GPIOB->MODER = ANALOG(0) | OUT(3) | ANALOG(1) | ANALOG(2) | ANALOG(4) | ANALOG(5) | ANALOG(6) | ANALOG(8) | OUT(7) | ANALOG(9); + GPIOC->MODER = OUT(15) | ANALOG(14) | ANALOG(9); + + DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP; + while (42) { + } +} + +void TIM1_BRK_UP_TRG_COM_IRQHandler(void) { + TIM1->SR &= ~TIM_SR_UIF; + GPIOB->BSRR = (1<<7); + if (!sync_running) { + while(DMA1_Channel1->CCR != 0) { + DMA1_Channel1->CCR = 0; + } + DMA1_Channel1->CCR = (1<<DMA_CCR_MSIZE_Pos) | (1<<DMA_CCR_PSIZE_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE; + DMA1_Channel1->CNDTR = COUNT_OF(adc_data); + DMA1_Channel1->CCR |= DMA_CCR_EN; + sync_running = true; + } +} + +void TIM1_CC_IRQHandler(void) { + TIM1->SR &= ~TIM_SR_CC1IF; + GPIOB->BRR = (1<<7); +} + +void DMA1_Channel1_IRQHandler(void) { + DMA1->IFCR = DMA_IFCR_CTCIF1; + quicksort(adc_data, &adc_data[COUNT_OF(adc_data)-1]); + asm volatile ("bkpt"); + sync_running = false; +} + +void delay_us(int duration_us) { + while (duration_us--) { + for (int i=0; i<32; i++) { + asm volatile ("nop"); + } + } +} + +void NMI_Handler(void) { + asm volatile ("bkpt"); +} + +void HardFault_Handler(void) __attribute__((naked)); +void HardFault_Handler() { + asm volatile ("bkpt"); +} + +void SVC_Handler(void) { + asm volatile ("bkpt"); +} + + +void PendSV_Handler(void) { + asm volatile ("bkpt"); +} + +void __libc_init_array (void) __attribute__((weak)); +void __libc_init_array () { +} + +/* https://github.com/openmv/openmv/blob/2e8d5d505dbe695b8009d832e5ef7691009148e1/src/omv/common/array.c#L117 */ +static void quicksort(uint16_t *head, uint16_t *tail) { + while (head < tail) { + uint16_t *h = head - 1; + uint16_t *t = tail; + uint16_t v = tail[0]; + for (;;) { + do { + ++h; + } while (h < t && h[0] < v); + do { + --t; + } while (h < t && v < t[0]); + if (h >= t) { + break; + } + uint16_t x = h[0]; + h[0] = t[0]; + t[0] = x; + } + uint16_t x = h[0]; + h[0] = tail[0]; + tail[0] = x; + // do the smaller recursive call first, to keep stack within O(log(N)) + if (t - head < tail - h - 1) { + quicksort(head, t); + head = h + 1; + } else { + quicksort(h + 1, tail); + tail = t; + } + } +} + diff --git a/center_fw/protocol.c b/center_fw/src/protocol.c index dfa0d3e..dfa0d3e 100644 --- a/center_fw/protocol.c +++ b/center_fw/src/protocol.c diff --git a/center_fw/protocol.h b/center_fw/src/protocol.h index 89c93e2..89c93e2 100644 --- a/center_fw/protocol.h +++ b/center_fw/src/protocol.h diff --git a/center_fw/protocol_test.c b/center_fw/src/protocol_test.c index 4a12ef5..4a12ef5 100644 --- a/center_fw/protocol_test.c +++ b/center_fw/src/protocol_test.c diff --git a/center_fw/transmit.c b/center_fw/src/transmit.c index c31c833..c31c833 100644 --- a/center_fw/transmit.c +++ b/center_fw/src/transmit.c diff --git a/center_fw/transmit.h b/center_fw/src/transmit.h index dd9bcb9..dd9bcb9 100644 --- a/center_fw/transmit.h +++ b/center_fw/src/transmit.h diff --git a/center_fw/startup.s b/center_fw/startup.s new file mode 100644 index 0000000..7dfdd84 --- /dev/null +++ b/center_fw/startup.s @@ -0,0 +1,282 @@ +/** + ****************************************************************************** + * @file startup_stm32g070xx.s + * @author MCD Application Team + * @brief STM32G070xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3, USART4 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_IRQHandler + .thumb_set USART3_4_IRQHandler,Default_Handler diff --git a/center_fw/startup_stm32f030x6.s b/center_fw/startup_stm32f030x6.s deleted file mode 100644 index 2f0eb42..0000000 --- a/center_fw/startup_stm32f030x6.s +++ /dev/null @@ -1,273 +0,0 @@ -/**
- ******************************************************************************
- * @file startup_stm32f030x6.s
- * copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc
- * @author MCD Application Team
- * @version V2.3.1
- * @date 04-November-2016
- * @brief STM32F030x4/STM32F030x6 devices vector table for Atollic TrueSTUDIO toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
-// bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler /* Window WatchDog */
- .word 0 /* Reserved */
- .word RTC_IRQHandler /* RTC through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
- .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
- .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
- .word 0 /* Reserved */
- .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
- .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
- .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
- .word ADC1_IRQHandler /* ADC1 */
- .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word 0 /* Reserved */
- .word TIM3_IRQHandler /* TIM3 */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word TIM14_IRQHandler /* TIM14 */
- .word 0 /* Reserved */
- .word TIM16_IRQHandler /* TIM16 */
- .word TIM17_IRQHandler /* TIM17 */
- .word I2C1_IRQHandler /* I2C1 */
- .word 0 /* Reserved */
- .word SPI1_IRQHandler /* SPI1 */
- .word 0 /* Reserved */
- .word USART1_IRQHandler /* USART1 */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/center_fw/stm32_buildinfo.defines b/center_fw/stm32_buildinfo.defines new file mode 100644 index 0000000..eb270dd --- /dev/null +++ b/center_fw/stm32_buildinfo.defines @@ -0,0 +1 @@ +STM32G030xx diff --git a/center_fw/stm32_flash.ld b/center_fw/stm32_flash.ld deleted file mode 100644 index cba7577..0000000 --- a/center_fw/stm32_flash.ld +++ /dev/null @@ -1,136 +0,0 @@ -
-ENTRY(Reset_Handler)
-
-MEMORY {
- FLASH (rx): ORIGIN = 0x08000000, LENGTH = 0x3C00
- CONFIGFLASH (rw): ORIGIN = 0x08003C00, LENGTH = 0x400
- RAM (xrw): ORIGIN = 0x20000000, LENGTH = 4K
-}
-
-/* highest address of the user mode stack */
-_estack = 0x20001000;
-
-SECTIONS {
- /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
- .isr_vector : {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* the program code is stored in the .text section, which goes to Flash */
- .text : {
- . = ALIGN(4);
-
- *(.text) /* normal code */
- *(.text.*) /* -ffunction-sections code */
- *(.rodata) /* read-only data (constants) */
- *(.rodata*) /* -fdata-sections read only data */
- *(.glue_7) /* TBD - needed ? */
- *(.glue_7t) /* TBD - needed ? */
-
- *(.source_tarball)
-
- /* Necessary KEEP sections (see http://sourceware.org/ml/newlib/2005/msg00255.html) */
- KEEP (*(.init))
- KEEP (*(.fini))
- KEEP (*(.source_tarball))
-
- . = ALIGN(4);
- _etext = .;
- /* This is used by the startup in order to initialize the .data section */
- _sidata = _etext;
- } >FLASH
-
- /*
- .configflash : {
- . = ALIGN(0x400);
- *(.configdata)
- _econfig = .;
- } >FLASH
- */
-
- /* This is the initialized data section
- The program executes knowing that the data is in the RAM
- but the loader puts the initial values in the FLASH (inidata).
- It is one task of the startup to copy the initial values from FLASH to RAM. */
- .data : AT ( _sidata ) {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _sdata = . ;
- _data = . ;
-
- *(.data)
- *(.data.*)
- *(.RAMtext)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .data secion */
- _edata = . ;
- } >RAM
-
- /* This is the uninitialized data section */
- .bss : {
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .;
- _bss = .;
-
- *(.bss)
- *(.bss.*) /* patched by elias - allows the use of -fdata-sections */
- *(COMMON)
-
- . = ALIGN(4);
- /* This is used by the startup in order to initialize the .bss secion */
- _ebss = . ;
- } >RAM
-
- PROVIDE ( end = _ebss);
- PROVIDE (_end = _ebss);
-
- __exidx_start = .;
- __exidx_end = .;
-
- /* after that it's only debugging information. */
-
- /* remove the debugging information from the standard libraries */
-/* /DISCARD/ : {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }*/
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /* DWARF debug sections.
- Symbols in the DWARF debugging sections are relative to the beginning
- of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
diff --git a/center_fw/system.c b/center_fw/system.c new file mode 100644 index 0000000..d4ca437 --- /dev/null +++ b/center_fw/system.c @@ -0,0 +1,302 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** @addtogroup STM32G0xx_System_Private_Includes + * @{ + */ + +#include "stm32g0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t pllvco; + uint32_t pllr; + uint32_t pllsource; + uint32_t pllm; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case RCC_CFGR_SWS_1: /* PLL used as system clock */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/center_fw/system_stm32f0xx.c b/center_fw/system_stm32f0xx.c deleted file mode 100644 index a43c3d6..0000000 --- a/center_fw/system_stm32f0xx.c +++ /dev/null @@ -1,336 +0,0 @@ -/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates
- * @author MCD Application Team
- * @version V2.3.1
- * @date 04-November-2016
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F0xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 8000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
- /* Reset PREDIV[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
- /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
- /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
- /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
- /* Set default USB clock to PLLCLK, since there is no HSI48 */
- RCC->CFGR3 |= (uint32_t)0x00000080U;
-#else
- #warning "No target selected"
-#endif
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000U;
-
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
- SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
- else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
- {
- /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
- SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
- else
- {
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
- SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
- /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
- STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
- STM32F091xC || STM32F098xx || STM32F030xC */
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/center_fw/tools/linkmem.py b/center_fw/tools/linkmem.py new file mode 100644 index 0000000..934a571 --- /dev/null +++ b/center_fw/tools/linkmem.py @@ -0,0 +1,276 @@ + +import tempfile +import os +from os import path +import sys +import re +import subprocess +from contextlib import contextmanager +from collections import defaultdict +import colorsys + +import cxxfilt +from elftools.elf.elffile import ELFFile +from elftools.elf.enums import ENUM_ST_SHNDX +from elftools.elf.descriptions import describe_symbol_type, describe_sh_type +import libarchive +import matplotlib.cm + +@contextmanager +def chdir(newdir): + old_cwd = os.getcwd() + try: + os.chdir(newdir) + yield + finally: + os.chdir(old_cwd) + +def keep_last(it, first=None): + last = first + for elem in it: + yield last, elem + last = elem + +def delim(start, end, it, first_only=True): + found = False + for elem in it: + if end(elem): + if first_only: + return + found = False + elif start(elem): + found = True + elif found: + yield elem + +def delim_prefix(start, end, it): + yield from delim(lambda l: l.startswith(start), lambda l: end is not None and l.startswith(end), it) + +def trace_source_files(linker, cmdline, trace_sections=[], total_sections=['.text', '.data', '.rodata']): + with tempfile.TemporaryDirectory() as tempdir: + out_path = path.join(tempdir, 'output.elf') + output = subprocess.check_output([linker, '-o', out_path, f'-Wl,--print-map', *cmdline]) + lines = [ line.strip() for line in output.decode().splitlines() ] + # FIXME also find isr vector table references + + defs = {} + objs = defaultdict(lambda: 0) + aliases = {} + sec_name = None + last_loc = None + last_sym = None + line_cont = None + for last_line, line in keep_last(delim_prefix('Linker script and memory map', 'OUTPUT', lines), first=''): + if not line or line.startswith('LOAD '): + sec_name = None + continue + + # first part of continuation line + if m := re.match('^(\.[0-9a-zA-Z-_.]+)$', line): + line_cont = line + sec_name = None + continue + + if line_cont: + line = line_cont + ' ' + line + line_cont = None + + # -ffunction-sections/-fdata-sections section + if m := re.match('^(\.[0-9a-zA-Z-_.]+)\.([0-9a-zA-Z-_.]+)\s+(0x[0-9a-f]+)\s+(0x[0-9a-f]+)\s+(\S+)$', line): + sec, sym, loc, size, obj = m.groups() + *_, sym = sym.rpartition('.') + sym = cxxfilt.demangle(sym) + size = int(size, 16) + obj = path.abspath(obj) + + if sec not in total_sections: + size = 0 + + objs[obj] += size + defs[sym] = (sec, size, obj) + + sec_name, last_loc, last_sym = sec, loc, sym + continue + + # regular (no -ffunction-sections/-fdata-sections) section + if m := re.match('^(\.[0-9a-zA-Z-_]+)\s+(0x[0-9a-f]+)\s+(0x[0-9a-f]+)\s+(\S+)$', line): + sec, _loc, size, obj = m.groups() + size = int(size, 16) + obj = path.abspath(obj) + + if sec in total_sections: + objs[obj] += size + + sec_name = sec + last_loc, last_sym = None, None + continue + + # symbol def + if m := re.match('^(0x[0-9a-f]+)\s+(\S+)$', line): + loc, sym = m.groups() + sym = cxxfilt.demangle(sym) + loc = int(loc, 16) + if sym in defs: + continue + + if loc == last_loc: + assert last_sym is not None + aliases[sym] = last_sym + else: + assert sec_name + defs[sym] = (sec_name, None, obj) + last_loc, last_sym = loc, sym + + continue + + refs = defaultdict(lambda: set()) + for sym, (sec, size, obj) in defs.items(): + fn, _, member = re.match('^([^()]+)(\((.+)\))?$', obj).groups() + fn = path.abspath(fn) + + if member: + subprocess.check_call(['ar', 'x', '--output', tempdir, fn, member]) + fn = path.join(tempdir, member) + + with open(fn, 'rb') as f: + elf = ELFFile(f) + + symtab = elf.get_section_by_name('.symtab') + + symtab_demangled = { cxxfilt.demangle(nsym.name).replace(' ', ''): i + for i, nsym in enumerate(symtab.iter_symbols()) } + + s = set() + sec_map = { sec.name: i for i, sec in enumerate(elf.iter_sections()) } + matches = [ i for name, i in sec_map.items() if re.match(f'\.rel\..*\.{sym}', name) ] + if matches: + sec = elf.get_section(matches[0]) + for reloc in sec.iter_relocations(): + refsym = symtab.get_symbol(reloc['r_info_sym']) + name = refsym.name if refsym.name else elf.get_section(refsym['st_shndx']).name.split('.')[-1] + s.add(name) + refs[sym] = s + + for tsec in trace_sections: + matches = [ i for name, i in sec_map.items() if name == f'.rel{tsec}' ] + s = set() + if matches: + sec = elf.get_section(matches[0]) + for reloc in sec.iter_relocations(): + refsym = symtab.get_symbol(reloc['r_info_sym']) + s.add(refsym.name) + refs[tsec.replace('.', '_')] |= s + + return objs, aliases, defs, refs + +@contextmanager +def wrap(leader='', print=print, left='{', right='}'): + print(leader, left) + yield lambda *args, **kwargs: print(' ', *args, **kwargs) + print(right) + +def mangle(name): + return re.sub('[^a-zA-Z0-9_]', '_', name) + +hexcolor = lambda r, g, b, *_a: f'#{int(r*255):02x}{int(g*255):02x}{int(b*255):02x}' +def vhex(val): + r,g,b,_a = matplotlib.cm.viridis(1.0-val) + fc = hexcolor(r, g, b) + h,s,v = colorsys.rgb_to_hsv(r,g,b) + cc = '#000000' if v > 0.8 else '#ffffff' + return fc, cc + +if __name__ == '__main__': + import argparse + parser = argparse.ArgumentParser() + parser.add_argument('--trace-sections', type=str, action='append', default=[]) + parser.add_argument('--trim-stubs', type=str, action='append', default=[]) + parser.add_argument('--highlight-subdirs', type=str, default=None) + parser.add_argument('linker_binary') + parser.add_argument('linker_args', nargs=argparse.REMAINDER) + args = parser.parse_args() + + trace_sections = args.trace_sections + trace_sections_mangled = { sec.replace('.', '_') for sec in trace_sections } + objs, aliases, syms, refs = trace_source_files(args.linker_binary, args.linker_args, trace_sections) + + clusters = defaultdict(lambda: []) + for sym, (sec, size, obj) in syms.items(): + clusters[obj].append((sym, sec, size)) + + max_ssize = max(size or 0 for _sec, size, _obj in syms.values()) + max_osize = max(objs.values()) + + subdir_prefix = path.abspath(args.highlight_subdirs) + '/' if args.highlight_subdirs else '### NO HIGHLIGHT ###' + first_comp = lambda le_path: path.dirname(le_path).partition(os.sep)[0] + subdir_colors = sorted({ first_comp(obj[len(subdir_prefix):]) for obj in objs if obj.startswith(subdir_prefix) }) + subdir_colors = { path: hexcolor(*matplotlib.cm.Pastel1(i/len(subdir_colors))) for i, path in enumerate(subdir_colors) } + + subdir_sizes = defaultdict(lambda: 0) + for obj, size in objs.items(): + if not isinstance(size, int): + continue + if obj.startswith(subdir_prefix): + subdir_sizes[first_comp(obj[len(subdir_prefix):])] += size + else: + subdir_sizes['<others>'] += size + + print('Subdir sizes:', file=sys.stderr) + for subdir, size in sorted(subdir_sizes.items(), key=lambda x: x[1]): + print(f'{subdir:>20}: {size:>6,d} B', file=sys.stderr) + + def lookup_highlight(path): + if args.highlight_subdirs: + if obj.startswith(subdir_prefix): + highlight_head = first_comp(path[len(subdir_prefix):]) + return subdir_colors[highlight_head], highlight_head + else: + return '#e0e0e0', None + else: + return '#ddf7f4', None + + with wrap('digraph G', print) as lvl1print: + print('size="23.4,16.5!";') + print('graph [fontsize=40];') + print('node [fontsize=40];') + #print('ratio="fill";') + + print('rankdir=LR;') + print('ranksep=5;') + print('nodesep=0.2;') + print() + + for i, (obj, obj_syms) in enumerate(clusters.items()): + with wrap(f'subgraph cluster_{i}', lvl1print) as lvl2print: + print('style = "filled";') + highlight_color, highlight_head = lookup_highlight(obj) + print(f'bgcolor = "{highlight_color}";') + print('pencolor = none;') + fc, cc = vhex(objs[obj]/max_osize) + highlight_subdir_part = f'<font face="carlito" color="{cc}" point-size="40">{highlight_head} / </font>' if highlight_head else '' + lvl2print(f'label = <<table border="0"><tr><td border="0" cellpadding="5" bgcolor="{fc}">' + f'{highlight_subdir_part}' + f'<font face="carlito" color="{cc}"><b>{path.basename(obj)} ({objs[obj]}B)</b></font>' + f'</td></tr></table>>;') + lvl2print() + for sym, sec, size in obj_syms: + has_size = isinstance(size, int) and size > 0 + size_s = f' ({size}B)' if has_size else '' + fc, cc = vhex(size/max_ssize) if has_size else ('#ffffff', '#000000') + shape = 'box' if sec == '.text' else 'oval' + lvl2print(f'{mangle(sym)}[label = "{sym}{size_s}", style="rounded,filled", shape="{shape}", fillcolor="{fc}", fontname="carlito", fontcolor="{cc}" color=none];') + lvl1print() + + edges = set() + for start, ends in refs.items(): + for end in ends: + end = aliases.get(end, end) + if (start in syms or start in trace_sections_mangled) and end in syms: + edges.add((start, end)) + + for start, end in edges: + lvl1print(f'{mangle(start)} -> {mangle(end)} [style="bold", color="#333333"];') + + for sec in trace_sections: + lvl1print(f'{sec.replace(".", "_")} [label = "section {sec}", shape="box", style="filled,bold"];') + diff --git a/driver/driver.kicad_sch b/driver/driver.kicad_sch index ac5eb1d..529a66d 100644 --- a/driver/driver.kicad_sch +++ b/driver/driver.kicad_sch @@ -4735,7 +4735,7 @@ (junction (at 63.5 328.93) (diameter 1.016) (color 0 0 0 0) (uuid e48f7b35-32c2-4f21-8f16-b643e635e96e) ) - (junction (at 538.48 102.87) (diameter 0) (color 0 0 0 0) + (junction (at 538.48 90.17) (diameter 0) (color 0 0 0 0) (uuid e4dcf46d-35ca-4eb8-9f0a-88039139f35a) ) (junction (at 427.99 295.91) (diameter 0) (color 0 0 0 0) @@ -4815,7 +4815,7 @@ (no_connect (at 523.24 336.55) (uuid ed34b661-daf0-4e2b-bcde-b8cd1cfc0f39)) (no_connect (at 523.24 326.39) (uuid ee45a50c-ebfd-40d3-9b4b-c2b9bf90055d)) (no_connect (at 523.24 339.09) (uuid eee60b3c-25b9-475e-a949-38aec09eec65)) - (no_connect (at 535.94 105.41) (uuid ef77bb6b-94ba-436b-ad9f-5fc5cbc010bc)) + (no_connect (at 535.94 92.71) (uuid ef77bb6b-94ba-436b-ad9f-5fc5cbc010bc)) (wire (pts (xy 425.45 35.56) (xy 435.61 35.56)) (stroke (width 0) (type solid)) @@ -5113,7 +5113,7 @@ (stroke (width 0) (type default)) (uuid 1d47adbf-4e2c-48c3-bea2-54815367415e) ) - (wire (pts (xy 535.94 102.87) (xy 538.48 102.87)) + (wire (pts (xy 535.94 90.17) (xy 538.48 90.17)) (stroke (width 0) (type default)) (uuid 1e0cb541-95c2-4d23-9e9e-1434dbbf1075) ) @@ -5225,7 +5225,7 @@ (stroke (width 0) (type solid)) (uuid 2883da6b-707a-42ff-bc47-667e594bdcee) ) - (wire (pts (xy 535.94 100.33) (xy 549.91 100.33)) + (wire (pts (xy 535.94 87.63) (xy 549.91 87.63)) (stroke (width 0) (type default)) (uuid 299c69df-b066-4288-8746-a45f7bb6d49e) ) @@ -6517,7 +6517,7 @@ (stroke (width 0) (type default)) (uuid 9eb52da1-d4ad-4a66-a3d5-11824e5e27c3) ) - (wire (pts (xy 538.48 96.52) (xy 538.48 102.87)) + (wire (pts (xy 538.48 83.82) (xy 538.48 90.17)) (stroke (width 0) (type default)) (uuid 9ef05ab3-f0e5-464a-b89f-77225073bac4) ) @@ -6621,7 +6621,7 @@ (stroke (width 0) (type solid)) (uuid ac559db4-2d9d-4b23-b103-4f681061c467) ) - (wire (pts (xy 520.7 110.49) (xy 520.7 100.33)) + (wire (pts (xy 520.7 97.79) (xy 520.7 87.63)) (stroke (width 0) (type default)) (uuid aca9b541-518e-4cb1-8831-1dfaeddba1aa) ) @@ -6645,7 +6645,7 @@ (stroke (width 0) (type solid)) (uuid ae92b140-6068-4d87-aea7-79aa2c0aad64) ) - (wire (pts (xy 509.27 107.95) (xy 523.24 107.95)) + (wire (pts (xy 509.27 95.25) (xy 523.24 95.25)) (stroke (width 0) (type default)) (uuid aea6a645-a96e-4451-a60d-f809d138d2cf) ) @@ -6717,7 +6717,7 @@ (stroke (width 0) (type default)) (uuid b3565867-12f5-4b5c-ab05-ffcfe7505f06) ) - (wire (pts (xy 509.27 105.41) (xy 523.24 105.41)) + (wire (pts (xy 509.27 92.71) (xy 523.24 92.71)) (stroke (width 0) (type default)) (uuid b3659fc1-b2fa-47f9-b4d5-38f788a0c0c3) ) @@ -6981,7 +6981,7 @@ (stroke (width 0) (type solid)) (uuid cb99a2af-eeb2-4a83-8a35-78f889fd80be) ) - (wire (pts (xy 509.27 102.87) (xy 523.24 102.87)) + (wire (pts (xy 509.27 90.17) (xy 523.24 90.17)) (stroke (width 0) (type default)) (uuid cbe879f7-71e6-45ee-bbf2-bbe846c3a721) ) @@ -7101,7 +7101,7 @@ (stroke (width 0) (type default)) (uuid d9a80219-baa7-4199-97fa-26b755716a7e) ) - (wire (pts (xy 520.7 100.33) (xy 523.24 100.33)) + (wire (pts (xy 520.7 87.63) (xy 523.24 87.63)) (stroke (width 0) (type default)) (uuid dab01942-7764-4024-b101-6c689dc98293) ) @@ -7253,7 +7253,7 @@ (stroke (width 0) (type default)) (uuid e9c18492-1e72-4953-9804-7211bd174244) ) - (wire (pts (xy 538.48 102.87) (xy 538.48 107.95)) + (wire (pts (xy 538.48 90.17) (xy 538.48 95.25)) (stroke (width 0) (type default)) (uuid ea573547-2be9-4562-acb7-fa3dbd385904) ) @@ -7329,7 +7329,7 @@ (stroke (width 0) (type solid)) (uuid f0d618f4-d711-4151-9d80-94647f13dde7) ) - (wire (pts (xy 538.48 107.95) (xy 535.94 107.95)) + (wire (pts (xy 538.48 95.25) (xy 535.94 95.25)) (stroke (width 0) (type default)) (uuid f32c3c17-42a6-4b3d-acde-94440b6bf7e1) ) @@ -7469,7 +7469,7 @@ (uuid 099abf23-a9c8-4635-a71b-adf31cbb97f5) ) (text "Debug port" (exclude_from_sim no) - (at 529.59 91.44 0) + (at 529.59 78.74 0) (effects (font (size 1.27 1.27))) (uuid 15a07c66-b123-4816-b626-7b1e3bc70e5d) ) @@ -7549,7 +7549,7 @@ (uuid aad8e04f-b807-43ee-9f96-bb3ab90e0c3d) ) (text "ESP8266 module w/\nblackmagic-espidf\nfirmware" (exclude_from_sim no) - (at 527.05 114.3 0) + (at 527.05 101.6 0) (effects (font (size 1.27 1.27)) (justify left)) (uuid dbdcfe53-c5ba-4cbe-a2c6-53ffdbec0d03) ) @@ -7678,7 +7678,7 @@ (effects (font (size 1.27 1.27)) (justify left bottom)) (uuid 2885545a-7013-409c-81de-3e54db4b90b4) ) - (label "DBG_TX" (at 509.27 107.95 0) (fields_autoplaced) + (label "DBG_TX" (at 509.27 95.25 0) (fields_autoplaced) (effects (font (size 1.27 1.27)) (justify left bottom)) (uuid 2c320ddb-dd90-4104-98c3-f6cf87cd3a0d) ) @@ -7790,7 +7790,7 @@ (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid 7015ee41-8596-4a05-ae54-93b4f6dadcad) ) - (label "SWCLK" (at 509.27 102.87 0) (fields_autoplaced) + (label "SWCLK" (at 509.27 90.17 0) (fields_autoplaced) (effects (font (size 1.27 1.27)) (justify left bottom)) (uuid 7706670a-a27a-4c8a-ba61-08d1aa46b959) ) @@ -7850,7 +7850,7 @@ (effects (font (size 1.27 1.27)) (justify left bottom)) (uuid 98d51a89-4a64-40ac-8469-0d32838985d5) ) - (label "SWDIO" (at 509.27 105.41 0) (fields_autoplaced) + (label "SWDIO" (at 509.27 92.71 0) (fields_autoplaced) (effects (font (size 1.27 1.27)) (justify left bottom)) (uuid 9a7d37c6-ee29-4f24-9abd-ab9bc9491241) ) @@ -7910,7 +7910,7 @@ (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid bb8abb6b-7ab8-4487-81b2-005129acf8b2) ) - (label "DBG_RX" (at 549.91 100.33 180) (fields_autoplaced) + (label "DBG_RX" (at 549.91 87.63 180) (fields_autoplaced) (effects (font (size 1.27 1.27)) (justify right bottom)) (uuid bd7b0100-8486-4945-8d64-81060133df87) ) @@ -15728,22 +15728,22 @@ ) ) - (symbol (lib_id "driver-rescue:GND-power") (at 520.7 110.49 0) (unit 1) + (symbol (lib_id "driver-rescue:GND-power") (at 520.7 97.79 0) (unit 1) (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid d0b24130-fc54-415d-9228-ff40baac402c) - (property "Reference" "#PWR0132" (at 520.7 116.84 0) + (property "Reference" "#PWR0132" (at 520.7 104.14 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Value" "GND" (at 520.827 114.8842 0) + (property "Value" "GND" (at 520.827 102.1842 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "" (at 520.7 110.49 0) + (property "Footprint" "" (at 520.7 97.79 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Datasheet" "" (at 520.7 110.49 0) + (property "Datasheet" "" (at 520.7 97.79 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Description" "" (at 520.7 110.49 0) + (property "Description" "" (at 520.7 97.79 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid 17bb5ca9-655e-4dae-ac21-4731eaea8f72)) @@ -15788,25 +15788,25 @@ ) ) - (symbol (lib_id "Connector_Generic:Conn_02x04_Odd_Even") (at 528.32 102.87 0) (unit 1) + (symbol (lib_id "Connector_Generic:Conn_02x04_Odd_Even") (at 528.32 90.17 0) (unit 1) (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (fields_autoplaced) (uuid d2eeb85c-560f-42eb-81c3-dd6e17365b91) - (property "Reference" "J3" (at 529.59 96.2279 0) + (property "Reference" "J3" (at 529.59 83.5279 0) (effects (font (size 1.27 1.27))) ) - (property "Value" "ESP" (at 529.59 97.9901 0) + (property "Value" "ESP" (at 529.59 85.2901 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "Connector_PinSocket_2.54mm:PinSocket_2x04_P2.54mm_Vertical" (at 528.32 102.87 0) + (property "Footprint" "Connector_PinSocket_2.54mm:PinSocket_2x04_P2.54mm_Vertical" (at 528.32 90.17 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Datasheet" "~" (at 528.32 102.87 0) + (property "Datasheet" "~" (at 528.32 90.17 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Description" "" (at 528.32 102.87 0) + (property "Description" "" (at 528.32 90.17 0) (effects (font (size 1.27 1.27)) hide) ) - (property "DNP" "DNP" (at 528.32 102.87 0) + (property "DNP" "DNP" (at 528.32 90.17 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid 47a06a28-6d57-4ac5-ab15-77caf5cec09b)) @@ -16473,22 +16473,22 @@ ) ) - (symbol (lib_id "driver-rescue:+3V3-power") (at 538.48 96.52 0) (unit 1) + (symbol (lib_id "driver-rescue:+3V3-power") (at 538.48 83.82 0) (unit 1) (exclude_from_sim no) (in_bom yes) (on_board yes) (dnp no) (uuid eb3d31ac-a6a7-49a0-addf-f90b47169935) - (property "Reference" "#PWR0131" (at 538.48 100.33 0) + (property "Reference" "#PWR0131" (at 538.48 87.63 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Value" "+3V3" (at 538.861 92.1258 0) + (property "Value" "+3V3" (at 538.861 79.4258 0) (effects (font (size 1.27 1.27))) ) - (property "Footprint" "" (at 538.48 96.52 0) + (property "Footprint" "" (at 538.48 83.82 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Datasheet" "" (at 538.48 96.52 0) + (property "Datasheet" "" (at 538.48 83.82 0) (effects (font (size 1.27 1.27)) hide) ) - (property "Description" "" (at 538.48 96.52 0) + (property "Description" "" (at 538.48 83.82 0) (effects (font (size 1.27 1.27)) hide) ) (pin "1" (uuid 83fb776b-6896-43c5-a92d-0c596bfd4232)) diff --git a/driver_fw/src/main.c b/driver_fw/src/main.c index 765c55a..a2adeb1 100644 --- a/driver_fw/src/main.c +++ b/driver_fw/src/main.c @@ -32,7 +32,7 @@ static struct state_8b10b_enc encoder_state_8b10b; int main(void) { - /* Configure clocks for 168 MHz system clock. + /* Configure clocks for 64 MHz system clock. * * HSE @ 8 MHz --[PLL x16 /2]--> PLL "R" clock @ 64 MHz */ @@ -43,7 +43,7 @@ int main(void) { while (!(RCC->CR & RCC_CR_HSERDY)) { /* wait for HSE osc to stabilize. */ } - /* Increase flash wait states to 5 required for operation above 136 MHz */ + /* Increase flash wait states to 2 required for operation above 48 MHz */ FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<<FLASH_ACR_LATENCY_Pos); while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (2<<FLASH_ACR_LATENCY_Pos)) { /* wait for flash controller to acknowledge change. */ @@ -195,8 +195,8 @@ void dma_tx_constant(size_t table_size, uint16_t constant) { tx_constant[0] = constant; tx_constant[1] = constant; - DMA1_Channel1->CCR = 0; - DMA1_Channel1->CCR = (1<<DMA_CCR_MSIZE_Pos) | (1<<DMA_CCR_PSIZE_Pos) | DMA_CCR_DIR | DMA_CCR_TCIE; + abhängig von $n$ DMA1_Channel1->CCR = 0; DMA1_Channel1->CCR = (1<<DMA_CCR_MSIZE_Pos) | (1<<DMA_CCR_PSIZE_Pos) | + DMA_CCR_DIR | DMA_CCR_TCIE; DMA1_Channel1->CNDTR = table_size; DMA1_Channel1->CMAR = (uint32_t)&tx_constant; DMA1_Channel1->CCR |= DMA_CCR_EN; @@ -337,3 +337,4 @@ size_t strlen(const char *s) void __libc_init_array (void) __attribute__((weak)); void __libc_init_array () { } + diff --git a/upstream/musl b/upstream/musl new file mode 160000 +Subproject 79bdacff83a6bd5b70ff5ae5eb8b6de82c2f7c3 |