Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-01-05 | Add some documentation | jaseg | 3 | -7/+29 |
2017-12-10 | Make status request work, fix uc-side cobs encoding bug | jaseg | 1 | -0/+0 |
2017-09-18 | hw v0.4 | jaseg | 12 | -2269/+2255 |
2017-09-06 | Fix up RS485/digital power label | jaseg | 12 | -77/+1986 |
2017-09-06 | Fix up version label and one ground trace | jaseg | 15 | -28917/+29500 |
2017-09-06 | Fixes for second prototype (v0.3) | jaseg | 20 | -9151/+10638 |
2017-07-21 | Second production run, v0.3 | jaseg | 15 | -8822/+9494 |
2017-07-21 | Final silk art positioning | jaseg | 12 | -111925/+111925 |
2017-07-20 | Second board revision | jaseg | 16 | -160767/+167539 |
2017-07-15 | Schematic fixed up so far | jaseg | 13 | -3006/+3496 |
2017-06-12 | Add resistor calculation script | jaseg | 1 | -0/+127 |
2017-06-10 | foo | jaseg | 12 | -1689/+1542 |
2017-05-17 | Release v0.2 | jaseg | 28 | -17464/+18529 |
2017-05-04 | Design mostly done | jaseg | 52 | -4218/+352110 |
2017-05-02 | Layout mostly done | jaseg | 4 | -1139/+5319 |
2017-04-30 | Foo | jaseg | 6 | -4957/+4778 |
2017-04-29 | Pre safety fixup | jaseg | 8 | -1438/+7443 |
2017-04-28 | Added protection stuff | jaseg | 5 | -2518/+4612 |
2017-04-26 | Initial commit | jaseg | 19 | -0/+12924 |