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2017-09-18hw v0.4jaseg12-2269/+2255
2017-09-06Fix up RS485/digital power labeljaseg12-77/+1986
2017-09-06Fix up version label and one ground tracejaseg15-28917/+29500
2017-09-06Fixes for second prototype (v0.3)jaseg20-9151/+10638
2017-07-21Second production run, v0.3jaseg15-8822/+9494
2017-07-21Final silk art positioningjaseg12-111925/+111925
2017-07-20Second board revisionjaseg16-160767/+167539
2017-07-15Schematic fixed up so farjaseg13-3006/+3496
2017-06-12Add resistor calculation scriptjaseg1-0/+127
2017-06-10foojaseg12-1689/+1542
2017-05-17Release v0.2jaseg28-17464/+18529
2017-05-04Design mostly donejaseg52-4218/+352110
2017-05-02Layout mostly donejaseg4-1139/+5319
2017-04-30Foojaseg6-4957/+4778
2017-04-29Pre safety fixupjaseg8-1438/+7443
2017-04-28Added protection stuffjaseg5-2518/+4612
2017-04-26Initial commitjaseg19-0/+12924