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AgeCommit message (Collapse)AuthorFilesLines
2017-12-09Fixed aux cyclejaseg1-50/+55
2017-12-09Cycle timing is fixed againjaseg1-54/+76
2017-12-08Basic UART working, but too slowjaseg1-297/+54
2017-09-18hw v0.4jaseg1-95/+177
2017-09-06Fixes for second prototype (v0.3)jaseg1-3/+5
2017-09-02Temperature/VCC ADC workingjaseg2-21/+95
2017-09-01Now with working source extraction from firmwarejaseg4-10/+18
2017-09-01Add missing filesjaseg6-2/+298
2017-09-01UART magic seems to be working nowjaseg4-121/+216
2017-09-01DMA channel assignments redone, basic protocol stuff workingjaseg3-34/+121
2017-08-24Serial protocol now working including CRCjaseg2-9/+37
2017-08-23Interrupt-driven SPI1 fundamentally workingjaseg1-44/+78
2017-08-23Comms working except for TIM3/SPI1 racejaseg2-6/+17
2017-08-23Add cmsis export generatorjaseg2-0/+32
2017-08-23Add transpose testjaseg6-129/+280
2017-08-22Add profiling scriptjaseg2-0/+31
2017-08-15Benchmark codejaseg2-7/+24
2017-08-15working commitjaseg3-19/+60
2017-08-15Temporary for bit shufflingjaseg1-11/+5
2017-08-15Working on uart codejaseg2-35/+147
2017-08-14Multiplexing is workingjaseg3-65/+166
2017-08-13Board rev 0.3 workingjaseg1-12/+45
2017-07-20Add missing firmware build filesjaseg2-0/+286
2017-06-12Add resistor calculation scriptjaseg1-22/+22
2017-06-11Test program workingjaseg1-30/+54
2017-06-10fw working commitjaseg8-0/+802
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