| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-08-24 | Serial protocol now working including CRC | jaseg | 2 | -9/+37 |
| 2017-08-23 | Interrupt-driven SPI1 fundamentally working | jaseg | 1 | -44/+78 |
| 2017-08-23 | Comms working except for TIM3/SPI1 race | jaseg | 2 | -6/+17 |
| 2017-08-23 | Add cmsis export generator | jaseg | 2 | -0/+32 |
| 2017-08-23 | Add transpose test | jaseg | 6 | -129/+280 |
| 2017-08-22 | Add profiling script | jaseg | 2 | -0/+31 |
| 2017-08-15 | Benchmark code | jaseg | 2 | -7/+24 |
| 2017-08-15 | working commit | jaseg | 3 | -19/+60 |
| 2017-08-15 | Temporary for bit shuffling | jaseg | 1 | -11/+5 |
| 2017-08-15 | Working on uart code | jaseg | 2 | -35/+147 |
| 2017-08-14 | Multiplexing is working | jaseg | 3 | -65/+166 |
| 2017-08-13 | Board rev 0.3 working | jaseg | 1 | -12/+45 |
| 2017-07-20 | Add missing firmware build files | jaseg | 2 | -0/+286 |
| 2017-06-12 | Add resistor calculation script | jaseg | 1 | -22/+22 |
| 2017-06-11 | Test program working | jaseg | 1 | -30/+54 |
| 2017-06-10 | fw working commit | jaseg | 8 | -0/+802 |
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index : 7seg.git | |
| 7seg: Large display made up of hundreds of 7-segment displays | jaseg |
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