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| author | jaseg <git@jaseg.net> | 2018-04-20 14:04:16 +0200 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2018-04-20 14:04:16 +0200 |
| commit | bc136ef5b17b89bc42efd222fe5aed894942639d (patch) | |
| tree | 1b1256611774a636f5e838f4a8f989d2e37bfa92 /fw | |
| parent | 6d5c101e2fa717f2c8b55e628feb4678e4e8f262 (diff) | |
| download | 7seg-bc136ef5b17b89bc42efd222fe5aed894942639d.tar.gz 7seg-bc136ef5b17b89bc42efd222fe5aed894942639d.tar.bz2 7seg-bc136ef5b17b89bc42efd222fe5aed894942639d.zip | |
Small firmware foo
Diffstat (limited to 'fw')
| -rw-r--r-- | fw/serial.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fw/serial.c b/fw/serial.c index fc797e3..891a7a6 100644 --- a/fw/serial.c +++ b/fw/serial.c @@ -43,7 +43,7 @@ void serial_init() { | USART_CR1_RE; //USART1->CR2 = USART_CR2_RTOEN; /* Timeout enable */ USART1->CR3 = USART_CR3_DEM; /* RS485 DE enable (output on RTS) */ - /* Set divider for 25MHz baud rate @50MHz system clock. */ + /* Set divider for 2MHz baud rate @50MHz system clock. */ int usartdiv = 25; USART1->BRR = usartdiv; |