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| author | jaseg <git@jaseg.net> | 2018-07-01 13:55:01 +0200 |
|---|---|---|
| committer | jaseg <git@jaseg.net> | 2018-07-01 13:55:01 +0200 |
| commit | e6ce637b340f59ec1f0e4047d8ad61758dc86685 (patch) | |
| tree | 08c097dccaa1f2d540e2fc7ca7709fca18a7785d /frontend_board.kicad_pcb | |
| parent | 5d487243016eeff20bddb8271d245215a9902443 (diff) | |
| download | 002-e6ce637b340f59ec1f0e4047d8ad61758dc86685.tar.gz 002-e6ce637b340f59ec1f0e4047d8ad61758dc86685.tar.bz2 002-e6ce637b340f59ec1f0e4047d8ad61758dc86685.zip | |
Add cable breakout board
Diffstat (limited to 'frontend_board.kicad_pcb')
| -rw-r--r-- | frontend_board.kicad_pcb | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/frontend_board.kicad_pcb b/frontend_board.kicad_pcb index cadfd61..6a824a7 100644 --- a/frontend_board.kicad_pcb +++ b/frontend_board.kicad_pcb @@ -3,9 +3,9 @@ (general (links 305) (no_connects 0) - (area 109.924999 89.924999 180.075001 140.075001) + (area 97.150001 82.3 188.446143 144.564) (thickness 1.6) - (drawings 210) + (drawings 214) (tracks 945) (zones 0) (modules 127) @@ -74,7 +74,7 @@ (grid_origin 0 115) (visible_elements FFFFFF7F) (pcbplotparams - (layerselection 0x010fc_80000001) + (layerselection 0x010fc_80000007) (usegerberextensions true) (excludeedgelayer true) (linewidth 0.100000) @@ -5078,6 +5078,10 @@ ) ) + (gr_line (start 110 140) (end 110.5 140) (layer B.SilkS) (width 0.15)) + (gr_line (start 110 139.5) (end 110 140) (layer B.SilkS) (width 0.15)) + (gr_line (start 180 90) (end 180 90.5) (layer B.SilkS) (width 0.15)) + (gr_line (start 179.5 90) (end 180 90) (layer B.SilkS) (width 0.15)) (gr_text "Project 002\nv0.1\n(c) 2018 jaseg\ncc-by-sa\ngithub.com/jaseg/002" (at 163.35 139.4 270) (layer F.SilkS) (effects (font (size 1.3 1.3) (thickness 0.25)) (justify right)) ) |