diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/cmsis_compiler.h | 283 | ||||
| -rw-r--r-- | include/cmsis_gcc.h | 2168 | ||||
| -rw-r--r-- | include/cmsis_version.h | 39 | ||||
| -rw-r--r-- | include/core_cm3.h | 1937 | ||||
| -rw-r--r-- | include/global.h | 108 | ||||
| -rw-r--r-- | include/iomacros.h | 14 | ||||
| -rw-r--r-- | include/irqs.h | 56 | ||||
| -rw-r--r-- | include/stm32.h | 2 | ||||
| -rw-r--r-- | include/stm32_irqs.h | 56 | ||||
| -rw-r--r-- | include/stm32f103xb.h | 10240 | ||||
| -rw-r--r-- | include/stm32f1xx.h | 273 | ||||
| -rw-r--r-- | include/system_stm32f1xx.h | 103 |
12 files changed, 15279 insertions, 0 deletions
diff --git a/include/cmsis_compiler.h b/include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include <stdint.h> + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include <cmsis_iccarm.h> + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include <cmsis_ccs.h> + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include <cmsis_csm.h> + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/include/cmsis_gcc.h b/include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; i<pTable->wlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; i<pTable->wlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/include/cmsis_version.h b/include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/include/core_cm3.h b/include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include <stdint.h> + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.<br> + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.<br> + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + <strong>IO Type Qualifiers</strong> are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/include/global.h b/include/global.h new file mode 100644 index 0000000..4b93867 --- /dev/null +++ b/include/global.h @@ -0,0 +1,108 @@ + +#ifndef __GLOBAL_H__ +#define __GLOBAL_H__ + +#include <stdbool.h> +#include <stdint.h> +#include <sys/types.h> +#include <assert.h> +#include <string.h> + +/* The IRQ header must be included before stm32_device.h since ST defines a bunch of messy macros there. */ +#include <stm32_irqs.h> /* Header generated from stm32***_startup.s in Makefile */ + +#include <stm32f1xx.h> +#include <core_cm3.h> + +#define DMA_ISR_FLAGS_Pos(channel) (4 * ((channel) - 1)) +#define DMA_ISR_FLAGS_CH(channel) (0xf << DMA_ISR_FLAGS_Pos(channel)) + +#define COUNT_OF(x) ((sizeof(x)/sizeof(0[x])) / ((size_t)(!(sizeof(x) % sizeof(0[x]))))) + +#define APB1_PRESC (1<<(APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1_Msk) >> RCC_CFGR_PPRE1_Pos])) +#define AHB_PRESC (1<<(AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE_Msk) >> RCC_CFGR_HPRE_Pos])) + +#define AFRL(pin, val) ((val) << ((pin)*4)) +#define AFRH(pin, val) ((val) << (((pin)-8)*4)) +#define AF(pin) (2<<(2*(pin))) +#define OUT(pin) (1<<(2*(pin))) +#define IN(pin) (0) +#define ANALOG(pin) (3<<(2*(pin))) +#define CLEAR(pin) (3<<(2*(pin))) +#define PULLUP(pin) (1<<(2*pin)) +#define PULLDOWN(pin) (2<<(2*pin)) +#define BSRR_CLEAR(pin) ((1<<pin)<<16) +#define BSRR_SET(pin) (1<<pin) +#define BSRR_VALUE(pin, value) ((((!(value))<<pin)<<16) | ((!!(value))<<pin)) + +#ifndef SYSTICK_INTERVAL_US +#define SYSTICK_INTERVAL_US 1000 +#endif /* SYSTICK_INTERVAL_US */ + + +enum ErrorCode { + ERR_SUCCESS = 0, + ERR_TIMEOUT, + ERR_PHYSICAL_LAYER, + ERR_FRAMING, + ERR_PROTOCOL, + ERR_DMA, + ERR_BUSY, + ERR_BUFFER_OVERFLOW, + ERR_RX_OVERRUN, + ERR_TX_OVERRUN, +}; + +typedef enum ErrorCode ErrorCode; + +enum board_config { + BCFG_UNCONFIGURED = 0, + + /* The board assumes one of three configurations depending on connected periphery. + * + */ + + BCFG_DISPLAY, + /* When an I2C 1602 display is connected to the LCD connector on powerup, the board assumes its display + * configuration. In this configuration, the board scans the buttons connected on the Buttons connector and acts as + * a peripheral on the RS-485 bus, relaying information between the bus and the HCI peripherals. In addition to the + * LCD, the board controls three 8-digit 7-segment LED displays connected on the Buttons connector along with the + * buttons. + * + * RS-485 board address: BADDR_DISPLAY + */ + + BCFG_MOTOR, + /* When no LCD is connected and the BT0 input on the buttons connector is open, the board assumes its + * motor configuration. In this configuration, the board controls a motor connected through the Buttons and LCD + * connectors, and the USB control interface is enabled. The board acts as the host on the RS-485 bus. + * + * RS-485 board address: BADDR_MOTOR + */ + + BCFG_MEAS, + /* When no LCD is connected and the BT0 input on the buttons connector is tied to ground, the board assumes its + * senesor configuration. In this configuration, the board periodically. The board acts as a peripheral on the + * RS-485 bus, relaying measurements on the bus when requested by the host. The board's bus address is set by pins + * BT1 and BT0 of the buttons connector. Both pins have pullups enabled, and will read zero when tied to ground on + * the connector. The address is the binary value of {BT2, BT1} added to BADDR_MES_BASE. With both pins open, the + * address is 11 (decimal), with BT1 tied to ground it is 10 (decimal). + * + * RS-485 board address: BADDR_MEAS_BASE + [BT2:1] + */ +}; + +enum board_addr { + BADDR_DISPLAY = 1, + BADDR_MOTOR = 2, + BADDR_MEAS_BASE = 8, +}; + +void delay_us(int duration_us); +uint64_t get_sync_time(void); + +extern enum board_config board_config; +extern volatile uint64_t sys_time_us; +extern volatile uint64_t sync_time_us; + +#endif /* __GLOBAL_H__ */ diff --git a/include/iomacros.h b/include/iomacros.h new file mode 100644 index 0000000..8d84c9e --- /dev/null +++ b/include/iomacros.h @@ -0,0 +1,14 @@ +#ifndef __IOMACROS_H__ +#define __IOMACROS_H__ + +#define IN(pin) (0) +#define OUT(pin) (1<<(2*(pin))) +#define AF(pin) (2<<(2*(pin))) +#define ANALOG(pin) (3<<(2*(pin))) + +#define CLEAR(pin) (~(3<<(2*(pin)))) + +#define AFRL(pin, val) ((val) << ((pin)*4)) +#define AFRH(pin, val) ((val) << (((pin)-8)*4)) + +#endif __IOMACROS_H__ diff --git a/include/irqs.h b/include/irqs.h new file mode 100644 index 0000000..f530a4d --- /dev/null +++ b/include/irqs.h @@ -0,0 +1,56 @@ +/* AUTOGENERATED FILE! DO NOT MODIFY! */ +/* Generated {datetime.datetime.utcnow()} from {args.input} */ + +void _estack(void); /* 0 */ +void Reset_Handler(void); /* 1 */ +void NMI_Handler(void); /* 2 */ +void HardFault_Handler(void); /* 3 */ +/* IRQ 4 is undefined for this part. */ +/* IRQ 5 is undefined for this part. */ +/* IRQ 6 is undefined for this part. */ +/* IRQ 7 is undefined for this part. */ +/* IRQ 8 is undefined for this part. */ +/* IRQ 9 is undefined for this part. */ +/* IRQ 10 is undefined for this part. */ +void SVC_Handler(void); /* 11 */ +/* IRQ 12 is undefined for this part. */ +/* IRQ 13 is undefined for this part. */ +void PendSV_Handler(void); /* 14 */ +void SysTick_Handler(void); /* 15 */ +void WWDG_IRQHandler(void); /* 16 */ +void PVD_VDDIO2_IRQHandler(void); /* 17 */ +void RTC_IRQHandler(void); /* 18 */ +void FLASH_IRQHandler(void); /* 19 */ +void RCC_CRS_IRQHandler(void); /* 20 */ +void EXTI0_1_IRQHandler(void); /* 21 */ +void EXTI2_3_IRQHandler(void); /* 22 */ +void EXTI4_15_IRQHandler(void); /* 23 */ +void TSC_IRQHandler(void); /* 24 */ +void DMA1_Channel1_IRQHandler(void); /* 25 */ +void DMA1_Channel2_3_IRQHandler(void); /* 26 */ +void DMA1_Channel4_5_6_7_IRQHandler(void); /* 27 */ +void ADC1_COMP_IRQHandler(void); /* 28 */ +void TIM1_BRK_UP_TRG_COM_IRQHandler(void); /* 29 */ +void TIM1_CC_IRQHandler(void); /* 30 */ +void TIM2_IRQHandler(void); /* 31 */ +void TIM3_IRQHandler(void); /* 32 */ +void TIM6_DAC_IRQHandler(void); /* 33 */ +void TIM7_IRQHandler(void); /* 34 */ +void TIM14_IRQHandler(void); /* 35 */ +void TIM15_IRQHandler(void); /* 36 */ +void TIM16_IRQHandler(void); /* 37 */ +void TIM17_IRQHandler(void); /* 38 */ +void I2C1_IRQHandler(void); /* 39 */ +void I2C2_IRQHandler(void); /* 40 */ +void SPI1_IRQHandler(void); /* 41 */ +void SPI2_IRQHandler(void); /* 42 */ +void USART1_IRQHandler(void); /* 43 */ +void USART2_IRQHandler(void); /* 44 */ +void USART3_4_IRQHandler(void); /* 45 */ +void CEC_CAN_IRQHandler(void); /* 46 */ +void USB_IRQHandler(void); /* 47 */ + +#define NUM_IRQs 48 +extern uint32_t g_pfnVectors[NUM_IRQs]; +#define isr_vector g_pfnVectors + diff --git a/include/stm32.h b/include/stm32.h new file mode 100644 index 0000000..1db4903 --- /dev/null +++ b/include/stm32.h @@ -0,0 +1,2 @@ +/* libusb_stm compatibility file */ +#include "stm32f072xb.h" diff --git a/include/stm32_irqs.h b/include/stm32_irqs.h new file mode 100644 index 0000000..f530a4d --- /dev/null +++ b/include/stm32_irqs.h @@ -0,0 +1,56 @@ +/* AUTOGENERATED FILE! DO NOT MODIFY! */ +/* Generated {datetime.datetime.utcnow()} from {args.input} */ + +void _estack(void); /* 0 */ +void Reset_Handler(void); /* 1 */ +void NMI_Handler(void); /* 2 */ +void HardFault_Handler(void); /* 3 */ +/* IRQ 4 is undefined for this part. */ +/* IRQ 5 is undefined for this part. */ +/* IRQ 6 is undefined for this part. */ +/* IRQ 7 is undefined for this part. */ +/* IRQ 8 is undefined for this part. */ +/* IRQ 9 is undefined for this part. */ +/* IRQ 10 is undefined for this part. */ +void SVC_Handler(void); /* 11 */ +/* IRQ 12 is undefined for this part. */ +/* IRQ 13 is undefined for this part. */ +void PendSV_Handler(void); /* 14 */ +void SysTick_Handler(void); /* 15 */ +void WWDG_IRQHandler(void); /* 16 */ +void PVD_VDDIO2_IRQHandler(void); /* 17 */ +void RTC_IRQHandler(void); /* 18 */ +void FLASH_IRQHandler(void); /* 19 */ +void RCC_CRS_IRQHandler(void); /* 20 */ +void EXTI0_1_IRQHandler(void); /* 21 */ +void EXTI2_3_IRQHandler(void); /* 22 */ +void EXTI4_15_IRQHandler(void); /* 23 */ +void TSC_IRQHandler(void); /* 24 */ +void DMA1_Channel1_IRQHandler(void); /* 25 */ +void DMA1_Channel2_3_IRQHandler(void); /* 26 */ +void DMA1_Channel4_5_6_7_IRQHandler(void); /* 27 */ +void ADC1_COMP_IRQHandler(void); /* 28 */ +void TIM1_BRK_UP_TRG_COM_IRQHandler(void); /* 29 */ +void TIM1_CC_IRQHandler(void); /* 30 */ +void TIM2_IRQHandler(void); /* 31 */ +void TIM3_IRQHandler(void); /* 32 */ +void TIM6_DAC_IRQHandler(void); /* 33 */ +void TIM7_IRQHandler(void); /* 34 */ +void TIM14_IRQHandler(void); /* 35 */ +void TIM15_IRQHandler(void); /* 36 */ +void TIM16_IRQHandler(void); /* 37 */ +void TIM17_IRQHandler(void); /* 38 */ +void I2C1_IRQHandler(void); /* 39 */ +void I2C2_IRQHandler(void); /* 40 */ +void SPI1_IRQHandler(void); /* 41 */ +void SPI2_IRQHandler(void); /* 42 */ +void USART1_IRQHandler(void); /* 43 */ +void USART2_IRQHandler(void); /* 44 */ +void USART3_4_IRQHandler(void); /* 45 */ +void CEC_CAN_IRQHandler(void); /* 46 */ +void USB_IRQHandler(void); /* 47 */ + +#define NUM_IRQs 48 +extern uint32_t g_pfnVectors[NUM_IRQs]; +#define isr_vector g_pfnVectors + diff --git a/include/stm32f103xb.h b/include/stm32f103xb.h new file mode 100644 index 0000000..82df4b0 --- /dev/null +++ b/include/stm32f103xb.h @@ -0,0 +1,10240 @@ +/** + ****************************************************************************** + * @file stm32f103xb.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f103xb + * @{ + */ + +#ifndef __STM32F103xB_H +#define __STM32F103xB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ + #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f1xx.h" +#include <stdint.h> + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ + __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ + uint32_t RESERVED[16]; + __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ +} ADC_Common_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; + __IO uint32_t DR8; + __IO uint32_t DR9; + __IO uint32_t DR10; + __IO uint32_t RTCCR; + __IO uint32_t CR; + __IO uint32_t CSR; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[14]; +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ + uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t CRH; + __IO uint32_t CRL; + __IO uint32_t PRLH; + __IO uint32_t PRLL; + __IO uint32_t DIVH; + __IO uint32_t DIVL; + __IO uint32_t CNTH; + __IO uint32_t CNTL; + __IO uint32_t ALRH; + __IO uint32_t ALRL; +} RTC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t CRCPR; + __IO uint32_t RXCRCR; + __IO uint32_t TXCRCR; + __IO uint32_t I2SCFGR; +} SPI_TypeDef; + +/** + * @brief TIM Timers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +}TIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ +} USB_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) + + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ + +/* USB device FS */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ + + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define USB ((USB_TypeDef *)USB_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS_Pos (0U) +#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ +#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS_Pos (1U) +#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ +#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF_Pos (2U) +#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ +#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF_Pos (3U) +#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ +#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ +#define PWR_CR_PVDE_Pos (4U) +#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS_Pos (5U) +#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 + +#define PWR_CR_DBP_Pos (8U) +#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF_Pos (0U) +#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ +#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ +#define PWR_CSR_SBF_Pos (1U) +#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ +#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ +#define PWR_CSR_PVDO_Pos (2U) +#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ +#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ +#define PWR_CSR_EWUP_Pos (8U) +#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D_Pos (0U) +#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D_Pos (0U) +#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D_Pos (0U) +#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D_Pos (0U) +#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D_Pos (0U) +#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D_Pos (0U) +#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D_Pos (0U) +#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D_Pos (0U) +#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D_Pos (0U) +#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D_Pos (0U) +#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ +#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ + +#define RTC_BKP_NUMBER 10 + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL_Pos (0U) +#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ +#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ +#define BKP_RTCCR_CCO_Pos (7U) +#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ +#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE_Pos (8U) +#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ +#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS_Pos (9U) +#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ +#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE_Pos (0U) +#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ +#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ +#define BKP_CR_TPAL_Pos (1U) +#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ +#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE_Pos (0U) +#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ +#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ +#define BKP_CSR_CTI_Pos (1U) +#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ +#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE_Pos (2U) +#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ +#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF_Pos (8U) +#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ +#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ +#define BKP_CSR_TIF_Pos (9U) +#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ +#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY_Pos (1U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM_Pos (3U) +#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ +#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL_Pos (8U) +#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ +#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON_Pos (19U) +#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ +#define RCC_CR_PLLON_Pos (24U) +#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ +#define RCC_CR_PLLRDY_Pos (25U) +#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ + + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ + +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (2U) +#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ + +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_Pos (4U) +#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ +#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ +#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ + +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_Pos (8U) +#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ +#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ + +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_Pos (11U) +#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ +#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE_Pos (14U) +#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ +#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ +#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ + +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC_Pos (16U) +#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE_Pos (17U) +#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL_Pos (18U) +#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ + +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL3_Pos (18U) +#define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ +#define RCC_CFGR_PLLMULL4_Pos (19U) +#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ +#define RCC_CFGR_PLLMULL5_Pos (18U) +#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ +#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ +#define RCC_CFGR_PLLMULL6_Pos (20U) +#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ +#define RCC_CFGR_PLLMULL7_Pos (18U) +#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ +#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ +#define RCC_CFGR_PLLMULL8_Pos (19U) +#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ +#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ +#define RCC_CFGR_PLLMULL9_Pos (18U) +#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ +#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ +#define RCC_CFGR_PLLMULL10_Pos (21U) +#define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ +#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ +#define RCC_CFGR_PLLMULL11_Pos (18U) +#define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ +#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ +#define RCC_CFGR_PLLMULL12_Pos (19U) +#define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ +#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ +#define RCC_CFGR_PLLMULL13_Pos (18U) +#define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ +#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ +#define RCC_CFGR_PLLMULL14_Pos (20U) +#define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ +#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ +#define RCC_CFGR_PLLMULL15_Pos (18U) +#define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ +#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ +#define RCC_CFGR_PLLMULL16_Pos (19U) +#define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ +#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ +#define RCC_CFGR_USBPRE_Pos (22U) +#define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_Pos (24U) +#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ +#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ + +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ + + /* Reference defines */ + #define RCC_CFGR_MCOSEL RCC_CFGR_MCO + #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 + #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 + #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 + #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK + #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK + #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI + #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE + #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF_Pos (0U) +#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF_Pos (1U) +#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF_Pos (2U) +#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF_Pos (3U) +#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF_Pos (4U) +#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF_Pos (7U) +#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ +#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE_Pos (8U) +#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE_Pos (9U) +#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ +#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE_Pos (10U) +#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ +#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE_Pos (11U) +#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ +#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE_Pos (12U) +#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ +#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC_Pos (16U) +#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ +#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC_Pos (17U) +#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ +#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC_Pos (18U) +#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ +#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC_Pos (19U) +#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ +#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC_Pos (20U) +#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ +#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC_Pos (23U) +#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ +#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ + + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST_Pos (0U) +#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST_Pos (2U) +#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ +#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST_Pos (3U) +#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ +#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST_Pos (4U) +#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST_Pos (5U) +#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ +#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST_Pos (9U) +#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ + +#define RCC_APB2RSTR_ADC2RST_Pos (10U) +#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ +#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ + +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ + + +#define RCC_APB2RSTR_IOPERST_Pos (6U) +#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ +#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ + + + + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST_Pos (0U) +#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST_Pos (1U) +#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST_Pos (11U) +#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ +#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST_Pos (17U) +#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST_Pos (21U) +#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ + +#define RCC_APB1RSTR_CAN1RST_Pos (25U) +#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ +#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ + +#define RCC_APB1RSTR_BKPRST_Pos (27U) +#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST_Pos (28U) +#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ +#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ + +#define RCC_APB1RSTR_TIM4RST_Pos (2U) +#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ +#define RCC_APB1RSTR_SPI2RST_Pos (14U) +#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ +#define RCC_APB1RSTR_USART3RST_Pos (18U) +#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ +#define RCC_APB1RSTR_I2C2RST_Pos (22U) +#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ + +#define RCC_APB1RSTR_USBRST_Pos (23U) +#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ + + + + + + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN_Pos (0U) +#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN_Pos (2U) +#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN_Pos (4U) +#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ +#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN_Pos (6U) +#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ +#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ + + + + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN_Pos (0U) +#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN_Pos (2U) +#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ +#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN_Pos (3U) +#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ +#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN_Pos (4U) +#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN_Pos (5U) +#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ +#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN_Pos (9U) +#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ + +#define RCC_APB2ENR_ADC2EN_Pos (10U) +#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ +#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ + +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ + + +#define RCC_APB2ENR_IOPEEN_Pos (6U) +#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ +#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ + + + + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN_Pos (0U) +#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN_Pos (1U) +#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN_Pos (11U) +#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN_Pos (17U) +#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN_Pos (21U) +#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ + +#define RCC_APB1ENR_CAN1EN_Pos (25U) +#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ +#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ + +#define RCC_APB1ENR_BKPEN_Pos (27U) +#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN_Pos (28U) +#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ +#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ + +#define RCC_APB1ENR_TIM4EN_Pos (2U) +#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_SPI2EN_Pos (14U) +#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_USART3EN_Pos (18U) +#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ +#define RCC_APB1ENR_I2C2EN_Pos (22U) +#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ + +#define RCC_APB1ENR_USBEN_Pos (23U) +#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ + + + + + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ + +/*!< RTC configuration */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ +#define RCC_BDCR_BDRST_Pos (16U) +#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF_Pos (24U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF_Pos (27U) +#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ + + + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE_Pos (0U) +#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0_Pos (0U) +#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ + +#define GPIO_CRL_MODE1_Pos (4U) +#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ +#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ +#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ + +#define GPIO_CRL_MODE2_Pos (8U) +#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ +#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ +#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ + +#define GPIO_CRL_MODE3_Pos (12U) +#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ +#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ +#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ + +#define GPIO_CRL_MODE4_Pos (16U) +#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ +#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ +#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ + +#define GPIO_CRL_MODE5_Pos (20U) +#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ +#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ +#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ + +#define GPIO_CRL_MODE6_Pos (24U) +#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ +#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ +#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ + +#define GPIO_CRL_MODE7_Pos (28U) +#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ +#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ +#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ + +#define GPIO_CRL_CNF_Pos (2U) +#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0_Pos (2U) +#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ +#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ +#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ + +#define GPIO_CRL_CNF1_Pos (6U) +#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ +#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ +#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ + +#define GPIO_CRL_CNF2_Pos (10U) +#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ +#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ +#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ + +#define GPIO_CRL_CNF3_Pos (14U) +#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ +#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ +#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ + +#define GPIO_CRL_CNF4_Pos (18U) +#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ +#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ +#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ + +#define GPIO_CRL_CNF5_Pos (22U) +#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ +#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ +#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ + +#define GPIO_CRL_CNF6_Pos (26U) +#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ +#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ +#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ + +#define GPIO_CRL_CNF7_Pos (30U) +#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ +#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ +#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE_Pos (0U) +#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ +#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8_Pos (0U) +#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ +#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ +#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ + +#define GPIO_CRH_MODE9_Pos (4U) +#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ +#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ +#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ + +#define GPIO_CRH_MODE10_Pos (8U) +#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ +#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ +#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ + +#define GPIO_CRH_MODE11_Pos (12U) +#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ +#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ +#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ + +#define GPIO_CRH_MODE12_Pos (16U) +#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ +#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ +#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ + +#define GPIO_CRH_MODE13_Pos (20U) +#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ +#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ +#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ + +#define GPIO_CRH_MODE14_Pos (24U) +#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ +#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ +#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ + +#define GPIO_CRH_MODE15_Pos (28U) +#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ +#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ +#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ + +#define GPIO_CRH_CNF_Pos (2U) +#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ +#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8_Pos (2U) +#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ +#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ +#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ + +#define GPIO_CRH_CNF9_Pos (6U) +#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ +#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ +#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ + +#define GPIO_CRH_CNF10_Pos (10U) +#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ +#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ +#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ + +#define GPIO_CRH_CNF11_Pos (14U) +#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ +#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ +#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ + +#define GPIO_CRH_CNF12_Pos (18U) +#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ +#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ +#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ + +#define GPIO_CRH_CNF13_Pos (22U) +#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ +#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ +#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ + +#define GPIO_CRH_CNF14_Pos (26U) +#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ +#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ +#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ + +#define GPIO_CRH_CNF15_Pos (30U) +#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ +#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ +#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0_Pos (0U) +#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1_Pos (1U) +#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2_Pos (2U) +#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3_Pos (3U) +#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4_Pos (4U) +#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5_Pos (5U) +#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6_Pos (6U) +#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7_Pos (7U) +#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8_Pos (8U) +#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9_Pos (9U) +#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10_Pos (10U) +#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11_Pos (11U) +#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12_Pos (12U) +#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13_Pos (13U) +#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14_Pos (14U) +#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15_Pos (15U) +#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0_Pos (0U) +#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1_Pos (1U) +#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2_Pos (2U) +#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3_Pos (3U) +#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4_Pos (4U) +#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5_Pos (5U) +#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6_Pos (6U) +#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7_Pos (7U) +#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8_Pos (8U) +#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9_Pos (9U) +#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10_Pos (10U) +#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11_Pos (11U) +#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12_Pos (12U) +#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13_Pos (13U) +#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14_Pos (14U) +#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15_Pos (15U) +#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN_Pos (0U) +#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1_Pos (0U) +#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ +#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2_Pos (1U) +#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ +#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3_Pos (0U) +#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ +#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4_Pos (2U) +#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ +#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5_Pos (0U) +#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ +#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6_Pos (1U) +#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ +#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7_Pos (0U) +#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ +#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8_Pos (3U) +#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ +#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9_Pos (0U) +#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ +#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10_Pos (1U) +#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ +#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11_Pos (0U) +#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ +#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12_Pos (2U) +#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ +#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13_Pos (0U) +#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ +#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14_Pos (1U) +#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ +#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15_Pos (0U) +#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ +#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT_Pos (4U) +#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ +#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB_Pos (4U) +#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC_Pos (5U) +#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD_Pos (4U) +#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE_Pos (6U) +#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ + +#define AFIO_EVCR_EVOE_Pos (7U) +#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ +#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP_Pos (0U) +#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ +#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP_Pos (1U) +#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ +#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP_Pos (2U) +#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ +#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP_Pos (3U) +#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ +#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) +#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ +#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP_Pos (12U) +#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ +#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ +#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) +#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) +#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP_Pos (15U) +#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ +#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ +#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ + +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) +#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) +#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ +#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ + + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0_Pos (0U) +#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1_Pos (4U) +#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2_Pos (8U) +#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3_Pos (12U) +#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) +#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) +#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) +#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) +#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) +#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) +#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) +#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) +#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) +#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) +#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) +#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) +#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4_Pos (0U) +#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5_Pos (4U) +#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6_Pos (8U) +#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7_Pos (12U) +#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) +#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) +#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) +#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) +#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) +#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) +#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) +#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) +#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) +#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) +#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) +#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) +#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8_Pos (0U) +#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9_Pos (4U) +#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10_Pos (8U) +#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11_Pos (12U) +#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) +#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) +#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) +#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) +#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) +#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) +#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) +#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) +#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) +#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) +#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) +#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) +#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12_Pos (0U) +#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ +#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13_Pos (4U) +#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ +#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14_Pos (8U) +#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ +#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15_Pos (12U) +#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ +#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ +#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ +#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ +#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) +#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ +#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) +#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ +#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) +#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ +#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ +#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ +#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ +#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) +#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ +#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) +#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ +#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) +#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ +#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ +#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ +#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ +#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) +#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ +#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) +#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ +#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) +#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ +#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ +#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ +#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ +#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) +#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ +#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) +#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ +#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) +#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ +#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ + +/****************** Bit definition for AFIO_MAPR2 register ******************/ + + + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0_Pos (0U) +#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1_Pos (1U) +#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2_Pos (2U) +#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3_Pos (3U) +#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4_Pos (4U) +#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5_Pos (5U) +#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6_Pos (6U) +#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7_Pos (7U) +#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8_Pos (8U) +#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9_Pos (9U) +#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10_Pos (10U) +#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11_Pos (11U) +#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12_Pos (12U) +#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13_Pos (13U) +#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14_Pos (14U) +#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15_Pos (15U) +#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16_Pos (16U) +#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17_Pos (17U) +#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18_Pos (18U) +#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ + +/* References Defines */ +#define EXTI_IMR_IM0 EXTI_IMR_MR0 +#define EXTI_IMR_IM1 EXTI_IMR_MR1 +#define EXTI_IMR_IM2 EXTI_IMR_MR2 +#define EXTI_IMR_IM3 EXTI_IMR_MR3 +#define EXTI_IMR_IM4 EXTI_IMR_MR4 +#define EXTI_IMR_IM5 EXTI_IMR_MR5 +#define EXTI_IMR_IM6 EXTI_IMR_MR6 +#define EXTI_IMR_IM7 EXTI_IMR_MR7 +#define EXTI_IMR_IM8 EXTI_IMR_MR8 +#define EXTI_IMR_IM9 EXTI_IMR_MR9 +#define EXTI_IMR_IM10 EXTI_IMR_MR10 +#define EXTI_IMR_IM11 EXTI_IMR_MR11 +#define EXTI_IMR_IM12 EXTI_IMR_MR12 +#define EXTI_IMR_IM13 EXTI_IMR_MR13 +#define EXTI_IMR_IM14 EXTI_IMR_MR14 +#define EXTI_IMR_IM15 EXTI_IMR_MR15 +#define EXTI_IMR_IM16 EXTI_IMR_MR16 +#define EXTI_IMR_IM17 EXTI_IMR_MR17 +#define EXTI_IMR_IM18 EXTI_IMR_MR18 +#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0_Pos (0U) +#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1_Pos (1U) +#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2_Pos (2U) +#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3_Pos (3U) +#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4_Pos (4U) +#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5_Pos (5U) +#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6_Pos (6U) +#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7_Pos (7U) +#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8_Pos (8U) +#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9_Pos (9U) +#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10_Pos (10U) +#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11_Pos (11U) +#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12_Pos (12U) +#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13_Pos (13U) +#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14_Pos (14U) +#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15_Pos (15U) +#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16_Pos (16U) +#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17_Pos (17U) +#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18_Pos (18U) +#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ + +/* References Defines */ +#define EXTI_EMR_EM0 EXTI_EMR_MR0 +#define EXTI_EMR_EM1 EXTI_EMR_MR1 +#define EXTI_EMR_EM2 EXTI_EMR_MR2 +#define EXTI_EMR_EM3 EXTI_EMR_MR3 +#define EXTI_EMR_EM4 EXTI_EMR_MR4 +#define EXTI_EMR_EM5 EXTI_EMR_MR5 +#define EXTI_EMR_EM6 EXTI_EMR_MR6 +#define EXTI_EMR_EM7 EXTI_EMR_MR7 +#define EXTI_EMR_EM8 EXTI_EMR_MR8 +#define EXTI_EMR_EM9 EXTI_EMR_MR9 +#define EXTI_EMR_EM10 EXTI_EMR_MR10 +#define EXTI_EMR_EM11 EXTI_EMR_MR11 +#define EXTI_EMR_EM12 EXTI_EMR_MR12 +#define EXTI_EMR_EM13 EXTI_EMR_MR13 +#define EXTI_EMR_EM14 EXTI_EMR_MR14 +#define EXTI_EMR_EM15 EXTI_EMR_MR15 +#define EXTI_EMR_EM16 EXTI_EMR_MR16 +#define EXTI_EMR_EM17 EXTI_EMR_MR17 +#define EXTI_EMR_EM18 EXTI_EMR_MR18 + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0_Pos (0U) +#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1_Pos (1U) +#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2_Pos (2U) +#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3_Pos (3U) +#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4_Pos (4U) +#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5_Pos (5U) +#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6_Pos (6U) +#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7_Pos (7U) +#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8_Pos (8U) +#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9_Pos (9U) +#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10_Pos (10U) +#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11_Pos (11U) +#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12_Pos (12U) +#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13_Pos (13U) +#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14_Pos (14U) +#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15_Pos (15U) +#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16_Pos (16U) +#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17_Pos (17U) +#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18_Pos (18U) +#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_RTSR_RT0 EXTI_RTSR_TR0 +#define EXTI_RTSR_RT1 EXTI_RTSR_TR1 +#define EXTI_RTSR_RT2 EXTI_RTSR_TR2 +#define EXTI_RTSR_RT3 EXTI_RTSR_TR3 +#define EXTI_RTSR_RT4 EXTI_RTSR_TR4 +#define EXTI_RTSR_RT5 EXTI_RTSR_TR5 +#define EXTI_RTSR_RT6 EXTI_RTSR_TR6 +#define EXTI_RTSR_RT7 EXTI_RTSR_TR7 +#define EXTI_RTSR_RT8 EXTI_RTSR_TR8 +#define EXTI_RTSR_RT9 EXTI_RTSR_TR9 +#define EXTI_RTSR_RT10 EXTI_RTSR_TR10 +#define EXTI_RTSR_RT11 EXTI_RTSR_TR11 +#define EXTI_RTSR_RT12 EXTI_RTSR_TR12 +#define EXTI_RTSR_RT13 EXTI_RTSR_TR13 +#define EXTI_RTSR_RT14 EXTI_RTSR_TR14 +#define EXTI_RTSR_RT15 EXTI_RTSR_TR15 +#define EXTI_RTSR_RT16 EXTI_RTSR_TR16 +#define EXTI_RTSR_RT17 EXTI_RTSR_TR17 +#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0_Pos (0U) +#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1_Pos (1U) +#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2_Pos (2U) +#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3_Pos (3U) +#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4_Pos (4U) +#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5_Pos (5U) +#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6_Pos (6U) +#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7_Pos (7U) +#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8_Pos (8U) +#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9_Pos (9U) +#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10_Pos (10U) +#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11_Pos (11U) +#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12_Pos (12U) +#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13_Pos (13U) +#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14_Pos (14U) +#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15_Pos (15U) +#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16_Pos (16U) +#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17_Pos (17U) +#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18_Pos (18U) +#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ + +/* References Defines */ +#define EXTI_FTSR_FT0 EXTI_FTSR_TR0 +#define EXTI_FTSR_FT1 EXTI_FTSR_TR1 +#define EXTI_FTSR_FT2 EXTI_FTSR_TR2 +#define EXTI_FTSR_FT3 EXTI_FTSR_TR3 +#define EXTI_FTSR_FT4 EXTI_FTSR_TR4 +#define EXTI_FTSR_FT5 EXTI_FTSR_TR5 +#define EXTI_FTSR_FT6 EXTI_FTSR_TR6 +#define EXTI_FTSR_FT7 EXTI_FTSR_TR7 +#define EXTI_FTSR_FT8 EXTI_FTSR_TR8 +#define EXTI_FTSR_FT9 EXTI_FTSR_TR9 +#define EXTI_FTSR_FT10 EXTI_FTSR_TR10 +#define EXTI_FTSR_FT11 EXTI_FTSR_TR11 +#define EXTI_FTSR_FT12 EXTI_FTSR_TR12 +#define EXTI_FTSR_FT13 EXTI_FTSR_TR13 +#define EXTI_FTSR_FT14 EXTI_FTSR_TR14 +#define EXTI_FTSR_FT15 EXTI_FTSR_TR15 +#define EXTI_FTSR_FT16 EXTI_FTSR_TR16 +#define EXTI_FTSR_FT17 EXTI_FTSR_TR17 +#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0_Pos (0U) +#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1_Pos (1U) +#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2_Pos (2U) +#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3_Pos (3U) +#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4_Pos (4U) +#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5_Pos (5U) +#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6_Pos (6U) +#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7_Pos (7U) +#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8_Pos (8U) +#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9_Pos (9U) +#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10_Pos (10U) +#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11_Pos (11U) +#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12_Pos (12U) +#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13_Pos (13U) +#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14_Pos (14U) +#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15_Pos (15U) +#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16_Pos (16U) +#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17_Pos (17U) +#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18_Pos (18U) +#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ + +/* References Defines */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4_Pos (4U) +#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ +#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5_Pos (5U) +#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ +#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6_Pos (6U) +#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ +#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7_Pos (7U) +#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ +#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8_Pos (8U) +#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ +#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9_Pos (9U) +#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ +#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10_Pos (10U) +#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ +#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11_Pos (11U) +#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ +#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12_Pos (12U) +#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ +#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13_Pos (13U) +#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ +#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14_Pos (14U) +#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ +#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15_Pos (15U) +#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ +#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16_Pos (16U) +#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ +#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17_Pos (17U) +#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ +#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18_Pos (18U) +#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ +#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ + +/* References Defines */ +#define EXTI_PR_PIF0 EXTI_PR_PR0 +#define EXTI_PR_PIF1 EXTI_PR_PR1 +#define EXTI_PR_PIF2 EXTI_PR_PR2 +#define EXTI_PR_PIF3 EXTI_PR_PR3 +#define EXTI_PR_PIF4 EXTI_PR_PR4 +#define EXTI_PR_PIF5 EXTI_PR_PR5 +#define EXTI_PR_PIF6 EXTI_PR_PR6 +#define EXTI_PR_PIF7 EXTI_PR_PR7 +#define EXTI_PR_PIF8 EXTI_PR_PR8 +#define EXTI_PR_PIF9 EXTI_PR_PR9 +#define EXTI_PR_PIF10 EXTI_PR_PR10 +#define EXTI_PR_PIF11 EXTI_PR_PR11 +#define EXTI_PR_PIF12 EXTI_PR_PR12 +#define EXTI_PR_PIF13 EXTI_PR_PR13 +#define EXTI_PR_PIF14 EXTI_PR_PR14 +#define EXTI_PR_PIF15 EXTI_PR_PR15 +#define EXTI_PR_PIF16 EXTI_PR_PR16 +#define EXTI_PR_PIF17 EXTI_PR_PR17 +#define EXTI_PR_PIF18 EXTI_PR_PR18 + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register *******************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register ******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register *******************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register *******************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_SR_EOS_Pos (1U) +#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ +#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_SR_JEOS_Pos (2U) +#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ + +/* Legacy defines */ +#define ADC_SR_EOC (ADC_SR_EOS) +#define ADC_SR_JEOC (ADC_SR_JEOS) + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ + +#define ADC_CR1_EOSIE_Pos (5U) +#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_CR1_JEOSIE_Pos (7U) +#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ + +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ + +#define ADC_CR1_DUALMOD_Pos (16U) +#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ +#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ +#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ +#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ +#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ +#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ + +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +/* Legacy defines */ +#define ADC_CR1_EOCIE (ADC_CR1_EOSIE) +#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ +#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ +#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ +#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ +#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ + +#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ + +#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ + +#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ +#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ +#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10_Pos (0U) +#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP11_Pos (3U) +#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP12_Pos (6U) +#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP13_Pos (9U) +#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP14_Pos (12U) +#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP15_Pos (15U) +#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP16_Pos (18U) +#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP17_Pos (21U) +#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0_Pos (0U) +#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP1_Pos (3U) +#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP2_Pos (6U) +#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP3_Pos (9U) +#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP4_Pos (12U) +#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP5_Pos (15U) +#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP6_Pos (18U) +#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP7_Pos (21U) +#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP8_Pos (24U) +#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP9_Pos (27U) +#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ + +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ + +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ + +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ + +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ + +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ + +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ + +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ + +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ + +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ + +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ + +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ +#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ + +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ + +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ + +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ + +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_ADC2DATA_Pos (16U) +#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ +#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ + + +/*****************************************************************************/ +/* */ +/* Timers (TIM) */ +/* */ +/*****************************************************************************/ +/******************* Bit definition for TIM_CR1 register *******************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ +#define TIM_CR1_UDIS_Pos (1U) +#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ +#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ +#define TIM_CR1_URS_Pos (2U) +#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ +#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ +#define TIM_CR1_OPM_Pos (3U) +#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ +#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ +#define TIM_CR1_DIR_Pos (4U) +#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ +#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ + +#define TIM_CR1_CMS_Pos (5U) +#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ +#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ +#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ + +#define TIM_CR1_ARPE_Pos (7U) +#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ +#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ + +#define TIM_CR1_CKD_Pos (8U) +#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ +#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ +#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ + +/******************* Bit definition for TIM_CR2 register *******************/ +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ +#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ +#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ +#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS_Pos (4U) +#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ +#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ +#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ +#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ + +#define TIM_CR2_TI1S_Pos (7U) +#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ +#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ +#define TIM_CR2_OIS1_Pos (8U) +#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ +#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N_Pos (9U) +#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ +#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2_Pos (10U) +#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ +#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N_Pos (11U) +#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ +#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3_Pos (12U) +#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ +#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N_Pos (13U) +#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ +#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4_Pos (14U) +#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ +#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register ******************/ +#define TIM_SMCR_SMS_Pos (0U) +#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ +#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ +#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ +#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ + +#define TIM_SMCR_TS_Pos (4U) +#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ +#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ +#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ +#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ + +#define TIM_SMCR_MSM_Pos (7U) +#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ +#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ + +#define TIM_SMCR_ETF_Pos (8U) +#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ +#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ +#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ +#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ +#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ + +#define TIM_SMCR_ETPS_Pos (12U) +#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ +#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ +#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ + +#define TIM_SMCR_ECE_Pos (14U) +#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ +#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ +#define TIM_SMCR_ETP_Pos (15U) +#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ +#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ + +/******************* Bit definition for TIM_DIER register ******************/ +#define TIM_DIER_UIE_Pos (0U) +#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ +#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ +#define TIM_DIER_CC1IE_Pos (1U) +#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ +#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE_Pos (2U) +#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ +#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE_Pos (3U) +#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ +#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE_Pos (4U) +#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ +#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE_Pos (5U) +#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ +#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ +#define TIM_DIER_TIE_Pos (6U) +#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ +#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ +#define TIM_DIER_BIE_Pos (7U) +#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ +#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ +#define TIM_DIER_UDE_Pos (8U) +#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ +#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ +#define TIM_DIER_CC1DE_Pos (9U) +#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ +#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE_Pos (10U) +#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ +#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE_Pos (11U) +#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ +#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE_Pos (12U) +#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ +#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE_Pos (13U) +#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ +#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ +#define TIM_DIER_TDE_Pos (14U) +#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ +#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register *******************/ +#define TIM_SR_UIF_Pos (0U) +#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ +#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ +#define TIM_SR_CC1IF_Pos (1U) +#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ +#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF_Pos (2U) +#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ +#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF_Pos (3U) +#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ +#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF_Pos (4U) +#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ +#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF_Pos (5U) +#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ +#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ +#define TIM_SR_TIF_Pos (6U) +#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ +#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ +#define TIM_SR_BIF_Pos (7U) +#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ +#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ +#define TIM_SR_CC1OF_Pos (9U) +#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ +#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF_Pos (10U) +#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ +#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF_Pos (11U) +#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ +#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF_Pos (12U) +#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ +#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register *******************/ +#define TIM_EGR_UG_Pos (0U) +#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ +#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ +#define TIM_EGR_CC1G_Pos (1U) +#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ +#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G_Pos (2U) +#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ +#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G_Pos (3U) +#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ +#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G_Pos (4U) +#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ +#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ +#define TIM_EGR_COMG_Pos (5U) +#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ +#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ +#define TIM_EGR_TG_Pos (6U) +#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ +#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ +#define TIM_EGR_BG_Pos (7U) +#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ +#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register ******************/ +#define TIM_CCMR1_CC1S_Pos (0U) +#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ +#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ +#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ + +#define TIM_CCMR1_OC1FE_Pos (2U) +#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE_Pos (3U) +#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M_Pos (4U) +#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ +#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ +#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ +#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ + +#define TIM_CCMR1_OC1CE_Pos (7U) +#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S_Pos (8U) +#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ +#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ +#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ + +#define TIM_CCMR1_OC2FE_Pos (10U) +#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE_Pos (11U) +#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M_Pos (12U) +#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ +#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ +#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ +#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ + +#define TIM_CCMR1_OC2CE_Pos (15U) +#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ + +/*---------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC_Pos (2U) +#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ +#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ +#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ + +#define TIM_CCMR1_IC1F_Pos (4U) +#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ +#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ +#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ +#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ +#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ + +#define TIM_CCMR1_IC2PSC_Pos (10U) +#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ +#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ +#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ + +#define TIM_CCMR1_IC2F_Pos (12U) +#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ +#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ +#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ +#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ +#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for TIM_CCMR2 register ******************/ +#define TIM_CCMR2_CC3S_Pos (0U) +#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ +#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ +#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ + +#define TIM_CCMR2_OC3FE_Pos (2U) +#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ +#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE_Pos (3U) +#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ +#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M_Pos (4U) +#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ +#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ +#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ +#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ + +#define TIM_CCMR2_OC3CE_Pos (7U) +#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ +#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S_Pos (8U) +#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ +#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ +#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ + +#define TIM_CCMR2_OC4FE_Pos (10U) +#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ +#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE_Pos (11U) +#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ +#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M_Pos (12U) +#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ +#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ +#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ +#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ + +#define TIM_CCMR2_OC4CE_Pos (15U) +#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ +#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ + +/*---------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC_Pos (2U) +#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ +#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ +#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ + +#define TIM_CCMR2_IC3F_Pos (4U) +#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ +#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ +#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ +#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ +#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ + +#define TIM_CCMR2_IC4PSC_Pos (10U) +#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ +#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ +#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ + +#define TIM_CCMR2_IC4F_Pos (12U) +#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ +#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ +#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ +#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ +#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ + +/******************* Bit definition for TIM_CCER register ******************/ +#define TIM_CCER_CC1E_Pos (0U) +#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ +#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P_Pos (1U) +#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ +#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE_Pos (2U) +#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ +#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP_Pos (3U) +#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ +#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E_Pos (4U) +#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ +#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P_Pos (5U) +#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ +#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE_Pos (6U) +#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ +#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP_Pos (7U) +#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ +#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E_Pos (8U) +#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ +#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P_Pos (9U) +#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ +#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE_Pos (10U) +#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ +#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP_Pos (11U) +#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ +#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E_Pos (12U) +#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ +#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P_Pos (13U) +#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ +#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register *******************/ +#define TIM_CNT_CNT_Pos (0U) +#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ + +/******************* Bit definition for TIM_PSC register *******************/ +#define TIM_PSC_PSC_Pos (0U) +#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ +#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ + +/******************* Bit definition for TIM_ARR register *******************/ +#define TIM_ARR_ARR_Pos (0U) +#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ +#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register *******************/ +#define TIM_RCR_REP_Pos (0U) +#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ +#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register ******************/ +#define TIM_CCR1_CCR1_Pos (0U) +#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register ******************/ +#define TIM_CCR2_CCR2_Pos (0U) +#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register ******************/ +#define TIM_CCR3_CCR3_Pos (0U) +#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register ******************/ +#define TIM_CCR4_CCR4_Pos (0U) +#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register ******************/ +#define TIM_BDTR_DTG_Pos (0U) +#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ +#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ +#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ +#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ +#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ +#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ +#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ +#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ +#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ + +#define TIM_BDTR_LOCK_Pos (8U) +#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ +#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ +#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ + +#define TIM_BDTR_OSSI_Pos (10U) +#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ +#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR_Pos (11U) +#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ +#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ +#define TIM_BDTR_BKE_Pos (12U) +#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ +#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ +#define TIM_BDTR_BKP_Pos (13U) +#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ +#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ +#define TIM_BDTR_AOE_Pos (14U) +#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ +#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ +#define TIM_BDTR_MOE_Pos (15U) +#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ +#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ + +/******************* Bit definition for TIM_DCR register *******************/ +#define TIM_DCR_DBA_Pos (0U) +#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ +#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ +#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ +#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ +#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ +#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ + +#define TIM_DCR_DBL_Pos (8U) +#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ +#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ +#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ +#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ +#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ +#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ + +/******************* Bit definition for TIM_DMAR register ******************/ +#define TIM_DMAR_DMAB_Pos (0U) +#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ +#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE_Pos (0U) +#define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ +#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE_Pos (1U) +#define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ +#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE_Pos (2U) +#define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ +#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF_Pos (0U) +#define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ +#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ +#define RTC_CRL_ALRF_Pos (1U) +#define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ +#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ +#define RTC_CRL_OWF_Pos (2U) +#define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ +#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ +#define RTC_CRL_RSF_Pos (3U) +#define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ +#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF_Pos (4U) +#define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ +#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ +#define RTC_CRL_RTOFF_Pos (5U) +#define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ +#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL_Pos (0U) +#define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ +#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL_Pos (0U) +#define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ +#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV_Pos (0U) +#define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ +#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV_Pos (0U) +#define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ +#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT_Pos (0U) +#define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ +#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT_Pos (0U) +#define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ +#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR_Pos (0U) +#define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ +#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR_Pos (0U) +#define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ +#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR_Pos (0U) +#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ +#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ +#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ +#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL_Pos (0U) +#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ +#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU_Pos (0U) +#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ +#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU_Pos (1U) +#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ +#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG (WWDG) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T_Pos (0U) +#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ +#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ +#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ +#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ +#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ +#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ +#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ +#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDG_CR_T0 WWDG_CR_T_0 +#define WWDG_CR_T1 WWDG_CR_T_1 +#define WWDG_CR_T2 WWDG_CR_T_2 +#define WWDG_CR_T3 WWDG_CR_T_3 +#define WWDG_CR_T4 WWDG_CR_T_4 +#define WWDG_CR_T5 WWDG_CR_T_5 +#define WWDG_CR_T6 WWDG_CR_T_6 + +#define WWDG_CR_WDGA_Pos (7U) +#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ +#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W_Pos (0U) +#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ +#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ +#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ +#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ +#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ +#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ +#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ +#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDG_CFR_W0 WWDG_CFR_W_0 +#define WWDG_CFR_W1 WWDG_CFR_W_1 +#define WWDG_CFR_W2 WWDG_CFR_W_2 +#define WWDG_CFR_W3 WWDG_CFR_W_3 +#define WWDG_CFR_W4 WWDG_CFR_W_4 +#define WWDG_CFR_W5 WWDG_CFR_W_5 +#define WWDG_CFR_W6 WWDG_CFR_W_6 + +#define WWDG_CFR_WDGTB_Pos (7U) +#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ +#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ +#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 +#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 + +#define WWDG_CFR_EWI_Pos (9U) +#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ +#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF_Pos (0U) +#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ +#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ + +/* bit positions */ +#define USB_EP_CTR_RX_Pos (15U) +#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX_Pos (14U) +#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT_Pos (12U) +#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ +#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP_Pos (11U) +#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD_Pos (9U) +#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ +#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ +#define USB_EP_KIND_Pos (8U) +#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ +#define USB_EP_CTR_TX_Pos (7U) +#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX_Pos (6U) +#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT_Pos (4U) +#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ +#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD_Pos (0U) +#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ +#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK_Pos (9U) +#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ +#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */ +#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA_Pos (0U) +#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX_Pos (4U) +#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP0R_DTOG_TX_Pos (6U) +#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX_Pos (7U) +#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND_Pos (8U) +#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE_Pos (9U) +#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP0R_SETUP_Pos (11U) +#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX_Pos (12U) +#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP0R_DTOG_RX_Pos (14U) +#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX_Pos (15U) +#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA_Pos (0U) +#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX_Pos (4U) +#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP1R_DTOG_TX_Pos (6U) +#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX_Pos (7U) +#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND_Pos (8U) +#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE_Pos (9U) +#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP1R_SETUP_Pos (11U) +#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX_Pos (12U) +#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP1R_DTOG_RX_Pos (14U) +#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX_Pos (15U) +#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA_Pos (0U) +#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX_Pos (4U) +#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP2R_DTOG_TX_Pos (6U) +#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX_Pos (7U) +#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND_Pos (8U) +#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE_Pos (9U) +#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP2R_SETUP_Pos (11U) +#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX_Pos (12U) +#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP2R_DTOG_RX_Pos (14U) +#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX_Pos (15U) +#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA_Pos (0U) +#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX_Pos (4U) +#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP3R_DTOG_TX_Pos (6U) +#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX_Pos (7U) +#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND_Pos (8U) +#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE_Pos (9U) +#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP3R_SETUP_Pos (11U) +#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX_Pos (12U) +#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP3R_DTOG_RX_Pos (14U) +#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX_Pos (15U) +#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA_Pos (0U) +#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX_Pos (4U) +#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP4R_DTOG_TX_Pos (6U) +#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX_Pos (7U) +#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND_Pos (8U) +#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE_Pos (9U) +#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP4R_SETUP_Pos (11U) +#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX_Pos (12U) +#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP4R_DTOG_RX_Pos (14U) +#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX_Pos (15U) +#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA_Pos (0U) +#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX_Pos (4U) +#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP5R_DTOG_TX_Pos (6U) +#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX_Pos (7U) +#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND_Pos (8U) +#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE_Pos (9U) +#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP5R_SETUP_Pos (11U) +#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX_Pos (12U) +#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP5R_DTOG_RX_Pos (14U) +#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX_Pos (15U) +#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA_Pos (0U) +#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX_Pos (4U) +#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP6R_DTOG_TX_Pos (6U) +#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX_Pos (7U) +#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND_Pos (8U) +#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE_Pos (9U) +#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP6R_SETUP_Pos (11U) +#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX_Pos (12U) +#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP6R_DTOG_RX_Pos (14U) +#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX_Pos (15U) +#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA_Pos (0U) +#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX_Pos (4U) +#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP7R_DTOG_TX_Pos (6U) +#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX_Pos (7U) +#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND_Pos (8U) +#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE_Pos (9U) +#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP7R_SETUP_Pos (11U) +#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX_Pos (12U) +#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP7R_DTOG_RX_Pos (14U) +#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX_Pos (15U) +#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES_Pos (0U) +#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ +#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ +#define USB_CNTR_PDWN_Pos (1U) +#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ +#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ +#define USB_CNTR_LP_MODE_Pos (2U) +#define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ +#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ +#define USB_CNTR_FSUSP_Pos (3U) +#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ +#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ +#define USB_CNTR_RESUME_Pos (4U) +#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ +#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ +#define USB_CNTR_ESOFM_Pos (8U) +#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ +#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM_Pos (9U) +#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ +#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM_Pos (10U) +#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ +#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM_Pos (11U) +#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ +#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM_Pos (12U) +#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ +#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM_Pos (13U) +#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ +#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM_Pos (14U) +#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM_Pos (15U) +#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ +#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID_Pos (0U) +#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ +#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ +#define USB_ISTR_DIR_Pos (4U) +#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ +#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ +#define USB_ISTR_ESOF_Pos (8U) +#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ +#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF_Pos (9U) +#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ +#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ +#define USB_ISTR_RESET_Pos (10U) +#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ +#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ +#define USB_ISTR_SUSP_Pos (11U) +#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ +#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ +#define USB_ISTR_WKUP_Pos (12U) +#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ +#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ +#define USB_ISTR_ERR_Pos (13U) +#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ +#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ +#define USB_ISTR_PMAOVR_Pos (14U) +#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ +#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR_Pos (15U) +#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ +#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN_Pos (0U) +#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ +#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ +#define USB_FNR_LSOF_Pos (11U) +#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ +#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ +#define USB_FNR_LCK_Pos (13U) +#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ +#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ +#define USB_FNR_RXDM_Pos (14U) +#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ +#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP_Pos (15U) +#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ +#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD_Pos (0U) +#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ +#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0_Pos (0U) +#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ +#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ +#define USB_DADDR_ADD1_Pos (1U) +#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ +#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ +#define USB_DADDR_ADD2_Pos (2U) +#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ +#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ +#define USB_DADDR_ADD3_Pos (3U) +#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ +#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ +#define USB_DADDR_ADD4_Pos (4U) +#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ +#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ +#define USB_DADDR_ADD5_Pos (5U) +#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ +#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ +#define USB_DADDR_ADD6_Pos (6U) +#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ +#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ + +#define USB_DADDR_EF_Pos (7U) +#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ +#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE_Pos (3U) +#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ +#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) +#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) +#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) +#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) +#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) +#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) +#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) +#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) +#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) +#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) +#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) +#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) +#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) +#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) +#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) +#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) +#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) +#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) +#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) +#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) +#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) +#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) +#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) +#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) +#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) +#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT0_RX_BLSIZE_Pos (15U) +#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) +#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT1_RX_BLSIZE_Pos (15U) +#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) +#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT2_RX_BLSIZE_Pos (15U) +#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) +#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT3_RX_BLSIZE_Pos (15U) +#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) +#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT4_RX_BLSIZE_Pos (15U) +#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) +#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT5_RX_BLSIZE_Pos (15U) +#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) +#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT6_RX_BLSIZE_Pos (15U) +#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) +#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT7_RX_BLSIZE_Pos (15U) +#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ_Pos (0U) +#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ +#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */ +#define CAN_MCR_SLEEP_Pos (1U) +#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ +#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP_Pos (2U) +#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ +#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM_Pos (3U) +#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ +#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART_Pos (4U) +#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ +#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM_Pos (5U) +#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ +#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM_Pos (6U) +#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ +#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM_Pos (7U) +#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ +#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET_Pos (15U) +#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ +#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */ +#define CAN_MCR_DBF_Pos (16U) +#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ +#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK_Pos (0U) +#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ +#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK_Pos (1U) +#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ +#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI_Pos (2U) +#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ +#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */ +#define CAN_MSR_WKUI_Pos (3U) +#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ +#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI_Pos (4U) +#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ +#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM_Pos (8U) +#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ +#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */ +#define CAN_MSR_RXM_Pos (9U) +#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ +#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */ +#define CAN_MSR_SAMP_Pos (10U) +#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ +#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */ +#define CAN_MSR_RX_Pos (11U) +#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ +#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0_Pos (0U) +#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ +#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0_Pos (1U) +#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ +#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0_Pos (2U) +#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ +#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0_Pos (3U) +#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ +#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0_Pos (7U) +#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ +#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1_Pos (8U) +#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ +#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1_Pos (9U) +#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ +#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1_Pos (10U) +#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ +#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1_Pos (11U) +#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ +#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1_Pos (15U) +#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ +#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2_Pos (16U) +#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ +#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2_Pos (17U) +#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ +#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2_Pos (18U) +#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ +#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2_Pos (19U) +#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ +#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2_Pos (23U) +#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ +#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE_Pos (24U) +#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ +#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */ + +#define CAN_TSR_TME_Pos (26U) +#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ +#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */ +#define CAN_TSR_TME0_Pos (26U) +#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ +#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1_Pos (27U) +#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ +#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2_Pos (28U) +#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ +#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW_Pos (29U) +#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ +#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0_Pos (29U) +#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ +#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1_Pos (30U) +#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ +#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2_Pos (31U) +#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ +#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0_Pos (0U) +#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ +#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0_Pos (3U) +#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ +#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0_Pos (4U) +#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ +#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0_Pos (5U) +#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ +#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1_Pos (0U) +#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ +#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1_Pos (3U) +#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ +#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1_Pos (4U) +#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ +#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1_Pos (5U) +#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ +#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE_Pos (0U) +#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ +#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0_Pos (1U) +#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ +#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0_Pos (2U) +#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ +#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0_Pos (3U) +#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ +#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1_Pos (4U) +#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ +#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1_Pos (5U) +#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ +#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1_Pos (6U) +#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ +#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE_Pos (8U) +#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ +#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE_Pos (9U) +#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ +#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE_Pos (10U) +#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ +#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE_Pos (11U) +#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ +#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE_Pos (15U) +#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ +#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE_Pos (16U) +#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ +#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE_Pos (17U) +#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ +#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF_Pos (0U) +#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ +#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */ +#define CAN_ESR_EPVF_Pos (1U) +#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ +#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */ +#define CAN_ESR_BOFF_Pos (2U) +#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ +#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC_Pos (4U) +#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ +#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ +#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ +#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ + +#define CAN_ESR_TEC_Pos (16U) +#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC_Pos (24U) +#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP_Pos (0U) +#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ +#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ +#define CAN_BTR_TS1_Pos (16U) +#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ +#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ +#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ +#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ +#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ +#define CAN_BTR_TS2_Pos (20U) +#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ +#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ +#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ +#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ +#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ +#define CAN_BTR_SJW_Pos (24U) +#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ +#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ +#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ +#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ +#define CAN_BTR_LBKM_Pos (30U) +#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ +#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ +#define CAN_BTR_SILM_Pos (31U) +#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ +#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ_Pos (0U) +#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ +#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR_Pos (1U) +#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ +#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE_Pos (2U) +#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ +#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */ +#define CAN_TI0R_EXID_Pos (3U) +#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */ +#define CAN_TI0R_STID_Pos (21U) +#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ +#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC_Pos (0U) +#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ +#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */ +#define CAN_TDT0R_TGT_Pos (8U) +#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ +#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME_Pos (16U) +#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ +#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0_Pos (0U) +#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ +#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1_Pos (8U) +#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ +#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2_Pos (16U) +#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ +#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3_Pos (24U) +#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ +#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4_Pos (0U) +#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ +#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5_Pos (8U) +#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ +#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6_Pos (16U) +#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ +#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7_Pos (24U) +#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ +#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ_Pos (0U) +#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ +#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR_Pos (1U) +#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ +#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE_Pos (2U) +#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ +#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */ +#define CAN_TI1R_EXID_Pos (3U) +#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */ +#define CAN_TI1R_STID_Pos (21U) +#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ +#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC_Pos (0U) +#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ +#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */ +#define CAN_TDT1R_TGT_Pos (8U) +#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ +#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME_Pos (16U) +#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ +#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0_Pos (0U) +#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ +#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1_Pos (8U) +#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ +#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2_Pos (16U) +#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ +#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3_Pos (24U) +#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ +#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4_Pos (0U) +#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ +#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5_Pos (8U) +#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ +#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6_Pos (16U) +#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ +#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7_Pos (24U) +#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ +#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ_Pos (0U) +#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ +#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR_Pos (1U) +#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ +#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE_Pos (2U) +#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ +#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */ +#define CAN_TI2R_EXID_Pos (3U) +#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */ +#define CAN_TI2R_STID_Pos (21U) +#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ +#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC_Pos (0U) +#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ +#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */ +#define CAN_TDT2R_TGT_Pos (8U) +#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ +#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME_Pos (16U) +#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ +#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0_Pos (0U) +#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ +#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1_Pos (8U) +#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ +#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2_Pos (16U) +#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ +#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3_Pos (24U) +#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ +#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4_Pos (0U) +#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ +#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5_Pos (8U) +#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ +#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6_Pos (16U) +#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ +#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7_Pos (24U) +#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ +#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR_Pos (1U) +#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ +#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE_Pos (2U) +#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ +#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */ +#define CAN_RI0R_EXID_Pos (3U) +#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */ +#define CAN_RI0R_STID_Pos (21U) +#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ +#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC_Pos (0U) +#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ +#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */ +#define CAN_RDT0R_FMI_Pos (8U) +#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ +#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */ +#define CAN_RDT0R_TIME_Pos (16U) +#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ +#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0_Pos (0U) +#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ +#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1_Pos (8U) +#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ +#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2_Pos (16U) +#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ +#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3_Pos (24U) +#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ +#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4_Pos (0U) +#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ +#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5_Pos (8U) +#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ +#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6_Pos (16U) +#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ +#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7_Pos (24U) +#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ +#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR_Pos (1U) +#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ +#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE_Pos (2U) +#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ +#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */ +#define CAN_RI1R_EXID_Pos (3U) +#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */ +#define CAN_RI1R_STID_Pos (21U) +#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ +#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC_Pos (0U) +#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ +#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */ +#define CAN_RDT1R_FMI_Pos (8U) +#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ +#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */ +#define CAN_RDT1R_TIME_Pos (16U) +#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ +#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0_Pos (0U) +#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ +#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1_Pos (8U) +#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ +#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2_Pos (16U) +#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ +#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3_Pos (24U) +#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ +#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4_Pos (0U) +#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ +#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5_Pos (8U) +#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ +#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6_Pos (16U) +#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ +#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7_Pos (24U) +#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ +#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT_Pos (0U) +#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ +#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */ +#define CAN_FMR_CAN2SB_Pos (8U) +#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ +#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM_Pos (0U) +#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ +#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */ +#define CAN_FM1R_FBM0_Pos (0U) +#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ +#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */ +#define CAN_FM1R_FBM1_Pos (1U) +#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ +#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */ +#define CAN_FM1R_FBM2_Pos (2U) +#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ +#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */ +#define CAN_FM1R_FBM3_Pos (3U) +#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ +#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */ +#define CAN_FM1R_FBM4_Pos (4U) +#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ +#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */ +#define CAN_FM1R_FBM5_Pos (5U) +#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ +#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */ +#define CAN_FM1R_FBM6_Pos (6U) +#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ +#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */ +#define CAN_FM1R_FBM7_Pos (7U) +#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ +#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */ +#define CAN_FM1R_FBM8_Pos (8U) +#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ +#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */ +#define CAN_FM1R_FBM9_Pos (9U) +#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ +#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */ +#define CAN_FM1R_FBM10_Pos (10U) +#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ +#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */ +#define CAN_FM1R_FBM11_Pos (11U) +#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ +#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */ +#define CAN_FM1R_FBM12_Pos (12U) +#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ +#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */ +#define CAN_FM1R_FBM13_Pos (13U) +#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ +#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC_Pos (0U) +#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ +#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0_Pos (0U) +#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ +#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */ +#define CAN_FS1R_FSC1_Pos (1U) +#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ +#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */ +#define CAN_FS1R_FSC2_Pos (2U) +#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ +#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */ +#define CAN_FS1R_FSC3_Pos (3U) +#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ +#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */ +#define CAN_FS1R_FSC4_Pos (4U) +#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ +#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */ +#define CAN_FS1R_FSC5_Pos (5U) +#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ +#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */ +#define CAN_FS1R_FSC6_Pos (6U) +#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ +#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */ +#define CAN_FS1R_FSC7_Pos (7U) +#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ +#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */ +#define CAN_FS1R_FSC8_Pos (8U) +#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ +#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */ +#define CAN_FS1R_FSC9_Pos (9U) +#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ +#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */ +#define CAN_FS1R_FSC10_Pos (10U) +#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ +#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */ +#define CAN_FS1R_FSC11_Pos (11U) +#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ +#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */ +#define CAN_FS1R_FSC12_Pos (12U) +#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ +#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */ +#define CAN_FS1R_FSC13_Pos (13U) +#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ +#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA_Pos (0U) +#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ +#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0_Pos (0U) +#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ +#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */ +#define CAN_FFA1R_FFA1_Pos (1U) +#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ +#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */ +#define CAN_FFA1R_FFA2_Pos (2U) +#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ +#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */ +#define CAN_FFA1R_FFA3_Pos (3U) +#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ +#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */ +#define CAN_FFA1R_FFA4_Pos (4U) +#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ +#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */ +#define CAN_FFA1R_FFA5_Pos (5U) +#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ +#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */ +#define CAN_FFA1R_FFA6_Pos (6U) +#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ +#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */ +#define CAN_FFA1R_FFA7_Pos (7U) +#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ +#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */ +#define CAN_FFA1R_FFA8_Pos (8U) +#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ +#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */ +#define CAN_FFA1R_FFA9_Pos (9U) +#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ +#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */ +#define CAN_FFA1R_FFA10_Pos (10U) +#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ +#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */ +#define CAN_FFA1R_FFA11_Pos (11U) +#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ +#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */ +#define CAN_FFA1R_FFA12_Pos (12U) +#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ +#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */ +#define CAN_FFA1R_FFA13_Pos (13U) +#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ +#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT_Pos (0U) +#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ +#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */ +#define CAN_FA1R_FACT0_Pos (0U) +#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ +#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1_Pos (1U) +#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ +#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2_Pos (2U) +#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ +#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3_Pos (3U) +#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ +#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4_Pos (4U) +#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ +#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5_Pos (5U) +#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ +#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6_Pos (6U) +#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ +#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7_Pos (7U) +#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ +#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8_Pos (8U) +#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ +#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9_Pos (9U) +#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ +#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10_Pos (10U) +#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ +#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11_Pos (11U) +#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ +#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12_Pos (12U) +#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ +#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13_Pos (13U) +#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ +#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0_Pos (0U) +#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F0R1_FB1_Pos (1U) +#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F0R1_FB2_Pos (2U) +#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F0R1_FB3_Pos (3U) +#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F0R1_FB4_Pos (4U) +#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F0R1_FB5_Pos (5U) +#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F0R1_FB6_Pos (6U) +#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F0R1_FB7_Pos (7U) +#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F0R1_FB8_Pos (8U) +#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F0R1_FB9_Pos (9U) +#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F0R1_FB10_Pos (10U) +#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F0R1_FB11_Pos (11U) +#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F0R1_FB12_Pos (12U) +#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F0R1_FB13_Pos (13U) +#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F0R1_FB14_Pos (14U) +#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F0R1_FB15_Pos (15U) +#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F0R1_FB16_Pos (16U) +#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F0R1_FB17_Pos (17U) +#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F0R1_FB18_Pos (18U) +#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F0R1_FB19_Pos (19U) +#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F0R1_FB20_Pos (20U) +#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F0R1_FB21_Pos (21U) +#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F0R1_FB22_Pos (22U) +#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F0R1_FB23_Pos (23U) +#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F0R1_FB24_Pos (24U) +#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F0R1_FB25_Pos (25U) +#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F0R1_FB26_Pos (26U) +#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F0R1_FB27_Pos (27U) +#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F0R1_FB28_Pos (28U) +#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F0R1_FB29_Pos (29U) +#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F0R1_FB30_Pos (30U) +#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F0R1_FB31_Pos (31U) +#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0_Pos (0U) +#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F1R1_FB1_Pos (1U) +#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F1R1_FB2_Pos (2U) +#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F1R1_FB3_Pos (3U) +#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F1R1_FB4_Pos (4U) +#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F1R1_FB5_Pos (5U) +#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F1R1_FB6_Pos (6U) +#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F1R1_FB7_Pos (7U) +#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F1R1_FB8_Pos (8U) +#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F1R1_FB9_Pos (9U) +#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F1R1_FB10_Pos (10U) +#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F1R1_FB11_Pos (11U) +#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F1R1_FB12_Pos (12U) +#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F1R1_FB13_Pos (13U) +#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F1R1_FB14_Pos (14U) +#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F1R1_FB15_Pos (15U) +#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F1R1_FB16_Pos (16U) +#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F1R1_FB17_Pos (17U) +#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F1R1_FB18_Pos (18U) +#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F1R1_FB19_Pos (19U) +#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F1R1_FB20_Pos (20U) +#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F1R1_FB21_Pos (21U) +#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F1R1_FB22_Pos (22U) +#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F1R1_FB23_Pos (23U) +#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F1R1_FB24_Pos (24U) +#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F1R1_FB25_Pos (25U) +#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F1R1_FB26_Pos (26U) +#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F1R1_FB27_Pos (27U) +#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F1R1_FB28_Pos (28U) +#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F1R1_FB29_Pos (29U) +#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F1R1_FB30_Pos (30U) +#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F1R1_FB31_Pos (31U) +#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0_Pos (0U) +#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F2R1_FB1_Pos (1U) +#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F2R1_FB2_Pos (2U) +#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F2R1_FB3_Pos (3U) +#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F2R1_FB4_Pos (4U) +#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F2R1_FB5_Pos (5U) +#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F2R1_FB6_Pos (6U) +#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F2R1_FB7_Pos (7U) +#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F2R1_FB8_Pos (8U) +#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F2R1_FB9_Pos (9U) +#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F2R1_FB10_Pos (10U) +#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F2R1_FB11_Pos (11U) +#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F2R1_FB12_Pos (12U) +#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F2R1_FB13_Pos (13U) +#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F2R1_FB14_Pos (14U) +#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F2R1_FB15_Pos (15U) +#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F2R1_FB16_Pos (16U) +#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F2R1_FB17_Pos (17U) +#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F2R1_FB18_Pos (18U) +#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F2R1_FB19_Pos (19U) +#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F2R1_FB20_Pos (20U) +#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F2R1_FB21_Pos (21U) +#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F2R1_FB22_Pos (22U) +#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F2R1_FB23_Pos (23U) +#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F2R1_FB24_Pos (24U) +#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F2R1_FB25_Pos (25U) +#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F2R1_FB26_Pos (26U) +#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F2R1_FB27_Pos (27U) +#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F2R1_FB28_Pos (28U) +#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F2R1_FB29_Pos (29U) +#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F2R1_FB30_Pos (30U) +#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F2R1_FB31_Pos (31U) +#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0_Pos (0U) +#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F3R1_FB1_Pos (1U) +#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F3R1_FB2_Pos (2U) +#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F3R1_FB3_Pos (3U) +#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F3R1_FB4_Pos (4U) +#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F3R1_FB5_Pos (5U) +#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F3R1_FB6_Pos (6U) +#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F3R1_FB7_Pos (7U) +#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F3R1_FB8_Pos (8U) +#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F3R1_FB9_Pos (9U) +#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F3R1_FB10_Pos (10U) +#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F3R1_FB11_Pos (11U) +#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F3R1_FB12_Pos (12U) +#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F3R1_FB13_Pos (13U) +#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F3R1_FB14_Pos (14U) +#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F3R1_FB15_Pos (15U) +#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F3R1_FB16_Pos (16U) +#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F3R1_FB17_Pos (17U) +#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F3R1_FB18_Pos (18U) +#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F3R1_FB19_Pos (19U) +#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F3R1_FB20_Pos (20U) +#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F3R1_FB21_Pos (21U) +#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F3R1_FB22_Pos (22U) +#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F3R1_FB23_Pos (23U) +#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F3R1_FB24_Pos (24U) +#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F3R1_FB25_Pos (25U) +#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F3R1_FB26_Pos (26U) +#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F3R1_FB27_Pos (27U) +#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F3R1_FB28_Pos (28U) +#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F3R1_FB29_Pos (29U) +#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F3R1_FB30_Pos (30U) +#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F3R1_FB31_Pos (31U) +#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0_Pos (0U) +#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F4R1_FB1_Pos (1U) +#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F4R1_FB2_Pos (2U) +#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F4R1_FB3_Pos (3U) +#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F4R1_FB4_Pos (4U) +#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F4R1_FB5_Pos (5U) +#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F4R1_FB6_Pos (6U) +#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F4R1_FB7_Pos (7U) +#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F4R1_FB8_Pos (8U) +#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F4R1_FB9_Pos (9U) +#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F4R1_FB10_Pos (10U) +#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F4R1_FB11_Pos (11U) +#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F4R1_FB12_Pos (12U) +#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F4R1_FB13_Pos (13U) +#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F4R1_FB14_Pos (14U) +#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F4R1_FB15_Pos (15U) +#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F4R1_FB16_Pos (16U) +#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F4R1_FB17_Pos (17U) +#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F4R1_FB18_Pos (18U) +#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F4R1_FB19_Pos (19U) +#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F4R1_FB20_Pos (20U) +#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F4R1_FB21_Pos (21U) +#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F4R1_FB22_Pos (22U) +#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F4R1_FB23_Pos (23U) +#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F4R1_FB24_Pos (24U) +#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F4R1_FB25_Pos (25U) +#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F4R1_FB26_Pos (26U) +#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F4R1_FB27_Pos (27U) +#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F4R1_FB28_Pos (28U) +#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F4R1_FB29_Pos (29U) +#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F4R1_FB30_Pos (30U) +#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F4R1_FB31_Pos (31U) +#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0_Pos (0U) +#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F5R1_FB1_Pos (1U) +#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F5R1_FB2_Pos (2U) +#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F5R1_FB3_Pos (3U) +#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F5R1_FB4_Pos (4U) +#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F5R1_FB5_Pos (5U) +#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F5R1_FB6_Pos (6U) +#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F5R1_FB7_Pos (7U) +#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F5R1_FB8_Pos (8U) +#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F5R1_FB9_Pos (9U) +#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F5R1_FB10_Pos (10U) +#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F5R1_FB11_Pos (11U) +#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F5R1_FB12_Pos (12U) +#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F5R1_FB13_Pos (13U) +#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F5R1_FB14_Pos (14U) +#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F5R1_FB15_Pos (15U) +#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F5R1_FB16_Pos (16U) +#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F5R1_FB17_Pos (17U) +#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F5R1_FB18_Pos (18U) +#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F5R1_FB19_Pos (19U) +#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F5R1_FB20_Pos (20U) +#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F5R1_FB21_Pos (21U) +#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F5R1_FB22_Pos (22U) +#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F5R1_FB23_Pos (23U) +#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F5R1_FB24_Pos (24U) +#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F5R1_FB25_Pos (25U) +#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F5R1_FB26_Pos (26U) +#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F5R1_FB27_Pos (27U) +#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F5R1_FB28_Pos (28U) +#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F5R1_FB29_Pos (29U) +#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F5R1_FB30_Pos (30U) +#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F5R1_FB31_Pos (31U) +#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0_Pos (0U) +#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F6R1_FB1_Pos (1U) +#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F6R1_FB2_Pos (2U) +#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F6R1_FB3_Pos (3U) +#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F6R1_FB4_Pos (4U) +#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F6R1_FB5_Pos (5U) +#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F6R1_FB6_Pos (6U) +#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F6R1_FB7_Pos (7U) +#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F6R1_FB8_Pos (8U) +#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F6R1_FB9_Pos (9U) +#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F6R1_FB10_Pos (10U) +#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F6R1_FB11_Pos (11U) +#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F6R1_FB12_Pos (12U) +#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F6R1_FB13_Pos (13U) +#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F6R1_FB14_Pos (14U) +#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F6R1_FB15_Pos (15U) +#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F6R1_FB16_Pos (16U) +#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F6R1_FB17_Pos (17U) +#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F6R1_FB18_Pos (18U) +#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F6R1_FB19_Pos (19U) +#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F6R1_FB20_Pos (20U) +#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F6R1_FB21_Pos (21U) +#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F6R1_FB22_Pos (22U) +#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F6R1_FB23_Pos (23U) +#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F6R1_FB24_Pos (24U) +#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F6R1_FB25_Pos (25U) +#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F6R1_FB26_Pos (26U) +#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F6R1_FB27_Pos (27U) +#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F6R1_FB28_Pos (28U) +#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F6R1_FB29_Pos (29U) +#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F6R1_FB30_Pos (30U) +#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F6R1_FB31_Pos (31U) +#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0_Pos (0U) +#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F7R1_FB1_Pos (1U) +#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F7R1_FB2_Pos (2U) +#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F7R1_FB3_Pos (3U) +#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F7R1_FB4_Pos (4U) +#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F7R1_FB5_Pos (5U) +#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F7R1_FB6_Pos (6U) +#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F7R1_FB7_Pos (7U) +#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F7R1_FB8_Pos (8U) +#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F7R1_FB9_Pos (9U) +#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F7R1_FB10_Pos (10U) +#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F7R1_FB11_Pos (11U) +#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F7R1_FB12_Pos (12U) +#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F7R1_FB13_Pos (13U) +#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F7R1_FB14_Pos (14U) +#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F7R1_FB15_Pos (15U) +#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F7R1_FB16_Pos (16U) +#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F7R1_FB17_Pos (17U) +#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F7R1_FB18_Pos (18U) +#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F7R1_FB19_Pos (19U) +#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F7R1_FB20_Pos (20U) +#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F7R1_FB21_Pos (21U) +#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F7R1_FB22_Pos (22U) +#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F7R1_FB23_Pos (23U) +#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F7R1_FB24_Pos (24U) +#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F7R1_FB25_Pos (25U) +#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F7R1_FB26_Pos (26U) +#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F7R1_FB27_Pos (27U) +#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F7R1_FB28_Pos (28U) +#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F7R1_FB29_Pos (29U) +#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F7R1_FB30_Pos (30U) +#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F7R1_FB31_Pos (31U) +#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0_Pos (0U) +#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F8R1_FB1_Pos (1U) +#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F8R1_FB2_Pos (2U) +#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F8R1_FB3_Pos (3U) +#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F8R1_FB4_Pos (4U) +#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F8R1_FB5_Pos (5U) +#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F8R1_FB6_Pos (6U) +#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F8R1_FB7_Pos (7U) +#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F8R1_FB8_Pos (8U) +#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F8R1_FB9_Pos (9U) +#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F8R1_FB10_Pos (10U) +#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F8R1_FB11_Pos (11U) +#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F8R1_FB12_Pos (12U) +#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F8R1_FB13_Pos (13U) +#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F8R1_FB14_Pos (14U) +#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F8R1_FB15_Pos (15U) +#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F8R1_FB16_Pos (16U) +#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F8R1_FB17_Pos (17U) +#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F8R1_FB18_Pos (18U) +#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F8R1_FB19_Pos (19U) +#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F8R1_FB20_Pos (20U) +#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F8R1_FB21_Pos (21U) +#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F8R1_FB22_Pos (22U) +#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F8R1_FB23_Pos (23U) +#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F8R1_FB24_Pos (24U) +#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F8R1_FB25_Pos (25U) +#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F8R1_FB26_Pos (26U) +#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F8R1_FB27_Pos (27U) +#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F8R1_FB28_Pos (28U) +#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F8R1_FB29_Pos (29U) +#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F8R1_FB30_Pos (30U) +#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F8R1_FB31_Pos (31U) +#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0_Pos (0U) +#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F9R1_FB1_Pos (1U) +#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F9R1_FB2_Pos (2U) +#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F9R1_FB3_Pos (3U) +#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F9R1_FB4_Pos (4U) +#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F9R1_FB5_Pos (5U) +#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F9R1_FB6_Pos (6U) +#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F9R1_FB7_Pos (7U) +#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F9R1_FB8_Pos (8U) +#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F9R1_FB9_Pos (9U) +#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F9R1_FB10_Pos (10U) +#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F9R1_FB11_Pos (11U) +#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F9R1_FB12_Pos (12U) +#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F9R1_FB13_Pos (13U) +#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F9R1_FB14_Pos (14U) +#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F9R1_FB15_Pos (15U) +#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F9R1_FB16_Pos (16U) +#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F9R1_FB17_Pos (17U) +#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F9R1_FB18_Pos (18U) +#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F9R1_FB19_Pos (19U) +#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F9R1_FB20_Pos (20U) +#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F9R1_FB21_Pos (21U) +#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F9R1_FB22_Pos (22U) +#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F9R1_FB23_Pos (23U) +#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F9R1_FB24_Pos (24U) +#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F9R1_FB25_Pos (25U) +#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F9R1_FB26_Pos (26U) +#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F9R1_FB27_Pos (27U) +#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F9R1_FB28_Pos (28U) +#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F9R1_FB29_Pos (29U) +#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F9R1_FB30_Pos (30U) +#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F9R1_FB31_Pos (31U) +#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0_Pos (0U) +#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F10R1_FB1_Pos (1U) +#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F10R1_FB2_Pos (2U) +#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F10R1_FB3_Pos (3U) +#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F10R1_FB4_Pos (4U) +#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F10R1_FB5_Pos (5U) +#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F10R1_FB6_Pos (6U) +#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F10R1_FB7_Pos (7U) +#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F10R1_FB8_Pos (8U) +#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F10R1_FB9_Pos (9U) +#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F10R1_FB10_Pos (10U) +#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F10R1_FB11_Pos (11U) +#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F10R1_FB12_Pos (12U) +#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F10R1_FB13_Pos (13U) +#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F10R1_FB14_Pos (14U) +#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F10R1_FB15_Pos (15U) +#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F10R1_FB16_Pos (16U) +#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F10R1_FB17_Pos (17U) +#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F10R1_FB18_Pos (18U) +#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F10R1_FB19_Pos (19U) +#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F10R1_FB20_Pos (20U) +#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F10R1_FB21_Pos (21U) +#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F10R1_FB22_Pos (22U) +#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F10R1_FB23_Pos (23U) +#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F10R1_FB24_Pos (24U) +#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F10R1_FB25_Pos (25U) +#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F10R1_FB26_Pos (26U) +#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F10R1_FB27_Pos (27U) +#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F10R1_FB28_Pos (28U) +#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F10R1_FB29_Pos (29U) +#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F10R1_FB30_Pos (30U) +#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F10R1_FB31_Pos (31U) +#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0_Pos (0U) +#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F11R1_FB1_Pos (1U) +#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F11R1_FB2_Pos (2U) +#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F11R1_FB3_Pos (3U) +#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F11R1_FB4_Pos (4U) +#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F11R1_FB5_Pos (5U) +#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F11R1_FB6_Pos (6U) +#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F11R1_FB7_Pos (7U) +#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F11R1_FB8_Pos (8U) +#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F11R1_FB9_Pos (9U) +#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F11R1_FB10_Pos (10U) +#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F11R1_FB11_Pos (11U) +#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F11R1_FB12_Pos (12U) +#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F11R1_FB13_Pos (13U) +#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F11R1_FB14_Pos (14U) +#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F11R1_FB15_Pos (15U) +#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F11R1_FB16_Pos (16U) +#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F11R1_FB17_Pos (17U) +#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F11R1_FB18_Pos (18U) +#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F11R1_FB19_Pos (19U) +#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F11R1_FB20_Pos (20U) +#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F11R1_FB21_Pos (21U) +#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F11R1_FB22_Pos (22U) +#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F11R1_FB23_Pos (23U) +#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F11R1_FB24_Pos (24U) +#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F11R1_FB25_Pos (25U) +#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F11R1_FB26_Pos (26U) +#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F11R1_FB27_Pos (27U) +#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F11R1_FB28_Pos (28U) +#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F11R1_FB29_Pos (29U) +#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F11R1_FB30_Pos (30U) +#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F11R1_FB31_Pos (31U) +#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0_Pos (0U) +#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F12R1_FB1_Pos (1U) +#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F12R1_FB2_Pos (2U) +#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F12R1_FB3_Pos (3U) +#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F12R1_FB4_Pos (4U) +#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F12R1_FB5_Pos (5U) +#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F12R1_FB6_Pos (6U) +#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F12R1_FB7_Pos (7U) +#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F12R1_FB8_Pos (8U) +#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F12R1_FB9_Pos (9U) +#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F12R1_FB10_Pos (10U) +#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F12R1_FB11_Pos (11U) +#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F12R1_FB12_Pos (12U) +#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F12R1_FB13_Pos (13U) +#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F12R1_FB14_Pos (14U) +#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F12R1_FB15_Pos (15U) +#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F12R1_FB16_Pos (16U) +#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F12R1_FB17_Pos (17U) +#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F12R1_FB18_Pos (18U) +#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F12R1_FB19_Pos (19U) +#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F12R1_FB20_Pos (20U) +#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F12R1_FB21_Pos (21U) +#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F12R1_FB22_Pos (22U) +#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F12R1_FB23_Pos (23U) +#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F12R1_FB24_Pos (24U) +#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F12R1_FB25_Pos (25U) +#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F12R1_FB26_Pos (26U) +#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F12R1_FB27_Pos (27U) +#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F12R1_FB28_Pos (28U) +#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F12R1_FB29_Pos (29U) +#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F12R1_FB30_Pos (30U) +#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F12R1_FB31_Pos (31U) +#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0_Pos (0U) +#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F13R1_FB1_Pos (1U) +#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F13R1_FB2_Pos (2U) +#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F13R1_FB3_Pos (3U) +#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F13R1_FB4_Pos (4U) +#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F13R1_FB5_Pos (5U) +#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F13R1_FB6_Pos (6U) +#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F13R1_FB7_Pos (7U) +#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F13R1_FB8_Pos (8U) +#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F13R1_FB9_Pos (9U) +#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F13R1_FB10_Pos (10U) +#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F13R1_FB11_Pos (11U) +#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F13R1_FB12_Pos (12U) +#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F13R1_FB13_Pos (13U) +#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F13R1_FB14_Pos (14U) +#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F13R1_FB15_Pos (15U) +#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F13R1_FB16_Pos (16U) +#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F13R1_FB17_Pos (17U) +#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F13R1_FB18_Pos (18U) +#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F13R1_FB19_Pos (19U) +#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F13R1_FB20_Pos (20U) +#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F13R1_FB21_Pos (21U) +#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F13R1_FB22_Pos (22U) +#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F13R1_FB23_Pos (23U) +#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F13R1_FB24_Pos (24U) +#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F13R1_FB25_Pos (25U) +#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F13R1_FB26_Pos (26U) +#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F13R1_FB27_Pos (27U) +#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F13R1_FB28_Pos (28U) +#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F13R1_FB29_Pos (29U) +#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F13R1_FB30_Pos (30U) +#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F13R1_FB31_Pos (31U) +#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0_Pos (0U) +#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F0R2_FB1_Pos (1U) +#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F0R2_FB2_Pos (2U) +#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F0R2_FB3_Pos (3U) +#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F0R2_FB4_Pos (4U) +#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F0R2_FB5_Pos (5U) +#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F0R2_FB6_Pos (6U) +#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F0R2_FB7_Pos (7U) +#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F0R2_FB8_Pos (8U) +#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F0R2_FB9_Pos (9U) +#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F0R2_FB10_Pos (10U) +#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F0R2_FB11_Pos (11U) +#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F0R2_FB12_Pos (12U) +#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F0R2_FB13_Pos (13U) +#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F0R2_FB14_Pos (14U) +#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F0R2_FB15_Pos (15U) +#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F0R2_FB16_Pos (16U) +#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F0R2_FB17_Pos (17U) +#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F0R2_FB18_Pos (18U) +#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F0R2_FB19_Pos (19U) +#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F0R2_FB20_Pos (20U) +#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F0R2_FB21_Pos (21U) +#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F0R2_FB22_Pos (22U) +#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F0R2_FB23_Pos (23U) +#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F0R2_FB24_Pos (24U) +#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F0R2_FB25_Pos (25U) +#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F0R2_FB26_Pos (26U) +#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F0R2_FB27_Pos (27U) +#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F0R2_FB28_Pos (28U) +#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F0R2_FB29_Pos (29U) +#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F0R2_FB30_Pos (30U) +#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F0R2_FB31_Pos (31U) +#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0_Pos (0U) +#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F1R2_FB1_Pos (1U) +#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F1R2_FB2_Pos (2U) +#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F1R2_FB3_Pos (3U) +#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F1R2_FB4_Pos (4U) +#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F1R2_FB5_Pos (5U) +#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F1R2_FB6_Pos (6U) +#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F1R2_FB7_Pos (7U) +#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F1R2_FB8_Pos (8U) +#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F1R2_FB9_Pos (9U) +#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F1R2_FB10_Pos (10U) +#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F1R2_FB11_Pos (11U) +#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F1R2_FB12_Pos (12U) +#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F1R2_FB13_Pos (13U) +#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F1R2_FB14_Pos (14U) +#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F1R2_FB15_Pos (15U) +#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F1R2_FB16_Pos (16U) +#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F1R2_FB17_Pos (17U) +#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F1R2_FB18_Pos (18U) +#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F1R2_FB19_Pos (19U) +#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F1R2_FB20_Pos (20U) +#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F1R2_FB21_Pos (21U) +#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F1R2_FB22_Pos (22U) +#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F1R2_FB23_Pos (23U) +#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F1R2_FB24_Pos (24U) +#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F1R2_FB25_Pos (25U) +#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F1R2_FB26_Pos (26U) +#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F1R2_FB27_Pos (27U) +#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F1R2_FB28_Pos (28U) +#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F1R2_FB29_Pos (29U) +#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F1R2_FB30_Pos (30U) +#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F1R2_FB31_Pos (31U) +#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0_Pos (0U) +#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F2R2_FB1_Pos (1U) +#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F2R2_FB2_Pos (2U) +#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F2R2_FB3_Pos (3U) +#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F2R2_FB4_Pos (4U) +#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F2R2_FB5_Pos (5U) +#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F2R2_FB6_Pos (6U) +#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F2R2_FB7_Pos (7U) +#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F2R2_FB8_Pos (8U) +#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F2R2_FB9_Pos (9U) +#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F2R2_FB10_Pos (10U) +#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F2R2_FB11_Pos (11U) +#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F2R2_FB12_Pos (12U) +#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F2R2_FB13_Pos (13U) +#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F2R2_FB14_Pos (14U) +#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F2R2_FB15_Pos (15U) +#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F2R2_FB16_Pos (16U) +#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F2R2_FB17_Pos (17U) +#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F2R2_FB18_Pos (18U) +#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F2R2_FB19_Pos (19U) +#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F2R2_FB20_Pos (20U) +#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F2R2_FB21_Pos (21U) +#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F2R2_FB22_Pos (22U) +#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F2R2_FB23_Pos (23U) +#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F2R2_FB24_Pos (24U) +#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F2R2_FB25_Pos (25U) +#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F2R2_FB26_Pos (26U) +#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F2R2_FB27_Pos (27U) +#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F2R2_FB28_Pos (28U) +#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F2R2_FB29_Pos (29U) +#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F2R2_FB30_Pos (30U) +#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F2R2_FB31_Pos (31U) +#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0_Pos (0U) +#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F3R2_FB1_Pos (1U) +#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F3R2_FB2_Pos (2U) +#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F3R2_FB3_Pos (3U) +#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F3R2_FB4_Pos (4U) +#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F3R2_FB5_Pos (5U) +#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F3R2_FB6_Pos (6U) +#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F3R2_FB7_Pos (7U) +#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F3R2_FB8_Pos (8U) +#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F3R2_FB9_Pos (9U) +#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F3R2_FB10_Pos (10U) +#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F3R2_FB11_Pos (11U) +#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F3R2_FB12_Pos (12U) +#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F3R2_FB13_Pos (13U) +#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F3R2_FB14_Pos (14U) +#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F3R2_FB15_Pos (15U) +#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F3R2_FB16_Pos (16U) +#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F3R2_FB17_Pos (17U) +#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F3R2_FB18_Pos (18U) +#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F3R2_FB19_Pos (19U) +#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F3R2_FB20_Pos (20U) +#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F3R2_FB21_Pos (21U) +#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F3R2_FB22_Pos (22U) +#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F3R2_FB23_Pos (23U) +#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F3R2_FB24_Pos (24U) +#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F3R2_FB25_Pos (25U) +#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F3R2_FB26_Pos (26U) +#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F3R2_FB27_Pos (27U) +#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F3R2_FB28_Pos (28U) +#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F3R2_FB29_Pos (29U) +#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F3R2_FB30_Pos (30U) +#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F3R2_FB31_Pos (31U) +#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0_Pos (0U) +#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F4R2_FB1_Pos (1U) +#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F4R2_FB2_Pos (2U) +#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F4R2_FB3_Pos (3U) +#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F4R2_FB4_Pos (4U) +#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F4R2_FB5_Pos (5U) +#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F4R2_FB6_Pos (6U) +#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F4R2_FB7_Pos (7U) +#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F4R2_FB8_Pos (8U) +#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F4R2_FB9_Pos (9U) +#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F4R2_FB10_Pos (10U) +#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F4R2_FB11_Pos (11U) +#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F4R2_FB12_Pos (12U) +#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F4R2_FB13_Pos (13U) +#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F4R2_FB14_Pos (14U) +#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F4R2_FB15_Pos (15U) +#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F4R2_FB16_Pos (16U) +#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F4R2_FB17_Pos (17U) +#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F4R2_FB18_Pos (18U) +#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F4R2_FB19_Pos (19U) +#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F4R2_FB20_Pos (20U) +#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F4R2_FB21_Pos (21U) +#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F4R2_FB22_Pos (22U) +#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F4R2_FB23_Pos (23U) +#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F4R2_FB24_Pos (24U) +#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F4R2_FB25_Pos (25U) +#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F4R2_FB26_Pos (26U) +#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F4R2_FB27_Pos (27U) +#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F4R2_FB28_Pos (28U) +#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F4R2_FB29_Pos (29U) +#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F4R2_FB30_Pos (30U) +#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F4R2_FB31_Pos (31U) +#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0_Pos (0U) +#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F5R2_FB1_Pos (1U) +#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F5R2_FB2_Pos (2U) +#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F5R2_FB3_Pos (3U) +#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F5R2_FB4_Pos (4U) +#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F5R2_FB5_Pos (5U) +#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F5R2_FB6_Pos (6U) +#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F5R2_FB7_Pos (7U) +#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F5R2_FB8_Pos (8U) +#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F5R2_FB9_Pos (9U) +#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F5R2_FB10_Pos (10U) +#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F5R2_FB11_Pos (11U) +#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F5R2_FB12_Pos (12U) +#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F5R2_FB13_Pos (13U) +#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F5R2_FB14_Pos (14U) +#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F5R2_FB15_Pos (15U) +#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F5R2_FB16_Pos (16U) +#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F5R2_FB17_Pos (17U) +#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F5R2_FB18_Pos (18U) +#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F5R2_FB19_Pos (19U) +#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F5R2_FB20_Pos (20U) +#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F5R2_FB21_Pos (21U) +#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F5R2_FB22_Pos (22U) +#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F5R2_FB23_Pos (23U) +#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F5R2_FB24_Pos (24U) +#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F5R2_FB25_Pos (25U) +#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F5R2_FB26_Pos (26U) +#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F5R2_FB27_Pos (27U) +#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F5R2_FB28_Pos (28U) +#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F5R2_FB29_Pos (29U) +#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F5R2_FB30_Pos (30U) +#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F5R2_FB31_Pos (31U) +#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0_Pos (0U) +#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F6R2_FB1_Pos (1U) +#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F6R2_FB2_Pos (2U) +#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F6R2_FB3_Pos (3U) +#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F6R2_FB4_Pos (4U) +#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F6R2_FB5_Pos (5U) +#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F6R2_FB6_Pos (6U) +#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F6R2_FB7_Pos (7U) +#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F6R2_FB8_Pos (8U) +#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F6R2_FB9_Pos (9U) +#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F6R2_FB10_Pos (10U) +#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F6R2_FB11_Pos (11U) +#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F6R2_FB12_Pos (12U) +#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F6R2_FB13_Pos (13U) +#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F6R2_FB14_Pos (14U) +#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F6R2_FB15_Pos (15U) +#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F6R2_FB16_Pos (16U) +#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F6R2_FB17_Pos (17U) +#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F6R2_FB18_Pos (18U) +#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F6R2_FB19_Pos (19U) +#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F6R2_FB20_Pos (20U) +#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F6R2_FB21_Pos (21U) +#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F6R2_FB22_Pos (22U) +#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F6R2_FB23_Pos (23U) +#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F6R2_FB24_Pos (24U) +#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F6R2_FB25_Pos (25U) +#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F6R2_FB26_Pos (26U) +#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F6R2_FB27_Pos (27U) +#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F6R2_FB28_Pos (28U) +#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F6R2_FB29_Pos (29U) +#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F6R2_FB30_Pos (30U) +#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F6R2_FB31_Pos (31U) +#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0_Pos (0U) +#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F7R2_FB1_Pos (1U) +#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F7R2_FB2_Pos (2U) +#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F7R2_FB3_Pos (3U) +#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F7R2_FB4_Pos (4U) +#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F7R2_FB5_Pos (5U) +#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F7R2_FB6_Pos (6U) +#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F7R2_FB7_Pos (7U) +#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F7R2_FB8_Pos (8U) +#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F7R2_FB9_Pos (9U) +#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F7R2_FB10_Pos (10U) +#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F7R2_FB11_Pos (11U) +#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F7R2_FB12_Pos (12U) +#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F7R2_FB13_Pos (13U) +#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F7R2_FB14_Pos (14U) +#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F7R2_FB15_Pos (15U) +#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F7R2_FB16_Pos (16U) +#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F7R2_FB17_Pos (17U) +#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F7R2_FB18_Pos (18U) +#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F7R2_FB19_Pos (19U) +#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F7R2_FB20_Pos (20U) +#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F7R2_FB21_Pos (21U) +#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F7R2_FB22_Pos (22U) +#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F7R2_FB23_Pos (23U) +#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F7R2_FB24_Pos (24U) +#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F7R2_FB25_Pos (25U) +#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F7R2_FB26_Pos (26U) +#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F7R2_FB27_Pos (27U) +#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F7R2_FB28_Pos (28U) +#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F7R2_FB29_Pos (29U) +#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F7R2_FB30_Pos (30U) +#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F7R2_FB31_Pos (31U) +#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0_Pos (0U) +#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F8R2_FB1_Pos (1U) +#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F8R2_FB2_Pos (2U) +#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F8R2_FB3_Pos (3U) +#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F8R2_FB4_Pos (4U) +#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F8R2_FB5_Pos (5U) +#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F8R2_FB6_Pos (6U) +#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F8R2_FB7_Pos (7U) +#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F8R2_FB8_Pos (8U) +#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F8R2_FB9_Pos (9U) +#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F8R2_FB10_Pos (10U) +#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F8R2_FB11_Pos (11U) +#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F8R2_FB12_Pos (12U) +#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F8R2_FB13_Pos (13U) +#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F8R2_FB14_Pos (14U) +#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F8R2_FB15_Pos (15U) +#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F8R2_FB16_Pos (16U) +#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F8R2_FB17_Pos (17U) +#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F8R2_FB18_Pos (18U) +#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F8R2_FB19_Pos (19U) +#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F8R2_FB20_Pos (20U) +#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F8R2_FB21_Pos (21U) +#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F8R2_FB22_Pos (22U) +#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F8R2_FB23_Pos (23U) +#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F8R2_FB24_Pos (24U) +#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F8R2_FB25_Pos (25U) +#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F8R2_FB26_Pos (26U) +#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F8R2_FB27_Pos (27U) +#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F8R2_FB28_Pos (28U) +#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F8R2_FB29_Pos (29U) +#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F8R2_FB30_Pos (30U) +#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F8R2_FB31_Pos (31U) +#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0_Pos (0U) +#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F9R2_FB1_Pos (1U) +#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F9R2_FB2_Pos (2U) +#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F9R2_FB3_Pos (3U) +#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F9R2_FB4_Pos (4U) +#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F9R2_FB5_Pos (5U) +#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F9R2_FB6_Pos (6U) +#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F9R2_FB7_Pos (7U) +#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F9R2_FB8_Pos (8U) +#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F9R2_FB9_Pos (9U) +#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F9R2_FB10_Pos (10U) +#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F9R2_FB11_Pos (11U) +#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F9R2_FB12_Pos (12U) +#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F9R2_FB13_Pos (13U) +#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F9R2_FB14_Pos (14U) +#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F9R2_FB15_Pos (15U) +#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F9R2_FB16_Pos (16U) +#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F9R2_FB17_Pos (17U) +#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F9R2_FB18_Pos (18U) +#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F9R2_FB19_Pos (19U) +#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F9R2_FB20_Pos (20U) +#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F9R2_FB21_Pos (21U) +#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F9R2_FB22_Pos (22U) +#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F9R2_FB23_Pos (23U) +#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F9R2_FB24_Pos (24U) +#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F9R2_FB25_Pos (25U) +#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F9R2_FB26_Pos (26U) +#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F9R2_FB27_Pos (27U) +#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F9R2_FB28_Pos (28U) +#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F9R2_FB29_Pos (29U) +#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F9R2_FB30_Pos (30U) +#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F9R2_FB31_Pos (31U) +#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0_Pos (0U) +#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F10R2_FB1_Pos (1U) +#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F10R2_FB2_Pos (2U) +#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F10R2_FB3_Pos (3U) +#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F10R2_FB4_Pos (4U) +#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F10R2_FB5_Pos (5U) +#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F10R2_FB6_Pos (6U) +#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F10R2_FB7_Pos (7U) +#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F10R2_FB8_Pos (8U) +#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F10R2_FB9_Pos (9U) +#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F10R2_FB10_Pos (10U) +#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F10R2_FB11_Pos (11U) +#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F10R2_FB12_Pos (12U) +#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F10R2_FB13_Pos (13U) +#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F10R2_FB14_Pos (14U) +#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F10R2_FB15_Pos (15U) +#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F10R2_FB16_Pos (16U) +#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F10R2_FB17_Pos (17U) +#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F10R2_FB18_Pos (18U) +#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F10R2_FB19_Pos (19U) +#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F10R2_FB20_Pos (20U) +#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F10R2_FB21_Pos (21U) +#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F10R2_FB22_Pos (22U) +#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F10R2_FB23_Pos (23U) +#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F10R2_FB24_Pos (24U) +#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F10R2_FB25_Pos (25U) +#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F10R2_FB26_Pos (26U) +#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F10R2_FB27_Pos (27U) +#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F10R2_FB28_Pos (28U) +#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F10R2_FB29_Pos (29U) +#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F10R2_FB30_Pos (30U) +#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F10R2_FB31_Pos (31U) +#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0_Pos (0U) +#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F11R2_FB1_Pos (1U) +#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F11R2_FB2_Pos (2U) +#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F11R2_FB3_Pos (3U) +#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F11R2_FB4_Pos (4U) +#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F11R2_FB5_Pos (5U) +#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F11R2_FB6_Pos (6U) +#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F11R2_FB7_Pos (7U) +#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F11R2_FB8_Pos (8U) +#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F11R2_FB9_Pos (9U) +#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F11R2_FB10_Pos (10U) +#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F11R2_FB11_Pos (11U) +#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F11R2_FB12_Pos (12U) +#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F11R2_FB13_Pos (13U) +#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F11R2_FB14_Pos (14U) +#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F11R2_FB15_Pos (15U) +#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F11R2_FB16_Pos (16U) +#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F11R2_FB17_Pos (17U) +#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F11R2_FB18_Pos (18U) +#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F11R2_FB19_Pos (19U) +#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F11R2_FB20_Pos (20U) +#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F11R2_FB21_Pos (21U) +#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F11R2_FB22_Pos (22U) +#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F11R2_FB23_Pos (23U) +#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F11R2_FB24_Pos (24U) +#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F11R2_FB25_Pos (25U) +#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F11R2_FB26_Pos (26U) +#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F11R2_FB27_Pos (27U) +#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F11R2_FB28_Pos (28U) +#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F11R2_FB29_Pos (29U) +#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F11R2_FB30_Pos (30U) +#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F11R2_FB31_Pos (31U) +#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0_Pos (0U) +#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F12R2_FB1_Pos (1U) +#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F12R2_FB2_Pos (2U) +#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F12R2_FB3_Pos (3U) +#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F12R2_FB4_Pos (4U) +#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F12R2_FB5_Pos (5U) +#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F12R2_FB6_Pos (6U) +#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F12R2_FB7_Pos (7U) +#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F12R2_FB8_Pos (8U) +#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F12R2_FB9_Pos (9U) +#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F12R2_FB10_Pos (10U) +#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F12R2_FB11_Pos (11U) +#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F12R2_FB12_Pos (12U) +#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F12R2_FB13_Pos (13U) +#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F12R2_FB14_Pos (14U) +#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F12R2_FB15_Pos (15U) +#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F12R2_FB16_Pos (16U) +#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F12R2_FB17_Pos (17U) +#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F12R2_FB18_Pos (18U) +#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F12R2_FB19_Pos (19U) +#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F12R2_FB20_Pos (20U) +#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F12R2_FB21_Pos (21U) +#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F12R2_FB22_Pos (22U) +#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F12R2_FB23_Pos (23U) +#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F12R2_FB24_Pos (24U) +#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F12R2_FB25_Pos (25U) +#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F12R2_FB26_Pos (26U) +#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F12R2_FB27_Pos (27U) +#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F12R2_FB28_Pos (28U) +#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F12R2_FB29_Pos (29U) +#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F12R2_FB30_Pos (30U) +#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F12R2_FB31_Pos (31U) +#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0_Pos (0U) +#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ +#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */ +#define CAN_F13R2_FB1_Pos (1U) +#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ +#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */ +#define CAN_F13R2_FB2_Pos (2U) +#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ +#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */ +#define CAN_F13R2_FB3_Pos (3U) +#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ +#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */ +#define CAN_F13R2_FB4_Pos (4U) +#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ +#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */ +#define CAN_F13R2_FB5_Pos (5U) +#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ +#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */ +#define CAN_F13R2_FB6_Pos (6U) +#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ +#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */ +#define CAN_F13R2_FB7_Pos (7U) +#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ +#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */ +#define CAN_F13R2_FB8_Pos (8U) +#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ +#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */ +#define CAN_F13R2_FB9_Pos (9U) +#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ +#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */ +#define CAN_F13R2_FB10_Pos (10U) +#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ +#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */ +#define CAN_F13R2_FB11_Pos (11U) +#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ +#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */ +#define CAN_F13R2_FB12_Pos (12U) +#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ +#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */ +#define CAN_F13R2_FB13_Pos (13U) +#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ +#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */ +#define CAN_F13R2_FB14_Pos (14U) +#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ +#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */ +#define CAN_F13R2_FB15_Pos (15U) +#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ +#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */ +#define CAN_F13R2_FB16_Pos (16U) +#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ +#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */ +#define CAN_F13R2_FB17_Pos (17U) +#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ +#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */ +#define CAN_F13R2_FB18_Pos (18U) +#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ +#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */ +#define CAN_F13R2_FB19_Pos (19U) +#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ +#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */ +#define CAN_F13R2_FB20_Pos (20U) +#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ +#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */ +#define CAN_F13R2_FB21_Pos (21U) +#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ +#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */ +#define CAN_F13R2_FB22_Pos (22U) +#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ +#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */ +#define CAN_F13R2_FB23_Pos (23U) +#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ +#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */ +#define CAN_F13R2_FB24_Pos (24U) +#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ +#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */ +#define CAN_F13R2_FB25_Pos (25U) +#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ +#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */ +#define CAN_F13R2_FB26_Pos (26U) +#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ +#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */ +#define CAN_F13R2_FB27_Pos (27U) +#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ +#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */ +#define CAN_F13R2_FB28_Pos (28U) +#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ +#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */ +#define CAN_F13R2_FB29_Pos (29U) +#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ +#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */ +#define CAN_F13R2_FB30_Pos (30U) +#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ +#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */ +#define CAN_F13R2_FB31_Pos (31U) +#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ +#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ +#define SPI_CR1_CPOL_Pos (1U) +#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ +#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ +#define SPI_CR1_MSTR_Pos (2U) +#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ +#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ + +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ +#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ +#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ + +#define SPI_CR1_SPE_Pos (6U) +#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST_Pos (7U) +#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ +#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ +#define SPI_CR1_SSI_Pos (8U) +#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ +#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ +#define SPI_CR1_SSM_Pos (9U) +#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ +#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ +#define SPI_CR1_RXONLY_Pos (10U) +#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ +#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ +#define SPI_CR1_DFF_Pos (11U) +#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ +#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT_Pos (12U) +#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ +#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN_Pos (13U) +#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ +#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE_Pos (14U) +#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ +#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE_Pos (15U) +#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ +#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN_Pos (0U) +#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ +#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN_Pos (1U) +#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ +#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE_Pos (2U) +#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ +#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ +#define SPI_CR2_ERRIE_Pos (5U) +#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE_Pos (6U) +#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ +#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE_Pos (7U) +#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ +#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE_Pos (0U) +#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ +#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE_Pos (1U) +#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ +#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE_Pos (2U) +#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ +#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ +#define SPI_SR_UDR_Pos (3U) +#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ +#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ +#define SPI_SR_CRCERR_Pos (4U) +#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ +#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ +#define SPI_SR_MODF_Pos (5U) +#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ +#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ +#define SPI_SR_OVR_Pos (6U) +#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ +#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ +#define SPI_SR_BSY_Pos (7U) +#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ +#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR_Pos (0U) +#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ +#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY_Pos (0U) +#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC_Pos (0U) +#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC_Pos (0U) +#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ + +#define SPI_I2SCFGR_I2SMOD_Pos (11U) +#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ +#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS_Pos (1U) +#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ +#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE_Pos (3U) +#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ +#define I2C_CR1_ENARP_Pos (4U) +#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ +#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ +#define I2C_CR1_ENPEC_Pos (5U) +#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ +#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ +#define I2C_CR1_ENGC_Pos (6U) +#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ +#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH_Pos (7U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START_Pos (8U) +#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ +#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ +#define I2C_CR1_STOP_Pos (9U) +#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ +#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ +#define I2C_CR1_ACK_Pos (10U) +#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ +#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ +#define I2C_CR1_POS_Pos (11U) +#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ +#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC_Pos (12U) +#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ +#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ +#define I2C_CR1_ALERT_Pos (13U) +#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ +#define I2C_CR1_SWRST_Pos (15U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ_Pos (0U) +#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ +#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ +#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ +#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ +#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ +#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ +#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ + +#define I2C_CR2_ITERREN_Pos (8U) +#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ +#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN_Pos (9U) +#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ +#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN_Pos (10U) +#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN_Pos (11U) +#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ +#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ +#define I2C_CR2_LAST_Pos (12U) +#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ +#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OAR1_ADD0_Pos (0U) +#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ +#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ +#define I2C_OAR1_ADD1_Pos (1U) +#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ +#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ +#define I2C_OAR1_ADD2_Pos (2U) +#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ +#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ +#define I2C_OAR1_ADD3_Pos (3U) +#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ +#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ +#define I2C_OAR1_ADD4_Pos (4U) +#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ +#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ +#define I2C_OAR1_ADD5_Pos (5U) +#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ +#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ +#define I2C_OAR1_ADD6_Pos (6U) +#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ +#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ +#define I2C_OAR1_ADD7_Pos (7U) +#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ +#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ +#define I2C_OAR1_ADD8_Pos (8U) +#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ +#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ +#define I2C_OAR1_ADD9_Pos (9U) +#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ +#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE_Pos (15U) +#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL_Pos (0U) +#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ +#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2_Pos (1U) +#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR_Pos (0U) +#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ +#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB_Pos (0U) +#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ +#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR_Pos (1U) +#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ +#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF_Pos (2U) +#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ +#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10_Pos (3U) +#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ +#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF_Pos (4U) +#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ +#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE_Pos (6U) +#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ +#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE_Pos (7U) +#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ +#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR_Pos (8U) +#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ +#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ +#define I2C_SR1_ARLO_Pos (9U) +#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF_Pos (10U) +#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ +#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ +#define I2C_SR1_OVR_Pos (11U) +#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ +#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR_Pos (12U) +#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ +#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT_Pos (14U) +#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ +#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT_Pos (15U) +#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ +#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL_Pos (0U) +#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ +#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ +#define I2C_SR2_BUSY_Pos (1U) +#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ +#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ +#define I2C_SR2_TRA_Pos (2U) +#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ +#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL_Pos (4U) +#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ +#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT_Pos (5U) +#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ +#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST_Pos (6U) +#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ +#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF_Pos (7U) +#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ +#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC_Pos (8U) +#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ +#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR_Pos (0U) +#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ +#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY_Pos (14U) +#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ +#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS_Pos (15U) +#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ +#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE_Pos (0U) +#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ +#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE_Pos (0U) +#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ +#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ +#define USART_SR_FE_Pos (1U) +#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ +#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ +#define USART_SR_NE_Pos (2U) +#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ +#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ +#define USART_SR_ORE_Pos (3U) +#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ +#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ +#define USART_SR_IDLE_Pos (4U) +#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ +#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ +#define USART_SR_RXNE_Pos (5U) +#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ +#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ +#define USART_SR_TC_Pos (6U) +#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ +#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ +#define USART_SR_TXE_Pos (7U) +#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ +#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ +#define USART_SR_LBD_Pos (8U) +#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ +#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ +#define USART_SR_CTS_Pos (9U) +#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ +#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR_Pos (0U) +#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ +#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction_Pos (0U) +#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ +#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa_Pos (4U) +#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ +#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK_Pos (0U) +#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ +#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ +#define USART_CR1_RWU_Pos (1U) +#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ +#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ +#define USART_CR1_RE_Pos (2U) +#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ +#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ +#define USART_CR1_TE_Pos (3U) +#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ +#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE_Pos (4U) +#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ +#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE_Pos (5U) +#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ +#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE_Pos (6U) +#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE_Pos (7U) +#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE_Pos (8U) +#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ +#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ +#define USART_CR1_PS_Pos (9U) +#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ +#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ +#define USART_CR1_PCE_Pos (10U) +#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ +#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ +#define USART_CR1_WAKE_Pos (11U) +#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ +#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ +#define USART_CR1_M_Pos (12U) +#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ +#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ +#define USART_CR1_UE_Pos (13U) +#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ +#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD_Pos (0U) +#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ +#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ +#define USART_CR2_LBDL_Pos (5U) +#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ +#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE_Pos (6U) +#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ +#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL_Pos (8U) +#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ +#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA_Pos (9U) +#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ +#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ +#define USART_CR2_CPOL_Pos (10U) +#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ +#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ +#define USART_CR2_CLKEN_Pos (11U) +#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ + +#define USART_CR2_STOP_Pos (12U) +#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ +#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ +#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ + +#define USART_CR2_LINEN_Pos (14U) +#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE_Pos (0U) +#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ +#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ +#define USART_CR3_IREN_Pos (1U) +#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ +#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ +#define USART_CR3_IRLP_Pos (2U) +#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ +#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL_Pos (3U) +#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ +#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ +#define USART_CR3_NACK_Pos (4U) +#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ +#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN_Pos (5U) +#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ +#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ +#define USART_CR3_DMAR_Pos (6U) +#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ +#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT_Pos (7U) +#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ +#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE_Pos (8U) +#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ +#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ +#define USART_CR3_CTSE_Pos (9U) +#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ +#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ +#define USART_CR3_CTSIE_Pos (10U) +#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ +#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC_Pos (0U) +#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ +#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ +#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ +#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ +#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ +#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ +#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ +#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ +#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ + +#define USART_GTPR_GT_Pos (8U) +#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ +#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ +#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ +#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ +#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ +#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ +#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ +#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ +#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ +#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ +#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ +#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ +#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ +#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ +#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ +#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ +#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY_Pos (2U) +#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN_Pos (5U) +#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ +#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE_Pos (6U) +#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ +#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ +#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ + +#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) +#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ +#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) +#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ +#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) +#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) +#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) +#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) +#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ +#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) +#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ +#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ + +#define FLASH_ACR_HLFCYA_Pos (3U) +#define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE_Pos (4U) +#define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS_Pos (5U) +#define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR_Pos (0U) +#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ + +#define RDP_KEY_Pos (0U) +#define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ +#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR_Pos (0U) +#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ + +#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ +#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ + +/****************** Bit definition for FLASH_SR register ********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ +#define FLASH_SR_PGERR_Pos (2U) +#define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ +#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ +#define FLASH_SR_WRPRTERR_Pos (4U) +#define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ +#define FLASH_SR_EOP_Pos (5U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ +#define FLASH_CR_OPTPG_Pos (4U) +#define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ +#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ +#define FLASH_CR_OPTER_Pos (5U) +#define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ +#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ +#define FLASH_CR_STRT_Pos (6U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ +#define FLASH_CR_LOCK_Pos (7U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ +#define FLASH_CR_OPTWRE_Pos (9U) +#define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ +#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE_Pos (10U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE_Pos (12U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR_Pos (0U) +#define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR_Pos (0U) +#define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ +#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT_Pos (1U) +#define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ +#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ + +#define FLASH_OBR_IWDG_SW_Pos (2U) +#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ +#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ +#define FLASH_OBR_nRST_STOP_Pos (3U) +#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ +#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY_Pos (4U) +#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ +#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OBR_USER_Pos (2U) +#define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ +#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ +#define FLASH_OBR_DATA0_Pos (10U) +#define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ +#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ +#define FLASH_OBR_DATA1_Pos (18U) +#define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ +#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP_Pos (0U) +#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP_Pos (0U) +#define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ +#define FLASH_RDP_nRDP_Pos (8U) +#define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ +#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER_Pos (16U) +#define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ +#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ +#define FLASH_USER_nUSER_Pos (24U) +#define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ +#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0_Pos (0U) +#define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ +#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0_Pos (8U) +#define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1_Pos (16U) +#define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1_Pos (24U) +#define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ +#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2_Pos (0U) +#define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2_Pos (8U) +#define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3_Pos (16U) +#define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3_Pos (24U) +#define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ +#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ + + + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +/****************************** ADC Instances *********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ + ((INSTANCE) == ADC2)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) + +/****************************** CAN Instances *********************************/ +#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) + +/****************************** CRC Instances *********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) + +/****************************** DAC Instances *********************************/ + +/****************************** DMA Instances *********************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ + ((INSTANCE) == DMA1_Channel2) || \ + ((INSTANCE) == DMA1_Channel3) || \ + ((INSTANCE) == DMA1_Channel4) || \ + ((INSTANCE) == DMA1_Channel5) || \ + ((INSTANCE) == DMA1_Channel6) || \ + ((INSTANCE) == DMA1_Channel7)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ + ((INSTANCE) == GPIOB) || \ + ((INSTANCE) == GPIOC) || \ + ((INSTANCE) == GPIOD) || \ + ((INSTANCE) == GPIOE)) + +/**************************** GPIO Alternate Function Instances ***************/ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2)) + +/******************************* SMBUS Instances ******************************/ +#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2)) + +/****************************** START TIM Instances ***************************/ +/****************************** TIM Instances *********************************/ +#define IS_TIM_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) + +#define IS_TIM_CC1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CC2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CC3_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CC4_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_XOR_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_MASTER_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_BREAK_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)))) + +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3))) + +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_DMA_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ + (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ + ((INSTANCE) == TIM1) + +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4)) + +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U + +/****************************** END TIM Instances *****************************/ + + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/********************* UART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/***************** UART Instances : Multi-Processor mode **********************/ +#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/***************** UART Instances : DMA mode available **********************/ +#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ + ((INSTANCE) == USART2) || \ + ((INSTANCE) == USART3)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) + +/**************************** WWDG Instances *****************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) + +/****************************** USB Instances ********************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) + + + +#define RCC_HSE_MIN 4000000U +#define RCC_HSE_MAX 16000000U + +#define RCC_MAX_FREQUENCY 72000000U + +/** + * @} + */ +/******************************************************************************/ +/* For a painless codes migration between the STM32F1xx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32F1 Family */ +/******************************************************************************/ + +/* Aliases for __IRQn */ +#define ADC1_IRQn ADC1_2_IRQn +#define TIM9_IRQn TIM1_BRK_IRQn +#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn +#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn +#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn +#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM11_IRQn TIM1_TRG_COM_IRQn +#define TIM10_IRQn TIM1_UP_IRQn +#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn +#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn +#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn +#define CEC_IRQn USBWakeUp_IRQn +#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn +#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn +#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn +#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn + + +/* Aliases for __IRQHandler */ +#define ADC1_IRQHandler ADC1_2_IRQHandler +#define TIM9_IRQHandler TIM1_BRK_IRQHandler +#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler +#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler +#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler +#define TIM10_IRQHandler TIM1_UP_IRQHandler +#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler +#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler +#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler +#define CEC_IRQHandler USBWakeUp_IRQHandler +#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler +#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler +#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler +#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler + + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus + } +#endif /* __cplusplus */ + +#endif /* __STM32F103xB_H */ + + + diff --git a/include/stm32f1xx.h b/include/stm32f1xx.h new file mode 100644 index 0000000..bc1c89b --- /dev/null +++ b/include/stm32f1xx.h @@ -0,0 +1,273 @@ +/** + ****************************************************************************** + * @file stm32f1xx.h + * @author MCD Application Team + * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32F1xx device used in the target application + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f1xx + * @{ + */ + +#ifndef __STM32F1XX_H +#define __STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32F1) +#define STM32F1 +#endif /* STM32F1 */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ + !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ + !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) + /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ + /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ + /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ + /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ + /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ + /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ + /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ + /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ + /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ + /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ + /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ + /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ + /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ + /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ +#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ + |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32F1_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32F100xB) + #include "stm32f100xb.h" +#elif defined(STM32F100xE) + #include "stm32f100xe.h" +#elif defined(STM32F101x6) + #include "stm32f101x6.h" +#elif defined(STM32F101xB) + #include "stm32f101xb.h" +#elif defined(STM32F101xE) + #include "stm32f101xe.h" +#elif defined(STM32F101xG) + #include "stm32f101xg.h" +#elif defined(STM32F102x6) + #include "stm32f102x6.h" +#elif defined(STM32F102xB) + #include "stm32f102xb.h" +#elif defined(STM32F103x6) + #include "stm32f103x6.h" +#elif defined(STM32F103xB) + #include "stm32f103xb.h" +#elif defined(STM32F103xE) + #include "stm32f103xe.h" +#elif defined(STM32F103xG) + #include "stm32f103xg.h" +#elif defined(STM32F105xC) + #include "stm32f105xc.h" +#elif defined(STM32F107xC) + #include "stm32f107xc.h" +#else + #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32f1xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F1xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + diff --git a/include/system_stm32f1xx.h b/include/system_stm32f1xx.h new file mode 100644 index 0000000..196a6eb --- /dev/null +++ b/include/system_stm32f1xx.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F1XX_H +#define __SYSTEM_STM32F1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 3) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) by calling HAL API function HAL_RCC_ClockConfig() + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F0XX_H */ + +/** + * @} + */ + +/** + * @} + */ + |