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<title>CMSIS-Core (Cortex-A): Auxiliary Control Register (ACTLR)</title>
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<div class="title">Auxiliary Control Register (ACTLR)<div class="ingroups"><a class="el" href="group__CMSIS__core__register.html">Core Register Access</a></div></div> </div>
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<p>The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
<a href="#details">More...</a></p>
<table class="memberdecls">
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Content</h2></td></tr>
<tr class="memitem:group__CMSIS__ACTLR__BITS"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html">ACTLR Bits</a></td></tr>
<tr class="memdesc:group__CMSIS__ACTLR__BITS"><td class="mdescLeft"> </td><td class="mdescRight">Bit position and mask macros. <br/></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html">ACTLR_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for ACTLR layout. <a href="unionACTLR__Type.html#details">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:gabe7491eac1652f740050bd905baea187"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187">__set_ACTRL</a> (uint32_t actrl)</td></tr>
<tr class="memdesc:gabe7491eac1652f740050bd905baea187"><td class="mdescLeft"> </td><td class="mdescRight">Set ACTRL. <a href="#gabe7491eac1652f740050bd905baea187">More...</a><br/></td></tr>
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<tr class="memdesc:gae75d412bfd6fe873ade00b021aefcab3"><td class="mdescLeft"> </td><td class="mdescRight">Get ACTLR. <a href="#gae75d412bfd6fe873ade00b021aefcab3">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The ACTLR characteristics are differs between various Armv7-A implementations.</p>
<p><b>Cortex-A5</b></p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:29] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[28] </td><td align="left">DBDI </td><td align="left">Disable Branch Dual Issue </td></tr>
<tr>
<td align="left">[27:19] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[18] </td><td align="left">BTDIS </td><td align="left">Disable indirect Branch Target Address Cache (BTAC). </td></tr>
<tr>
<td align="left">[17] </td><td align="left">RSDIS </td><td align="left">Disable return stack operation. </td></tr>
<tr>
<td align="left">[16:15] </td><td align="left">BP </td><td align="left">Branch prediction policy. </td></tr>
<tr>
<td align="left">[14:13] </td><td align="left">L1PCTL </td><td align="left">L1 Data prefetch control. </td></tr>
<tr>
<td align="left">[12] </td><td align="left">RADIS </td><td align="left">Disable Data Cache read-allocate mode. </td></tr>
<tr>
<td align="left">[11] </td><td align="left">DWBST </td><td align="left">Disable AXI data write bursts to Normal memory. </td></tr>
<tr>
<td align="left">[10] </td><td align="left">DODMBS </td><td align="left">Disable optimized data memory barrier behavior. </td></tr>
<tr>
<td align="left">[9:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[7] </td><td align="left">EXCL </td><td align="left">Exclusive L1/L2 cache control. </td></tr>
<tr>
<td align="left">[6] </td><td align="left">SMP </td><td align="left">Enables coherent requests to the processor. </td></tr>
<tr>
<td align="left">[5:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">FW </td><td align="left">Cache and TLB maintenance broadcast. </td></tr>
</table>
<p><b>Cortex-A7</b></p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:29] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[28] </td><td align="left">DDI </td><td align="left">Disable Dual Issue </td></tr>
<tr>
<td align="left">[27:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[15] </td><td align="left">DDVM </td><td align="left">Disable Distributed Virtual Memory transactions. </td></tr>
<tr>
<td align="left">[14:13] </td><td align="left">L1PCTL </td><td align="left">L1 Data prefetch control. </td></tr>
<tr>
<td align="left">[12] </td><td align="left">L1RADIS </td><td align="left">L1 Data Cache read-allocate mode disable. </td></tr>
<tr>
<td align="left">[11] </td><td align="left">L2RADIS </td><td align="left">L2 Data Cache read-allocate mode disable. </td></tr>
<tr>
<td align="left">[10] </td><td align="left">DODMBS </td><td align="left">Disable optimized data memory barrier behavior. </td></tr>
<tr>
<td align="left">[9:7] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[6] </td><td align="left">SMP </td><td align="left">Enables coherent requests to the processor. </td></tr>
<tr>
<td align="left">[5:0] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
</table>
<p><b>Cortex-A9</b></p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[9] </td><td align="left">PARITY </td><td align="left">Support for parity checking, if implemented. </td></tr>
<tr>
<td align="left">[8] </td><td align="left">AOW </td><td align="left">Enable allocation in one cache way only. </td></tr>
<tr>
<td align="left">[7] </td><td align="left">EXCL </td><td align="left">Exclusive L1/L2 cache control. </td></tr>
<tr>
<td align="left">[6] </td><td align="left">SMP </td><td align="left">Enables coherent requests to the processor. </td></tr>
<tr>
<td align="left">[5:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[3] </td><td align="left">WFLZM </td><td align="left">Enable write full line of zeros modea. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">L1PE </td><td align="left">Dside prefetch. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">FW </td><td align="left">Cache and TLB maintenance broadcast. </td></tr>
</table>
<p>Consider using <a class="el" href="group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3">__get_ACTLR</a> and <a class="el" href="group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187">__set_ACTRL</a> to access ACTRL register. </p>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="gae75d412bfd6fe873ade00b021aefcab3"></a>
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<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t __get_ACTLR </td>
<td>(</td>
<td class="paramtype">void </td>
<td class="paramname"></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="section return"><dt>Returns</dt><dd>Auxiliary Control register value</dd></dl>
<p>This function returns the value of the <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a>. </p>
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<td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void __set_ACTRL </td>
<td>(</td>
<td class="paramtype">uint32_t </td>
<td class="paramname"><em>actrl</em></td><td>)</td>
<td></td>
</tr>
</table>
</div><div class="memdoc">
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">actrl</td><td>Auxiliary Control Register value to set</td></tr>
</table>
</dd>
</dl>
<p>This function assigns the given value to the <a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a>. </p>
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