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<div id="projectname">CMSIS-CORE
 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Describes naming conventions, requirements, and optional features for accessing peripherals</td></tr>
<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Describes system_<em>device</em>.c file that contains functions for system and clock setup</td></tr>
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___n_v_i_c__gr.html" target="_self">Interrupts and Exceptions (NVIC)</a></td><td class="desc">Explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC)</td></tr>
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___core___register__gr.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-M core registers</td></tr>
<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic___c_p_u__gr.html" target="_self">Intrinsic Functions for CPU Instructions</a></td><td class="desc">Functions that generate specific Cortex-M CPU Instructions</td></tr>
<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic___s_i_m_d__gr.html" target="_self">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a></td><td class="desc">Access to dedicated SIMD instructions</td></tr>
<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___sys_tick__gr.html" target="_self">Systick Timer (SYSTICK)</a></td><td class="desc">Initialize and start the SysTick timer</td></tr>
<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___i_t_m___debug__gr.html" target="_self">Debug Access</a></td><td class="desc">Debug Access to the Instrumented Trace Macrocell (ITM)</td></tr>
<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__fpu__functions__m7.html" target="_self">FPU Functions (only Cortex-M7)</a></td><td class="desc">Functions that relate to the Floating-Point Arithmetic Unit</td></tr>
<tr id="row_9_"><td class="entry"><img id="arr_9_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('9_')"/><a class="el" href="group__cache__functions__m7.html" target="_self">Cache Functions (only Cortex-M7)</a></td><td class="desc">Functions for Instruction and Data Cache</td></tr>
<tr id="row_9_0_" class="even"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___icache__functions__m7.html" target="_self">I-Cache Functions</a></td><td class="desc">Functions for the instruction cache</td></tr>
<tr id="row_9_1_"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group___dcache__functions__m7.html" target="_self">D-Cache Functions</a></td><td class="desc">Functions for the data cache</td></tr>
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