Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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__IOM uint32_t | ISER [8] |
| Offset: 0x000 (R/W) Interrupt Set Enable Register.
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uint32_t | RESERVED0 [24] |
| Reserved.
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__IOM uint32_t | ICER [8] |
| Offset: 0x080 (R/W) Interrupt Clear Enable Register.
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uint32_t | RSERVED1 [24] |
| Reserved.
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__IOM uint32_t | ISPR [8] |
| Offset: 0x100 (R/W) Interrupt Set Pending Register.
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uint32_t | RESERVED2 [24] |
| Reserved.
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__IOM uint32_t | ICPR [8] |
| Offset: 0x180 (R/W) Interrupt Clear Pending Register.
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uint32_t | RESERVED3 [24] |
| Reserved.
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__IOM uint32_t | IABR [8] |
| Offset: 0x200 (R/W) Interrupt Active bit Register.
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uint32_t | RESERVED4 [56] |
| Reserved.
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__IOM uint8_t | IP [240] |
| Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
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uint32_t | RESERVED5 [644] |
| Reserved.
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__OM uint32_t | STIR |
| Offset: 0xE00 ( /W) Software Trigger Interrupt Register.
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__IOM uint32_t NVIC_Type::IABR[8] |
__IOM uint32_t NVIC_Type::ICER[8] |
__IOM uint32_t NVIC_Type::ICPR[8] |
__IOM uint8_t NVIC_Type::IP[240] |
__IOM uint32_t NVIC_Type::ISER[8] |
__IOM uint32_t NVIC_Type::ISPR[8] |
uint32_t NVIC_Type::RESERVED0[24] |
uint32_t NVIC_Type::RESERVED2[24] |
uint32_t NVIC_Type::RESERVED3[24] |
uint32_t NVIC_Type::RESERVED4[56] |
uint32_t NVIC_Type::RESERVED5[644] |
uint32_t NVIC_Type::RSERVED1[24] |
__OM uint32_t NVIC_Type::STIR |