From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Zone/html/format_memory_map.html | 153 ++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 docs/Zone/html/format_memory_map.html (limited to 'docs/Zone/html/format_memory_map.html') diff --git a/docs/Zone/html/format_memory_map.html b/docs/Zone/html/format_memory_map.html new file mode 100644 index 0000000..1c1514f --- /dev/null +++ b/docs/Zone/html/format_memory_map.html @@ -0,0 +1,153 @@ + + + + + +/memory_map element +CMSIS-Zone (Preview): /memory_map element + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Zone (Preview) +  Version 0.0.1 +
+
System Resource Management
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
/memory_map element
+
+
+

The memory_map element is used to to define the logical address mappings (i.e. the "memory map").

+

Example

+
<memory_map>
+
<!-- Logical address to access integrated SRAM -->
+
<memory name="SRAM" start="0x10000000"/>
+
:
+
<!-- Logical address to access peripheral ADC0 registers -->
+
<peripheral name="ADC0" start="0x40010000"/>
+
:
+
</memory_map>
+

Schema Description

+ + + + + + + + + + + + + +
Parent Element Element Chain
device /device element
processor /processor element
Child Elements Description Type Occurrence
memory One memory entry per memory region mapped into the logical address space. complexType 0..*
peripheral One peripheral entry per peripheral mapped into the logical address space. complexType 0..*
+
+
+ + + + -- cgit