From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- docs/RTOS2/html/pHardwareRequirements.html | 33 +++++++++++++++--------------- 1 file changed, 17 insertions(+), 16 deletions(-) (limited to 'docs/RTOS2/html/pHardwareRequirements.html') diff --git a/docs/RTOS2/html/pHardwareRequirements.html b/docs/RTOS2/html/pHardwareRequirements.html index fac09bb..275e23d 100644 --- a/docs/RTOS2/html/pHardwareRequirements.html +++ b/docs/RTOS2/html/pHardwareRequirements.html @@ -114,7 +114,7 @@ $(document).ready(function(){initNavTree('pHardwareRequirements.html','');});

The following section lists the hardware requirements for RTX v5 on the various supported target processors:

Processor Requirements

-

RTX assumes a fully function-able processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.

+

RTX assumes a fully functionable processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.

Cortex-M0/M0+/M23 target processor

@@ -131,7 +131,7 @@ Cortex-M0/M0+/M23 target processor
Interrupt Control The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register.
-

The interface files to the processor hardware are:

+

The RTX implements interfaces to the processor hardware in following files:

Note
    -
  • The CMSIS-Core variable SystemCoreClock is used to configure the SysTick timer.
    • +
  • The CMSIS-Core variable SystemCoreClock is used by RTX to configure the SysTick timer.
-

-Cortex-M3/M4/M7/M33 target processor

+

+Cortex-M3/M4/M7/M33/M35P target processor

+

RTX assumes a fully function-able processor and uses the following hardware features:

- + - + - + - + - + - + - +
Hardware Requirement Description
Hardware Item Requirement Description
SysTick timer The SysTick timer generates the kernel tick interrupts and the interface is implemented in os_systick.c using the OS Tick API
SysTick timer The SysTick timer shall be available in the processor.
Exception Handler RTX implements exception handlers for SVC, PendSV, and SysTick interrupt
System Exceptions The RTX requires SVC, PendSV, and SysTick exceptions and implements corresponding exception handlers.
Core Registers The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK, BASEPRI
Core Registers The RTX uses CONTROL, IPSR , PRIMASK and BASEPRI core registers for reading processor status.
System Control Block (SBC) To control and setup the processor exceptions including PendSV and SVC
System Control Block (SCB) The RTX uses SCB registers to control and setup the processor system exceptions including PendSV and SVC.
NVIC Interface The CMSIS-Core function NVIC_GetPriorityGrouping to setup interrupt priorities.
NVIC Interface CMSIS-Core function NVIC_GetPriorityGrouping is used by the RTX to setup interrupt priorities.
LDREX, STREX instruction Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions.
LDREX, STREX instructions Exclusive access instructions LDREX and STREX are used to implement atomic execution without disabling interrupts.

The interface files to the processor hardware are:

Note
    -
  • The CMSIS-Core variable SystemCoreClock is used to configure the SysTick timer.
    • +
  • The CMSIS-Core variable SystemCoreClock is used by RTX to configure the SysTick timer.

@@ -196,7 +197,7 @@ Cortex-A5/A7/A9 target processor

  • irq_ctrl.h is the IRQ Controller API that defines the interface functions to the interrupt controller.
    • Note
      -
    • The CMSIS-Core variable SystemCoreClock is used to configure the timer peripheral.
      • +
    • The CMSIS-Core variable SystemCoreClock is used by RTX to configure the timer peripheral.

    @@ -209,7 +210,7 @@ Memory Requirements