From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- .../group__nand__driver__seq__exec__codes.html | 362 +++++++++++++++++++++ 1 file changed, 362 insertions(+) create mode 100644 docs/Driver/html/group__nand__driver__seq__exec__codes.html (limited to 'docs/Driver/html/group__nand__driver__seq__exec__codes.html') diff --git a/docs/Driver/html/group__nand__driver__seq__exec__codes.html b/docs/Driver/html/group__nand__driver__seq__exec__codes.html new file mode 100644 index 0000000..70bd570 --- /dev/null +++ b/docs/Driver/html/group__nand__driver__seq__exec__codes.html @@ -0,0 +1,362 @@ + + + + + +NAND Sequence Execution Codes +CMSIS-Driver: NAND Sequence Execution Codes + + + + + + + + + + + + + + +
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CMSIS-Driver +  Version 2.6.0 +
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Peripheral Interface for Middleware and Application Code
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NAND Sequence Execution Codes
NAND Interface
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Specify execution codes. +More...

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+Macros

#define ARM_NAND_CODE_SEND_CMD1   (1UL << 17)
 Send Command 1. More...
 
#define ARM_NAND_CODE_SEND_ADDR_COL1   (1UL << 18)
 Send Column Address 1. More...
 
#define ARM_NAND_CODE_SEND_ADDR_COL2   (1UL << 19)
 Send Column Address 2. More...
 
#define ARM_NAND_CODE_SEND_ADDR_ROW1   (1UL << 20)
 Send Row Address 1. More...
 
#define ARM_NAND_CODE_SEND_ADDR_ROW2   (1UL << 21)
 Send Row Address 2. More...
 
#define ARM_NAND_CODE_SEND_ADDR_ROW3   (1UL << 22)
 Send Row Address 3. More...
 
#define ARM_NAND_CODE_INC_ADDR_ROW   (1UL << 23)
 Auto-increment Row Address. More...
 
#define ARM_NAND_CODE_WRITE_DATA   (1UL << 24)
 Write Data. More...
 
#define ARM_NAND_CODE_SEND_CMD2   (1UL << 25)
 Send Command 2. More...
 
#define ARM_NAND_CODE_WAIT_BUSY   (1UL << 26)
 Wait while R/Bn busy. More...
 
#define ARM_NAND_CODE_READ_DATA   (1UL << 27)
 Read Data. More...
 
#define ARM_NAND_CODE_SEND_CMD3   (1UL << 28)
 Send Command 3. More...
 
#define ARM_NAND_CODE_READ_STATUS   (1UL << 29)
 Read Status byte and check FAIL bit (bit 0) More...
 
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Description

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Specify execution codes.

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The defines can be used in the function ARM_NAND_ExecuteSequence for the parameter code.

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Macro Definition Documentation

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#define ARM_NAND_CODE_SEND_CMD1   (1UL << 17)
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Send Command 1.

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#define ARM_NAND_CODE_SEND_ADDR_COL1   (1UL << 18)
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Send Column Address 1.

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#define ARM_NAND_CODE_SEND_ADDR_COL2   (1UL << 19)
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Send Column Address 2.

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#define ARM_NAND_CODE_SEND_ADDR_ROW1   (1UL << 20)
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Send Row Address 1.

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#define ARM_NAND_CODE_SEND_ADDR_ROW2   (1UL << 21)
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Send Row Address 2.

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#define ARM_NAND_CODE_SEND_ADDR_ROW3   (1UL << 22)
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Send Row Address 3.

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#define ARM_NAND_CODE_INC_ADDR_ROW   (1UL << 23)
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Auto-increment Row Address.

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#define ARM_NAND_CODE_WRITE_DATA   (1UL << 24)
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Write Data.

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#define ARM_NAND_CODE_SEND_CMD2   (1UL << 25)
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Send Command 2.

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#define ARM_NAND_CODE_WAIT_BUSY   (1UL << 26)
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Wait while R/Bn busy.

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#define ARM_NAND_CODE_READ_DATA   (1UL << 27)
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Read Data.

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#define ARM_NAND_CODE_SEND_CMD3   (1UL << 28)
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Send Command 3.

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#define ARM_NAND_CODE_READ_STATUS   (1UL << 29)
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Read Status byte and check FAIL bit (bit 0)

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