From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- docs/Core_A/html/ARMCA9_8h.html | 157 ++-- docs/Core_A/html/MISRA_8txt.html | 4 +- docs/Core_A/html/Overview_8txt.html | 4 +- docs/Core_A/html/Ref__SystemAndClock_8txt.html | 4 +- docs/Core_A/html/Template_8txt.html | 4 +- docs/Core_A/html/Using_8txt.html | 4 +- docs/Core_A/html/annotated.html | 4 +- docs/Core_A/html/classes.html | 4 +- docs/Core_A/html/cmsis.css | 2 +- docs/Core_A/html/cmsis__armcc_8h.html | 25 +- docs/Core_A/html/cmsis__armcc_8txt.html | 29 +- docs/Core_A/html/cmsis__cp15_8h.html | 6 +- docs/Core_A/html/coreMISRA_Exceptions_pg.html | 4 +- docs/Core_A/html/core__ca_8h.html | 8 +- docs/Core_A/html/core__ca_8txt.html | 4 +- docs/Core_A/html/deprecated.html | 14 +- docs/Core_A/html/device_h_pg.html | 4 +- .../html/dir_3541bd7f1207d85fb277b58db6e0335d.html | 4 +- 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4 +- docs/Core_A/html/globals_p.html | 4 +- docs/Core_A/html/globals_r.html | 4 +- docs/Core_A/html/globals_s.html | 11 +- docs/Core_A/html/globals_t.html | 4 +- docs/Core_A/html/globals_type.html | 4 +- docs/Core_A/html/globals_u.html | 4 +- docs/Core_A/html/globals_v.html | 17 +- docs/Core_A/html/globals_vars.html | 5 +- docs/Core_A/html/globals_w.html | 4 +- docs/Core_A/html/group__CMSIS__ACTLR.html | 4 +- docs/Core_A/html/group__CMSIS__ACTLR__BITS.html | 4 +- docs/Core_A/html/group__CMSIS__CBAR.html | 4 +- docs/Core_A/html/group__CMSIS__CBAR__BITS.html | 4 +- docs/Core_A/html/group__CMSIS__CBPM.html | 4 +- docs/Core_A/html/group__CMSIS__CNTFRQ.html | 4 +- docs/Core_A/html/group__CMSIS__CNTPCT.html | 4 +- docs/Core_A/html/group__CMSIS__CNTP__CTL.html | 4 +- docs/Core_A/html/group__CMSIS__CNTP__CVAL.html | 4 +- docs/Core_A/html/group__CMSIS__CNTP__TVAL.html | 4 +- docs/Core_A/html/group__CMSIS__CPACR.html | 4 +- docs/Core_A/html/group__CMSIS__CPACR__BITS.html | 4 +- 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docs/Core_A/html/group__CMSIS__MVBAR.html | 4 +- docs/Core_A/html/group__CMSIS__SCTLR.html | 4 +- docs/Core_A/html/group__CMSIS__SCTLR__BITS.html | 4 +- docs/Core_A/html/group__CMSIS__SP.html | 4 +- docs/Core_A/html/group__CMSIS__TLB.html | 4 +- docs/Core_A/html/group__CMSIS__TTBR.html | 4 +- docs/Core_A/html/group__CMSIS__VBAR.html | 4 +- docs/Core_A/html/group__CMSIS__core__register.html | 4 +- docs/Core_A/html/group__FPU__functions.html | 4 +- docs/Core_A/html/group__GIC__functions.html | 4 +- docs/Core_A/html/group__L1__cache__functions.html | 6 +- docs/Core_A/html/group__L2__cache__functions.html | 4 +- docs/Core_A/html/group__MMU__defs__gr.html | 4 +- docs/Core_A/html/group__MMU__functions.html | 4 +- docs/Core_A/html/group__PL1__timer__functions.html | 4 +- docs/Core_A/html/group__PTM__timer__functions.html | 4 +- docs/Core_A/html/group__comp__cntrl__gr.html | 161 +++- docs/Core_A/html/group__comp__cntrl__gr.js | 7 + docs/Core_A/html/group__irq__ctrl__gr.html | 4 +- docs/Core_A/html/group__irq__mode__defs.html | 4 +- docs/Core_A/html/group__irq__priority__defs.html | 4 +- docs/Core_A/html/group__peripheral__gr.html | 4 +- docs/Core_A/html/group__system__init__gr.html | 6 +- docs/Core_A/html/group__version__ctrl.html | 4 +- docs/Core_A/html/index.doxyidx | 937 +++++++++++++++++++++ docs/Core_A/html/index.html | 8 +- docs/Core_A/html/irq__ctrl_8h.html | 4 +- docs/Core_A/html/irq__ctrl_8txt.html | 4 +- docs/Core_A/html/irq__ctrl__gic_8c.html | 4 +- docs/Core_A/html/mem__ARMCA9_8h.html | 353 -------- docs/Core_A/html/mem_h_pg.html | 4 +- docs/Core_A/html/mmu_c_pg.html | 22 +- docs/Core_A/html/modules.html | 4 +- docs/Core_A/html/navtree.js | 2 +- docs/Core_A/html/navtreeindex2.js | 24 +- docs/Core_A/html/navtreeindex3.js | 7 + docs/Core_A/html/pages.html | 4 +- docs/Core_A/html/ref__cache_8txt.html | 4 +- docs/Core_A/html/ref__core__register_8txt.html | 4 +- docs/Core_A/html/ref__gic_8txt.html | 4 +- docs/Core_A/html/ref__mmu_8txt.html | 4 +- docs/Core_A/html/ref__timer_8txt.html | 4 +- docs/Core_A/html/rev_histCoreA.html | 18 +- docs/Core_A/html/search/all_0.js | 29 +- docs/Core_A/html/search/all_13.js | 7 +- docs/Core_A/html/search/all_16.js | 5 +- docs/Core_A/html/search/all_d.js | 2 - docs/Core_A/html/search/defines_0.js | 16 +- docs/Core_A/html/search/defines_c.js | 5 +- docs/Core_A/html/search/files_3.js | 1 - docs/Core_A/html/search/files_6.js | 3 +- docs/Core_A/html/search/functions_5.js | 1 - docs/Core_A/html/search/functions_8.js | 4 +- docs/Core_A/html/search/variables_12.js | 2 +- docs/Core_A/html/startup__ARMCA9_8c.html | 4 +- docs/Core_A/html/startup_c_pg.html | 6 +- docs/Core_A/html/structFPSCR__Type.html | 4 +- docs/Core_A/html/structGICDistributor__Type.html | 4 +- docs/Core_A/html/structGICInterface__Type.html | 4 +- docs/Core_A/html/structL2C__310__TypeDef.html | 4 +- docs/Core_A/html/structTimer__Type.html | 4 +- .../html/structmmu__region__attributes__Type.html | 4 +- docs/Core_A/html/system__ARMCA9_8h.html | 203 ----- docs/Core_A/html/system_c_pg.html | 4 +- docs/Core_A/html/templates_pg.html | 4 +- docs/Core_A/html/unionACTLR__Type.html | 4 +- docs/Core_A/html/unionCNTP__CTL__Type.html | 4 +- docs/Core_A/html/unionCPACR__Type.html | 4 +- docs/Core_A/html/unionCPSR__Type.html | 4 +- docs/Core_A/html/unionDFSR__Type.html | 4 +- docs/Core_A/html/unionIFSR__Type.html | 4 +- docs/Core_A/html/unionISR__Type.html | 4 +- docs/Core_A/html/unionSCTLR__Type.html | 4 +- docs/Core_A/html/using_ARM_pg.html | 5 +- docs/Core_A/html/using_CMSIS.html | 7 +- docs/Core_A/html/using_pg.html | 7 +- 224 files changed, 1802 insertions(+), 1234 deletions(-) create mode 100644 docs/Core_A/html/index.doxyidx delete mode 100644 docs/Core_A/html/mem__ARMCA9_8h.html delete mode 100644 docs/Core_A/html/system__ARMCA9_8h.html (limited to 'docs/Core_A') diff --git a/docs/Core_A/html/ARMCA9_8h.html b/docs/Core_A/html/ARMCA9_8h.html index 208e401..1c43346 100644 --- a/docs/Core_A/html/ARMCA9_8h.html +++ b/docs/Core_A/html/ARMCA9_8h.html @@ -32,7 +32,7 @@ Logo
CMSIS-Core (Cortex-A) -  Version 1.1.2 +  Version 1.1.4
CMSIS-Core support for Cortex-A processor-based devices
@@ -119,60 +119,66 @@ $(document).ready(function(){initNavTree('ARMCA9_8h.html','');}); Macros #define VE_A9_MP_FLASH_BASE0   (0x00000000UL)   -#define VE_A9_MP_FLASH_BASE1   (0x08000000UL) +#define VE_A9_MP_FLASH_BASE1   (0x0C000000UL)   -#define VE_A9_MP_PERIPH_BASE   (0x18000000UL) -  -#define VE_A9_MP_SRAM_BASE   (0x2E000000UL) +#define VE_A9_MP_SRAM_BASE   (0x14000000UL)   -#define VE_A9_MP_DRAM_BASE   (0x80000000UL) -  -#define VE_A9_MP_VRAM_BASE   (0x18000000UL) +#define VE_A9_MP_PERIPH_BASE_CS2   (0x18000000UL) +  +#define VE_A9_MP_VRAM_BASE   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)   -#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE) +#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)   -#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE) +#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)   -#define VE_A9_MP_DAP_BASE   (0x1C000000UL) +#define VE_A9_MP_PERIPH_BASE_CS3   (0x1C000000UL) +  +#define VE_A9_MP_DAP_BASE   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + 0x1C000000UL) +#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + 0x1C000000UL) +#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_AACI_BASE   (0x00040000UL + 0x1C000000UL) +#define VE_A9_MP_AACI_BASE   (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_MMCI_BASE   (0x00050000UL + 0x1C000000UL) +#define VE_A9_MP_MMCI_BASE   (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_KMI0_BASE   (0x00060000UL + 0x1C000000UL) +#define VE_A9_MP_KMI0_BASE   (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_UART_BASE   (0x00090000UL + 0x1C000000UL) +#define VE_A9_MP_UART_BASE   (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_WDT_BASE   (0x000F0000UL + 0x1C000000UL) +#define VE_A9_MP_WDT_BASE   (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_TIMER_BASE   (0x00110000UL + 0x1C000000UL) +#define VE_A9_MP_TIMER_BASE   (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_DVI_BASE   (0x00160000UL + 0x1C000000UL) +#define VE_A9_MP_DVI_BASE   (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_RTC_BASE   (0x00170000UL + 0x1C000000UL) +#define VE_A9_MP_RTC_BASE   (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_UART4_BASE   (0x001B0000UL + 0x1C000000UL) +#define VE_A9_MP_UART4_BASE   (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + 0x1C000000UL) +#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)   -#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + 0x2C000000UL) +#define VE_A9_MP_PL310_BASE   (0x1E00A000UL) +  +#define VE_A9_MP_PRIVATE_PERIPH_BASE   (0x2C000000UL) +  +#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE)   -#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + 0x2C000000UL) +#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE)   -#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + 0x2C000000UL) +#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE)   +#define VE_A9_MP_SSRAM_BASE   (0x2E000000UL) +  +#define VE_A9_MP_DRAM_BASE   (0x80000000UL) +  #define GIC_DISTRIBUTOR_BASE   VE_A9_MP_GIC_DISTRIBUTOR_BASE   #define GIC_INTERFACE_BASE   VE_A9_MP_GIC_INTERFACE_BASE   #define TIMER_BASE   VE_A9_MP_PRIVATE_TIMER   -#define VE_A9_MP_PL310_BASE   (0x1E00A000UL) -  #define L2C_310_BASE   VE_A9_MP_PL310_BASE   #define __CA_REV   0x0000U @@ -368,7 +374,7 @@ Enumerations
- +
#define VE_A9_MP_AACI_BASE   (0x00040000UL + 0x1C000000UL)#define VE_A9_MP_AACI_BASE   (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -381,7 +387,7 @@ Enumerations
- +
#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + 0x1C000000UL)#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -394,11 +400,11 @@ Enumerations
- +
#define VE_A9_MP_DAP_BASE   (0x1C000000UL)#define VE_A9_MP_DAP_BASE   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)
-

(DAP ) Base Address

+

(LOCAL DAP ) Base Address

@@ -420,7 +426,7 @@ Enumerations
- +
#define VE_A9_MP_DVI_BASE   (0x00160000UL + 0x1C000000UL)#define VE_A9_MP_DVI_BASE   (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -433,7 +439,7 @@ Enumerations
- +
#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE)#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)
@@ -459,7 +465,7 @@ Enumerations
- +
#define VE_A9_MP_FLASH_BASE1   (0x08000000UL)#define VE_A9_MP_FLASH_BASE1   (0x0C000000UL)
@@ -472,7 +478,7 @@ Enumerations
- +
#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + 0x2C000000UL)#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE)
@@ -485,11 +491,11 @@ Enumerations
- +
#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + 0x2C000000UL)#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE)
-

(GIC CPU IF) Base Address

+

(GIC CPU IF ) Base Address

@@ -498,7 +504,7 @@ Enumerations
- +
#define VE_A9_MP_KMI0_BASE   (0x00060000UL + 0x1C000000UL)#define VE_A9_MP_KMI0_BASE   (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -511,7 +517,7 @@ Enumerations
- +
#define VE_A9_MP_MMCI_BASE   (0x00050000UL + 0x1C000000UL)#define VE_A9_MP_MMCI_BASE   (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -519,16 +525,29 @@ Enumerations
- +
- +
#define VE_A9_MP_PERIPH_BASE   (0x18000000UL)#define VE_A9_MP_PERIPH_BASE_CS2   (0x18000000UL)
-

(Peripheral) Base Address

+

(Peripheral ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_PERIPH_BASE_CS3   (0x1C000000UL)
+
+

(Peripheral ) Base Address

@@ -543,6 +562,19 @@ Enumerations

(L2C-310 ) Base Address

+
+
+ +
+
+ + + + +
#define VE_A9_MP_PRIVATE_PERIPH_BASE   (0x2C000000UL)
+
+

(Peripheral ) Base Address

+
@@ -550,7 +582,7 @@ Enumerations
- +
#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + 0x2C000000UL)#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE)
@@ -563,7 +595,7 @@ Enumerations
- +
#define VE_A9_MP_RTC_BASE   (0x00170000UL + 0x1C000000UL)#define VE_A9_MP_RTC_BASE   (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -576,7 +608,7 @@ Enumerations
- +
#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + 0x1C000000UL)#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -589,12 +621,25 @@ Enumerations
- +
#define VE_A9_MP_SRAM_BASE   (0x2E000000UL)#define VE_A9_MP_SRAM_BASE   (0x14000000UL)

(SRAM ) Base Address

+
+
+ +
+
+ + + + +
#define VE_A9_MP_SSRAM_BASE   (0x2E000000UL)
+
+

(System SRAM) Base Address

+
@@ -602,11 +647,11 @@ Enumerations
- +
#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + 0x1C000000UL)#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)
-

(SYSTEM REG) Base Address

+

(SYSTEM REG ) Base Address

@@ -615,7 +660,7 @@ Enumerations
- +
#define VE_A9_MP_TIMER_BASE   (0x00110000UL + 0x1C000000UL)#define VE_A9_MP_TIMER_BASE   (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -628,7 +673,7 @@ Enumerations
- +
#define VE_A9_MP_UART4_BASE   (0x001B0000UL + 0x1C000000UL)#define VE_A9_MP_UART4_BASE   (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -641,7 +686,7 @@ Enumerations
- +
#define VE_A9_MP_UART_BASE   (0x00090000UL + 0x1C000000UL)#define VE_A9_MP_UART_BASE   (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -654,7 +699,7 @@ Enumerations
- +
#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE)#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)
@@ -667,7 +712,7 @@ Enumerations
- +
#define VE_A9_MP_VRAM_BASE   (0x18000000UL)#define VE_A9_MP_VRAM_BASE   (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)
@@ -680,7 +725,7 @@ Enumerations
- +
#define VE_A9_MP_WDT_BASE   (0x000F0000UL + 0x1C000000UL)#define VE_A9_MP_WDT_BASE   (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)
@@ -815,7 +860,7 @@ Enumerations