From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/ARMCA9_8h.html | 827 ++++++++ docs/Core_A/html/CMSIS_CORE_A_Files_user.png | Bin 0 -> 48399 bytes docs/Core_A/html/CMSIS_Logo_Final.png | Bin 0 -> 12402 bytes docs/Core_A/html/MISRA_8txt.html | 129 ++ docs/Core_A/html/Overview_8txt.html | 129 ++ docs/Core_A/html/Ref__SystemAndClock_8txt.html | 148 ++ docs/Core_A/html/Template_8txt.html | 129 ++ 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mode 100644 docs/Core_A/html/startup_c_pg.html create mode 100644 docs/Core_A/html/structFPSCR__Type.html create mode 100644 docs/Core_A/html/structGICDistributor__Type.html create mode 100644 docs/Core_A/html/structGICDistributor__Type.js create mode 100644 docs/Core_A/html/structGICInterface__Type.html create mode 100644 docs/Core_A/html/structGICInterface__Type.js create mode 100644 docs/Core_A/html/structL2C__310__TypeDef.html create mode 100644 docs/Core_A/html/structL2C__310__TypeDef.js create mode 100644 docs/Core_A/html/structTimer__Type.html create mode 100644 docs/Core_A/html/structTimer__Type.js create mode 100644 docs/Core_A/html/structmmu__region__attributes__Type.html create mode 100644 docs/Core_A/html/structmmu__region__attributes__Type.js create mode 100644 docs/Core_A/html/sync_off.png create mode 100644 docs/Core_A/html/sync_on.png create mode 100644 docs/Core_A/html/system__ARMCA9_8h.html create mode 100644 docs/Core_A/html/system_c_pg.html create mode 100644 docs/Core_A/html/tab_a.png create mode 100644 docs/Core_A/html/tab_b.png create mode 100644 docs/Core_A/html/tab_h.png create mode 100644 docs/Core_A/html/tab_s.png create mode 100644 docs/Core_A/html/tab_topnav.png create mode 100644 docs/Core_A/html/tabs.css create mode 100644 docs/Core_A/html/templates_pg.html create mode 100644 docs/Core_A/html/templates_pg.js create mode 100644 docs/Core_A/html/unionACTLR__Type.html create mode 100644 docs/Core_A/html/unionACTLR__Type.js create mode 100644 docs/Core_A/html/unionCNTP__CTL__Type.html create mode 100644 docs/Core_A/html/unionCNTP__CTL__Type.js create mode 100644 docs/Core_A/html/unionCPACR__Type.html create mode 100644 docs/Core_A/html/unionCPACR__Type.js create mode 100644 docs/Core_A/html/unionCPSR__Type.html create mode 100644 docs/Core_A/html/unionCPSR__Type.js create mode 100644 docs/Core_A/html/unionDFSR__Type.html create mode 100644 docs/Core_A/html/unionDFSR__Type.js create mode 100644 docs/Core_A/html/unionIFSR__Type.html create mode 100644 docs/Core_A/html/unionIFSR__Type.js create mode 100644 docs/Core_A/html/unionISR__Type.html create mode 100644 docs/Core_A/html/unionISR__Type.js create mode 100644 docs/Core_A/html/unionSCTLR__Type.html create mode 100644 docs/Core_A/html/unionSCTLR__Type.js create mode 100644 docs/Core_A/html/using_ARM_pg.html create mode 100644 docs/Core_A/html/using_CMSIS.html create mode 100644 docs/Core_A/html/using_pg.html create mode 100644 docs/Core_A/html/using_pg.js (limited to 'docs/Core_A/html') diff --git a/docs/Core_A/html/ARMCA9_8h.html b/docs/Core_A/html/ARMCA9_8h.html new file mode 100644 index 0000000..208e401 --- /dev/null +++ b/docs/Core_A/html/ARMCA9_8h.html @@ -0,0 +1,827 @@ + + + + + +ARMCA9.h File Reference +CMSIS-Core (Cortex-A): ARMCA9.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Enumerations
+
+
ARMCA9.h File Reference
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define VE_A9_MP_FLASH_BASE0   (0x00000000UL)
 
#define VE_A9_MP_FLASH_BASE1   (0x08000000UL)
 
#define VE_A9_MP_PERIPH_BASE   (0x18000000UL)
 
#define VE_A9_MP_SRAM_BASE   (0x2E000000UL)
 
#define VE_A9_MP_DRAM_BASE   (0x80000000UL)
 
#define VE_A9_MP_VRAM_BASE   (0x18000000UL)
 
#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE)
 
#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE)
 
#define VE_A9_MP_DAP_BASE   (0x1C000000UL)
 
#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + 0x1C000000UL)
 
#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + 0x1C000000UL)
 
#define VE_A9_MP_AACI_BASE   (0x00040000UL + 0x1C000000UL)
 
#define VE_A9_MP_MMCI_BASE   (0x00050000UL + 0x1C000000UL)
 
#define VE_A9_MP_KMI0_BASE   (0x00060000UL + 0x1C000000UL)
 
#define VE_A9_MP_UART_BASE   (0x00090000UL + 0x1C000000UL)
 
#define VE_A9_MP_WDT_BASE   (0x000F0000UL + 0x1C000000UL)
 
#define VE_A9_MP_TIMER_BASE   (0x00110000UL + 0x1C000000UL)
 
#define VE_A9_MP_DVI_BASE   (0x00160000UL + 0x1C000000UL)
 
#define VE_A9_MP_RTC_BASE   (0x00170000UL + 0x1C000000UL)
 
#define VE_A9_MP_UART4_BASE   (0x001B0000UL + 0x1C000000UL)
 
#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + 0x1C000000UL)
 
#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + 0x2C000000UL)
 
#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + 0x2C000000UL)
 
#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + 0x2C000000UL)
 
#define GIC_DISTRIBUTOR_BASE   VE_A9_MP_GIC_DISTRIBUTOR_BASE
 
#define GIC_INTERFACE_BASE   VE_A9_MP_GIC_INTERFACE_BASE
 
#define TIMER_BASE   VE_A9_MP_PRIVATE_TIMER
 
#define VE_A9_MP_PL310_BASE   (0x1E00A000UL)
 
#define L2C_310_BASE   VE_A9_MP_PL310_BASE
 
#define __CA_REV   0x0000U
 Contains the core revision for a Cortex-A class device. More...
 
#define __CORTEX_A   9U
 Contains the core family for a Cortex-A class device. More...
 
#define __FPU_PRESENT   1U /* FPU present */
 
#define __GIC_PRESENT   1U /* GIC present */
 
#define __TIM_PRESENT   1U /* TIM present */
 
#define __L2C_PRESENT   0U /* L2C present */
 
+ + + +

+Enumerations

enum  IRQn_Type {
+  SGI0_IRQn = 0, +
+  SGI1_IRQn = 1, +
+  SGI2_IRQn = 2, +
+  SGI3_IRQn = 3, +
+  SGI4_IRQn = 4, +
+  SGI5_IRQn = 5, +
+  SGI6_IRQn = 6, +
+  SGI7_IRQn = 7, +
+  SGI8_IRQn = 8, +
+  SGI9_IRQn = 9, +
+  SGI10_IRQn = 10, +
+  SGI11_IRQn = 11, +
+  SGI12_IRQn = 12, +
+  SGI13_IRQn = 13, +
+  SGI14_IRQn = 14, +
+  SGI15_IRQn = 15, +
+  GlobalTimer_IRQn = 27, +
+  PrivTimer_IRQn = 29, +
+  PrivWatchdog_IRQn = 30, +
+  Watchdog_IRQn = 32, +
+  Timer0_IRQn = 34, +
+  Timer1_IRQn = 35, +
+  RTClock_IRQn = 36, +
+  UART0_IRQn = 37, +
+  UART1_IRQn = 38, +
+  UART2_IRQn = 39, +
+  UART3_IRQn = 40, +
+  MCI0_IRQn = 41, +
+  MCI1_IRQn = 42, +
+  AACI_IRQn = 43, +
+  Keyboard_IRQn = 44, +
+  Mouse_IRQn = 45, +
+  CLCD_IRQn = 46, +
+  Ethernet_IRQn = 47, +
+  VFS2_IRQn = 73 +
+ }
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __FPU_PRESENT   1U /* FPU present */
+
+ +
+
+ +
+
+ + + + +
#define __GIC_PRESENT   1U /* GIC present */
+
+ +
+
+ +
+
+ + + + +
#define __L2C_PRESENT   0U /* L2C present */
+
+ +
+
+ +
+
+ + + + +
#define __TIM_PRESENT   1U /* TIM present */
+
+ +
+
+ +
+
+ + + + +
#define GIC_DISTRIBUTOR_BASE   VE_A9_MP_GIC_DISTRIBUTOR_BASE
+
+ +
+
+ +
+
+ + + + +
#define GIC_INTERFACE_BASE   VE_A9_MP_GIC_INTERFACE_BASE
+
+ +
+
+ +
+
+ + + + +
#define L2C_310_BASE   VE_A9_MP_PL310_BASE
+
+ +
+
+ +
+
+ + + + +
#define TIMER_BASE   VE_A9_MP_PRIVATE_TIMER
+
+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_AACI_BASE   (0x00040000UL + 0x1C000000UL)
+
+

(AACI ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + 0x1C000000UL)
+
+

(CLCD ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_DAP_BASE   (0x1C000000UL)
+
+

(DAP ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_DRAM_BASE   (0x80000000UL)
+
+

(DRAM ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_DVI_BASE   (0x00160000UL + 0x1C000000UL)
+
+

(DVI ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE)
+
+

(ETHERNET ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_FLASH_BASE0   (0x00000000UL)
+
+

(FLASH0 ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_FLASH_BASE1   (0x08000000UL)
+
+

(FLASH1 ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + 0x2C000000UL)
+
+

(GIC DIST ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + 0x2C000000UL)
+
+

(GIC CPU IF) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_KMI0_BASE   (0x00060000UL + 0x1C000000UL)
+
+

(KMI0 ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_MMCI_BASE   (0x00050000UL + 0x1C000000UL)
+
+

(MMCI ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_PERIPH_BASE   (0x18000000UL)
+
+

(Peripheral) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_PL310_BASE   (0x1E00A000UL)
+
+

(L2C-310 ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + 0x2C000000UL)
+
+

(PTIM ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_RTC_BASE   (0x00170000UL + 0x1C000000UL)
+
+

(RTC ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + 0x1C000000UL)
+
+

(SERIAL ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_SRAM_BASE   (0x2E000000UL)
+
+

(SRAM ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + 0x1C000000UL)
+
+

(SYSTEM REG) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_TIMER_BASE   (0x00110000UL + 0x1C000000UL)
+
+

(TIMER ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_UART4_BASE   (0x001B0000UL + 0x1C000000UL)
+
+

(UART4 ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_UART_BASE   (0x00090000UL + 0x1C000000UL)
+
+

(UART ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE)
+
+

(USB ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_VRAM_BASE   (0x18000000UL)
+
+

(VRAM ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_WDT_BASE   (0x000F0000UL + 0x1C000000UL)
+
+

(WDT ) Base Address

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn_Type
+
+

Device specific Interrupt IDs

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
SGI0_IRQn  +

Software Generated Interrupt 0

+
SGI1_IRQn  +

Software Generated Interrupt 1

+
SGI2_IRQn  +

Software Generated Interrupt 2

+
SGI3_IRQn  +

Software Generated Interrupt 3

+
SGI4_IRQn  +

Software Generated Interrupt 4

+
SGI5_IRQn  +

Software Generated Interrupt 5

+
SGI6_IRQn  +

Software Generated Interrupt 6

+
SGI7_IRQn  +

Software Generated Interrupt 7

+
SGI8_IRQn  +

Software Generated Interrupt 8

+
SGI9_IRQn  +

Software Generated Interrupt 9

+
SGI10_IRQn  +

Software Generated Interrupt 10

+
SGI11_IRQn  +

Software Generated Interrupt 11

+
SGI12_IRQn  +

Software Generated Interrupt 12

+
SGI13_IRQn  +

Software Generated Interrupt 13

+
SGI14_IRQn  +

Software Generated Interrupt 14

+
SGI15_IRQn  +

Software Generated Interrupt 15

+
GlobalTimer_IRQn  +

Global Timer Interrupt

+
PrivTimer_IRQn  +

Private Timer Interrupt

+
PrivWatchdog_IRQn  +

Private Watchdog Interrupt

+
Watchdog_IRQn  +

SP805 Interrupt

+
Timer0_IRQn  +

SP804 Interrupt

+
Timer1_IRQn  +

SP804 Interrupt

+
RTClock_IRQn  +

PL031 Interrupt

+
UART0_IRQn  +

PL011 Interrupt

+
UART1_IRQn  +

PL011 Interrupt

+
UART2_IRQn  +

PL011 Interrupt

+
UART3_IRQn  +

PL011 Interrupt

+
MCI0_IRQn  +

PL180 Interrupt (1st)

+
MCI1_IRQn  +

PL180 Interrupt (2nd)

+
AACI_IRQn  +

PL041 Interrupt

+
Keyboard_IRQn  +

PL050 Interrupt

+
Mouse_IRQn  +

PL050 Interrupt

+
CLCD_IRQn  +

PL111 Interrupt

+
Ethernet_IRQn  +

SMSC_91C111 Interrupt

+
VFS2_IRQn  +

VFS2 Interrupt

+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/CMSIS_CORE_A_Files_user.png b/docs/Core_A/html/CMSIS_CORE_A_Files_user.png new file mode 100644 index 0000000..d72b312 Binary files /dev/null and b/docs/Core_A/html/CMSIS_CORE_A_Files_user.png differ diff --git a/docs/Core_A/html/CMSIS_Logo_Final.png b/docs/Core_A/html/CMSIS_Logo_Final.png new file mode 100644 index 0000000..2056b7e Binary files /dev/null and b/docs/Core_A/html/CMSIS_Logo_Final.png differ diff --git a/docs/Core_A/html/MISRA_8txt.html b/docs/Core_A/html/MISRA_8txt.html new file mode 100644 index 0000000..0f61a93 --- /dev/null +++ b/docs/Core_A/html/MISRA_8txt.html @@ -0,0 +1,129 @@ + + + + + +MISRA.txt File Reference +CMSIS-Core (Cortex-A): MISRA.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
MISRA.txt File Reference
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/Overview_8txt.html b/docs/Core_A/html/Overview_8txt.html new file mode 100644 index 0000000..61fd91b --- /dev/null +++ b/docs/Core_A/html/Overview_8txt.html @@ -0,0 +1,129 @@ + + + + + +Overview.txt File Reference +CMSIS-Core (Cortex-A): Overview.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview.txt File Reference
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/Ref__SystemAndClock_8txt.html b/docs/Core_A/html/Ref__SystemAndClock_8txt.html new file mode 100644 index 0000000..bdad358 --- /dev/null +++ b/docs/Core_A/html/Ref__SystemAndClock_8txt.html @@ -0,0 +1,148 @@ + + + + + +Ref_SystemAndClock.txt File Reference +CMSIS-Core (Cortex-A): Ref_SystemAndClock.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
Ref_SystemAndClock.txt File Reference
+
+
+ + + + + + + + +

+Functions

void SystemInit (void)
 Function to Initialize the system. More...
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock. More...
 
+ + + + +

+Variables

uint32_t SystemCoreClock
 Variable to hold the system core clock value. More...
 
+
+
+ + + + diff --git a/docs/Core_A/html/Template_8txt.html b/docs/Core_A/html/Template_8txt.html new file mode 100644 index 0000000..95b79fd --- /dev/null +++ b/docs/Core_A/html/Template_8txt.html @@ -0,0 +1,129 @@ + + + + + +Template.txt File Reference +CMSIS-Core (Cortex-A): Template.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Template.txt File Reference
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/Using_8txt.html b/docs/Core_A/html/Using_8txt.html new file mode 100644 index 0000000..236fe62 --- /dev/null +++ b/docs/Core_A/html/Using_8txt.html @@ -0,0 +1,129 @@ + + + + + +Using.txt File Reference +CMSIS-Core (Cortex-A): Using.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using.txt File Reference
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/annotated.html b/docs/Core_A/html/annotated.html new file mode 100644 index 0000000..ed5849b --- /dev/null +++ b/docs/Core_A/html/annotated.html @@ -0,0 +1,152 @@ + + + + + +Data Structures +CMSIS-Core (Cortex-A): Data Structures + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structures
+
+
+
Here are the data structures with brief descriptions:
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oCACTLR_TypeBit field declaration for ACTLR layout
oCCNTP_CTL_TypePhysical Timer Control register
oCCPACR_TypeBit field declaration for CPACR layout
oCCPSR_TypeBit field declaration for CPSR layout
oCDFSR_TypeBit field declaration for DFSR layout
oCFPSCR_TypeBit field declaration for FPSCR layout
oCGICDistributor_TypeStructure type to access the Generic Interrupt Controller Distributor (GICD)
oCGICInterface_TypeStructure type to access the Generic Interrupt Controller Interface (GICC)
oCIFSR_TypeBit field declaration for IFSR layout
oCISR_TypeBit field declaration for ISR layout
oCL2C_310_TypeDefUnion type to access the L2C_310 Cache Controller
oCmmu_region_attributes_Type
oCSCTLR_TypeBit field declaration for SCTLR layout
\CTimer_TypeStructure type to access the Private Timer
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+ + + + diff --git a/docs/Core_A/html/annotated.js b/docs/Core_A/html/annotated.js new file mode 100644 index 0000000..803f41c --- /dev/null +++ b/docs/Core_A/html/annotated.js @@ -0,0 +1,17 @@ +var annotated = +[ + [ "ACTLR_Type", "unionACTLR__Type.html", "unionACTLR__Type" ], + [ "CNTP_CTL_Type", "unionCNTP__CTL__Type.html", "unionCNTP__CTL__Type" ], + [ "CPACR_Type", "unionCPACR__Type.html", "unionCPACR__Type" ], + [ "CPSR_Type", "unionCPSR__Type.html", "unionCPSR__Type" ], + [ "DFSR_Type", "unionDFSR__Type.html", "unionDFSR__Type" ], + [ "FPSCR_Type", "structFPSCR__Type.html", null ], + [ "GICDistributor_Type", "structGICDistributor__Type.html", "structGICDistributor__Type" ], + [ "GICInterface_Type", "structGICInterface__Type.html", "structGICInterface__Type" ], + [ "IFSR_Type", "unionIFSR__Type.html", "unionIFSR__Type" ], + [ "ISR_Type", "unionISR__Type.html", "unionISR__Type" ], + [ "L2C_310_TypeDef", "structL2C__310__TypeDef.html", "structL2C__310__TypeDef" ], + [ "mmu_region_attributes_Type", "structmmu__region__attributes__Type.html", "structmmu__region__attributes__Type" ], + [ "SCTLR_Type", "unionSCTLR__Type.html", "unionSCTLR__Type" ], + [ "Timer_Type", "structTimer__Type.html", "structTimer__Type" ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/bc_s.png b/docs/Core_A/html/bc_s.png new file mode 100644 index 0000000..66f8e9a Binary files /dev/null and b/docs/Core_A/html/bc_s.png differ diff --git a/docs/Core_A/html/bdwn.png b/docs/Core_A/html/bdwn.png new file mode 100644 index 0000000..d400769 Binary files /dev/null and b/docs/Core_A/html/bdwn.png differ diff --git a/docs/Core_A/html/check.png b/docs/Core_A/html/check.png new file mode 100644 index 0000000..094e59c Binary files /dev/null and b/docs/Core_A/html/check.png differ diff --git a/docs/Core_A/html/classes.html b/docs/Core_A/html/classes.html new file mode 100644 index 0000000..ecdef5e --- /dev/null +++ b/docs/Core_A/html/classes.html @@ -0,0 +1,156 @@ + + + + + +Data Structure Index +CMSIS-Core (Cortex-A): Data Structure Index + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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Data Structure Index
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A | C | D | F | G | I | L | M | S | T
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  A  
+		CPSR_Type   
  G  
+		ISR_Type   
  T  
+
  D  
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  L  
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ACTLR_Type   GICDistributor_Type   Timer_Type   
  C  
+		DFSR_Type   GICInterface_Type   L2C_310_TypeDef   
  m  
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  F  
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  I  
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  S  
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CNTP_CTL_Type   mmu_region_attributes_Type   
CPACR_Type   FPSCR_Type   IFSR_Type   SCTLR_Type   
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A | C | D | F | G | I | L | M | S | T
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+ + + + diff --git a/docs/Core_A/html/closed.png b/docs/Core_A/html/closed.png new file mode 100644 index 0000000..ccbcf62 Binary files /dev/null and b/docs/Core_A/html/closed.png differ diff --git a/docs/Core_A/html/cmsis.css b/docs/Core_A/html/cmsis.css new file mode 100644 index 0000000..bba1010 --- /dev/null +++ b/docs/Core_A/html/cmsis.css @@ -0,0 +1,1282 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +td.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +span.h2 +{ + font-size: 120%; + font-weight: bold; +} + +div.new +{ + background-color:#ccffcc; /* light green */ +} + +div.mod +{ + background-color:#ffe6cc; /* light amber */ +} + +div.del +{ + background-color:#ffcccc; /* light red */ +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #EBEFF6; + color: #000000; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + margin-left: 5px; + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 7px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/docs/Core_A/html/cmsis__armcc_8h.html b/docs/Core_A/html/cmsis__armcc_8h.html new file mode 100644 index 0000000..7579eb8 --- /dev/null +++ b/docs/Core_A/html/cmsis__armcc_8h.html @@ -0,0 +1,1013 @@ + + + + + +cmsis_armcc.h File Reference +CMSIS-Core (Cortex-A): cmsis_armcc.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
cmsis_armcc.h File Reference
+
+
+ +

CMSIS compiler specific macros, functions, instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define __ARM_ARCH_7A__   1
 Set to 1 when generating code for Armv7-A (Cortex-A7) More...
 
#define __ASM   __asm
 Pass information from the compiler to the assembler. More...
 
#define __INLINE   __inline
 Recommend that function should be inlined by the compiler. More...
 
#define __FORCEINLINE   __forceinline
 
#define __STATIC_INLINE   static __inline
 Define a static function should be inlined by the compiler. More...
 
#define __STATIC_FORCEINLINE   static __forceinline
 
#define __NO_RETURN   __declspec(noreturn)
 Inform the compiler that a function does not return. More...
 
#define CMSIS_DEPRECATED   __attribute__((deprecated))
 
#define __USED   __attribute__((used))
 Inform that a variable shall be retained in executable image. More...
 
#define __WEAK   __attribute__((weak))
 Export a function or variable weakly to allow overwrites. More...
 
#define __PACKED   __attribute__((packed))
 Request smallest possible alignment. More...
 
#define __PACKED_STRUCT   __packed struct
 
#define __UNALIGNED_UINT16_WRITE(addr, val)   ((*((__packed uint16_t *)(addr))) = (val))
 
#define __UNALIGNED_UINT16_READ(addr)   (*((const __packed uint16_t *)(addr)))
 
#define __UNALIGNED_UINT32_WRITE(addr, val)   ((*((__packed uint32_t *)(addr))) = (val))
 
#define __UNALIGNED_UINT32_READ(addr)   (*((const __packed uint32_t *)(addr)))
 
#define __ALIGNED(x)   __attribute__((aligned(x)))
 Minimum alignment for a variable. More...
 
#define __NOP   __nop
 No Operation. More...
 
#define __WFI   __wfi
 Wait For Interrupt. More...
 
#define __WFE   __wfe
 Wait For Event. More...
 
#define __SEV   __sev
 Send Event. More...
 
#define __ISB()
 Instruction Synchronization Barrier. More...
 
#define __DSB()
 Data Synchronization Barrier. More...
 
#define __DMB()
 Data Memory Barrier. More...
 
#define __REV   __rev
 Reverse byte order (32 bit) More...
 
#define __ROR   __ror
 Reverse byte order (16 bit) More...
 
#define __BKPT(value)   __breakpoint(value)
 Breakpoint. More...
 
#define __RBIT   __rbit
 Reverse bit order of value. More...
 
#define __CLZ   __clz
 Count leading zeros. More...
 
#define __LDREXB(ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
 LDR Exclusive (8 bit) More...
 
#define __LDREXH(ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
 LDR Exclusive (16 bit) More...
 
#define __LDREXW(ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
 LDR Exclusive (32 bit) More...
 
#define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 STR Exclusive (8 bit) More...
 
#define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 STR Exclusive (16 bit) More...
 
#define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
 STR Exclusive (32 bit) More...
 
#define __CLREX   __clrex
 Remove the exclusive lock. More...
 
#define __SSAT   __ssat
 Signed Saturate. More...
 
#define __USAT   __usat
 Unsigned Saturate. More...
 
#define __get_CP(cp, op1, Rt, CRn, CRm, op2)   do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
 
#define __set_CP(cp, op1, Rt, CRn, CRm, op2)   do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
 
#define __get_CP64(cp, op1, Rt, CRm)
 
#define __set_CP64(cp, op1, Rt, CRm)
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE uint32_t __get_FPSCR (void)
 Get FPSCR (Floating Point Status/Control) More...
 
__STATIC_INLINE void __set_FPSCR (uint32_t fpscr)
 Set FPSCR (Floating Point Status/Control) More...
 
__STATIC_INLINE uint32_t __get_CPSR (void)
 Get CPSR (Current Program Status Register) More...
 
__STATIC_INLINE void __set_CPSR (uint32_t cpsr)
 Set CPSR (Current Program Status Register) More...
 
__STATIC_INLINE uint32_t __get_mode (void)
 Get Mode. More...
 
__STATIC_INLINE __ASM void __set_mode (uint32_t mode)
 Set Mode. More...
 
__STATIC_INLINE __ASM uint32_t __get_SP (void)
 Get Stack Pointer. More...
 
__STATIC_INLINE __ASM void __set_SP (uint32_t stack)
 Set Stack Pointer. More...
 
__STATIC_INLINE __ASM uint32_t __get_SP_usr (void)
 Get USR/SYS Stack Pointer. More...
 
__STATIC_INLINE __ASM void __set_SP_usr (uint32_t topOfProcStack)
 Set USR/SYS Stack Pointer. More...
 
__STATIC_INLINE uint32_t __get_FPEXC (void)
 Get FPEXC (Floating Point Exception Control Register) More...
 
__STATIC_INLINE void __set_FPEXC (uint32_t fpexc)
 Set FPEXC (Floating Point Exception Control Register) More...
 
__STATIC_INLINE __ASM void __FPU_Enable (void)
 Enable Floating Point Unit. More...
 
+

Description

+
Version
V1.0.2
+
Date
10. January 2018
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CLREX   __clrex
+
+

Removes the exclusive lock which is created by LDREX.

+ +
+
+ +
+
+ + + + +
#define __CLZ   __clz
+
+
Parameters
+ + +
[in]valueValue to count the leading zeros
+
+
+
Returns
number of leading zeros in value
+ +
+
+ +
+
+ + + + +
#define __FORCEINLINE   __forceinline
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define __get_CP( cp,
 op1,
 Rt,
 CRn,
 CRm,
 op2 
)   do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define __get_CP64( cp,
 op1,
 Rt,
 CRm 
)
+
+ +
+
+ +
+
+ + + + + + + + +
#define __LDREXB( ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+
+

Executes a exclusive LDR instruction for 8 bit value.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint8_t at (*ptr)
+ +
+
+ +
+
+ + + + + + + + +
#define __LDREXH( ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+
+

Executes a exclusive LDR instruction for 16 bit values.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint16_t at (*ptr)
+ +
+
+ +
+
+ + + + + + + + +
#define __LDREXW( ptr)   _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+
+

Executes a exclusive LDR instruction for 32 bit values.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint32_t at (*ptr)
+ +
+
+ +
+
+ + + + +
#define __PACKED_STRUCT   __packed struct
+
+ +
+
+ +
+
+ + + + +
#define __RBIT   __rbit
+
+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + +
#define __REV   __rev
+
+

Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + +
#define __ROR   __ror
+
+

Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value Reverse byte order (16 bit)
+

Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value Rotate Right in unsigned value (32 bit)
+
Parameters
+ + + +
[in]op1Value to rotate
[in]op2Number of Bits to rotate
+
+
+
Returns
Rotated value
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define __set_CP( cp,
 op1,
 Rt,
 CRn,
 CRm,
 op2 
)   do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define __set_CP64( cp,
 op1,
 Rt,
 CRm 
)
+
+ +
+
+ +
+
+ + + + +
#define __SSAT   __ssat
+
+

Saturates a signed value.

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to (1..32)
+
+
+
Returns
Saturated value
+ +
+
+ +
+
+ + + + +
#define __STATIC_FORCEINLINE   static __forceinline
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define __STREXB( value,
 ptr 
)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+
+

Executes a exclusive STR instruction for 8 bit values.

+
Parameters
+ + + +
[in]valueValue to store
[in]ptrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define __STREXH( value,
 ptr 
)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+
+

Executes a exclusive STR instruction for 16 bit values.

+
Parameters
+ + + +
[in]valueValue to store
[in]ptrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define __STREXW( value,
 ptr 
)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+
+

Executes a exclusive STR instruction for 32 bit values.

+
Parameters
+ + + +
[in]valueValue to store
[in]ptrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + +
#define __UNALIGNED_UINT16_READ( addr)   (*((const __packed uint16_t *)(addr)))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define __UNALIGNED_UINT16_WRITE( addr,
 val 
)   ((*((__packed uint16_t *)(addr))) = (val))
+
+ +
+
+ +
+
+ + + + + + + + +
#define __UNALIGNED_UINT32_READ( addr)   (*((const __packed uint32_t *)(addr)))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define __UNALIGNED_UINT32_WRITE( addr,
 val 
)   ((*((__packed uint32_t *)(addr))) = (val))
+
+ +
+
+ +
+
+ + + + +
#define __USAT   __usat
+
+

Saturates an unsigned value.

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to (0..31)
+
+
+
Returns
Saturated value
+ +
+
+ +
+
+ + + + +
#define CMSIS_DEPRECATED   __attribute__((deprecated))
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_mode (void )
+
+
Returns
Processor Mode
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM uint32_t __get_SP (void )
+
+
Returns
Stack Pointer
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM uint32_t __get_SP_usr (void )
+
+
Returns
USR/SYSStack Pointer
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM void __set_mode (uint32_t mode)
+
+
Parameters
+ + +
[in]modeMode value to set
+
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/cmsis__armcc_8txt.html b/docs/Core_A/html/cmsis__armcc_8txt.html new file mode 100644 index 0000000..5bf0b9b --- /dev/null +++ b/docs/Core_A/html/cmsis__armcc_8txt.html @@ -0,0 +1,159 @@ + + + + + +cmsis_armcc.txt File Reference +CMSIS-Core (Cortex-A): cmsis_armcc.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
cmsis_armcc.txt File Reference
+
+
+ +

CMSIS compiler specific macros, functions, instructions. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit) More...
 
uint16_t __REV16 (uint16_t value)
 Reverse byte order (16 bit) More...
 
int32_t __REVSH (int32_t value)
 Reverse byte order (16 bit) More...
 
uint32_t __ROR (uint32_t op1, uint32_t op2)
 Rotate Right in unsigned value (32 bit) More...
 
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value. More...
 
uint8_t __CLZ (uint32_t value)
 Count leading zeros. More...
 
+

Description

+
Version
V1.00
+
Date
22. Feb 2017
+
+
+ + + + diff --git a/docs/Core_A/html/cmsis__cp15_8h.html b/docs/Core_A/html/cmsis__cp15_8h.html new file mode 100644 index 0000000..4111115 --- /dev/null +++ b/docs/Core_A/html/cmsis__cp15_8h.html @@ -0,0 +1,494 @@ + + + + + +cmsis_cp15.h File Reference +CMSIS-Core (Cortex-A): cmsis_cp15.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
cmsis_cp15.h File Reference
+
+
+ +

CMSIS compiler specific macros, functions, instructions. +More...

+ + + + +

+Macros

#define __CMSIS_CP15_H
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_ACTLR (void)
 Get ACTLR. More...
 
__STATIC_FORCEINLINE void __set_ACTLR (uint32_t actlr)
 Set ACTLR. More...
 
__STATIC_FORCEINLINE uint32_t __get_CPACR (void)
 Get CPACR. More...
 
__STATIC_FORCEINLINE void __set_CPACR (uint32_t cpacr)
 Set CPACR. More...
 
__STATIC_FORCEINLINE uint32_t __get_DFSR (void)
 Get DFSR. More...
 
__STATIC_FORCEINLINE void __set_DFSR (uint32_t dfsr)
 Set DFSR. More...
 
__STATIC_FORCEINLINE uint32_t __get_IFSR (void)
 Get IFSR. More...
 
__STATIC_FORCEINLINE void __set_IFSR (uint32_t ifsr)
 Set IFSR. More...
 
__STATIC_FORCEINLINE uint32_t __get_ISR (void)
 Get ISR. More...
 
__STATIC_FORCEINLINE uint32_t __get_CBAR (void)
 Get CBAR. More...
 
__STATIC_FORCEINLINE uint32_t __get_TTBR0 (void)
 Get TTBR0. More...
 
__STATIC_FORCEINLINE void __set_TTBR0 (uint32_t ttbr0)
 Set TTBR0. More...
 
__STATIC_FORCEINLINE uint32_t __get_DACR (void)
 Get DACR. More...
 
__STATIC_FORCEINLINE void __set_DACR (uint32_t dacr)
 Set DACR. More...
 
__STATIC_FORCEINLINE void __set_SCTLR (uint32_t sctlr)
 Set SCTLR. More...
 
__STATIC_FORCEINLINE uint32_t __get_SCTLR (void)
 Get SCTLR. More...
 
__STATIC_FORCEINLINE void __set_ACTRL (uint32_t actrl)
 Set ACTRL. More...
 
__STATIC_FORCEINLINE uint32_t __get_ACTRL (void)
 Get ACTRL. More...
 
__STATIC_FORCEINLINE uint32_t __get_MPIDR (void)
 Get MPIDR. More...
 
__STATIC_FORCEINLINE uint32_t __get_VBAR (void)
 Get VBAR. More...
 
__STATIC_FORCEINLINE void __set_VBAR (uint32_t vbar)
 Set VBAR. More...
 
__STATIC_FORCEINLINE uint32_t __get_MVBAR (void)
 Get MVBAR. More...
 
__STATIC_FORCEINLINE void __set_MVBAR (uint32_t mvbar)
 Set MVBAR. More...
 
__STATIC_FORCEINLINE void __set_CNTFRQ (uint32_t value)
 Set CNTFRQ. More...
 
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ (void)
 Get CNTFRQ. More...
 
__STATIC_FORCEINLINE void __set_CNTP_TVAL (uint32_t value)
 Set CNTP_TVAL. More...
 
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL (void)
 Get CNTP_TVAL. More...
 
__STATIC_FORCEINLINE uint64_t __get_CNTPCT (void)
 Get CNTPCT. More...
 
__STATIC_FORCEINLINE void __set_CNTP_CVAL (uint64_t value)
 Set CNTP_CVAL. More...
 
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL (void)
 Get CNTP_CVAL. More...
 
__STATIC_FORCEINLINE void __set_CNTP_CTL (uint32_t value)
 Set CNTP_CTL. More...
 
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL (void)
 Get CNTP_CTL register. More...
 
__STATIC_FORCEINLINE void __set_TLBIALL (uint32_t value)
 Set TLBIALL. More...
 
__STATIC_FORCEINLINE void __set_BPIALL (uint32_t value)
 Set BPIALL. More...
 
__STATIC_FORCEINLINE void __set_ICIALLU (uint32_t value)
 Set ICIALLU. More...
 
__STATIC_FORCEINLINE void __set_DCCMVAC (uint32_t value)
 Set DCCMVAC. More...
 
__STATIC_FORCEINLINE void __set_DCIMVAC (uint32_t value)
 Set DCIMVAC. More...
 
__STATIC_FORCEINLINE void __set_DCCIMVAC (uint32_t value)
 Set DCCIMVAC. More...
 
__STATIC_FORCEINLINE void __set_CSSELR (uint32_t value)
 Set CSSELR. More...
 
__STATIC_FORCEINLINE uint32_t __get_CSSELR (void)
 Get CSSELR. More...
 
CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void 		__set_CCSIDR (uint32_t value)
 Set CCSIDR. More...
 
__STATIC_FORCEINLINE uint32_t __get_CCSIDR (void)
 Get CCSIDR. More...
 
__STATIC_FORCEINLINE uint32_t __get_CLIDR (void)
 Get CLIDR. More...
 
__STATIC_FORCEINLINE void __set_DCISW (uint32_t value)
 Set DCISW. More...
 
__STATIC_FORCEINLINE void __set_DCCSW (uint32_t value)
 Set DCCSW. More...
 
__STATIC_FORCEINLINE void __set_DCCISW (uint32_t value)
 Set DCCISW. More...
 
+

Description

+
Version
V1.0.1
+
Date
07. Sep 2017
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CMSIS_CP15_H
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE uint32_t __get_ACTRL (void )
+
+
Returns
Auxiliary Control Register value
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE uint32_t __get_CCSIDR (void )
+
+
Returns
CCSIDR Register value
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE uint32_t __get_CLIDR (void )
+
+
Returns
CLIDR Register value
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE uint32_t __get_CSSELR (void )
+
+
Returns
CSSELR Register value
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE void __set_ACTLR (uint32_t actlr)
+
+
Parameters
+ + +
[in]actlrAuxiliary Control value to set
+
+
+ +
+
+ +
+
+ + + + + + + + +
CMSIS_DEPRECATED __STATIC_FORCEINLINE void __set_CCSIDR (uint32_t value)
+
+
Deprecated:
CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE void __set_CNTP_CVAL (uint64_t value)
+
+

This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).

+
Parameters
+ + +
[in]valueCNTP_CVAL Register value to set
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE void __set_CSSELR (uint32_t value)
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE void __set_DCCISW (uint32_t value)
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE void __set_DCCSW (uint32_t value)
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE void __set_DCISW (uint32_t value)
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/coreMISRA_Exceptions_pg.html b/docs/Core_A/html/coreMISRA_Exceptions_pg.html new file mode 100644 index 0000000..0d712a3 --- /dev/null +++ b/docs/Core_A/html/coreMISRA_Exceptions_pg.html @@ -0,0 +1,131 @@ + + + + + +MISRA-C Deviations +CMSIS-Core (Cortex-A): MISRA-C Deviations + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
MISRA-C Deviations
+
+
+

CMSIS-Core (Cortex-A) uses the common coding rules for CMSIS components that are documented under Introduction.

+

CMSIS-Core (Cortex-A) violates the following MISRA-C:2004 rules:

+

TO BE EVALUATED

+
+
+ + + + diff --git a/docs/Core_A/html/core__ca_8h.html b/docs/Core_A/html/core__ca_8h.html new file mode 100644 index 0000000..ccb7454 --- /dev/null +++ b/docs/Core_A/html/core__ca_8h.html @@ -0,0 +1,2103 @@ + + + + + +core_ca.h File Reference +CMSIS-Core (Cortex-A): core_ca.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Enumerations | +Functions
+
+
core_ca.h File Reference
+
+
+ +

CMSIS Cortex-A Core Peripheral Access Layer Header File. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Structures

struct  CPSR_Type
 Bit field declaration for CPSR layout. More...
 
struct  SCTLR_Type
 Bit field declaration for SCTLR layout. More...
 
struct  ACTLR_Type
 Bit field declaration for ACTLR layout. More...
 
struct  CPACR_Type
 Bit field declaration for CPACR layout. More...
 
struct  DFSR_Type
 Bit field declaration for DFSR layout. More...
 
struct  IFSR_Type
 Bit field declaration for IFSR layout. More...
 
struct  ISR_Type
 Bit field declaration for ISR layout. More...
 
struct  L2C_310_TypeDef
 Union type to access the L2C_310 Cache Controller. More...
 
struct  GICDistributor_Type
 Structure type to access the Generic Interrupt Controller Distributor (GICD) More...
 
struct  GICInterface_Type
 Structure type to access the Generic Interrupt Controller Interface (GICC) More...
 
struct  Timer_Type
 Structure type to access the Private Timer. More...
 
union  CNTP_CTL_Type
 Physical Timer Control register. More...
 
struct  mmu_region_attributes_Type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define __CORE_CA_H_GENERIC
 
#define __CA_CMSIS_VERSION_MAIN   (1U)
 [31:16] CMSIS-Core(A) main version More...
 
#define __CA_CMSIS_VERSION_SUB   (1U)
 [15:0] CMSIS-Core(A) sub version More...
 
#define __CA_CMSIS_VERSION
 CMSIS-Core(A) version number. More...
 
#define __FPU_USED   0U
 
#define __CORE_CA_H_DEPENDANT
 
#define __FPU_PRESENT   0U
 
#define __GIC_PRESENT   1U
 
#define __TIM_PRESENT   1U
 
#define __I   volatile
 Defines 'read only' permissions. More...
 
#define __O   volatile
 Defines 'write only' permissions. More...
 
#define __IO   volatile
 Defines 'read / write' permissions. More...
 
#define __IM   volatile const
 Defines 'read only' structure member permissions. More...
 
#define __OM   volatile
 Defines 'write only' structure member permissions. More...
 
#define __IOM   volatile
 Defines 'read / write' structure member permissions. More...
 
#define RESERVED(N, T)   T RESERVED##N;
 
#define CPSR_N_Pos   31U
 CPSR: N Position. More...
 
#define CPSR_N_Msk   (1UL << CPSR_N_Pos)
 CPSR: N Mask. More...
 
#define CPSR_Z_Pos   30U
 CPSR: Z Position. More...
 
#define CPSR_Z_Msk   (1UL << CPSR_Z_Pos)
 CPSR: Z Mask. More...
 
#define CPSR_C_Pos   29U
 CPSR: C Position. More...
 
#define CPSR_C_Msk   (1UL << CPSR_C_Pos)
 CPSR: C Mask. More...
 
#define CPSR_V_Pos   28U
 CPSR: V Position. More...
 
#define CPSR_V_Msk   (1UL << CPSR_V_Pos)
 CPSR: V Mask. More...
 
#define CPSR_Q_Pos   27U
 CPSR: Q Position. More...
 
#define CPSR_Q_Msk   (1UL << CPSR_Q_Pos)
 CPSR: Q Mask. More...
 
#define CPSR_IT0_Pos   25U
 CPSR: IT0 Position. More...
 
#define CPSR_IT0_Msk   (3UL << CPSR_IT0_Pos)
 CPSR: IT0 Mask. More...
 
#define CPSR_J_Pos   24U
 CPSR: J Position. More...
 
#define CPSR_J_Msk   (1UL << CPSR_J_Pos)
 CPSR: J Mask. More...
 
#define CPSR_GE_Pos   16U
 CPSR: GE Position. More...
 
#define CPSR_GE_Msk   (0xFUL << CPSR_GE_Pos)
 CPSR: GE Mask. More...
 
#define CPSR_IT1_Pos   10U
 CPSR: IT1 Position. More...
 
#define CPSR_IT1_Msk   (0x3FUL << CPSR_IT1_Pos)
 CPSR: IT1 Mask. More...
 
#define CPSR_E_Pos   9U
 CPSR: E Position. More...
 
#define CPSR_E_Msk   (1UL << CPSR_E_Pos)
 CPSR: E Mask. More...
 
#define CPSR_A_Pos   8U
 CPSR: A Position. More...
 
#define CPSR_A_Msk   (1UL << CPSR_A_Pos)
 CPSR: A Mask. More...
 
#define CPSR_I_Pos   7U
 CPSR: I Position. More...
 
#define CPSR_I_Msk   (1UL << CPSR_I_Pos)
 CPSR: I Mask. More...
 
#define CPSR_F_Pos   6U
 CPSR: F Position. More...
 
#define CPSR_F_Msk   (1UL << CPSR_F_Pos)
 CPSR: F Mask. More...
 
#define CPSR_T_Pos   5U
 CPSR: T Position. More...
 
#define CPSR_T_Msk   (1UL << CPSR_T_Pos)
 CPSR: T Mask. More...
 
#define CPSR_M_Pos   0U
 CPSR: M Position. More...
 
#define CPSR_M_Msk   (0x1FUL << CPSR_M_Pos)
 CPSR: M Mask. More...
 
#define CPSR_M_USR   0x10U
 CPSR: M User mode (PL0) More...
 
#define CPSR_M_FIQ   0x11U
 CPSR: M Fast Interrupt mode (PL1) More...
 
#define CPSR_M_IRQ   0x12U
 CPSR: M Interrupt mode (PL1) More...
 
#define CPSR_M_SVC   0x13U
 CPSR: M Supervisor mode (PL1) More...
 
#define CPSR_M_MON   0x16U
 CPSR: M Monitor mode (PL1) More...
 
#define CPSR_M_ABT   0x17U
 CPSR: M Abort mode (PL1) More...
 
#define CPSR_M_HYP   0x1AU
 CPSR: M Hypervisor mode (PL2) More...
 
#define CPSR_M_UND   0x1BU
 CPSR: M Undefined mode (PL1) More...
 
#define CPSR_M_SYS   0x1FU
 CPSR: M System mode (PL1) More...
 
#define SCTLR_TE_Pos   30U
 SCTLR: TE Position. More...
 
#define SCTLR_TE_Msk   (1UL << SCTLR_TE_Pos)
 SCTLR: TE Mask. More...
 
#define SCTLR_AFE_Pos   29U
 SCTLR: AFE Position. More...
 
#define SCTLR_AFE_Msk   (1UL << SCTLR_AFE_Pos)
 SCTLR: AFE Mask. More...
 
#define SCTLR_TRE_Pos   28U
 SCTLR: TRE Position. More...
 
#define SCTLR_TRE_Msk   (1UL << SCTLR_TRE_Pos)
 SCTLR: TRE Mask. More...
 
#define SCTLR_NMFI_Pos   27U
 SCTLR: NMFI Position. More...
 
#define SCTLR_NMFI_Msk   (1UL << SCTLR_NMFI_Pos)
 SCTLR: NMFI Mask. More...
 
#define SCTLR_EE_Pos   25U
 SCTLR: EE Position. More...
 
#define SCTLR_EE_Msk   (1UL << SCTLR_EE_Pos)
 SCTLR: EE Mask. More...
 
#define SCTLR_VE_Pos   24U
 SCTLR: VE Position. More...
 
#define SCTLR_VE_Msk   (1UL << SCTLR_VE_Pos)
 SCTLR: VE Mask. More...
 
#define SCTLR_U_Pos   22U
 SCTLR: U Position. More...
 
#define SCTLR_U_Msk   (1UL << SCTLR_U_Pos)
 SCTLR: U Mask. More...
 
#define SCTLR_FI_Pos   21U
 SCTLR: FI Position. More...
 
#define SCTLR_FI_Msk   (1UL << SCTLR_FI_Pos)
 SCTLR: FI Mask. More...
 
#define SCTLR_UWXN_Pos   20U
 SCTLR: UWXN Position. More...
 
#define SCTLR_UWXN_Msk   (1UL << SCTLR_UWXN_Pos)
 SCTLR: UWXN Mask. More...
 
#define SCTLR_WXN_Pos   19U
 SCTLR: WXN Position. More...
 
#define SCTLR_WXN_Msk   (1UL << SCTLR_WXN_Pos)
 SCTLR: WXN Mask. More...
 
#define SCTLR_HA_Pos   17U
 SCTLR: HA Position. More...
 
#define SCTLR_HA_Msk   (1UL << SCTLR_HA_Pos)
 SCTLR: HA Mask. More...
 
#define SCTLR_RR_Pos   14U
 SCTLR: RR Position. More...
 
#define SCTLR_RR_Msk   (1UL << SCTLR_RR_Pos)
 SCTLR: RR Mask. More...
 
#define SCTLR_V_Pos   13U
 SCTLR: V Position. More...
 
#define SCTLR_V_Msk   (1UL << SCTLR_V_Pos)
 SCTLR: V Mask. More...
 
#define SCTLR_I_Pos   12U
 SCTLR: I Position. More...
 
#define SCTLR_I_Msk   (1UL << SCTLR_I_Pos)
 SCTLR: I Mask. More...
 
#define SCTLR_Z_Pos   11U
 SCTLR: Z Position. More...
 
#define SCTLR_Z_Msk   (1UL << SCTLR_Z_Pos)
 SCTLR: Z Mask. More...
 
#define SCTLR_SW_Pos   10U
 SCTLR: SW Position. More...
 
#define SCTLR_SW_Msk   (1UL << SCTLR_SW_Pos)
 SCTLR: SW Mask. More...
 
#define SCTLR_B_Pos   7U
 SCTLR: B Position. More...
 
#define SCTLR_B_Msk   (1UL << SCTLR_B_Pos)
 SCTLR: B Mask. More...
 
#define SCTLR_CP15BEN_Pos   5U
 SCTLR: CP15BEN Position. More...
 
#define SCTLR_CP15BEN_Msk   (1UL << SCTLR_CP15BEN_Pos)
 SCTLR: CP15BEN Mask. More...
 
#define SCTLR_C_Pos   2U
 SCTLR: C Position. More...
 
#define SCTLR_C_Msk   (1UL << SCTLR_C_Pos)
 SCTLR: C Mask. More...
 
#define SCTLR_A_Pos   1U
 SCTLR: A Position. More...
 
#define SCTLR_A_Msk   (1UL << SCTLR_A_Pos)
 SCTLR: A Mask. More...
 
#define SCTLR_M_Pos   0U
 SCTLR: M Position. More...
 
#define SCTLR_M_Msk   (1UL << SCTLR_M_Pos)
 SCTLR: M Mask. More...
 
#define ACTLR_DDI_Pos   28U
 ACTLR: DDI Position. More...
 
#define ACTLR_DDI_Msk   (1UL << ACTLR_DDI_Pos)
 ACTLR: DDI Mask. More...
 
#define ACTLR_DBDI_Pos   28U
 ACTLR: DBDI Position. More...
 
#define ACTLR_DBDI_Msk   (1UL << ACTLR_DBDI_Pos)
 ACTLR: DBDI Mask. More...
 
#define ACTLR_BTDIS_Pos   18U
 ACTLR: BTDIS Position. More...
 
#define ACTLR_BTDIS_Msk   (1UL << ACTLR_BTDIS_Pos)
 ACTLR: BTDIS Mask. More...
 
#define ACTLR_RSDIS_Pos   17U
 ACTLR: RSDIS Position. More...
 
#define ACTLR_RSDIS_Msk   (1UL << ACTLR_RSDIS_Pos)
 ACTLR: RSDIS Mask. More...
 
#define ACTLR_BP_Pos   15U
 ACTLR: BP Position. More...
 
#define ACTLR_BP_Msk   (3UL << ACTLR_BP_Pos)
 ACTLR: BP Mask. More...
 
#define ACTLR_DDVM_Pos   15U
 ACTLR: DDVM Position. More...
 
#define ACTLR_DDVM_Msk   (1UL << ACTLR_DDVM_Pos)
 ACTLR: DDVM Mask. More...
 
#define ACTLR_L1PCTL_Pos   13U
 ACTLR: L1PCTL Position. More...
 
#define ACTLR_L1PCTL_Msk   (3UL << ACTLR_L1PCTL_Pos)
 ACTLR: L1PCTL Mask. More...
 
#define ACTLR_RADIS_Pos   12U
 ACTLR: RADIS Position. More...
 
#define ACTLR_RADIS_Msk   (1UL << ACTLR_RADIS_Pos)
 ACTLR: RADIS Mask. More...
 
#define ACTLR_L1RADIS_Pos   12U
 ACTLR: L1RADIS Position. More...
 
#define ACTLR_L1RADIS_Msk   (1UL << ACTLR_L1RADIS_Pos)
 ACTLR: L1RADIS Mask. More...
 
#define ACTLR_DWBST_Pos   11U
 ACTLR: DWBST Position. More...
 
#define ACTLR_DWBST_Msk   (1UL << ACTLR_DWBST_Pos)
 ACTLR: DWBST Mask. More...
 
#define ACTLR_L2RADIS_Pos   11U
 ACTLR: L2RADIS Position. More...
 
#define ACTLR_L2RADIS_Msk   (1UL << ACTLR_L2RADIS_Pos)
 ACTLR: L2RADIS Mask. More...
 
#define ACTLR_DODMBS_Pos   10U
 ACTLR: DODMBS Position. More...
 
#define ACTLR_DODMBS_Msk   (1UL << ACTLR_DODMBS_Pos)
 ACTLR: DODMBS Mask. More...
 
#define ACTLR_PARITY_Pos   9U
 ACTLR: PARITY Position. More...
 
#define ACTLR_PARITY_Msk   (1UL << ACTLR_PARITY_Pos)
 ACTLR: PARITY Mask. More...
 
#define ACTLR_AOW_Pos   8U
 ACTLR: AOW Position. More...
 
#define ACTLR_AOW_Msk   (1UL << ACTLR_AOW_Pos)
 ACTLR: AOW Mask. More...
 
#define ACTLR_EXCL_Pos   7U
 ACTLR: EXCL Position. More...
 
#define ACTLR_EXCL_Msk   (1UL << ACTLR_EXCL_Pos)
 ACTLR: EXCL Mask. More...
 
#define ACTLR_SMP_Pos   6U
 ACTLR: SMP Position. More...
 
#define ACTLR_SMP_Msk   (1UL << ACTLR_SMP_Pos)
 ACTLR: SMP Mask. More...
 
#define ACTLR_WFLZM_Pos   3U
 ACTLR: WFLZM Position. More...
 
#define ACTLR_WFLZM_Msk   (1UL << ACTLR_WFLZM_Pos)
 ACTLR: WFLZM Mask. More...
 
#define ACTLR_L1PE_Pos   2U
 ACTLR: L1PE Position. More...
 
#define ACTLR_L1PE_Msk   (1UL << ACTLR_L1PE_Pos)
 ACTLR: L1PE Mask. More...
 
#define ACTLR_FW_Pos   0U
 ACTLR: FW Position. More...
 
#define ACTLR_FW_Msk   (1UL << ACTLR_FW_Pos)
 ACTLR: FW Mask. More...
 
#define CPACR_ASEDIS_Pos   31U
 CPACR: ASEDIS Position. More...
 
#define CPACR_ASEDIS_Msk   (1UL << CPACR_ASEDIS_Pos)
 CPACR: ASEDIS Mask. More...
 
#define CPACR_D32DIS_Pos   30U
 CPACR: D32DIS Position. More...
 
#define CPACR_D32DIS_Msk   (1UL << CPACR_D32DIS_Pos)
 CPACR: D32DIS Mask. More...
 
#define CPACR_TRCDIS_Pos   28U
 CPACR: D32DIS Position. More...
 
#define CPACR_TRCDIS_Msk   (1UL << CPACR_D32DIS_Pos)
 CPACR: D32DIS Mask. More...
 
#define CPACR_CP_Pos_(n)   (n*2U)
 CPACR: CPn Position. More...
 
#define CPACR_CP_Msk_(n)   (3UL << CPACR_CP_Pos_(n))
 CPACR: CPn Mask. More...
 
#define CPACR_CP_NA   0U
 CPACR CPn field: Access denied. More...
 
#define CPACR_CP_PL1   1U
 CPACR CPn field: Accessible from PL1 only. More...
 
#define CPACR_CP_FA   3U
 CPACR CPn field: Full access. More...
 
#define DFSR_CM_Pos   13U
 DFSR: CM Position. More...
 
#define DFSR_CM_Msk   (1UL << DFSR_CM_Pos)
 DFSR: CM Mask. More...
 
#define DFSR_Ext_Pos   12U
 DFSR: Ext Position. More...
 
#define DFSR_Ext_Msk   (1UL << DFSR_Ext_Pos)
 DFSR: Ext Mask. More...
 
#define DFSR_WnR_Pos   11U
 DFSR: WnR Position. More...
 
#define DFSR_WnR_Msk   (1UL << DFSR_WnR_Pos)
 DFSR: WnR Mask. More...
 
#define DFSR_FS1_Pos   10U
 DFSR: FS1 Position. More...
 
#define DFSR_FS1_Msk   (1UL << DFSR_FS1_Pos)
 DFSR: FS1 Mask. More...
 
#define DFSR_LPAE_Pos   9U
 DFSR: LPAE Position. More...
 
#define DFSR_LPAE_Msk   (1UL << DFSR_LPAE_Pos)
 DFSR: LPAE Mask. More...
 
#define DFSR_Domain_Pos   4U
 DFSR: Domain Position. More...
 
#define DFSR_Domain_Msk   (0xFUL << DFSR_Domain_Pos)
 DFSR: Domain Mask. More...
 
#define DFSR_FS0_Pos   0U
 DFSR: FS0 Position. More...
 
#define DFSR_FS0_Msk   (0xFUL << DFSR_FS0_Pos)
 DFSR: FS0 Mask. More...
 
#define DFSR_STATUS_Pos   0U
 DFSR: STATUS Position. More...
 
#define DFSR_STATUS_Msk   (0x3FUL << DFSR_STATUS_Pos)
 DFSR: STATUS Mask. More...
 
#define IFSR_ExT_Pos   12U
 IFSR: ExT Position. More...
 
#define IFSR_ExT_Msk   (1UL << IFSR_ExT_Pos)
 IFSR: ExT Mask. More...
 
#define IFSR_FS1_Pos   10U
 IFSR: FS1 Position. More...
 
#define IFSR_FS1_Msk   (1UL << IFSR_FS1_Pos)
 IFSR: FS1 Mask. More...
 
#define IFSR_LPAE_Pos   9U
 IFSR: LPAE Position. More...
 
#define IFSR_LPAE_Msk   (0x1UL << IFSR_LPAE_Pos)
 IFSR: LPAE Mask. More...
 
#define IFSR_FS0_Pos   0U
 IFSR: FS0 Position. More...
 
#define IFSR_FS0_Msk   (0xFUL << IFSR_FS0_Pos)
 IFSR: FS0 Mask. More...
 
#define IFSR_STATUS_Pos   0U
 IFSR: STATUS Position. More...
 
#define IFSR_STATUS_Msk   (0x3FUL << IFSR_STATUS_Pos)
 IFSR: STATUS Mask. More...
 
#define ISR_A_Pos   13U
 ISR: A Position. More...
 
#define ISR_A_Msk   (1UL << ISR_A_Pos)
 ISR: A Mask. More...
 
#define ISR_I_Pos   12U
 ISR: I Position. More...
 
#define ISR_I_Msk   (1UL << ISR_I_Pos)
 ISR: I Mask. More...
 
#define ISR_F_Pos   11U
 ISR: F Position. More...
 
#define ISR_F_Msk   (1UL << ISR_F_Pos)
 ISR: F Mask. More...
 
#define DACR_D_Pos_(n)   (2U*n)
 DACR: Dn Position. More...
 
#define DACR_D_Msk_(n)   (3UL << DACR_D_Pos_(n))
 DACR: Dn Mask. More...
 
#define DACR_Dn_NOACCESS   0U
 DACR Dn field: No access. More...
 
#define DACR_Dn_CLIENT   1U
 DACR Dn field: Client. More...
 
#define DACR_Dn_MANAGER   3U
 DACR Dn field: Manager. More...
 
#define _VAL2FLD(field, value)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 Mask and shift a bit field value for use in a register bit range. More...
 
#define _FLD2VAL(field, value)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 Mask and shift a register value to extract a bit filed value. More...
 
#define L2C_310   ((L2C_310_TypeDef *)L2C_310_BASE)
 L2C_310 register set access pointer. More...
 
#define GICDistributor   ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )
 GIC Distributor register set access pointer. More...
 
#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE )
 GIC Interface register set access pointer. More...
 
#define PTIM   ((Timer_Type *) TIMER_BASE )
 Timer register struct. More...
 
#define GIC_SetSecurity   GIC_SetGroup
 
#define GIC_GetSecurity   GIC_GetGroup
 
#define SECTION_DESCRIPTOR   (0x2)
 
#define SECTION_MASK   (0xFFFFFFFC)
 
#define SECTION_TEXCB_MASK   (0xFFFF8FF3)
 
#define SECTION_B_SHIFT   (2)
 
#define SECTION_C_SHIFT   (3)
 
#define SECTION_TEX0_SHIFT   (12)
 
#define SECTION_TEX1_SHIFT   (13)
 
#define SECTION_TEX2_SHIFT   (14)
 
#define SECTION_XN_MASK   (0xFFFFFFEF)
 
#define SECTION_XN_SHIFT   (4)
 
#define SECTION_DOMAIN_MASK   (0xFFFFFE1F)
 
#define SECTION_DOMAIN_SHIFT   (5)
 
#define SECTION_P_MASK   (0xFFFFFDFF)
 
#define SECTION_P_SHIFT   (9)
 
#define SECTION_AP_MASK   (0xFFFF73FF)
 
#define SECTION_AP_SHIFT   (10)
 
#define SECTION_AP2_SHIFT   (15)
 
#define SECTION_S_MASK   (0xFFFEFFFF)
 
#define SECTION_S_SHIFT   (16)
 
#define SECTION_NG_MASK   (0xFFFDFFFF)
 
#define SECTION_NG_SHIFT   (17)
 
#define SECTION_NS_MASK   (0xFFF7FFFF)
 
#define SECTION_NS_SHIFT   (19)
 
#define PAGE_L1_DESCRIPTOR   (0x1)
 
#define PAGE_L1_MASK   (0xFFFFFFFC)
 
#define PAGE_L2_4K_DESC   (0x2)
 
#define PAGE_L2_4K_MASK   (0xFFFFFFFD)
 
#define PAGE_L2_64K_DESC   (0x1)
 
#define PAGE_L2_64K_MASK   (0xFFFFFFFC)
 
#define PAGE_4K_TEXCB_MASK   (0xFFFFFE33)
 
#define PAGE_4K_B_SHIFT   (2)
 
#define PAGE_4K_C_SHIFT   (3)
 
#define PAGE_4K_TEX0_SHIFT   (6)
 
#define PAGE_4K_TEX1_SHIFT   (7)
 
#define PAGE_4K_TEX2_SHIFT   (8)
 
#define PAGE_64K_TEXCB_MASK   (0xFFFF8FF3)
 
#define PAGE_64K_B_SHIFT   (2)
 
#define PAGE_64K_C_SHIFT   (3)
 
#define PAGE_64K_TEX0_SHIFT   (12)
 
#define PAGE_64K_TEX1_SHIFT   (13)
 
#define PAGE_64K_TEX2_SHIFT   (14)
 
#define PAGE_TEXCB_MASK   (0xFFFF8FF3)
 
#define PAGE_B_SHIFT   (2)
 
#define PAGE_C_SHIFT   (3)
 
#define PAGE_TEX_SHIFT   (12)
 
#define PAGE_XN_4K_MASK   (0xFFFFFFFE)
 
#define PAGE_XN_4K_SHIFT   (0)
 
#define PAGE_XN_64K_MASK   (0xFFFF7FFF)
 
#define PAGE_XN_64K_SHIFT   (15)
 
#define PAGE_DOMAIN_MASK   (0xFFFFFE1F)
 
#define PAGE_DOMAIN_SHIFT   (5)
 
#define PAGE_P_MASK   (0xFFFFFDFF)
 
#define PAGE_P_SHIFT   (9)
 
#define PAGE_AP_MASK   (0xFFFFFDCF)
 
#define PAGE_AP_SHIFT   (4)
 
#define PAGE_AP2_SHIFT   (9)
 
#define PAGE_S_MASK   (0xFFFFFBFF)
 
#define PAGE_S_SHIFT   (10)
 
#define PAGE_NG_MASK   (0xFFFFF7FF)
 
#define PAGE_NG_SHIFT   (11)
 
#define PAGE_NS_MASK   (0xFFFFFFF7)
 
#define PAGE_NS_SHIFT   (3)
 
#define OFFSET_1M   (0x00100000)
 
#define OFFSET_64K   (0x00010000)
 
#define OFFSET_4K   (0x00001000)
 
#define DESCRIPTOR_FAULT   (0x00000000)
 
#define section_normal(descriptor_l1, region)
 
#define section_normal_nc(descriptor_l1, region)
 
#define section_normal_cod(descriptor_l1, region)
 
#define section_normal_ro(descriptor_l1, region)
 
#define section_normal_rw(descriptor_l1, region)
 
#define section_so(descriptor_l1, region)
 
#define section_device_ro(descriptor_l1, region)
 
#define section_device_rw(descriptor_l1, region)
 
#define page4k_device_rw(descriptor_l1, descriptor_l2, region)
 
#define page64k_device_rw(descriptor_l1, descriptor_l2, region)
 
+ + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  mmu_region_size_Type {
+  SECTION, +
+  PAGE_4k, +
+  PAGE_64k +
+ }
 
enum  mmu_memory_Type {
+  NORMAL, +
+  DEVICE, +
+  SHARED_DEVICE, +
+  NON_SHARED_DEVICE, +
+  STRONGLY_ORDERED +
+ }
 
enum  mmu_cacheability_Type {
+  NON_CACHEABLE, +
+  WB_WA, +
+  WT, +
+  WB_NO_WA +
+ }
 
enum  mmu_ecc_check_Type {
+  ECC_DISABLED, +
+  ECC_ENABLED +
+ }
 
enum  mmu_execute_Type {
+  EXECUTE, +
+  NON_EXECUTE +
+ }
 
enum  mmu_global_Type {
+  GLOBAL, +
+  NON_GLOBAL +
+ }
 
enum  mmu_shared_Type {
+  NON_SHARED, +
+  SHARED +
+ }
 
enum  mmu_secure_Type {
+  SECURE, +
+  NON_SECURE +
+ }
 
enum  mmu_access_Type {
+  NO_ACCESS, +
+  RW, +
+  READ +
+ }
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_FORCEINLINE void L1C_EnableCaches (void)
 Enable Caches by setting I and C bits in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_DisableCaches (void)
 Disable Caches by clearing I and C bits in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_EnableBTAC (void)
 Enable Branch Prediction by setting Z bit in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_DisableBTAC (void)
 Disable Branch Prediction by clearing Z bit in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateBTAC (void)
 Invalidate entire branch predictor array. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateICacheAll (void)
 Invalidate the whole instruction cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanDCacheMVA (void *va)
 Clean data cache line by address. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA (void *va)
 Invalidate data cache line by address. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA (void *va)
 Clean and Invalidate data cache by address. More...
 
__STATIC_FORCEINLINE uint8_t __log2_up (uint32_t n)
 Calculate log2 rounded up. More...
 
__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay (uint32_t level, uint32_t maint)
 Apply cache maintenance to given cache level. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateCache (uint32_t op)
 Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. More...
 
CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void 		__L1C_CleanInvalidateCache (uint32_t op)
 Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll (void)
 Invalidate the whole data cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanDCacheAll (void)
 Clean the whole data cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll (void)
 Clean and invalidate the whole data cache. More...
 
__STATIC_INLINE void L2C_Sync (void)
 Cache Sync operation by writing CACHE_SYNC register. More...
 
__STATIC_INLINE int L2C_GetID (void)
 Read cache controller cache ID from CACHE_ID register. More...
 
__STATIC_INLINE int L2C_GetType (void)
 Read cache controller cache type from CACHE_TYPE register. More...
 
__STATIC_INLINE void L2C_InvAllByWay (void)
 Invalidate all cache by way. More...
 
__STATIC_INLINE void L2C_CleanInvAllByWay (void)
 Clean and Invalidate all cache by way. More...
 
__STATIC_INLINE void L2C_Enable (void)
 Enable Level 2 Cache. More...
 
__STATIC_INLINE void L2C_Disable (void)
 Disable Level 2 Cache. More...
 
__STATIC_INLINE void L2C_InvPa (void *pa)
 Invalidate cache by physical address. More...
 
__STATIC_INLINE void L2C_CleanPa (void *pa)
 Clean cache by physical address. More...
 
__STATIC_INLINE void L2C_CleanInvPa (void *pa)
 Clean and invalidate cache by physical address. More...
 
__STATIC_INLINE void GIC_EnableDistributor (void)
 Enable the interrupt distributor using the GIC's CTLR register. More...
 
__STATIC_INLINE void GIC_DisableDistributor (void)
 Disable the interrupt distributor using the GIC's CTLR register. More...
 
__STATIC_INLINE uint32_t GIC_DistributorInfo (void)
 Read the GIC's TYPER register. More...
 
__STATIC_INLINE uint32_t GIC_DistributorImplementer (void)
 Reads the GIC's IIDR register. More...
 
__STATIC_INLINE void GIC_SetTarget (IRQn_Type IRQn, uint32_t cpu_target)
 Sets the GIC's ITARGETSR register for the given interrupt. More...
 
__STATIC_INLINE uint32_t GIC_GetTarget (IRQn_Type IRQn)
 Read the GIC's ITARGETSR register. More...
 
__STATIC_INLINE void GIC_EnableInterface (void)
 Enable the CPU's interrupt interface. More...
 
__STATIC_INLINE void GIC_DisableInterface (void)
 Disable the CPU's interrupt interface. More...
 
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending (void)
 Read the CPU's IAR register. More...
 
__STATIC_INLINE void GIC_EndInterrupt (IRQn_Type IRQn)
 Writes the given interrupt number to the CPU's EOIR register. More...
 
__STATIC_INLINE void GIC_EnableIRQ (IRQn_Type IRQn)
 Enables the given interrupt using GIC's ISENABLER register. More...
 
__STATIC_INLINE uint32_t GIC_GetEnableIRQ (IRQn_Type IRQn)
 Get interrupt enable status using GIC's ISENABLER register. More...
 
__STATIC_INLINE void GIC_DisableIRQ (IRQn_Type IRQn)
 Disables the given interrupt using GIC's ICENABLER register. More...
 
__STATIC_INLINE uint32_t GIC_GetPendingIRQ (IRQn_Type IRQn)
 Get interrupt pending status from GIC's ISPENDR register. More...
 
__STATIC_INLINE void GIC_SetPendingIRQ (IRQn_Type IRQn)
 Sets the given interrupt as pending using GIC's ISPENDR register. More...
 
__STATIC_INLINE void GIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clears the given interrupt from being pending using GIC's ICPENDR register. More...
 
__STATIC_INLINE void GIC_SetConfiguration (IRQn_Type IRQn, uint32_t int_config)
 Sets the interrupt configuration using GIC's ICFGR register. More...
 
__STATIC_INLINE uint32_t GIC_GetConfiguration (IRQn_Type IRQn)
 Get the interrupt configuration from the GIC's ICFGR register. More...
 
__STATIC_INLINE void GIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for the given interrupt in the GIC's IPRIORITYR register. More...
 
__STATIC_INLINE uint32_t GIC_GetPriority (IRQn_Type IRQn)
 Read the current interrupt priority from GIC's IPRIORITYR register. More...
 
__STATIC_INLINE void GIC_SetInterfacePriorityMask (uint32_t priority)
 Set the interrupt priority mask using CPU's PMR register. More...
 
__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask (void)
 Read the current interrupt priority mask from CPU's PMR register. More...
 
__STATIC_INLINE void GIC_SetBinaryPoint (uint32_t binary_point)
 Configures the group priority and subpriority split point using CPU's BPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetBinaryPoint (void)
 Read the current group priority and subpriority split point from CPU's BPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetIRQStatus (IRQn_Type IRQn)
 Get the status for a given interrupt. More...
 
__STATIC_INLINE void GIC_SendSGI (IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
 Generate a software interrupt using GIC's SGIR register. More...
 
__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ (void)
 Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. More...
 
__STATIC_INLINE uint32_t GIC_GetInterfaceId (void)
 Provides information about the implementer and revision of the CPU interface. More...
 
__STATIC_INLINE void GIC_SetGroup (IRQn_Type IRQn, uint32_t group)
 Set the interrupt group from the GIC's IGROUPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetGroup (IRQn_Type IRQn)
 Get the interrupt group from the GIC's IGROUPR register. More...
 
__STATIC_INLINE void GIC_DistInit (void)
 Initialize the interrupt distributor. More...
 
__STATIC_INLINE void GIC_CPUInterfaceInit (void)
 Initialize the CPU's interrupt interface. More...
 
__STATIC_INLINE void GIC_Enable (void)
 Initialize and enable the GIC. More...
 
__STATIC_INLINE void PL1_SetCounterFrequency (uint32_t value)
 Configures the frequency the timer shall run at. More...
 
__STATIC_INLINE void PL1_SetLoadValue (uint32_t value)
 Sets the reset value of the timer. More...
 
__STATIC_INLINE uint32_t PL1_GetCurrentValue (void)
 Get the current counter value. More...
 
__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue (void)
 Get the current physical counter value. More...
 
__STATIC_INLINE void PL1_SetPhysicalCompareValue (uint64_t value)
 Set the physical compare value. More...
 
__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue (void)
 Get the physical compare value. More...
 
__STATIC_INLINE void PL1_SetControl (uint32_t value)
 Configure the timer by setting the control value. More...
 
__STATIC_INLINE uint32_t PL1_GetControl (void)
 Get the control value. More...
 
__STATIC_INLINE void PTIM_SetLoadValue (uint32_t value)
 Set the load value to timers LOAD register. More...
 
__STATIC_INLINE uint32_t PTIM_GetLoadValue (void)
 Get the load value from timers LOAD register. More...
 
__STATIC_INLINE void PTIM_SetCurrentValue (uint32_t value)
 Set current counter value from its COUNTER register. More...
 
__STATIC_INLINE uint32_t PTIM_GetCurrentValue (void)
 Get current counter value from timers COUNTER register. More...
 
__STATIC_INLINE void PTIM_SetControl (uint32_t value)
 Configure the timer using its CONTROL register. More...
 
__STATIC_INLINE uint32_t PTIM_GetControl (void)
 
__STATIC_INLINE uint32_t PTIM_GetEventFlag (void)
 
__STATIC_INLINE void PTIM_ClearEventFlag (void)
 
__STATIC_INLINE int MMU_XNSection (uint32_t *descriptor_l1, mmu_execute_Type xn)
 Set section execution-never attribute. More...
 
__STATIC_INLINE int MMU_DomainSection (uint32_t *descriptor_l1, uint8_t domain)
 Set section domain. More...
 
__STATIC_INLINE int MMU_PSection (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 Set section parity check. More...
 
__STATIC_INLINE int MMU_APSection (uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
 Set section access privileges. More...
 
__STATIC_INLINE int MMU_SharedSection (uint32_t *descriptor_l1, mmu_shared_Type s_bit)
 Set section shareability. More...
 
__STATIC_INLINE int MMU_GlobalSection (uint32_t *descriptor_l1, mmu_global_Type g_bit)
 Set section Global attribute. More...
 
__STATIC_INLINE int MMU_SecureSection (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 Set section Security attribute. More...
 
__STATIC_INLINE int MMU_XNPage (uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
 Set 4k/64k page execution-never attribute. More...
 
__STATIC_INLINE int MMU_DomainPage (uint32_t *descriptor_l1, uint8_t domain)
 Set 4k/64k page domain. More...
 
__STATIC_INLINE int MMU_PPage (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 Set 4k/64k page parity check. More...
 
__STATIC_INLINE int MMU_APPage (uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
 Set 4k/64k page access privileges. More...
 
__STATIC_INLINE int MMU_SharedPage (uint32_t *descriptor_l2, mmu_shared_Type s_bit)
 Set 4k/64k page shareability. More...
 
__STATIC_INLINE int MMU_GlobalPage (uint32_t *descriptor_l2, mmu_global_Type g_bit)
 Set 4k/64k page Global attribute. More...
 
__STATIC_INLINE int MMU_SecurePage (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 Set 4k/64k page Security attribute. More...
 
__STATIC_INLINE int MMU_MemorySection (uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
 Set Section memory attributes. More...
 
__STATIC_INLINE int MMU_MemoryPage (uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
 Set 4k/64k page memory attributes. More...
 
__STATIC_INLINE int MMU_GetSectionDescriptor (uint32_t *descriptor, mmu_region_attributes_Type reg)
 Create a L1 section descriptor. More...
 
__STATIC_INLINE int MMU_GetPageDescriptor (uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
 Create a L1 and L2 4k/64k page descriptor. More...
 
__STATIC_INLINE void MMU_TTSection (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
 Create a 1MB Section. More...
 
__STATIC_INLINE void MMU_TTPage4k (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)
 Create a 4k page entry. More...
 
__STATIC_INLINE void MMU_TTPage64k (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)
 Create a 64k page entry. More...
 
__STATIC_INLINE void MMU_Enable (void)
 Enable MMU. More...
 
__STATIC_INLINE void MMU_Disable (void)
 Disable MMU. More...
 
__STATIC_INLINE void MMU_InvalidateTLB (void)
 Invalidate entire unified TLB. More...
 
+

Description

+
Version
V1.0.1
+
Date
07. May 2018
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CORE_CA_H_DEPENDANT
+
+ +
+
+ +
+
+ + + + +
#define __CORE_CA_H_GENERIC
+
+ +
+
+ +
+
+ + + + +
#define __FPU_PRESENT   0U
+
+ +
+
+ +
+
+ + + + +
#define __FPU_USED   0U
+
+ +
+
+ +
+
+ + + + +
#define __GIC_PRESENT   1U
+
+ +
+
+ +
+
+ + + + +
#define __I   volatile
+
+ +
+
+ +
+
+ + + + +
#define __IM   volatile const
+
+ +
+
+ +
+
+ + + + +
#define __IO   volatile
+
+ +
+
+ +
+
+ + + + +
#define __IOM   volatile
+
+ +
+
+ +
+
+ + + + +
#define __O   volatile
+
+ +
+
+ +
+
+ + + + +
#define __OM   volatile
+
+ +
+
+ +
+
+ + + + +
#define __TIM_PRESENT   1U
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _FLD2VAL( field,
 value 
)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+
Parameters
+ + + +
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
+
+
+
Returns
Masked and shifted bit field value.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _VAL2FLD( field,
 value 
)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+
Parameters
+ + + +
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
+
+
+
Returns
Masked and shifted value.
+ +
+
+ +
+
+ + + + +
#define GIC_GetSecurity   GIC_GetGroup
+
+ +
+
+ +
+
+ + + + +
#define GIC_SetSecurity   GIC_SetGroup
+
+ +
+
+ +
+
+ + + + +
#define PAGE_4K_TEXCB_MASK   (0xFFFFFE33)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_64K_TEXCB_MASK   (0xFFFF8FF3)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_AP_MASK   (0xFFFFFDCF)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_DOMAIN_MASK   (0xFFFFFE1F)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_L1_MASK   (0xFFFFFFFC)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_L2_4K_MASK   (0xFFFFFFFD)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_L2_64K_MASK   (0xFFFFFFFC)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_NG_MASK   (0xFFFFF7FF)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_NS_MASK   (0xFFFFFFF7)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_P_MASK   (0xFFFFFDFF)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_S_MASK   (0xFFFFFBFF)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_TEXCB_MASK   (0xFFFF8FF3)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_XN_4K_MASK   (0xFFFFFFFE)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_XN_64K_MASK   (0xFFFF7FFF)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define RESERVED( N,
 T 
)   T RESERVED##N;
+
+ +
+
+ +
+
+ + + + +
#define SECTION_AP_MASK   (0xFFFF73FF)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_DOMAIN_MASK   (0xFFFFFE1F)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_MASK   (0xFFFFFFFC)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_NG_MASK   (0xFFFDFFFF)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_normal_nc( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_NS_MASK   (0xFFF7FFFF)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_P_MASK   (0xFFFFFDFF)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_S_MASK   (0xFFFEFFFF)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_TEXCB_MASK   (0xFFFF8FF3)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_XN_MASK   (0xFFFFFFEF)
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay (uint32_t level,
uint32_t maint 
)
+
+
Parameters
+ + + +
[in]levelcache level to be maintained
[in]maint0 - invalidate, 1 - clean, otherwise - invalidate and clean
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_FORCEINLINE uint8_t __log2_up (uint32_t n)
+
+
    +
  • log(0) => 0
    • +
  • log(1) => 0
    • +
  • log(2) => 1
    • +
  • log(3) => 2
    • +
  • log(4) => 2
    • +
  • log(5) => 3 : :
    • +
  • log(16) => 4
    • +
  • log(32) => 5 : :
    Parameters
    + + +
    [in]ninput value parameter
    +
    +
    +
    Returns
    log2(n)
    +
    • +
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetConfiguration (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnInterrupt to acquire the configuration for.
+
+
+
Returns
Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetEnableIRQ (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be queried.
+
+
+
Returns
0 - interrupt is not enabled, 1 - interrupt is enabled.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetGroup (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be queried.
+
+
+
Returns
0 - Group 0, 1 - Group 1
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetPendingIRQ (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be queried.
+
+
+
Returns
0 - interrupt is not pending, 1 - interrupt is pendig.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void GIC_SetConfiguration (IRQn_Type IRQn,
uint32_t int_config 
)
+
+
Parameters
+ + + +
[in]IRQnThe interrupt to be configured.
[in]int_configInt_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void GIC_SetGroup (IRQn_Type IRQn,
uint32_t group 
)
+
+
Parameters
+ + + +
[in]IRQnThe interrupt to be queried.
[in]groupInterrupt group number: 0 - Group 0, 1 - Group 1
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t PTIM_GetEventFlag (void )
+
+

ref Timer_Type::CONTROL Get the event flag in timers ISR register.

+
Returns
0 - flag is not set, 1- flag is set
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PTIM_SetCurrentValue (uint32_t value)
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/core__ca_8txt.html b/docs/Core_A/html/core__ca_8txt.html new file mode 100644 index 0000000..5b92acf --- /dev/null +++ b/docs/Core_A/html/core__ca_8txt.html @@ -0,0 +1,144 @@ + + + + + +core_ca.txt File Reference +CMSIS-Core (Cortex-A): core_ca.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
core_ca.txt File Reference
+
+
+ +

CMSIS Cortex-A Core Peripheral Access Layer Header File. +More...

+ + + + + + + + +

+Macros

#define _VAL2FLD(field, value)
 Mask and shift a bit field value for assigning the result to a peripheral register. More...
 
#define _FLD2VAL(field, value)
 Extract from a peripheral register value the a bit field value. More...
 
+
+
+ + + + diff --git a/docs/Core_A/html/deprecated.html b/docs/Core_A/html/deprecated.html new file mode 100644 index 0000000..756826d --- /dev/null +++ b/docs/Core_A/html/deprecated.html @@ -0,0 +1,134 @@ + + + + + +Deprecated List +CMSIS-Core (Cortex-A): Deprecated List + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Deprecated List
+
+
+
+
Global __L1C_CleanInvalidateCache (uint32_t op)
+
Use generic L1C_CleanInvalidateCache instead.
+
Global __set_CCSIDR (uint32_t value)
+
CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
+
+
+
+ + + + diff --git a/docs/Core_A/html/device_h_pg.html b/docs/Core_A/html/device_h_pg.html new file mode 100644 index 0000000..df90fa6 --- /dev/null +++ b/docs/Core_A/html/device_h_pg.html @@ -0,0 +1,481 @@ + + + + + +Device Header File \<device.h> +CMSIS-Core (Cortex-A): Device Header File \<device.h> + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Device Header File <device.h>
+
+
+

The Device Header File <device.h> contains the following sections that are device specific:

+
    +
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • +
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • +
  • Device Peripheral Access Layer definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optioal) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • +
+

+Interrupt Number Definition

+

+Configuration of the Processor and Core Peripherals

+

+Device Peripheral Access Layer

+

The Device Header File <device.h> contains the following sections that are device specific:

+
    +
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • +
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • +
  • Device Peripheral Access Layer definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • +
+

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

+

+Interrupt Number Definition

+

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device. For devices implementing an Arm GIC these are defined as:

+
    +
  • IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.
    • +
  • IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.
    • +
  • IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.
    • +
  • IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.
    • +
+

Example:

+

The following example shows the extension of the interrupt vector table for Cortex-A9 class device.

+
typedef enum IRQn
+
{
+
/****** SGI Interrupts Numbers ****************************************/
+
SGI0_IRQn = 0,
+
SGI1_IRQn = 1,
+
SGI2_IRQn = 2,
+
: :
+
SGI15_IRQn = 15,
+
+
/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
+
GlobalTimer_IRQn = 27,
+
PrivTimer_IRQn = 29,
+
PrivWatchdog_IRQn = 30,
+
/****** Platform Exceptions Numbers ***************************************************/
+
Watchdog_IRQn = 32,
+
Timer0_IRQn = 34,
+
Timer1_IRQn = 35,
+
RTClock_IRQn = 36,
+
UART0_IRQn = 37,
+
: :
+
: :
+
} IRQn_Type;
+

+Configuration of the Processor and Core Peripherals

+

The Device Header File <device.h> configures the Cortex-A processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

+

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

+ + + + + + + + + + + + + + + +
#define Value Range Default Description
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__CORTEX_A 5, 7, 9 (n/a) Core type number
__FPU_PRESENT 0 .. 1 0 Defines if an FPU is present or not
__GIC_PRESENT 0 ..1 Defines if an GIC is present or not Core revision number ([15:8] revision number, [7:0] patch number)
__TIM_PRESENT 0 .. 1 0 Defines if a private timer is present or not
__L2C_PRESENT 0 .. 1 0 Defines if a level 2 cache controller is present or not
+

Example

+

The following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.

+
#define __CA_REV 0x0000U
+
#define __CORTEX_A 9U
+
#define __FPU_PRESENT 1U
+
#define __GIC_PRESENT 1U
+
#define __TIM_PRESENT 0U
+
#define __L2C_PRESENT 0U
+
:
+
:
+
#include "core_ca.h" /* Cortex-A processor and core peripherals */
+

+CMSIS Version and Processor Information

+

Defines in the core_cpu.h file identify the version of the CMSIS-Core-A and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

+
#define __CA_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS Core main version */
+
#define __CA_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS Core sub version */
+
#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
+
__CA_CMSIS_VERSION_SUB ) /* CMSIS Core version number */
+

+Device Peripheral Access Layer

+

The Device Header File <device.h> contains for each peripheral:

+
    +
  • Register Layout Typedef
    • +
  • Base Address
    • +
  • Access Definitions
    • +
+

The section Peripheral Access shows examples for peripheral definitions.

+

+Device.h Template File

+

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

+
/**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
+ * @version  V1.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment   */
+/** @addtogroup <Vendor>
+  * @{
+  */
+
+
+/* ToDo: replace '<Device>' with device name; add your doxyGen comment   */
+/** @addtogroup <Device>
+  * @{
+  */
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+typedef enum IRQn
+{
+/* =======================================  ARM Cortex-A Specific Interrupt Numbers  ========================================= */
+
+  /* Software Generated Interrupts */
+  SGI0_IRQn                          =  0,      /*!< Software Generated Interrupt  0                                           */
+  SGI1_IRQn                          =  1,      /*!< Software Generated Interrupt  1                                           */
+  SGI2_IRQn                          =  2,      /*!< Software Generated Interrupt  2                                           */
+  SGI3_IRQn                          =  3,      /*!< Software Generated Interrupt  3                                           */
+  SGI4_IRQn                          =  4,      /*!< Software Generated Interrupt  4                                           */
+  SGI5_IRQn                          =  5,      /*!< Software Generated Interrupt  5                                           */
+  SGI6_IRQn                          =  6,      /*!< Software Generated Interrupt  6                                           */
+  SGI7_IRQn                          =  7,      /*!< Software Generated Interrupt  7                                           */
+  SGI8_IRQn                          =  8,      /*!< Software Generated Interrupt  8                                           */
+  SGI9_IRQn                          =  9,      /*!< Software Generated Interrupt  9                                           */
+  SGI10_IRQn                         = 10,      /*!< Software Generated Interrupt 10                                           */
+  SGI11_IRQn                         = 11,      /*!< Software Generated Interrupt 11                                           */
+  SGI12_IRQn                         = 12,      /*!< Software Generated Interrupt 12                                           */
+  SGI13_IRQn                         = 13,      /*!< Software Generated Interrupt 13                                           */
+  SGI14_IRQn                         = 14,      /*!< Software Generated Interrupt 14                                           */
+  SGI15_IRQn                         = 15,      /*!< Software Generated Interrupt 15                                           */
+  
+  /* Private Peripheral Interrupts */
+  VirtualMaintenanceInterrupt_IRQn   = 25,      /*!< Virtual Maintenance Interrupt                                             */
+  HypervisorTimer_IRQn               = 26,      /*!< Hypervisor Timer Interrupt                                                */
+  VirtualTimer_IRQn                  = 27,      /*!< Virtual Timer Interrupt                                                   */ 
+  Legacy_nFIQ_IRQn                   = 28,      /*!< Legacy nFIQ Interrupt                                                     */
+  SecurePhysicalTimer_IRQn           = 29,      /*!< Secure Physical Timer Interrupt                                           */
+  NonSecurePhysicalTimer_IRQn        = 30,      /*!< Non-Secure Physical Timer Interrupt                                       */
+  Legacy_nIRQ_IRQn                   = 31,      /*!< Legacy nIRQ Interrupt                                                     */ 
+
+ /* Shared Peripheral Interrupts */
+ /* ToDo: add here your device specific external interrupt numbers */
+  <DeviceInterrupt>_IRQn    = 0,                /*!< Device Interrupt                                                          */
+  
+} IRQn_Type;
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================  Configuration of the Arm Cortex-A Processor and Core Peripherals  ============================ */
+/* ToDo: set the defines according your Device */
+/* ToDo: define the correct core revision              
+         5U if your device is a CORTEX-A5 device
+         7U if your device is a CORTEX-A7 device
+         9U if your device is a CORTEX-A9 device */
+#define __CORTEX_A                    #U      /*!< Cortex-A# Core                              */
+#define __CA_REV                 0x0000U      /*!< Core revision r0p0                          */
+/* ToDo: define the correct core features for the <Device> */
+#define __FPU_PRESENT                 1U      /*!< Set to 1 if FPU is present                  */
+#define __GIC_PRESENT                 1U      /*!< Set to 1 if GIC is present                  */
+#define __TIM_PRESENT                 1U      /*!< Set to 1 if TIM is present                  */
+#define __L2C_PRESENT                 1U      /*!< Set to 1 if L2C is present                  */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+/* ToDo: include the correct core_ca#.h file
+         core_ca5.h if your device is a CORTEX-A5 device
+         core_ca7.h if your device is a CORTEX-A7 device
+         core_ca9.h if your device is a CORTEX-A9 device */
+#include <core_ca#.h>                         /*!< Arm Cortex-A# processor and core peripherals */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name */
+#include "system_<Device>.h"                  /*!< <Device> System */
+
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer */
+
+/* =========================================================================================================================== */
+/* ================                                            TMR                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer (TMR)
+  */
+
+typedef struct
+{                                               /*!< (@ 0x40000000) TIM Structure                                              */
+  __IOM uint32_t   TimerLoad;                   /*!< (@ 0x00000004) Timer Load                                                 */
+  __IM  uint32_t   TimerValue;                  /*!< (@ 0x00000008) Timer Counter Current Value                                */
+  __IOM uint32_t   TimerControl;                /*!< (@ 0x0000000C) Timer Control                                              */
+  __OM  uint32_t   TimerIntClr;                 /*!< (@ 0x00000010) Timer Interrupt Clear                                      */
+  __IM  uint32_t   TimerRIS;                    /*!< (@ 0x00000014) Timer Raw Interrupt Status                                 */
+  __IM  uint32_t   TimerMIS;                    /*!< (@ 0x00000018) Timer Masked Interrupt Status                              */
+  __IM  uint32_t   RESERVED[1];
+  __IOM uint32_t   TimerBGLoad;                 /*!< (@ 0x00000020) Background Load Register                                   */
+} <DeviceAbbreviation>_TMR_TypeDef;
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+
+/* ToDo: add here your device peripherals base addresses
+         following is an example for timer */
+/** @addtogroup Device_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+
+/* ToDo: add here your device peripherals pointer definitions
+         following is an example for timer */
+/** @addtogroup Device_Peripheral_declaration
+  * @{
+  */
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+
+
+/** @} */ /* End of group <Device> */
+
+/** @} */ /* End of group <Vendor> */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
+
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file  cmsis_armcc.h
 CMSIS compiler specific macros, functions, instructions.
 
file  cmsis_cp15.h
 CMSIS compiler specific macros, functions, instructions.
 
file  core_ca.h
 CMSIS Cortex-A Core Peripheral Access Layer Header File.
 
file  irq_ctrl.h
 Interrupt Controller API header file.
 
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file  mem_ARMCA9.h
 Memory base and size definitions (used in scatter file)
 
file  system_ARMCA9.h
 
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 Interrupt controller handling implementation for GIC.
 
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+ white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #27395E; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.diagraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; 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+} + +#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { + border-top-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} +#powerTip.n:before { + border-top-color: #808080; + border-width: 11px; + margin: 0px -11px; +} +#powerTip.n:after, #powerTip.n:before { + left: 50%; +} + +#powerTip.nw:after, #powerTip.nw:before { + right: 14px; +} + +#powerTip.ne:after, #powerTip.ne:before { + left: 14px; +} + +#powerTip.s:after, #powerTip.s:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.sw:after, #powerTip.sw:before { + bottom: 100%; +} + +#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { + border-bottom-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} + +#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { + border-bottom-color: #808080; + border-width: 11px; + margin: 0px -11px; +} + +#powerTip.s:after, #powerTip.s:before { + left: 50%; +} + +#powerTip.sw:after, #powerTip.sw:before { + right: 14px; +} + +#powerTip.se:after, #powerTip.se:before { + left: 14px; +} + +#powerTip.e:after, #powerTip.e:before { + left: 100%; +} +#powerTip.e:after { + border-left-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.e:before { + border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/docs/Core_A/html/doxygen.png b/docs/Core_A/html/doxygen.png new file mode 100644 index 0000000..7765a33 Binary files /dev/null and b/docs/Core_A/html/doxygen.png differ diff --git a/docs/Core_A/html/dynsections.js b/docs/Core_A/html/dynsections.js new file mode 100644 index 0000000..ed092c7 --- /dev/null +++ b/docs/Core_A/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +File List +CMSIS-Core (Cortex-A): File List + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
File List
+
+
+
Here is a list of all files with brief descriptions:
+ + + + + + + + + + +
o*ARMCA9.h
o*cmsis_armcc.hCMSIS compiler specific macros, functions, instructions
o*cmsis_cp15.hCMSIS compiler specific macros, functions, instructions
o*core_ca.hCMSIS Cortex-A Core Peripheral Access Layer Header File
o*irq_ctrl.hInterrupt Controller API header file
o*irq_ctrl_gic.cInterrupt controller handling implementation for GIC
o*mem_ARMCA9.hMemory base and size definitions (used in scatter file)
o*startup_ARMCA9.c
\*system_ARMCA9.h
+
+
+
+ + + + diff --git a/docs/Core_A/html/ftv2blank.png b/docs/Core_A/html/ftv2blank.png new file mode 100644 index 0000000..63c605b Binary files /dev/null and b/docs/Core_A/html/ftv2blank.png differ diff --git a/docs/Core_A/html/ftv2cl.png b/docs/Core_A/html/ftv2cl.png new file mode 100644 index 0000000..edd2ddc Binary files /dev/null and b/docs/Core_A/html/ftv2cl.png differ diff --git a/docs/Core_A/html/ftv2doc.png b/docs/Core_A/html/ftv2doc.png new file mode 100644 index 0000000..57fab09 Binary files /dev/null and b/docs/Core_A/html/ftv2doc.png differ diff --git a/docs/Core_A/html/ftv2folderclosed.png b/docs/Core_A/html/ftv2folderclosed.png new file mode 100644 index 0000000..23db980 Binary files /dev/null and b/docs/Core_A/html/ftv2folderclosed.png differ diff --git a/docs/Core_A/html/ftv2folderopen.png b/docs/Core_A/html/ftv2folderopen.png new file mode 100644 index 0000000..e9bd9eb Binary files /dev/null and b/docs/Core_A/html/ftv2folderopen.png differ diff --git a/docs/Core_A/html/ftv2lastnode.png b/docs/Core_A/html/ftv2lastnode.png new file mode 100644 index 0000000..63c605b Binary files /dev/null and b/docs/Core_A/html/ftv2lastnode.png differ diff --git a/docs/Core_A/html/ftv2link.png b/docs/Core_A/html/ftv2link.png new file mode 100644 index 0000000..57fab09 Binary files /dev/null and b/docs/Core_A/html/ftv2link.png differ diff --git a/docs/Core_A/html/ftv2mlastnode.png b/docs/Core_A/html/ftv2mlastnode.png new file mode 100644 index 0000000..40be5ae Binary files /dev/null and b/docs/Core_A/html/ftv2mlastnode.png differ diff --git a/docs/Core_A/html/ftv2mnode.png b/docs/Core_A/html/ftv2mnode.png new file mode 100644 index 0000000..40be5ae Binary files /dev/null and b/docs/Core_A/html/ftv2mnode.png differ diff --git a/docs/Core_A/html/ftv2mo.png b/docs/Core_A/html/ftv2mo.png new file mode 100644 index 0000000..7df39ae Binary files /dev/null and b/docs/Core_A/html/ftv2mo.png differ diff --git a/docs/Core_A/html/ftv2node.png b/docs/Core_A/html/ftv2node.png new file mode 100644 index 0000000..63c605b Binary files /dev/null and b/docs/Core_A/html/ftv2node.png differ diff --git a/docs/Core_A/html/ftv2ns.png b/docs/Core_A/html/ftv2ns.png new file mode 100644 index 0000000..fc2e484 Binary files /dev/null and b/docs/Core_A/html/ftv2ns.png differ diff --git a/docs/Core_A/html/ftv2plastnode.png b/docs/Core_A/html/ftv2plastnode.png new file mode 100644 index 0000000..687a9e1 Binary files /dev/null and b/docs/Core_A/html/ftv2plastnode.png differ diff --git a/docs/Core_A/html/ftv2pnode.png b/docs/Core_A/html/ftv2pnode.png new file mode 100644 index 0000000..687a9e1 Binary files /dev/null and b/docs/Core_A/html/ftv2pnode.png differ diff --git a/docs/Core_A/html/ftv2splitbar.png b/docs/Core_A/html/ftv2splitbar.png new file mode 100644 index 0000000..5e210e7 Binary files /dev/null and b/docs/Core_A/html/ftv2splitbar.png differ diff --git a/docs/Core_A/html/ftv2vertline.png b/docs/Core_A/html/ftv2vertline.png new file mode 100644 index 0000000..63c605b Binary files /dev/null and b/docs/Core_A/html/ftv2vertline.png differ diff --git a/docs/Core_A/html/functions.html b/docs/Core_A/html/functions.html new file mode 100644 index 0000000..5615822 --- /dev/null +++ b/docs/Core_A/html/functions.html @@ -0,0 +1,172 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- _ -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_a.html b/docs/Core_A/html/functions_a.html new file mode 100644 index 0000000..f03d091 --- /dev/null +++ b/docs/Core_A/html/functions_a.html @@ -0,0 +1,207 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- a -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_b.html b/docs/Core_A/html/functions_b.html new file mode 100644 index 0000000..e0666fa --- /dev/null +++ b/docs/Core_A/html/functions_b.html @@ -0,0 +1,191 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- b -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_c.html b/docs/Core_A/html/functions_c.html new file mode 100644 index 0000000..3a92d5f --- /dev/null +++ b/docs/Core_A/html/functions_c.html @@ -0,0 +1,268 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- c -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_d.html b/docs/Core_A/html/functions_d.html new file mode 100644 index 0000000..600a434 --- /dev/null +++ b/docs/Core_A/html/functions_d.html @@ -0,0 +1,223 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- d -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_dup.js b/docs/Core_A/html/functions_dup.js new file mode 100644 index 0000000..50e3df1 --- /dev/null +++ b/docs/Core_A/html/functions_dup.js @@ -0,0 +1,28 @@ +var functions_dup = +[ + [ "_", "functions.html", null ], + [ "a", "functions_a.html", null ], + [ "b", "functions_b.html", null ], + [ "c", "functions_c.html", null ], + [ "d", "functions_d.html", null ], + [ "e", "functions_e.html", null ], + [ "f", "functions_f.html", null ], + [ "g", "functions_g.html", null ], + [ "h", "functions_h.html", null ], + [ "i", "functions_i.html", null ], + [ "j", "functions_j.html", null ], + [ "l", "functions_l.html", null ], + [ "m", "functions_m.html", null ], + [ "n", "functions_n.html", null ], + [ "o", "functions_o.html", null ], + [ "p", "functions_p.html", null ], + [ "q", "functions_q.html", null ], + [ "r", "functions_r.html", null ], + [ "s", "functions_s.html", null ], + [ "t", "functions_t.html", null ], + [ "u", "functions_u.html", null ], + [ "v", "functions_v.html", null ], + [ "w", "functions_w.html", null ], + [ "x", "functions_x.html", null ], + [ "z", "functions_z.html", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/functions_e.html b/docs/Core_A/html/functions_e.html new file mode 100644 index 0000000..6df14eb --- /dev/null +++ b/docs/Core_A/html/functions_e.html @@ -0,0 +1,200 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- e -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_f.html b/docs/Core_A/html/functions_f.html new file mode 100644 index 0000000..c548bd3 --- /dev/null +++ b/docs/Core_A/html/functions_f.html @@ -0,0 +1,187 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- f -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_g.html b/docs/Core_A/html/functions_g.html new file mode 100644 index 0000000..9e355bf --- /dev/null +++ b/docs/Core_A/html/functions_g.html @@ -0,0 +1,175 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- g -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_h.html b/docs/Core_A/html/functions_h.html new file mode 100644 index 0000000..f965918 --- /dev/null +++ b/docs/Core_A/html/functions_h.html @@ -0,0 +1,175 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- h -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_i.html b/docs/Core_A/html/functions_i.html new file mode 100644 index 0000000..1821525 --- /dev/null +++ b/docs/Core_A/html/functions_i.html @@ -0,0 +1,271 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- i -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_j.html b/docs/Core_A/html/functions_j.html new file mode 100644 index 0000000..8769f3b --- /dev/null +++ b/docs/Core_A/html/functions_j.html @@ -0,0 +1,172 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- j -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_l.html b/docs/Core_A/html/functions_l.html new file mode 100644 index 0000000..4a18039 --- /dev/null +++ b/docs/Core_A/html/functions_l.html @@ -0,0 +1,195 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- l -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_m.html b/docs/Core_A/html/functions_m.html new file mode 100644 index 0000000..42a7a10 --- /dev/null +++ b/docs/Core_A/html/functions_m.html @@ -0,0 +1,179 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- m -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_n.html b/docs/Core_A/html/functions_n.html new file mode 100644 index 0000000..3c9b00e --- /dev/null +++ b/docs/Core_A/html/functions_n.html @@ -0,0 +1,181 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- n -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_o.html b/docs/Core_A/html/functions_o.html new file mode 100644 index 0000000..a6291c5 --- /dev/null +++ b/docs/Core_A/html/functions_o.html @@ -0,0 +1,172 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- o -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_p.html b/docs/Core_A/html/functions_p.html new file mode 100644 index 0000000..5759b96 --- /dev/null +++ b/docs/Core_A/html/functions_p.html @@ -0,0 +1,178 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- p -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_q.html b/docs/Core_A/html/functions_q.html new file mode 100644 index 0000000..a8d33dc --- /dev/null +++ b/docs/Core_A/html/functions_q.html @@ -0,0 +1,172 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
Here is a list of all struct and union fields with links to the structures/unions they belong to:
+ +

- q -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_r.html b/docs/Core_A/html/functions_r.html new file mode 100644 index 0000000..cb9ebf5 --- /dev/null +++ b/docs/Core_A/html/functions_r.html @@ -0,0 +1,187 @@ + + + + + +Data Fields +CMSIS-Core (Cortex-A): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
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- r -

+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- s -

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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- t -

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+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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Here is a list of all struct and union fields with links to the structures/unions they belong to:
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- u -

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+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- v -

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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- _ -

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CMSIS-Core support for Cortex-A processor-based devices
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- a -

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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- b -

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+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- c -

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+
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CMSIS-Core support for Cortex-A processor-based devices
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- d -

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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+ +
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- e -

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+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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- f -

+
+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+ +
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+
+ +
+ + + + +
+ +
+ +
+  + +

- g -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_h.html b/docs/Core_A/html/functions_vars_h.html new file mode 100644 index 0000000..dbd72ab --- /dev/null +++ b/docs/Core_A/html/functions_vars_h.html @@ -0,0 +1,175 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core support for Cortex-A processor-based devices
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+ +
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- h -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_i.html b/docs/Core_A/html/functions_vars_i.html new file mode 100644 index 0000000..ab04070 --- /dev/null +++ b/docs/Core_A/html/functions_vars_i.html @@ -0,0 +1,271 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core support for Cortex-A processor-based devices
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- i -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_j.html b/docs/Core_A/html/functions_vars_j.html new file mode 100644 index 0000000..023874f --- /dev/null +++ b/docs/Core_A/html/functions_vars_j.html @@ -0,0 +1,172 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- j -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_l.html b/docs/Core_A/html/functions_vars_l.html new file mode 100644 index 0000000..1529bfd --- /dev/null +++ b/docs/Core_A/html/functions_vars_l.html @@ -0,0 +1,195 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
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+ +
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    + +
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+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- l -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_m.html b/docs/Core_A/html/functions_vars_m.html new file mode 100644 index 0000000..9cb17dc --- /dev/null +++ b/docs/Core_A/html/functions_vars_m.html @@ -0,0 +1,179 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+ +
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    + +
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+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- m -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_n.html b/docs/Core_A/html/functions_vars_n.html new file mode 100644 index 0000000..7fb1351 --- /dev/null +++ b/docs/Core_A/html/functions_vars_n.html @@ -0,0 +1,181 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- n -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_o.html b/docs/Core_A/html/functions_vars_o.html new file mode 100644 index 0000000..5ec00bd --- /dev/null +++ b/docs/Core_A/html/functions_vars_o.html @@ -0,0 +1,172 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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+ + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- o -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_p.html b/docs/Core_A/html/functions_vars_p.html new file mode 100644 index 0000000..71e703a --- /dev/null +++ b/docs/Core_A/html/functions_vars_p.html @@ -0,0 +1,178 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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+ + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- p -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_q.html b/docs/Core_A/html/functions_vars_q.html new file mode 100644 index 0000000..16c01fc --- /dev/null +++ b/docs/Core_A/html/functions_vars_q.html @@ -0,0 +1,172 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- q -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_r.html b/docs/Core_A/html/functions_vars_r.html new file mode 100644 index 0000000..4975957 --- /dev/null +++ b/docs/Core_A/html/functions_vars_r.html @@ -0,0 +1,187 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- r -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_s.html b/docs/Core_A/html/functions_vars_s.html new file mode 100644 index 0000000..d57949f --- /dev/null +++ b/docs/Core_A/html/functions_vars_s.html @@ -0,0 +1,205 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- s -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_t.html b/docs/Core_A/html/functions_vars_t.html new file mode 100644 index 0000000..068ac2e --- /dev/null +++ b/docs/Core_A/html/functions_vars_t.html @@ -0,0 +1,184 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- t -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_u.html b/docs/Core_A/html/functions_vars_u.html new file mode 100644 index 0000000..313f1e3 --- /dev/null +++ b/docs/Core_A/html/functions_vars_u.html @@ -0,0 +1,181 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- u -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_v.html b/docs/Core_A/html/functions_vars_v.html new file mode 100644 index 0000000..ed5a087 --- /dev/null +++ b/docs/Core_A/html/functions_vars_v.html @@ -0,0 +1,176 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- v -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_w.html b/docs/Core_A/html/functions_vars_w.html new file mode 100644 index 0000000..7169219 --- /dev/null +++ b/docs/Core_A/html/functions_vars_w.html @@ -0,0 +1,206 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- w -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_x.html b/docs/Core_A/html/functions_vars_x.html new file mode 100644 index 0000000..5378ae5 --- /dev/null +++ b/docs/Core_A/html/functions_vars_x.html @@ -0,0 +1,172 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+  + +

- x -

+
+
+ + + + diff --git a/docs/Core_A/html/functions_vars_z.html b/docs/Core_A/html/functions_vars_z.html new file mode 100644 index 0000000..13e9316 --- /dev/null +++ b/docs/Core_A/html/functions_vars_z.html @@ -0,0 +1,173 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-A): Data Fields - Variables + + + + + + + + + + + + + + +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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+ +
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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CMSIS-Core support for Cortex-A processor-based devices
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+Content | +Data Structures | +Functions
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Auxiliary Control Register (ACTLR)
Core Register Access
+
+
+ +

The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. +More...

+ + + + + +

+Content

 ACTLR Bits
 Bit position and mask macros.
 
+ + + + +

+Data Structures

struct  ACTLR_Type
 Bit field declaration for ACTLR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_FORCEINLINE void __set_ACTRL (uint32_t actrl)
 Set ACTRL. More...
 
__STATIC_FORCEINLINE uint32_t __get_ACTLR (void)
 Get ACTLR. More...
 
+

Description

+

The ACTLR characteristics are differs between various Armv7-A implementations.

+

Cortex-A5

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:29] - Reserved.
[28] DBDI Disable Branch Dual Issue
[27:19] - Reserved.
[18] BTDIS Disable indirect Branch Target Address Cache (BTAC).
[17] RSDIS Disable return stack operation.
[16:15] BP Branch prediction policy.
[14:13] L1PCTL L1 Data prefetch control.
[12] RADIS Disable Data Cache read-allocate mode.
[11] DWBST Disable AXI data write bursts to Normal memory.
[10] DODMBS Disable optimized data memory barrier behavior.
[9:8] - Reserved.
[7] EXCL Exclusive L1/L2 cache control.
[6] SMP Enables coherent requests to the processor.
[5:1] - Reserved.
[0] FW Cache and TLB maintenance broadcast.
+

Cortex-A7

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:29] - Reserved.
[28] DDI Disable Dual Issue
[27:16] - Reserved.
[15] DDVM Disable Distributed Virtual Memory transactions.
[14:13] L1PCTL L1 Data prefetch control.
[12] L1RADIS L1 Data Cache read-allocate mode disable.
[11] L2RADIS L2 Data Cache read-allocate mode disable.
[10] DODMBS Disable optimized data memory barrier behavior.
[9:7] - Reserved.
[6] SMP Enables coherent requests to the processor.
[5:0] - Reserved.
+

Cortex-A9

+ + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:10] - Reserved.
[9] PARITY Support for parity checking, if implemented.
[8] AOW Enable allocation in one cache way only.
[7] EXCL Exclusive L1/L2 cache control.
[6] SMP Enables coherent requests to the processor.
[5:4] - Reserved.
[3] WFLZM Enable write full line of zeros modea.
[2] L1PE Dside prefetch.
[1] - Reserved.
[0] FW Cache and TLB maintenance broadcast.
+

Consider using __get_ACTLR and __set_ACTRL to access ACTRL register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_ACTLR (void )
+
+
Returns
Auxiliary Control register value
+

This function returns the value of the Auxiliary Control Register (ACTLR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_ACTRL (uint32_t actrl)
+
+
Parameters
+ + +
[in]actrlAuxiliary Control Register value to set
+
+
+

This function assigns the given value to the Auxiliary Control Register (ACTLR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__ACTLR.js b/docs/Core_A/html/group__CMSIS__ACTLR.js new file mode 100644 index 0000000..086d7bb --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ACTLR.js @@ -0,0 +1,31 @@ +var group__CMSIS__ACTLR = +[ + [ "ACTLR Bits", "group__CMSIS__ACTLR__BITS.html", "group__CMSIS__ACTLR__BITS" ], + [ "ACTLR_Type", "unionACTLR__Type.html", [ + [ "AOW", "unionACTLR__Type.html#a3f235030777fe4e20477063df416b515", null ], + [ "b", "unionACTLR__Type.html#ac953059faa3a1139f8787d87f58a875d", null ], + [ "b", "unionACTLR__Type.html#a94d750b9b337ce140b04d6e30e7a2ca2", null ], + [ "b", "unionACTLR__Type.html#a5044f19ce5ae1f73dda07f7187e70923", null ], + [ "BP", "unionACTLR__Type.html#ac8ac735e3001442e581ae37e773b5929", null ], + [ "BTDIS", "unionACTLR__Type.html#ad1a121373ae8df19f6d11bde3b3ba9c9", null ], + [ "DBDI", "unionACTLR__Type.html#a19e5f8f1a2ad8634619399b4eb50a449", null ], + [ "DDI", "unionACTLR__Type.html#ab938c32e10162d06ba6b02400e955e01", null ], + [ "DDVM", "unionACTLR__Type.html#a4fe04e95b26e089642bee6952f223f82", null ], + [ "DODMBS", "unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8", null ], + [ "DWBST", "unionACTLR__Type.html#ad8faaa57629f258c6eba678ba8efc9da", null ], + [ "EXCL", "unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91", null ], + [ "FW", "unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781", null ], + [ "L1PCTL", "unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c", null ], + [ "L1PE", "unionACTLR__Type.html#aacb87aa6bf093e1ee956342e0cb5903e", null ], + [ "L1RADIS", "unionACTLR__Type.html#a3800bdd7abfab1a51dcfa7069e245d65", null ], + [ "L2RADIS", "unionACTLR__Type.html#a947f73d64ebde186b9416fd6dc66bc26", null ], + [ "PARITY", "unionACTLR__Type.html#a6e8f053d01fb236cc7d002b04d93a19c", null ], + [ "RADIS", "unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3", null ], + [ "RSDIS", "unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3", null ], + [ "SMP", "unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149", null ], + [ "w", "unionACTLR__Type.html#ac65c09d839f8a78340c3b81d3bc90e4d", null ], + [ "WFLZM", "unionACTLR__Type.html#a67e005f7741b6d46cf95d9c477efef36", null ] + ] ], + [ "__get_ACTLR", "group__CMSIS__ACTLR.html#gae75d412bfd6fe873ade00b021aefcab3", null ], + [ "__set_ACTRL", "group__CMSIS__ACTLR.html#gabe7491eac1652f740050bd905baea187", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__ACTLR__BITS.html b/docs/Core_A/html/group__CMSIS__ACTLR__BITS.html new file mode 100644 index 0000000..e114608 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ACTLR__BITS.html @@ -0,0 +1,709 @@ + + + + + +ACTLR Bits +CMSIS-Core (Cortex-A): ACTLR Bits + + + + + + + + + + + + + + +
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+Macros
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+
ACTLR Bits
Auxiliary Control Register (ACTLR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define ACTLR_DDI_Pos   28U
 ACTLR: DDI Position. More...
 
#define ACTLR_DDI_Msk   (1UL << ACTLR_DDI_Pos)
 ACTLR: DDI Mask. More...
 
#define ACTLR_DBDI_Pos   28U
 ACTLR: DBDI Position. More...
 
#define ACTLR_DBDI_Msk   (1UL << ACTLR_DBDI_Pos)
 ACTLR: DBDI Mask. More...
 
#define ACTLR_BTDIS_Pos   18U
 ACTLR: BTDIS Position. More...
 
#define ACTLR_BTDIS_Msk   (1UL << ACTLR_BTDIS_Pos)
 ACTLR: BTDIS Mask. More...
 
#define ACTLR_RSDIS_Pos   17U
 ACTLR: RSDIS Position. More...
 
#define ACTLR_RSDIS_Msk   (1UL << ACTLR_RSDIS_Pos)
 ACTLR: RSDIS Mask. More...
 
#define ACTLR_BP_Pos   15U
 ACTLR: BP Position. More...
 
#define ACTLR_BP_Msk   (3UL << ACTLR_BP_Pos)
 ACTLR: BP Mask. More...
 
#define ACTLR_DDVM_Pos   15U
 ACTLR: DDVM Position. More...
 
#define ACTLR_DDVM_Msk   (1UL << ACTLR_DDVM_Pos)
 ACTLR: DDVM Mask. More...
 
#define ACTLR_L1PCTL_Pos   13U
 ACTLR: L1PCTL Position. More...
 
#define ACTLR_L1PCTL_Msk   (3UL << ACTLR_L1PCTL_Pos)
 ACTLR: L1PCTL Mask. More...
 
#define ACTLR_RADIS_Pos   12U
 ACTLR: RADIS Position. More...
 
#define ACTLR_RADIS_Msk   (1UL << ACTLR_RADIS_Pos)
 ACTLR: RADIS Mask. More...
 
#define ACTLR_L1RADIS_Pos   12U
 ACTLR: L1RADIS Position. More...
 
#define ACTLR_L1RADIS_Msk   (1UL << ACTLR_L1RADIS_Pos)
 ACTLR: L1RADIS Mask. More...
 
#define ACTLR_DWBST_Pos   11U
 ACTLR: DWBST Position. More...
 
#define ACTLR_DWBST_Msk   (1UL << ACTLR_DWBST_Pos)
 ACTLR: DWBST Mask. More...
 
#define ACTLR_L2RADIS_Pos   11U
 ACTLR: L2RADIS Position. More...
 
#define ACTLR_L2RADIS_Msk   (1UL << ACTLR_L2RADIS_Pos)
 ACTLR: L2RADIS Mask. More...
 
#define ACTLR_DODMBS_Pos   10U
 ACTLR: DODMBS Position. More...
 
#define ACTLR_DODMBS_Msk   (1UL << ACTLR_DODMBS_Pos)
 ACTLR: DODMBS Mask. More...
 
#define ACTLR_PARITY_Pos   9U
 ACTLR: PARITY Position. More...
 
#define ACTLR_PARITY_Msk   (1UL << ACTLR_PARITY_Pos)
 ACTLR: PARITY Mask. More...
 
#define ACTLR_AOW_Pos   8U
 ACTLR: AOW Position. More...
 
#define ACTLR_AOW_Msk   (1UL << ACTLR_AOW_Pos)
 ACTLR: AOW Mask. More...
 
#define ACTLR_EXCL_Pos   7U
 ACTLR: EXCL Position. More...
 
#define ACTLR_EXCL_Msk   (1UL << ACTLR_EXCL_Pos)
 ACTLR: EXCL Mask. More...
 
#define ACTLR_SMP_Pos   6U
 ACTLR: SMP Position. More...
 
#define ACTLR_SMP_Msk   (1UL << ACTLR_SMP_Pos)
 ACTLR: SMP Mask. More...
 
#define ACTLR_WFLZM_Pos   3U
 ACTLR: WFLZM Position. More...
 
#define ACTLR_WFLZM_Msk   (1UL << ACTLR_WFLZM_Pos)
 ACTLR: WFLZM Mask. More...
 
#define ACTLR_L1PE_Pos   2U
 ACTLR: L1PE Position. More...
 
#define ACTLR_L1PE_Msk   (1UL << ACTLR_L1PE_Pos)
 ACTLR: L1PE Mask. More...
 
#define ACTLR_FW_Pos   0U
 ACTLR: FW Position. More...
 
#define ACTLR_FW_Msk   (1UL << ACTLR_FW_Pos)
 ACTLR: FW Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ACTLR_AOW_Msk   (1UL << ACTLR_AOW_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_AOW_Pos   8U
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_BP_Msk   (3UL << ACTLR_BP_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_BP_Pos   15U
+
+ +
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+ +
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+ + + + +
#define ACTLR_BTDIS_Msk   (1UL << ACTLR_BTDIS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_BTDIS_Pos   18U
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+ +
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+ +
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+ + + + +
#define ACTLR_DBDI_Msk   (1UL << ACTLR_DBDI_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_DBDI_Pos   28U
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+ +
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+ + + + +
#define ACTLR_DDI_Msk   (1UL << ACTLR_DDI_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_DDI_Pos   28U
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+ +
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+ +
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+ + + + +
#define ACTLR_DDVM_Msk   (1UL << ACTLR_DDVM_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_DDVM_Pos   15U
+
+ +
+
+ +
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+ + + + +
#define ACTLR_DODMBS_Msk   (1UL << ACTLR_DODMBS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_DODMBS_Pos   10U
+
+ +
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+ +
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+ + + + +
#define ACTLR_DWBST_Msk   (1UL << ACTLR_DWBST_Pos)
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+ +
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+ +
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+ + + + +
#define ACTLR_DWBST_Pos   11U
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+ +
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+ +
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+ + + + +
#define ACTLR_EXCL_Msk   (1UL << ACTLR_EXCL_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_EXCL_Pos   7U
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+ +
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+ +
+
+ + + + +
#define ACTLR_FW_Msk   (1UL << ACTLR_FW_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_FW_Pos   0U
+
+ +
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+ +
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+ + + + +
#define ACTLR_L1PCTL_Msk   (3UL << ACTLR_L1PCTL_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_L1PCTL_Pos   13U
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+ + + + +
#define ACTLR_L1PE_Msk   (1UL << ACTLR_L1PE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_L1PE_Pos   2U
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+ +
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+ +
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+ + + + +
#define ACTLR_L1RADIS_Msk   (1UL << ACTLR_L1RADIS_Pos)
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+ +
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+ +
+
+ + + + +
#define ACTLR_L1RADIS_Pos   12U
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+ +
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+ +
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+ + + + +
#define ACTLR_L2RADIS_Msk   (1UL << ACTLR_L2RADIS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_L2RADIS_Pos   11U
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+ +
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+ + + + +
#define ACTLR_PARITY_Msk   (1UL << ACTLR_PARITY_Pos)
+
+ +
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+ +
+
+ + + + +
#define ACTLR_PARITY_Pos   9U
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+ +
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+ + + + +
#define ACTLR_RADIS_Msk   (1UL << ACTLR_RADIS_Pos)
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+ +
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+ +
+
+ + + + +
#define ACTLR_RADIS_Pos   12U
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+ + + + +
#define ACTLR_RSDIS_Msk   (1UL << ACTLR_RSDIS_Pos)
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+ +
+
+ + + + +
#define ACTLR_RSDIS_Pos   17U
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+ +
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+ +
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+ + + + +
#define ACTLR_SMP_Msk   (1UL << ACTLR_SMP_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_SMP_Pos   6U
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+ +
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+ +
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+ + + + +
#define ACTLR_WFLZM_Msk   (1UL << ACTLR_WFLZM_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ACTLR_WFLZM_Pos   3U
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__ACTLR__BITS.js b/docs/Core_A/html/group__CMSIS__ACTLR__BITS.js new file mode 100644 index 0000000..53d81da --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ACTLR__BITS.js @@ -0,0 +1,41 @@ +var group__CMSIS__ACTLR__BITS = +[ + [ "ACTLR_AOW_Msk", "group__CMSIS__ACTLR__BITS.html#ga5ca6754c31f90c7e5d1822dddfb4135c", null ], + [ "ACTLR_AOW_Pos", "group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f", null ], + [ "ACTLR_BP_Msk", "group__CMSIS__ACTLR__BITS.html#ga677211818d8a2c7b118115361fbef2e7", null ], + [ "ACTLR_BP_Pos", "group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6", null ], + [ "ACTLR_BTDIS_Msk", "group__CMSIS__ACTLR__BITS.html#gad48e0a1c1e59e6721547b45f37baa48b", null ], + [ "ACTLR_BTDIS_Pos", "group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d", null ], + [ "ACTLR_DBDI_Msk", "group__CMSIS__ACTLR__BITS.html#ga0a3d58754927731758c53bd945ac35fe", null ], + [ "ACTLR_DBDI_Pos", "group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee", null ], + [ "ACTLR_DDI_Msk", "group__CMSIS__ACTLR__BITS.html#gaeee8e0fc7b28f2a405b234e7d2c7486e", null ], + [ "ACTLR_DDI_Pos", "group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0", null ], + [ "ACTLR_DDVM_Msk", "group__CMSIS__ACTLR__BITS.html#ga4565f2632e5c4be5e1d3eb90fa6f2ac6", null ], + [ "ACTLR_DDVM_Pos", "group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d", null ], + [ "ACTLR_DODMBS_Msk", "group__CMSIS__ACTLR__BITS.html#ga88a85e6310334edb190a6e9298ae98b7", null ], + [ "ACTLR_DODMBS_Pos", "group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02", null ], + [ "ACTLR_DWBST_Msk", "group__CMSIS__ACTLR__BITS.html#gab948ab9af88a9357e2e383d948e9dc7e", null ], + [ "ACTLR_DWBST_Pos", "group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2", null ], + [ "ACTLR_EXCL_Msk", "group__CMSIS__ACTLR__BITS.html#ga8b704419a7ed130ecbee00de9fd72d55", null ], + [ "ACTLR_EXCL_Pos", "group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701", null ], + [ "ACTLR_FW_Msk", "group__CMSIS__ACTLR__BITS.html#ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1", null ], + [ "ACTLR_FW_Pos", "group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce", null ], + [ "ACTLR_L1PCTL_Msk", "group__CMSIS__ACTLR__BITS.html#gad701fa3ff69b89ba185b7482e81cb6fd", null ], + [ "ACTLR_L1PCTL_Pos", "group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae", null ], + [ "ACTLR_L1PE_Msk", "group__CMSIS__ACTLR__BITS.html#ga969c20495fe3e50e8c2a73454688a674", null ], + [ "ACTLR_L1PE_Pos", "group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b", null ], + [ "ACTLR_L1RADIS_Msk", "group__CMSIS__ACTLR__BITS.html#ga6aafd83ca6c02f705def8edc8c064c04", null ], + [ "ACTLR_L1RADIS_Pos", "group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1", null ], + [ "ACTLR_L2RADIS_Msk", "group__CMSIS__ACTLR__BITS.html#gad84b20f4f5d1979bb000a14a582cad12", null ], + [ "ACTLR_L2RADIS_Pos", "group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e", null ], + [ "ACTLR_PARITY_Msk", "group__CMSIS__ACTLR__BITS.html#gadec8e5d68791dc4749bf3f075a3559fb", null ], + [ "ACTLR_PARITY_Pos", "group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749", null ], + [ "ACTLR_RADIS_Msk", "group__CMSIS__ACTLR__BITS.html#gac6aea849e5320c0e93321d5d8b0c117c", null ], + [ "ACTLR_RADIS_Pos", "group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44", null ], + [ "ACTLR_RSDIS_Msk", "group__CMSIS__ACTLR__BITS.html#ga8487babc3514e2bb8f3d524e5f80d95f", null ], + [ "ACTLR_RSDIS_Pos", "group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6", null ], + [ "ACTLR_SMP_Msk", "group__CMSIS__ACTLR__BITS.html#gac6dcc315f6c4527434b9b0e4106771d8", null ], + [ "ACTLR_SMP_Pos", "group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf", null ], + [ "ACTLR_WFLZM_Msk", "group__CMSIS__ACTLR__BITS.html#gae5a89cb553773b10e86a9c826f11179f", null ], + [ "ACTLR_WFLZM_Pos", "group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CBAR.html b/docs/Core_A/html/group__CMSIS__CBAR.html new file mode 100644 index 0000000..c746f67 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CBAR.html @@ -0,0 +1,176 @@ + + + + + +Configuration Base Address Register (CBAR) +CMSIS-Core (Cortex-A): Configuration Base Address Register (CBAR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Functions
+
+
Configuration Base Address Register (CBAR)
Core Register Access
+
+
+ +

Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13]. +More...

+ + + + + +

+Content

 CBAR Bits
 Bit position and mask macros.
 
+ + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_CBAR (void)
 Get CBAR. More...
 
+

Description

+ + + + + + + +
Bits Name Function
[31:13] PERIPHBASE Peripheral base address.
[12:0] - Read as zero.
+

Consider __get_CBAR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CBAR (void )
+
+
Returns
Configuration Base Address register value
+

This function returns the value of the Configuration Base Address register.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CBAR.js b/docs/Core_A/html/group__CMSIS__CBAR.js new file mode 100644 index 0000000..6f1c811 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CBAR.js @@ -0,0 +1,5 @@ +var group__CMSIS__CBAR = +[ + [ "CBAR Bits", "group__CMSIS__CBAR__BITS.html", null ], + [ "__get_CBAR", "group__CMSIS__CBAR.html#gab0f00668bb0f6cbe3cc8b90535d66d8e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CBAR__BITS.html b/docs/Core_A/html/group__CMSIS__CBAR__BITS.html new file mode 100644 index 0000000..076b87e --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CBAR__BITS.html @@ -0,0 +1,131 @@ + + + + + +CBAR Bits +CMSIS-Core (Cortex-A): CBAR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
CBAR Bits
Configuration Base Address Register (CBAR)
+
+
+ +

Bit position and mask macros. +More...

+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CBPM.html b/docs/Core_A/html/group__CMSIS__CBPM.html new file mode 100644 index 0000000..5767d0b --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CBPM.html @@ -0,0 +1,246 @@ + + + + + +Cache and branch predictor maintenance operations +CMSIS-Core (Cortex-A): Cache and branch predictor maintenance operations + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Cache and branch predictor maintenance operations
Core Register Access
+
+
+ +

This section describes the cache and branch predictor maintenance operations. +More...

+ + + + + + + + + + + + + + + + + +

+Functions

__STATIC_FORCEINLINE void __set_BPIALL (uint32_t value)
 Set BPIALL. More...
 
__STATIC_FORCEINLINE void __set_DCCIMVAC (uint32_t value)
 Set DCCIMVAC. More...
 
__STATIC_FORCEINLINE void __set_DCCMVAC (uint32_t value)
 Set DCCMVAC. More...
 
__STATIC_FORCEINLINE void __set_DCIMVAC (uint32_t value)
 Set DCIMVAC. More...
 
__STATIC_FORCEINLINE void __set_ICIALLU (uint32_t value)
 Set ICIALLU. More...
 
+

Description

+

Cache maintenance operations are defined to act on particular memory locations. In addition, for instruction caches and branch predictors, there are operations that invalidate all entries.

+

Consider using L1 Cache Functions and L2C-310 Cache Controller Functions for cache maintenance instead of raw register usage.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_BPIALL (uint32_t value)
+
+

Branch Predictor Invalidate All

+

This function writes the provided value to the Branch Predictor Invalidate All (BPIALL) register.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_DCCIMVAC (uint32_t value)
+
+

Data cache clean and invalidate

+

This function cleans and invalidates data or unified cache line by MVA to PoC.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_DCCMVAC (uint32_t value)
+
+

Data cache clean

+

This function cleans data or unified cache line by MVA to PoC.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_DCIMVAC (uint32_t value)
+
+

Data cache invalidate

+

This function invalidates data or unified cache line by MVA to PoC.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_ICIALLU (uint32_t value)
+
+

Instruction Cache Invalidate All

+

This function invalidates all instruction cache.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CBPM.js b/docs/Core_A/html/group__CMSIS__CBPM.js new file mode 100644 index 0000000..667c8bf --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CBPM.js @@ -0,0 +1,8 @@ +var group__CMSIS__CBPM = +[ + [ "__set_BPIALL", "group__CMSIS__CBPM.html#gaa5a1bf5487bd00c61764ee2614bea3d4", null ], + [ "__set_DCCIMVAC", "group__CMSIS__CBPM.html#ga5a6dc4a371d0e5c5ea9f9a1dcea999ff", null ], + [ "__set_DCCMVAC", "group__CMSIS__CBPM.html#gaa47448c89b3134f5e9fbb7ba0b69c7d9", null ], + [ "__set_DCIMVAC", "group__CMSIS__CBPM.html#ga643b62f37449627ca2ec3de80c1b8abb", null ], + [ "__set_ICIALLU", "group__CMSIS__CBPM.html#gaee63f9c620f6d37775f80667bc5f724d", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CNTFRQ.html b/docs/Core_A/html/group__CMSIS__CNTFRQ.html new file mode 100644 index 0000000..fa377d8 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTFRQ.html @@ -0,0 +1,190 @@ + + + + + +Counter Frequency register (CNTFRQ) +CMSIS-Core (Cortex-A): Counter Frequency register (CNTFRQ) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Counter Frequency register (CNTFRQ)
Core Register Access
+
+
+ +

Indicates the clock frequency of the system counter. +More...

+ + + + + + + + +

+Functions

__STATIC_FORCEINLINE void __set_CNTFRQ (uint32_t value)
 Set CNTFRQ. More...
 
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ (void)
 Get CNTFRQ. More...
 
+

Description

+

Consider __get_CNTFRQ and __set_CNTFRQ to access this register.

+

Consider using Generic Physical Timer Functions for controlling the PL1 Timer instead.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CNTFRQ (void )
+
+

This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).

+
Returns
CNTFRQ Register value
+

This function returns the value of the Counter Frequency register (CNTFRQ).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_CNTFRQ (uint32_t value)
+
+

This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).

+
Parameters
+ + +
[in]valueCNTFRQ Register value to set
+
+
+

This function assigns the given value to Counter Frequency register (CNTFRQ).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CNTFRQ.js b/docs/Core_A/html/group__CMSIS__CNTFRQ.js new file mode 100644 index 0000000..a47e202 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTFRQ.js @@ -0,0 +1,5 @@ +var group__CMSIS__CNTFRQ = +[ + [ "__get_CNTFRQ", "group__CMSIS__CNTFRQ.html#ga4b6c8f8689077d9b57f65dcff910dbf8", null ], + [ "__set_CNTFRQ", "group__CMSIS__CNTFRQ.html#ga66d2d5070c8577f95e1d2e2bcb3ad143", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CNTPCT.html b/docs/Core_A/html/group__CMSIS__CNTPCT.html new file mode 100644 index 0000000..26162c2 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTPCT.html @@ -0,0 +1,163 @@ + + + + + +PL1 Physical Count register (CNTPCT) +CMSIS-Core (Cortex-A): PL1 Physical Count register (CNTPCT) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
PL1 Physical Count register (CNTPCT)
Core Register Access
+
+
+ +

Holds the 64-bit physical count value. +More...

+ + + + + +

+Functions

__STATIC_FORCEINLINE uint64_t __get_CNTPCT (void)
 Get CNTPCT. More...
 
+

Description

+

Consider __get_CNTPCT to access this register.

+

Consider using Generic Physical Timer Functions for controlling the PL1 Timer instead.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint64_t __get_CNTPCT (void )
+
+

This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).

+
Returns
CNTPCT Register value
+

This function returns the value of the PL1 Physical Count register (CNTPCT).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CNTPCT.js b/docs/Core_A/html/group__CMSIS__CNTPCT.js new file mode 100644 index 0000000..ef7624b --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTPCT.js @@ -0,0 +1,4 @@ +var group__CMSIS__CNTPCT = +[ + [ "__get_CNTPCT", "group__CMSIS__CNTPCT.html#ga42643f577dcc957d6928e170ce7a2d60", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CNTP__CTL.html b/docs/Core_A/html/group__CMSIS__CNTP__CTL.html new file mode 100644 index 0000000..e7e0ca5 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTP__CTL.html @@ -0,0 +1,201 @@ + + + + + +PL1 Physical Timer Control register (CNTP_CTL) +CMSIS-Core (Cortex-A): PL1 Physical Timer Control register (CNTP_CTL) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
PL1 Physical Timer Control register (CNTP_CTL)
Core Register Access
+
+
+ +

The control register for the physical timer. +More...

+ + + + + + + + +

+Functions

__STATIC_FORCEINLINE void __set_CNTP_CTL (uint32_t value)
 Set CNTP_CTL. More...
 
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL (void)
 Get CNTP_CTL register. More...
 
+

Description

+ + + + + + + + + + + +
Bits Name Function
[31:3] - Reserved.
[2] ISTATUS The status of the timer.
[1] IMASK Timer output signal mask bit.
[0] ENABLE Enables the timer.
+

Consider __get_CNTP_CTL and __set_CNTP_CTL to access this register.

+

Consider using Generic Physical Timer Functions for controlling the PL1 Timer instead.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CNTP_CTL (void )
+
+
Returns
CNTP_CTL Register value
+

This function returns the value of the PL1 Physical Timer Control Register. (CNTP_CTL).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_CNTP_CTL (uint32_t value)
+
+

This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).

+
Parameters
+ + +
[in]valueCNTP_CTL Register value to set
+
+
+

This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CNTP__CTL.js b/docs/Core_A/html/group__CMSIS__CNTP__CTL.js new file mode 100644 index 0000000..9afb4db --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTP__CTL.js @@ -0,0 +1,5 @@ +var group__CMSIS__CNTP__CTL = +[ + [ "__get_CNTP_CTL", "group__CMSIS__CNTP__CTL.html#gaca4b93d7543b49c1d7e6b4e1c1ff3768", null ], + [ "__set_CNTP_CTL", "group__CMSIS__CNTP__CTL.html#ga96a537cd4e121d58aa9f7d2bfccaa66d", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CNTP__CVAL.html b/docs/Core_A/html/group__CMSIS__CNTP__CVAL.html new file mode 100644 index 0000000..6fb1d71 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTP__CVAL.html @@ -0,0 +1,163 @@ + + + + + +PL1 Physical Timer Compare Value register (CNTP_CVAL) +CMSIS-Core (Cortex-A): PL1 Physical Timer Compare Value register (CNTP_CVAL) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
PL1 Physical Timer Compare Value register (CNTP_CVAL)
Core Register Access
+
+
+ +

Holds the 64-bit compare value for the PL1 physical timer. +More...

+ + + + + +

+Functions

__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL (void)
 Get CNTP_CVAL. More...
 
+

Description

+

Consider __get_CNTP_CVAL and __set_CNTP_CVAL to access this register.

+

Consider using Generic Physical Timer Functions for controlling the PL1 Timer instead.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CNTP_CVAL (void )
+
+

This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).

+
Returns
CNTP_CVAL Register value
+

This function returns the value of the PL1 Physical Timer Compare Value register (CNTP_CVAL).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CNTP__CVAL.js b/docs/Core_A/html/group__CMSIS__CNTP__CVAL.js new file mode 100644 index 0000000..c1388a9 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTP__CVAL.js @@ -0,0 +1,4 @@ +var group__CMSIS__CNTP__CVAL = +[ + [ "__get_CNTP_CVAL", "group__CMSIS__CNTP__CVAL.html#gafc37057a481a5357fb9d35a003941d1d", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CNTP__TVAL.html b/docs/Core_A/html/group__CMSIS__CNTP__TVAL.html new file mode 100644 index 0000000..6274605 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTP__TVAL.html @@ -0,0 +1,190 @@ + + + + + +PL1 Physical Timer Value register (CNTP_TVAL) +CMSIS-Core (Cortex-A): PL1 Physical Timer Value register (CNTP_TVAL) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
PL1 Physical Timer Value register (CNTP_TVAL)
Core Register Access
+
+
+ +

Holds the timer value for the PL1 physical timer. +More...

+ + + + + + + + +

+Functions

__STATIC_FORCEINLINE void __set_CNTP_TVAL (uint32_t value)
 Set CNTP_TVAL. More...
 
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL (void)
 Get CNTP_TVAL. More...
 
+

Description

+

Consider __get_CNTP_TVAL and __set_CNTP_TVAL to access this register.

+

Consider using Generic Physical Timer Functions for controlling the PL1 Timer instead.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CNTP_TVAL (void )
+
+

This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).

+
Returns
CNTP_TVAL Register value
+

This function returns the value of the PL1 Physical Timer Value register (CNTP_TVAL).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_CNTP_TVAL (uint32_t value)
+
+

This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).

+
Parameters
+ + +
[in]valueCNTP_TVAL Register value to set
+
+
+

This function assigns the given value to PL1 Physical Timer Value register (CNTP_TVAL).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CNTP__TVAL.js b/docs/Core_A/html/group__CMSIS__CNTP__TVAL.js new file mode 100644 index 0000000..aaa0f11 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CNTP__TVAL.js @@ -0,0 +1,5 @@ +var group__CMSIS__CNTP__TVAL = +[ + [ "__get_CNTP_TVAL", "group__CMSIS__CNTP__TVAL.html#ga94321d86e23339a3de6e48ae1b4e006d", null ], + [ "__set_CNTP_TVAL", "group__CMSIS__CNTP__TVAL.html#ga5cd55833483552e023c9b2ead0c97a02", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CPACR.html b/docs/Core_A/html/group__CMSIS__CPACR.html new file mode 100644 index 0000000..5eb2a85 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPACR.html @@ -0,0 +1,245 @@ + + + + + +Coprocessor Access Control Register (CPACR) +CMSIS-Core (Cortex-A): Coprocessor Access Control Register (CPACR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Functions
+
+
Coprocessor Access Control Register (CPACR)
Core Register Access
+
+
+ +

The CPACR controls access to coprocessors CP0 to CP13. +More...

+ + + + + + + + +

+Content

 CPACR Bits
 Bit position and mask macros.
 
 CPACR CP field values
 Valid values for CPACR CP field.
 
+ + + + +

+Data Structures

struct  CPACR_Type
 Bit field declaration for CPACR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_CPACR (void)
 Get CPACR. More...
 
__STATIC_FORCEINLINE void __set_CPACR (uint32_t cpacr)
 Set CPACR. More...
 
+

Description

+

The CPACR characteristics are:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31] ASEDIS Disable Advanced SIMD functionality.
[30] D32DIS Disable use of D16-D31 of the Floating-point Extension register file.
[29] - Reserved.
[28] TRCDIS Disable CP14 access to trace registers.
[27:26] CP13 Access rights for coprocessor 13.
[25:24] CP12 Access rights for coprocessor 12.
[23:22] CP11 Access rights for coprocessor 11.
[21:20] CP10 Access rights for coprocessor 10.
[19:18] CP9 Access rights for coprocessor 9.
[17:16] CP8 Access rights for coprocessor 8.
[15:14] CP7 Access rights for coprocessor 7.
[13:12] CP6 Access rights for coprocessor 6.
[11:10] CP5 Access rights for coprocessor 5.
[9:8] CP4 Access rights for coprocessor 4.
[7:6] CP3 Access rights for coprocessor 3.
[5:4] CP2 Access rights for coprocessor 2.
[3:2] CP1 Access rights for coprocessor 1.
[1:0] CP0 Access rights for coprocessor 0.
+

Consider __get_CPACR and __set_CPACR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CPACR (void )
+
+
Returns
Coprocessor Access Control register value
+

This function returns the current value of the Coprocessor Access Control Register (CPACR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_CPACR (uint32_t cpacr)
+
+
Parameters
+ + +
[in]cpacrCoprocessor Access Control value to set
+
+
+

This function assigns the given value to the Coprocessor Access Control Register (CPACR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CPACR.js b/docs/Core_A/html/group__CMSIS__CPACR.js new file mode 100644 index 0000000..33edf57 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPACR.js @@ -0,0 +1,28 @@ +var group__CMSIS__CPACR = +[ + [ "CPACR Bits", "group__CMSIS__CPACR__BITS.html", "group__CMSIS__CPACR__BITS" ], + [ "CPACR CP field values", "group__CMSIS__CPACR__CP.html", "group__CMSIS__CPACR__CP" ], + [ "CPACR_Type", "unionCPACR__Type.html", [ + [ "ASEDIS", "unionCPACR__Type.html#a792fabd71db2311eefbc9b896db37986", null ], + [ "b", "unionCPACR__Type.html#a7aa1870fa74e00241618df136e04141f", null ], + [ "CP0", "unionCPACR__Type.html#a1a29bc40d708ac1a43153b11f60b8195", null ], + [ "CP1", "unionCPACR__Type.html#acb2055cdbdf2a6c9b8279dc6f7cbc624", null ], + [ "CP10", "unionCPACR__Type.html#a0275dc6b0eb9f906ebc5c6431b03dc4e", null ], + [ "CP11", "unionCPACR__Type.html#ac54b8897f9358f37e0046b010c334e87", null ], + [ "CP12", "unionCPACR__Type.html#a68d69635225dd479d3035cc51b4c40ce", null ], + [ "CP13", "unionCPACR__Type.html#a45d9be266fc37a6ff9f31c2bef897f90", null ], + [ "CP2", "unionCPACR__Type.html#a2553fcdfd94ffc09407db9da9db9d586", null ], + [ "CP3", "unionCPACR__Type.html#af245b8dabfea0bf7dc06f5d4de7bfa79", null ], + [ "CP4", "unionCPACR__Type.html#a6424b7a81a440217aab8e51e4b623adb", null ], + [ "CP5", "unionCPACR__Type.html#ad5c0b15cd6a01a6f1db398e020809573", null ], + [ "CP6", "unionCPACR__Type.html#ad898cab7c89a07b80068d141ced869e3", null ], + [ "CP7", "unionCPACR__Type.html#a12002991719fb1af7a5db9a73deb323d", null ], + [ "CP8", "unionCPACR__Type.html#a5a6f694264518a813bdbc202ff47664f", null ], + [ "CP9", "unionCPACR__Type.html#a4de69636eb450fcc3f5f3e4a19a869f5", null ], + [ "D32DIS", "unionCPACR__Type.html#a6206695a548b18ce0e2ea5276d1eef1d", null ], + [ "TRCDIS", "unionCPACR__Type.html#ac6f2f67dd0250b9dc9a8271a05655bbe", null ], + [ "w", "unionCPACR__Type.html#ae2d9d724aff1f8f0060738f5d4527c33", null ] + ] ], + [ "__get_CPACR", "group__CMSIS__CPACR.html#gadb152ab7a893135695e608ecaa5b0c4e", null ], + [ "__set_CPACR", "group__CMSIS__CPACR.html#ga8bf7e1cfb0f28bc3bff3be7fec057668", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CPACR__BITS.html b/docs/Core_A/html/group__CMSIS__CPACR__BITS.html new file mode 100644 index 0000000..72a0e50 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPACR__BITS.html @@ -0,0 +1,267 @@ + + + + + +CPACR Bits +CMSIS-Core (Cortex-A): CPACR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
CPACR Bits
Coprocessor Access Control Register (CPACR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CPACR_ASEDIS_Pos   31U
 CPACR: ASEDIS Position. More...
 
#define CPACR_ASEDIS_Msk   (1UL << CPACR_ASEDIS_Pos)
 CPACR: ASEDIS Mask. More...
 
#define CPACR_D32DIS_Pos   30U
 CPACR: D32DIS Position. More...
 
#define CPACR_D32DIS_Msk   (1UL << CPACR_D32DIS_Pos)
 CPACR: D32DIS Mask. More...
 
#define CPACR_TRCDIS_Pos   28U
 CPACR: D32DIS Position. More...
 
#define CPACR_TRCDIS_Msk   (1UL << CPACR_D32DIS_Pos)
 CPACR: D32DIS Mask. More...
 
#define CPACR_CP_Pos_(n)   (n*2U)
 CPACR: CPn Position. More...
 
#define CPACR_CP_Msk_(n)   (3UL << CPACR_CP_Pos_(n))
 CPACR: CPn Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CPACR_ASEDIS_Msk   (1UL << CPACR_ASEDIS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define CPACR_ASEDIS_Pos   31U
+
+ +
+
+ +
+
+ + + + + + + + +
#define CPACR_CP_Msk_( n)   (3UL << CPACR_CP_Pos_(n))
+
+ +
+
+ +
+
+ + + + + + + + +
#define CPACR_CP_Pos_( n)   (n*2U)
+
+ +
+
+ +
+
+ + + + +
#define CPACR_D32DIS_Msk   (1UL << CPACR_D32DIS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define CPACR_D32DIS_Pos   30U
+
+ +
+
+ +
+
+ + + + +
#define CPACR_TRCDIS_Msk   (1UL << CPACR_D32DIS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define CPACR_TRCDIS_Pos   28U
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CPACR__BITS.js b/docs/Core_A/html/group__CMSIS__CPACR__BITS.js new file mode 100644 index 0000000..fdca77b --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPACR__BITS.js @@ -0,0 +1,11 @@ +var group__CMSIS__CPACR__BITS = +[ + [ "CPACR_ASEDIS_Msk", "group__CMSIS__CPACR__BITS.html#ga46d28804bfa370b0dd4ac520a7a67609", null ], + [ "CPACR_ASEDIS_Pos", "group__CMSIS__CPACR__BITS.html#ga3acd342ab1e88bd4ad73f5670e7af163", null ], + [ "CPACR_CP_Msk_", "group__CMSIS__CPACR__BITS.html#ga7c87723442baa681a80de8f644eda1a2", null ], + [ "CPACR_CP_Pos_", "group__CMSIS__CPACR__BITS.html#ga77dc035e6d16dee8f5cf53b36b86cfaf", null ], + [ "CPACR_D32DIS_Msk", "group__CMSIS__CPACR__BITS.html#ga96266eb6bf35c3c3f22718bd06b12d79", null ], + [ "CPACR_D32DIS_Pos", "group__CMSIS__CPACR__BITS.html#ga6df0c4e805105285e63b0f0e992bd416", null ], + [ "CPACR_TRCDIS_Msk", "group__CMSIS__CPACR__BITS.html#gab5d6ec83339e755bd3e7eacb914edf37", null ], + [ "CPACR_TRCDIS_Pos", "group__CMSIS__CPACR__BITS.html#ga6866c97020fdba42f7c287433c58d77c", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CPACR__CP.html b/docs/Core_A/html/group__CMSIS__CPACR__CP.html new file mode 100644 index 0000000..98bf02e --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPACR__CP.html @@ -0,0 +1,188 @@ + + + + + +CPACR CP field values +CMSIS-Core (Cortex-A): CPACR CP field values + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
CPACR CP field values
Coprocessor Access Control Register (CPACR)
+
+
+ +

Valid values for CPACR CP field. +More...

+ + + + + + + + + + + +

+Macros

#define CPACR_CP_NA   0U
 CPACR CPn field: Access denied. More...
 
#define CPACR_CP_PL1   1U
 CPACR CPn field: Accessible from PL1 only. More...
 
#define CPACR_CP_FA   3U
 CPACR CPn field: Full access. More...
 
+

Description

+

Defines the access rights for a coprocessor.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CPACR_CP_FA   3U
+
+

The meaning of full access is defined by the appropriate coprocessor.

+ +
+
+ +
+
+ + + + +
#define CPACR_CP_NA   0U
+
+

Any attempt to access the coprocessor generates an Undefined Instruction exception.

+ +
+
+ +
+
+ + + + +
#define CPACR_CP_PL1   1U
+
+

Any attempt to access the coprocessor from unprivileged software generates an Undefined Instruction exception.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CPACR__CP.js b/docs/Core_A/html/group__CMSIS__CPACR__CP.js new file mode 100644 index 0000000..18ee525 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPACR__CP.js @@ -0,0 +1,6 @@ +var group__CMSIS__CPACR__CP = +[ + [ "CPACR_CP_FA", "group__CMSIS__CPACR__CP.html#gaeaa29f06a74fadc7245d6bd183bad11b", null ], + [ "CPACR_CP_NA", "group__CMSIS__CPACR__CP.html#gabd03f590b34b809438eaa3df4af2e7db", null ], + [ "CPACR_CP_PL1", "group__CMSIS__CPACR__CP.html#ga8602342c0bad80f3a36d3bdee7418a46", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CPSR.html b/docs/Core_A/html/group__CMSIS__CPSR.html new file mode 100644 index 0000000..e06df4a --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPSR.html @@ -0,0 +1,239 @@ + + + + + +Current Program Status Register (CPSR) +CMSIS-Core (Cortex-A): Current Program Status Register (CPSR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
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+ + + + +
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+ +
+
+Content | +Data Structures | +Functions
+
+
Current Program Status Register (CPSR)
Core Register Access
+
+
+ +

The Current Program Status Register (CPSR) holds processor status and control information. +More...

+ + + + + + + + +

+Content

 CPSR Bits
 Bit position and mask macros.
 
 CPSR M field values
 Valid values for CPSR M field.
 
+ + + + +

+Data Structures

struct  CPSR_Type
 Bit field declaration for CPSR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_INLINE uint32_t __get_CPSR (void)
 Get CPSR (Current Program Status Register) More...
 
__STATIC_INLINE void __set_CPSR (uint32_t cpsr)
 Set CPSR (Current Program Status Register) More...
 
+

Description

+

The individual register bits have the following meaning:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31] N Negative condition code flag
[30] Z Zero condition code flag
[29] C Carry condition code flag
[28] V Overflow condition code flag
[27] Q Cumulative saturation bit
[26:25] IT[1:0] If-Then execution state bits for the Thumb IT (If-Then) instruction
[24] J Jazelle bit
[19:16] GE Greater than or Equal flags
[15:10] IT[7:2] If-Then execution state bits for the Thumb IT (If-Then) instruction
[9] E Endianness execution state bit: 0 - Little-endian, 1 - Big-endian
[8] A Asynchronous abort mask bit
[7] I IRQ mask bit
[6] F FIRQ mask bit
[5] T Thumb execution state bit
[4:0] M Mode field
+

Consider using __get_CPSR and __set_CPSR for accessing this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_CPSR (void )
+
+
Returns
CPSR Register value
+

This function returns the content of the Current Program Status Register (CPSR).

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+ +
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+ + + + + + + + +
__STATIC_INLINE void __set_CPSR (uint32_t cpsr)
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Parameters
+ + +
[in]cpsrCPSR value to set
+
+
+

This function assigns the given value to the Current Program Status Register (CPSR).

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+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CPSR.js b/docs/Core_A/html/group__CMSIS__CPSR.js new file mode 100644 index 0000000..789d976 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPSR.js @@ -0,0 +1,26 @@ +var group__CMSIS__CPSR = +[ + [ "CPSR Bits", "group__CMSIS__CPSR__BITS.html", "group__CMSIS__CPSR__BITS" ], + [ "CPSR M field values", "group__CMSIS__CPSR__M.html", "group__CMSIS__CPSR__M" ], + [ "CPSR_Type", "unionCPSR__Type.html", [ + [ "A", "unionCPSR__Type.html#a8dc2435a7c376c9b8dfdd9748c091458", null ], + [ "b", "unionCPSR__Type.html#a2e735da6b6156874d12aaceb2017da06", null ], + [ "C", "unionCPSR__Type.html#aa967d0e42ed00bd886b2c6df6f49a7e2", null ], + [ "E", "unionCPSR__Type.html#a96bd175ed9927279dba40e76259dcfa7", null ], + [ "F", "unionCPSR__Type.html#a20bbf5d5ba32cae380b7f181cf306f9e", null ], + [ "GE", "unionCPSR__Type.html#acc18314a4088adfb93a9662c76073704", null ], + [ "I", "unionCPSR__Type.html#a0d277e8b4d2147137407f526aa9e3214", null ], + [ "IT0", "unionCPSR__Type.html#a5299532c92c92babc22517a433686b95", null ], + [ "IT1", "unionCPSR__Type.html#a8bdd87822e3c00b3742c94a42b0654b9", null ], + [ "J", "unionCPSR__Type.html#a5d4e06d8dba8f512c54b16bfa7150d9d", null ], + [ "M", "unionCPSR__Type.html#a2bc38ab81bc2e2fd111526a58f94511f", null ], + [ "N", "unionCPSR__Type.html#a26907b41c086a9f9e7b8c7051481c643", null ], + [ "Q", "unionCPSR__Type.html#a0bdcd0ceaa1ecb8f55ea15075974eb5a", null ], + [ "T", "unionCPSR__Type.html#ac5ec7329b5be4722abc3cef6ef2e9c1b", null ], + [ "V", "unionCPSR__Type.html#aba74c9da04be21f1266d3816af79f8c3", null ], + [ "w", "unionCPSR__Type.html#afd5ed10bab25f324a6fbb3e124d16fc9", null ], + [ "Z", "unionCPSR__Type.html#a790f1950658257a87ac58d132eca9849", null ] + ] ], + [ "__get_CPSR", "group__CMSIS__CPSR.html#ga0308d7d313bced36c3d1a4c2f9741186", null ], + [ "__set_CPSR", "group__CMSIS__CPSR.html#gaf87faa3453333bcac5667fb1ccfc7f61", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CPSR__BITS.html b/docs/Core_A/html/group__CMSIS__CPSR__BITS.html new file mode 100644 index 0000000..5ec25ff --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPSR__BITS.html @@ -0,0 +1,589 @@ + + + + + +CPSR Bits +CMSIS-Core (Cortex-A): CPSR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
CPSR Bits
Current Program Status Register (CPSR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CPSR_N_Pos   31U
 CPSR: N Position. More...
 
#define CPSR_N_Msk   (1UL << CPSR_N_Pos)
 CPSR: N Mask. More...
 
#define CPSR_Z_Pos   30U
 CPSR: Z Position. More...
 
#define CPSR_Z_Msk   (1UL << CPSR_Z_Pos)
 CPSR: Z Mask. More...
 
#define CPSR_C_Pos   29U
 CPSR: C Position. More...
 
#define CPSR_C_Msk   (1UL << CPSR_C_Pos)
 CPSR: C Mask. More...
 
#define CPSR_V_Pos   28U
 CPSR: V Position. More...
 
#define CPSR_V_Msk   (1UL << CPSR_V_Pos)
 CPSR: V Mask. More...
 
#define CPSR_Q_Pos   27U
 CPSR: Q Position. More...
 
#define CPSR_Q_Msk   (1UL << CPSR_Q_Pos)
 CPSR: Q Mask. More...
 
#define CPSR_IT0_Pos   25U
 CPSR: IT0 Position. More...
 
#define CPSR_IT0_Msk   (3UL << CPSR_IT0_Pos)
 CPSR: IT0 Mask. More...
 
#define CPSR_J_Pos   24U
 CPSR: J Position. More...
 
#define CPSR_J_Msk   (1UL << CPSR_J_Pos)
 CPSR: J Mask. More...
 
#define CPSR_GE_Pos   16U
 CPSR: GE Position. More...
 
#define CPSR_GE_Msk   (0xFUL << CPSR_GE_Pos)
 CPSR: GE Mask. More...
 
#define CPSR_IT1_Pos   10U
 CPSR: IT1 Position. More...
 
#define CPSR_IT1_Msk   (0x3FUL << CPSR_IT1_Pos)
 CPSR: IT1 Mask. More...
 
#define CPSR_E_Pos   9U
 CPSR: E Position. More...
 
#define CPSR_E_Msk   (1UL << CPSR_E_Pos)
 CPSR: E Mask. More...
 
#define CPSR_A_Pos   8U
 CPSR: A Position. More...
 
#define CPSR_A_Msk   (1UL << CPSR_A_Pos)
 CPSR: A Mask. More...
 
#define CPSR_I_Pos   7U
 CPSR: I Position. More...
 
#define CPSR_I_Msk   (1UL << CPSR_I_Pos)
 CPSR: I Mask. More...
 
#define CPSR_F_Pos   6U
 CPSR: F Position. More...
 
#define CPSR_F_Msk   (1UL << CPSR_F_Pos)
 CPSR: F Mask. More...
 
#define CPSR_T_Pos   5U
 CPSR: T Position. More...
 
#define CPSR_T_Msk   (1UL << CPSR_T_Pos)
 CPSR: T Mask. More...
 
#define CPSR_M_Pos   0U
 CPSR: M Position. More...
 
#define CPSR_M_Msk   (0x1FUL << CPSR_M_Pos)
 CPSR: M Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CPSR_A_Msk   (1UL << CPSR_A_Pos)
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#define CPSR_A_Pos   8U
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#define CPSR_C_Msk   (1UL << CPSR_C_Pos)
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#define CPSR_C_Pos   29U
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+ + + + +
#define CPSR_E_Msk   (1UL << CPSR_E_Pos)
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+ + + + +
#define CPSR_E_Pos   9U
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+ + + + +
#define CPSR_F_Msk   (1UL << CPSR_F_Pos)
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+ + + + +
#define CPSR_F_Pos   6U
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#define CPSR_GE_Msk   (0xFUL << CPSR_GE_Pos)
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+ + + + +
#define CPSR_GE_Pos   16U
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+ + + + +
#define CPSR_I_Msk   (1UL << CPSR_I_Pos)
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+ + + + +
#define CPSR_I_Pos   7U
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+ + + + +
#define CPSR_IT0_Msk   (3UL << CPSR_IT0_Pos)
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+ + + + +
#define CPSR_IT0_Pos   25U
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#define CPSR_IT1_Msk   (0x3FUL << CPSR_IT1_Pos)
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+ + + + +
#define CPSR_IT1_Pos   10U
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#define CPSR_J_Msk   (1UL << CPSR_J_Pos)
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+ +
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+ + + + +
#define CPSR_J_Pos   24U
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+ + + + +
#define CPSR_M_Msk   (0x1FUL << CPSR_M_Pos)
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+ +
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+ +
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+ + + + +
#define CPSR_M_Pos   0U
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+ +
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+ + + + +
#define CPSR_N_Msk   (1UL << CPSR_N_Pos)
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+ +
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+ +
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+ + + + +
#define CPSR_N_Pos   31U
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+ + + + +
#define CPSR_Q_Msk   (1UL << CPSR_Q_Pos)
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+ +
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+ + + + +
#define CPSR_Q_Pos   27U
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#define CPSR_T_Msk   (1UL << CPSR_T_Pos)
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+ + + + +
#define CPSR_T_Pos   5U
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#define CPSR_V_Msk   (1UL << CPSR_V_Pos)
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+ +
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+ +
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+ + + + +
#define CPSR_V_Pos   28U
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+ + + + +
#define CPSR_Z_Msk   (1UL << CPSR_Z_Pos)
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+ +
+
+ +
+
+ + + + +
#define CPSR_Z_Pos   30U
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+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CPSR__BITS.js b/docs/Core_A/html/group__CMSIS__CPSR__BITS.js new file mode 100644 index 0000000..f1eafdd --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPSR__BITS.js @@ -0,0 +1,33 @@ +var group__CMSIS__CPSR__BITS = +[ + [ "CPSR_A_Msk", "group__CMSIS__CPSR__BITS.html#ga002803fa282333e0ead5c9b4cf748cb1", null ], + [ "CPSR_A_Pos", "group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b", null ], + [ "CPSR_C_Msk", "group__CMSIS__CPSR__BITS.html#ga3bc30b14b9b0bf113600eb882304244c", null ], + [ "CPSR_C_Pos", "group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131", null ], + [ "CPSR_E_Msk", "group__CMSIS__CPSR__BITS.html#ga6661712dd33a50ce4a42e13bf72aa35b", null ], + [ "CPSR_E_Pos", "group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f", null ], + [ "CPSR_F_Msk", "group__CMSIS__CPSR__BITS.html#ga4df09481ffd9dfb17823a8e9895b1566", null ], + [ "CPSR_F_Pos", "group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62", null ], + [ "CPSR_GE_Msk", "group__CMSIS__CPSR__BITS.html#ga9a3a6a87437892954cb37662ff27521a", null ], + [ "CPSR_GE_Pos", "group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760", null ], + [ "CPSR_I_Msk", "group__CMSIS__CPSR__BITS.html#gad9abe93ba1179e254a70e325cb1a5834", null ], + [ "CPSR_I_Pos", "group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59", null ], + [ "CPSR_IT0_Msk", "group__CMSIS__CPSR__BITS.html#ga128366788d0f94d52fbe4610162c97e5", null ], + [ "CPSR_IT0_Pos", "group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87", null ], + [ "CPSR_IT1_Msk", "group__CMSIS__CPSR__BITS.html#ga791263c8a9707795b5824dae5485cd39", null ], + [ "CPSR_IT1_Pos", "group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5", null ], + [ "CPSR_J_Msk", "group__CMSIS__CPSR__BITS.html#ga6b52a05ec2e95ade71b65090f19285c2", null ], + [ "CPSR_J_Pos", "group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990", null ], + [ "CPSR_M_Msk", "group__CMSIS__CPSR__BITS.html#gadce47959b814f70f802a139250daa04c", null ], + [ "CPSR_M_Pos", "group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1", null ], + [ "CPSR_N_Msk", "group__CMSIS__CPSR__BITS.html#ga6c4a636a3b5ec71e0f2eb021ac353544", null ], + [ "CPSR_N_Pos", "group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84", null ], + [ "CPSR_Q_Msk", "group__CMSIS__CPSR__BITS.html#gaba36b1ac0438594afdc6eef220d2e146", null ], + [ "CPSR_Q_Pos", "group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7", null ], + [ "CPSR_T_Msk", "group__CMSIS__CPSR__BITS.html#ga23ed422711cbd2f9a5dcbe6c05b2a720", null ], + [ "CPSR_T_Pos", "group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c", null ], + [ "CPSR_V_Msk", "group__CMSIS__CPSR__BITS.html#ga9b9fe5c1da5e922cbff18215b70b4252", null ], + [ "CPSR_V_Pos", "group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5", null ], + [ "CPSR_Z_Msk", "group__CMSIS__CPSR__BITS.html#gab091112988009fb8360b01c79d993f67", null ], + [ "CPSR_Z_Pos", "group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__CPSR__M.html b/docs/Core_A/html/group__CMSIS__CPSR__M.html new file mode 100644 index 0000000..8f42b37 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPSR__M.html @@ -0,0 +1,284 @@ + + + + + +CPSR M field values +CMSIS-Core (Cortex-A): CPSR M field values + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
CPSR M field values
Current Program Status Register (CPSR)
+
+
+ +

Valid values for CPSR M field. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define CPSR_M_USR   0x10U
 CPSR: M User mode (PL0) More...
 
#define CPSR_M_FIQ   0x11U
 CPSR: M Fast Interrupt mode (PL1) More...
 
#define CPSR_M_IRQ   0x12U
 CPSR: M Interrupt mode (PL1) More...
 
#define CPSR_M_SVC   0x13U
 CPSR: M Supervisor mode (PL1) More...
 
#define CPSR_M_MON   0x16U
 CPSR: M Monitor mode (PL1) More...
 
#define CPSR_M_ABT   0x17U
 CPSR: M Abort mode (PL1) More...
 
#define CPSR_M_HYP   0x1AU
 CPSR: M Hypervisor mode (PL2) More...
 
#define CPSR_M_UND   0x1BU
 CPSR: M Undefined mode (PL1) More...
 
#define CPSR_M_SYS   0x1FU
 CPSR: M System mode (PL1) More...
 
+

Description

+

The M field can contain one of these values which indicates the current processor mode.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define CPSR_M_ABT   0x17U
+
+

Abort mode is the default mode to which a Data Abort exception or Prefetch Abort exception is taken.

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+ + + + +
#define CPSR_M_FIQ   0x11U
+
+

FIQ mode is the default mode to which an FIQ interrupt is taken.

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+ + + + +
#define CPSR_M_HYP   0x1AU
+
+

Hyp mode is the Non-secure PL2 mode, implemented as part of the Virtualization Extensions. Hyp mode is entered on taking an exception from Non-secure state that must be taken to PL2.

+ +
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+ + + + +
#define CPSR_M_IRQ   0x12U
+
+

IRQ mode is the default mode to which an IRQ interrupt is taken.

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+ + + + +
#define CPSR_M_MON   0x16U
+
+

Monitor mode is the mode to which a Secure Monitor Call exception is taken.

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#define CPSR_M_SVC   0x13U
+
+

Supervisor mode is the default mode to which a Supervisor Call exception is taken.

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#define CPSR_M_SYS   0x1FU
+
+

Software executing in System mode executes at PL1. System mode has the same registers available as User mode, and is not entered by any exception.

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#define CPSR_M_UND   0x1BU
+
+

Undefined mode is the default mode to which an instruction-related exception, including any attempt to execute an UNDEFINED instruction, is taken.

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+ +
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+ + + + +
#define CPSR_M_USR   0x10U
+
+

An operating system runs applications in User mode to restrict the use of system resources. Software executing in User mode executes at PL0. Execution in User mode is sometimes described as unprivileged execution.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__CPSR__M.js b/docs/Core_A/html/group__CMSIS__CPSR__M.js new file mode 100644 index 0000000..789e440 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__CPSR__M.js @@ -0,0 +1,12 @@ +var group__CMSIS__CPSR__M = +[ + [ "CPSR_M_ABT", "group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa", null ], + [ "CPSR_M_FIQ", "group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74", null ], + [ "CPSR_M_HYP", "group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988", null ], + [ "CPSR_M_IRQ", "group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db", null ], + [ "CPSR_M_MON", "group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098", null ], + [ "CPSR_M_SVC", "group__CMSIS__CPSR__M.html#ga5afcb85bd2968acc2b09cb9d99c531ad", null ], + [ "CPSR_M_SYS", "group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c", null ], + [ "CPSR_M_UND", "group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef", null ], + [ "CPSR_M_USR", "group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html b/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html new file mode 100644 index 0000000..34277fd --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html @@ -0,0 +1,171 @@ + + + + + +Core Peripherals +CMSIS-Core (Cortex-A): Core Peripherals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
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+ +
+ + + + +
+ +
+ +
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+Content
+
+
Core Peripherals
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+ + + + + + + + + + + + + + + + + + + + + + + +

+Content

 Generic Interrupt Controller Functions
 The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).
 
 L1 Cache Functions
 L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache.
 
 L2C-310 Cache Controller Functions
 L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.
+Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual.
 
 Generic Physical Timer Functions
 Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.
+Reference: Cortex-A7 MPCore Technical Reference Manual.
 
 Private Timer Functions
 Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.
+References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual.
 
 Memory Management Unit Functions
 MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition.
 
 Floating Point Unit Functions
 FPU Functions enable the use of Floating Point instructions and extensions.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition.
 
+

Description

+

Hardware Abstraction Layer. The Core-A function interface contains:

+ +
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.js b/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.js new file mode 100644 index 0000000..93b8aa3 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.js @@ -0,0 +1,10 @@ +var group__CMSIS__Core__FunctionInterface = +[ + [ "Generic Interrupt Controller Functions", "group__GIC__functions.html", "group__GIC__functions" ], + [ "L1 Cache Functions", "group__L1__cache__functions.html", "group__L1__cache__functions" ], + [ "L2C-310 Cache Controller Functions", "group__L2__cache__functions.html", "group__L2__cache__functions" ], + [ "Generic Physical Timer Functions", "group__PL1__timer__functions.html", "group__PL1__timer__functions" ], + [ "Private Timer Functions", "group__PTM__timer__functions.html", "group__PTM__timer__functions" ], + [ "Memory Management Unit Functions", "group__MMU__functions.html", "group__MMU__functions" ], + [ "Floating Point Unit Functions", "group__FPU__functions.html", "group__FPU__functions" ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__Core__InstructionInterface.html b/docs/Core_A/html/group__CMSIS__Core__InstructionInterface.html new file mode 100644 index 0000000..d2e61a1 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__Core__InstructionInterface.html @@ -0,0 +1,464 @@ + + + + + +Intrinsic Functions +CMSIS-Core (Cortex-A): Intrinsic Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Functions
+
+
Intrinsic Functions
+
+
+ +

Functions that generate specific Cortex-A CPU Instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define __NOP   __nop
 No Operation. More...
 
#define __WFI   __wfi
 Wait For Interrupt. More...
 
#define __WFE   __wfe
 Wait For Event. More...
 
#define __SEV   __sev
 Send Event. More...
 
#define __ISB()
 Instruction Synchronization Barrier. More...
 
#define __DSB()
 Data Synchronization Barrier. More...
 
#define __DMB()
 Data Memory Barrier. More...
 
#define __BKPT(value)   __breakpoint(value)
 Breakpoint. More...
 
+ + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit) More...
 
uint16_t __REV16 (uint16_t value)
 Reverse byte order (16 bit) More...
 
int32_t __REVSH (int32_t value)
 Reverse byte order (16 bit) More...
 
uint32_t __ROR (uint32_t op1, uint32_t op2)
 Rotate Right in unsigned value (32 bit) More...
 
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value. More...
 
uint8_t __CLZ (uint32_t value)
 Count leading zeros. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define __BKPT( value)   __breakpoint(value)
+
+

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+
Parameters
+ + +
[in]valueis ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
+
+
+ +
+
+ +
+
+ + + + + + + +
#define __DMB()
+
+

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

+ +
+
+ +
+
+ + + + + + + +
#define __DSB()
+
+

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

+ +
+
+ +
+
+ + + + + + + +
#define __ISB()
+
+

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

+ +
+
+ +
+
+ + + + +
#define __NOP   __nop
+
+

No Operation does nothing. This instruction can be used for code alignment purposes.

+ +
+
+ +
+
+ + + + +
#define __SEV   __sev
+
+

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ +
+
+ +
+
+ + + + +
#define __WFE   __wfe
+
+

Wait For Event is a hint instruction that permits the processor to enter

+ +
+
+ +
+
+ + + + +
#define __WFI   __wfi
+
+

Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
uint8_t __CLZ (uint32_t value)
+
+

Counts the number of leading zeros of a data value.

+
Parameters
+ + +
[in]valueValue to count the leading zeros
+
+
+
Returns
number of leading zeros in value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __RBIT (uint32_t value)
+
+

Reverses the bit order of the given value.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __REV (uint32_t value)
+
+

Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
uint16_t __REV16 (uint16_t value)
+
+

Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
int32_t __REVSH (int32_t value)
+
+

Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __ROR (uint32_t op1,
uint32_t op2 
)
+
+

Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

+
Parameters
+ + + +
[in]op1Value to rotate
[in]op2Number of Bits to rotate
+
+
+
Returns
Rotated value
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__Core__InstructionInterface.js b/docs/Core_A/html/group__CMSIS__Core__InstructionInterface.js new file mode 100644 index 0000000..0f88b5c --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__Core__InstructionInterface.js @@ -0,0 +1,17 @@ +var group__CMSIS__Core__InstructionInterface = +[ + [ "__BKPT", "group__CMSIS__Core__InstructionInterface.html#ga15ea6bd3c507d3e81c3b3a1258e46397", null ], + [ "__DMB", "group__CMSIS__Core__InstructionInterface.html#ga671101179b5943990785f36f8c1e2269", null ], + [ "__DSB", "group__CMSIS__Core__InstructionInterface.html#ga067d257a2b34565410acefb5afef2203", null ], + [ "__ISB", "group__CMSIS__Core__InstructionInterface.html#gaad233022e850a009fc6f7602be1182f6", null ], + [ "__NOP", "group__CMSIS__Core__InstructionInterface.html#gabd585ddc865fb9b7f2493af1eee1a572", null ], + [ "__SEV", "group__CMSIS__Core__InstructionInterface.html#gaab4f296d0022b4b10dc0976eb22052f9", null ], + [ "__WFE", "group__CMSIS__Core__InstructionInterface.html#gaac6cc7dd4325d9cb40d3290fa5244b3d", null ], + [ "__WFI", "group__CMSIS__Core__InstructionInterface.html#gad23bf2b78a9a4524157c9de0d30b7448", null ], + [ "__CLZ", "group__CMSIS__Core__InstructionInterface.html#ga90884c591ac5d73d6069334eba9d6c02", null ], + [ "__RBIT", "group__CMSIS__Core__InstructionInterface.html#gad6f9f297f6b91a995ee199fbc796b863", null ], + [ "__REV", "group__CMSIS__Core__InstructionInterface.html#ga4717abc17af5ba29b1e4c055e0a0d9b8", null ], + [ "__REV16", "group__CMSIS__Core__InstructionInterface.html#ga926d702cf1de59d54f4e62ab8e3c8b8d", null ], + [ "__REVSH", "group__CMSIS__Core__InstructionInterface.html#ga1ec006e6d79063363cb0c2a2e0b3adbe", null ], + [ "__ROR", "group__CMSIS__Core__InstructionInterface.html#gae05c1a2dac5bb7a399420c804c3048ca", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__DACR.html b/docs/Core_A/html/group__CMSIS__DACR.html new file mode 100644 index 0000000..6b2de47 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DACR.html @@ -0,0 +1,235 @@ + + + + + +Domain Access Control Register (DACR) +CMSIS-Core (Cortex-A): Domain Access Control Register (DACR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Functions
+
+
Domain Access Control Register (DACR)
Core Register Access
+
+
+ +

DACR defines the access permission for each of the sixteen memory domains. +More...

+ + + + + + + + +

+Content

 DACR Bits
 Bit position and mask macros.
 
 DACR Dn field values
 Valid values for DACR Dn field.
 
+ + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_DACR (void)
 Get DACR. More...
 
__STATIC_FORCEINLINE void __set_DACR (uint32_t dacr)
 Set DACR. More...
 
+

Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:30] D15 Domain 15 access permission.
[29:28] D14 Domain 14 access permission.
[27:26] D13 Domain 13 access permission.
[25:24] D12 Domain 12 access permission.
[23:22] D11 Domain 11 access permission.
[21:20] D10 Domain 10 access permission.
[19:18] D9 Domain 9 access permission.
[17:16] D8 Domain 8 access permission.
[15:14] D7 Domain 7 access permission.
[13:12] D6 Domain 6 access permission.
[11:10] D5 Domain 5 access permission.
[9:8] D4 Domain 4 access permission.
[7:6] D3 Domain 3 access permission.
[5:4] D2 Domain 2 access permission.
[3:2] D1 Domain 1 access permission.
[1:0] D0 Domain 0 access permission.
+

Consider __get_DACR and __set_DACR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_DACR (void )
+
+

This function returns the value of the Domain Access Control Register.

+
Returns
Domain Access Control Register value
+

This function returns the value of the Domain Access Control Register (DACR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_DACR (uint32_t dacr)
+
+

This function assigns the given value to the Domain Access Control Register.

+
Parameters
+ + +
[in]dacrDomain Access Control Register value to set
+
+
+

This function assigns the given value to the Domain Access Control Register (DACR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__DACR.js b/docs/Core_A/html/group__CMSIS__DACR.js new file mode 100644 index 0000000..fbdaa25 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DACR.js @@ -0,0 +1,7 @@ +var group__CMSIS__DACR = +[ + [ "DACR Bits", "group__CMSIS__DACR__BITS.html", "group__CMSIS__DACR__BITS" ], + [ "DACR Dn field values", "group__CMSIS__DACR__Dn.html", "group__CMSIS__DACR__Dn" ], + [ "__get_DACR", "group__CMSIS__DACR.html#ga10278deb975c653555ee70178546aaa6", null ], + [ "__set_DACR", "group__CMSIS__DACR.html#ga72e050de5b19cd6b683f6c234968b78b", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__DACR__BITS.html b/docs/Core_A/html/group__CMSIS__DACR__BITS.html new file mode 100644 index 0000000..26d05a2 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DACR__BITS.html @@ -0,0 +1,185 @@ + + + + + +DACR Bits +CMSIS-Core (Cortex-A): DACR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
DACR Bits
Domain Access Control Register (DACR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + +

+Macros

#define DACR_D_Pos_(n)   (2U*n)
 DACR: Dn Position. More...
 
#define DACR_D_Msk_(n)   (3UL << DACR_D_Pos_(n))
 DACR: Dn Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define DACR_D_Msk_( n)   (3UL << DACR_D_Pos_(n))
+
+

Get the bit mask for domain n access permission.

+

Example:

+
// clear access permission for domain 7
+
__set_DACR(__get_DACR() & ~DACR_D_Msk_(7));
+
+
+
+ +
+
+ + + + + + + + +
#define DACR_D_Pos_( n)   (2U*n)
+
+

Get the bit position for domain n access permission.

+

Example:

+
// retrieve access permission for domain 5
+
uint32_t domain5 = (__get_DACR() & DACR_D_Msk_(5)) >> DACR_D_Pos_(5);
+
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__DACR__BITS.js b/docs/Core_A/html/group__CMSIS__DACR__BITS.js new file mode 100644 index 0000000..536ab6c --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DACR__BITS.js @@ -0,0 +1,5 @@ +var group__CMSIS__DACR__BITS = +[ + [ "DACR_D_Msk_", "group__CMSIS__DACR__BITS.html#ga41b90c8a7338fbe5e5b06be083ba22fe", null ], + [ "DACR_D_Pos_", "group__CMSIS__DACR__BITS.html#ga2c014e929b74e6ded5e89a74903ce975", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__DACR__Dn.html b/docs/Core_A/html/group__CMSIS__DACR__Dn.html new file mode 100644 index 0000000..e57a7b2 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DACR__Dn.html @@ -0,0 +1,188 @@ + + + + + +DACR Dn field values +CMSIS-Core (Cortex-A): DACR Dn field values + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
DACR Dn field values
Domain Access Control Register (DACR)
+
+
+ +

Valid values for DACR Dn field. +More...

+ + + + + + + + + + + +

+Macros

#define DACR_Dn_NOACCESS   0U
 DACR Dn field: No access. More...
 
#define DACR_Dn_CLIENT   1U
 DACR Dn field: Client. More...
 
#define DACR_Dn_MANAGER   3U
 DACR Dn field: Manager. More...
 
+

Description

+

The Dn field can contain one of these values which indicates the domain n access permission.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DACR_Dn_CLIENT   1U
+
+

Accesses are checked against the permission bits in the translation tables.

+ +
+
+ +
+
+ + + + +
#define DACR_Dn_MANAGER   3U
+
+

Accesses are not checked against the permission bits in the translation tables.

+ +
+
+ +
+
+ + + + +
#define DACR_Dn_NOACCESS   0U
+
+

Any access to the domain generates a Domain fault.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__DACR__Dn.js b/docs/Core_A/html/group__CMSIS__DACR__Dn.js new file mode 100644 index 0000000..636768e --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DACR__Dn.js @@ -0,0 +1,6 @@ +var group__CMSIS__DACR__Dn = +[ + [ "DACR_Dn_CLIENT", "group__CMSIS__DACR__Dn.html#gac76e6128758cd64a9fa92487ec49441b", null ], + [ "DACR_Dn_MANAGER", "group__CMSIS__DACR__Dn.html#gabbf27724d67055138bf7abdb651e9732", null ], + [ "DACR_Dn_NOACCESS", "group__CMSIS__DACR__Dn.html#ga281ebf97decb4ef4f7b1e5c4285c45ab", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__DFSR.html b/docs/Core_A/html/group__CMSIS__DFSR.html new file mode 100644 index 0000000..0278007 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DFSR.html @@ -0,0 +1,245 @@ + + + + + +Data Fault Status Register (DFSR) +CMSIS-Core (Cortex-A): Data Fault Status Register (DFSR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Functions
+
+
Data Fault Status Register (DFSR)
Core Register Access
+
+
+ +

The DFSR holds status information about the last data fault. +More...

+ + + + + +

+Content

 ACTLR Bits
 Bit position and mask macros.
 
+ + + + +

+Data Structures

struct  DFSR_Type
 Bit field declaration for DFSR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_DFSR (void)
 Get DFSR. More...
 
__STATIC_FORCEINLINE void __set_DFSR (uint32_t dfsr)
 Set DFSR. More...
 
+

Description

+

DFSR format when using the Short-descriptor translation table format

+ + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:14] - Reserved.
[13] CM Cache maintenance fault.
[12] ExT External abort type.
[11] WnR Write not Read bit.
[10] FS[4] Fault status bits.
[9] LPAE Large Physical Address Extension.
[8] - Reserved.
[7:4] Domain The domain of the fault address.
[3:0] FS[3:0] Fault status bits.
+

DFSR format when using the Long-descriptor translation table format

+ + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:14] - Reserved.
[13] CM Cache maintenance fault.
[12] ExT External abort type.
[11] WnR Write not Read bit.
[10] - Reserved.
[9] LPAE Large Physical Address Extension.
[8:6] - Reserved.
[5:0] STATUS Fault status bits.
+

Consider __get_DFSR and __set_DFSR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_DFSR (void )
+
+
Returns
Data Fault Status Register value
+

This function returns the current value of the Data Fault Status Register (DFSR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_DFSR (uint32_t dfsr)
+
+
Parameters
+ + +
[in]dfsrData Fault Status value to set
+
+
+

This function assigns the given value to the Data Fault Status Register (DFSR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__DFSR.js b/docs/Core_A/html/group__CMSIS__DFSR.js new file mode 100644 index 0000000..c219c80 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DFSR.js @@ -0,0 +1,19 @@ +var group__CMSIS__DFSR = +[ + [ "ACTLR Bits", "group__CMSIS__DFSR__BITS.html", "group__CMSIS__DFSR__BITS" ], + [ "DFSR_Type", "unionDFSR__Type.html", [ + [ "CM", "unionDFSR__Type.html#a38562a26cc210ea4c39c6b951c4a5b62", null ], + [ "Domain", "unionDFSR__Type.html#a38982c7088a4069f8a4b347f5eb400e9", null ], + [ "ExT", "unionDFSR__Type.html#aede34079d030df1977646c155a90f445", null ], + [ "FS0", "unionDFSR__Type.html#af29edf59ecfd29848b69e2bbfb7f3082", null ], + [ "FS1", "unionDFSR__Type.html#a869658f432d5e213b8cd55e8e58d1f56", null ], + [ "l", "unionDFSR__Type.html#a583e3138696be655c46f297e083ece52", null ], + [ "LPAE", "unionDFSR__Type.html#add7c7800b87cabdb4a9ecdf41e4469a7", null ], + [ "s", "unionDFSR__Type.html#a54c2eb668436a0f15d781265ceaa8c58", null ], + [ "STATUS", "unionDFSR__Type.html#a4cb3ba7b8c8075bfbff792b7e5b88103", null ], + [ "w", "unionDFSR__Type.html#ad827a36e38ce2dee796835122ae95dd2", null ], + [ "WnR", "unionDFSR__Type.html#a0512860c27723cd35f0abdaa68be9935", null ] + ] ], + [ "__get_DFSR", "group__CMSIS__DFSR.html#ga9897e96a6ccb50199d4968fd45ab7962", null ], + [ "__set_DFSR", "group__CMSIS__DFSR.html#ga824a3e4ae371ef38641375f9fa4cc29c", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__DFSR__BITS.html b/docs/Core_A/html/group__CMSIS__DFSR__BITS.html new file mode 100644 index 0000000..178ae64 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DFSR__BITS.html @@ -0,0 +1,379 @@ + + + + + +ACTLR Bits +CMSIS-Core (Cortex-A): ACTLR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
ACTLR Bits
Data Fault Status Register (DFSR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define DFSR_CM_Pos   13U
 DFSR: CM Position. More...
 
#define DFSR_CM_Msk   (1UL << DFSR_CM_Pos)
 DFSR: CM Mask. More...
 
#define DFSR_Ext_Pos   12U
 DFSR: Ext Position. More...
 
#define DFSR_Ext_Msk   (1UL << DFSR_Ext_Pos)
 DFSR: Ext Mask. More...
 
#define DFSR_WnR_Pos   11U
 DFSR: WnR Position. More...
 
#define DFSR_WnR_Msk   (1UL << DFSR_WnR_Pos)
 DFSR: WnR Mask. More...
 
#define DFSR_LPAE_Pos   9U
 DFSR: LPAE Position. More...
 
#define DFSR_LPAE_Msk   (1UL << DFSR_LPAE_Pos)
 DFSR: LPAE Mask. More...
 
#define DFSR_FS1_Pos   10U
 DFSR: FS1 Position. More...
 
#define DFSR_FS1_Msk   (1UL << DFSR_FS1_Pos)
 DFSR: FS1 Mask. More...
 
#define DFSR_Domain_Pos   4U
 DFSR: Domain Position. More...
 
#define DFSR_Domain_Msk   (0xFUL << DFSR_Domain_Pos)
 DFSR: Domain Mask. More...
 
#define DFSR_FS0_Pos   0U
 DFSR: FS0 Position. More...
 
#define DFSR_FS0_Msk   (0xFUL << DFSR_FS0_Pos)
 DFSR: FS0 Mask. More...
 
#define DFSR_STATUS_Pos   0U
 DFSR: STATUS Position. More...
 
#define DFSR_STATUS_Msk   (0x3FUL << DFSR_STATUS_Pos)
 DFSR: STATUS Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DFSR_CM_Msk   (1UL << DFSR_CM_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_CM_Pos   13U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_Domain_Msk   (0xFUL << DFSR_Domain_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_Domain_Pos   4U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_Ext_Msk   (1UL << DFSR_Ext_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_Ext_Pos   12U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_FS0_Msk   (0xFUL << DFSR_FS0_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_FS0_Pos   0U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_FS1_Msk   (1UL << DFSR_FS1_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_FS1_Pos   10U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_LPAE_Msk   (1UL << DFSR_LPAE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_LPAE_Pos   9U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_STATUS_Msk   (0x3FUL << DFSR_STATUS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_STATUS_Pos   0U
+
+ +
+
+ +
+
+ + + + +
#define DFSR_WnR_Msk   (1UL << DFSR_WnR_Pos)
+
+ +
+
+ +
+
+ + + + +
#define DFSR_WnR_Pos   11U
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__DFSR__BITS.js b/docs/Core_A/html/group__CMSIS__DFSR__BITS.js new file mode 100644 index 0000000..f50c8d5 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__DFSR__BITS.js @@ -0,0 +1,19 @@ +var group__CMSIS__DFSR__BITS = +[ + [ "DFSR_CM_Msk", "group__CMSIS__DFSR__BITS.html#ga91cf285dc43beda62ae72f043e83238c", null ], + [ "DFSR_CM_Pos", "group__CMSIS__DFSR__BITS.html#gac1c7d8f30e77bd1fe395d6e9a5a63a3e", null ], + [ "DFSR_Domain_Msk", "group__CMSIS__DFSR__BITS.html#ga59949776e069a5af7231ef63156f17cf", null ], + [ "DFSR_Domain_Pos", "group__CMSIS__DFSR__BITS.html#gac5a7afc43963dbc429792fb5a1569e15", null ], + [ "DFSR_Ext_Msk", "group__CMSIS__DFSR__BITS.html#gad3a97b4eb87f45df8ae539e59592f21b", null ], + [ "DFSR_Ext_Pos", "group__CMSIS__DFSR__BITS.html#ga8cc8dcb1b3a971a13b0575bf9083acf5", null ], + [ "DFSR_FS0_Msk", "group__CMSIS__DFSR__BITS.html#ga23b688e81c0378b5cd75acb53896bb5e", null ], + [ "DFSR_FS0_Pos", "group__CMSIS__DFSR__BITS.html#gae5d9bc62e71693bd9dc2a84bb4c82082", null ], + [ "DFSR_FS1_Msk", "group__CMSIS__DFSR__BITS.html#ga6540a3ca5b2dcf8f81bb37fbdbe9d746", null ], + [ "DFSR_FS1_Pos", "group__CMSIS__DFSR__BITS.html#ga3faee10970931cadf7ff16069ce65a1a", null ], + [ "DFSR_LPAE_Msk", "group__CMSIS__DFSR__BITS.html#ga104bfa1e333340616fdbdc804948276f", null ], + [ "DFSR_LPAE_Pos", "group__CMSIS__DFSR__BITS.html#ga10f7b48c4f128c9be07c377bb60cfa7a", null ], + [ "DFSR_STATUS_Msk", "group__CMSIS__DFSR__BITS.html#ga7541052737038d737fd9fe00b9815140", null ], + [ "DFSR_STATUS_Pos", "group__CMSIS__DFSR__BITS.html#gacb6fae1908b12c4900e2cdcc320c6c11", null ], + [ "DFSR_WnR_Msk", "group__CMSIS__DFSR__BITS.html#gabfbf482895e7620fe6727b54378c0f2a", null ], + [ "DFSR_WnR_Pos", "group__CMSIS__DFSR__BITS.html#ga410420633e9ba47cdd1ae2d3df146866", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__FPEXC.html b/docs/Core_A/html/group__CMSIS__FPEXC.html new file mode 100644 index 0000000..6dcee3f --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__FPEXC.html @@ -0,0 +1,197 @@ + + + + + +Floating-Point Exception Control register (FPEXC) +CMSIS-Core (Cortex-A): Floating-Point Exception Control register (FPEXC) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Floating-Point Exception Control register (FPEXC)
Core Register Access
+
+
+ +

Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded. +More...

+ + + + + + + + +

+Functions

__STATIC_INLINE uint32_t __get_FPEXC (void)
 Get FPEXC (Floating Point Exception Control Register) More...
 
__STATIC_INLINE void __set_FPEXC (uint32_t fpexc)
 Set FPEXC (Floating Point Exception Control Register) More...
 
+

Description

+ + + + + + + + + +
Bits Name Function
[31] EX Exception bit.
[30] EN Enable bit.
[29:0] - SUBARCHITECTURE DEFINED.
+

Consider __get_FPEXC and __set_FPEXC to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_FPEXC (void )
+
+
Returns
Floating Point Exception Control Register value
+

This function returns the current value of the Floating-Point Exception Control register (FPEXC).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_FPEXC (uint32_t fpexc)
+
+
Parameters
+ + +
[in]fpexcFloating Point Exception Control value to set
+
+
+

This function assigns the given value to the Floating-Point Exception Control register (FPEXC).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__FPEXC.js b/docs/Core_A/html/group__CMSIS__FPEXC.js new file mode 100644 index 0000000..51c239a --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__FPEXC.js @@ -0,0 +1,5 @@ +var group__CMSIS__FPEXC = +[ + [ "__get_FPEXC", "group__CMSIS__FPEXC.html#gadde57667b9f81c468a49268513624b90", null ], + [ "__set_FPEXC", "group__CMSIS__FPEXC.html#ga14ba90beb9b4712454f35ac453c45f5d", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__FPSCR.html b/docs/Core_A/html/group__CMSIS__FPSCR.html new file mode 100644 index 0000000..0e7be5d --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__FPSCR.html @@ -0,0 +1,257 @@ + + + + + +Floating-point Status and Control Register (FPSCR) +CMSIS-Core (Cortex-A): Floating-point Status and Control Register (FPSCR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Functions
+
+
Floating-point Status and Control Register (FPSCR)
Core Register Access
+
+
+ +

Provides floating-point system status information and control. +More...

+ + + + + +

+Content

 FPSCR Bits
 Bit position and mask macros.
 
+ + + + +

+Data Structures

struct  FPSCR_Type
 Bit field declaration for FPSCR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_INLINE uint32_t __get_FPSCR (void)
 Get FPSCR (Floating Point Status/Control) More...
 
__STATIC_INLINE void __set_FPSCR (uint32_t fpscr)
 Set FPSCR (Floating Point Status/Control) More...
 
+

Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31] N Negative condition flag.
[30] Z Zero condition flag.
[29] C Carry condition flag.
[28] V Overflow condition flag.
[27] QC External abort pending bit.
[26] AHP External abort pending bit.
[25] DN External abort pending bit.
[24] FZ External abort pending bit.
[23:22] RMode External abort pending bit.
[21:20] Stride External abort pending bit.
[19] - Reserved.
[18:16] Len External abort pending bit.
[15] IDE IRQ pending bit.
[14:13] - Reserved.
[12] IXE IRQ pending bit.
[11] UFE IRQ pending bit.
[10] OFE IRQ pending bit.
[9] DZE IRQ pending bit.
[8] IOE IRQ pending bit.
[7] IDC IRQ pending bit.
[6:5] - Reserved.
[4] IXC FIQ pending bit.
[3] UFC FIQ pending bit.
[2] OFC FIQ pending bit.
[1] DZC FIQ pending bit.
[0] IOC FIQ pending bit.
+

Consider __get_FPSCR and __set_FPSCR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_FPSCR (void )
+
+
Returns
Floating Point Status/Control register value
+

This function returns the current value of the Floating-point Status and Control Register (FPSCR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_FPSCR (uint32_t fpscr)
+
+
Parameters
+ + +
[in]fpscrFloating Point Status/Control value to set
+
+
+

Assigns the given value to the Floating-point Status and Control Register (FPSCR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__FPSCR.js b/docs/Core_A/html/group__CMSIS__FPSCR.js new file mode 100644 index 0000000..932c7fa --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__FPSCR.js @@ -0,0 +1,7 @@ +var group__CMSIS__FPSCR = +[ + [ "FPSCR Bits", "group__CMSIS__FPSCR__BITS.html", null ], + [ "FPSCR_Type", "structFPSCR__Type.html", null ], + [ "__get_FPSCR", "group__CMSIS__FPSCR.html#ga6a275172e274ea7ce6c22030d07c6c64", null ], + [ "__set_FPSCR", "group__CMSIS__FPSCR.html#ga17c6ff443c52c74125fefef7de5fee1d", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__FPSCR__BITS.html b/docs/Core_A/html/group__CMSIS__FPSCR__BITS.html new file mode 100644 index 0000000..d3caaef --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__FPSCR__BITS.html @@ -0,0 +1,131 @@ + + + + + +FPSCR Bits +CMSIS-Core (Cortex-A): FPSCR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
FPSCR Bits
Floating-point Status and Control Register (FPSCR)
+
+
+ +

Bit position and mask macros. +More...

+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__IFSR.html b/docs/Core_A/html/group__CMSIS__IFSR.html new file mode 100644 index 0000000..df94861 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__IFSR.html @@ -0,0 +1,237 @@ + + + + + +Instruction Fault Status Register (IFSR) +CMSIS-Core (Cortex-A): Instruction Fault Status Register (IFSR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Functions
+
+
Instruction Fault Status Register (IFSR)
Core Register Access
+
+
+ +

The IFSR holds status information about the last instruction fault. +More...

+ + + + + +

+Content

 IFSR Bits
 Bit position and mask macros.
 
+ + + + +

+Data Structures

struct  IFSR_Type
 Bit field declaration for IFSR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_IFSR (void)
 Get IFSR. More...
 
__STATIC_FORCEINLINE void __set_IFSR (uint32_t ifsr)
 Set IFSR. More...
 
+

Description

+

DFSR format when using the Short-descriptor translation table format

+ + + + + + + + + + + + + + + + + +
Bits Name Function
[31:13] - Reserved.
[12] ExT External abort type.
[11] - Reserved.
[10] FS[4] Fault status bits.
[9] LPAE Large Physical Address Extension.
[8:4] - Reserved.
[3:0] FS[3:0] Fault status bits.
+

DFSR format when using the Long-descriptor translation table format

+ + + + + + + + + + + + + + + +
Bits Name Function
[31:13] - Reserved.
[12] ExT External abort type.
[11:10] - Reserved.
[9] LPAE Large Physical Address Extension.
[8:6] - Reserved.
[5:0] STATUS Fault status bits.
+

Consider __get_IFSR and __set_IFSR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_IFSR (void )
+
+
Returns
Instruction Fault Status Register value
+

This function returns the current value of the Instruction Fault Status Register (IFSR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_IFSR (uint32_t ifsr)
+
+
Parameters
+ + +
[in]ifsrInstruction Fault Status value to set
+
+
+

This function assigns the given value to the Instruction Fault Status Register (IFSR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__IFSR.js b/docs/Core_A/html/group__CMSIS__IFSR.js new file mode 100644 index 0000000..ae930dd --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__IFSR.js @@ -0,0 +1,16 @@ +var group__CMSIS__IFSR = +[ + [ "IFSR Bits", "group__CMSIS__IFSR__BITS.html", "group__CMSIS__IFSR__BITS" ], + [ "IFSR_Type", "unionIFSR__Type.html", [ + [ "ExT", "unionIFSR__Type.html#aee6fed7525c5125e637acc8e957c8d0f", null ], + [ "FS0", "unionIFSR__Type.html#a9f9ae1ffa89d33e90159eec5c4b7cd6a", null ], + [ "FS1", "unionIFSR__Type.html#adb493acf17881eaf09a2e8629ee2243e", null ], + [ "l", "unionIFSR__Type.html#a8f4e4fe46a9cb9b6c8a6355f9b0938e3", null ], + [ "LPAE", "unionIFSR__Type.html#a40c5236caf0549cc1cc78945b0b0f131", null ], + [ "s", "unionIFSR__Type.html#a4ece60d66e87e10e78aab83ac05e957c", null ], + [ "STATUS", "unionIFSR__Type.html#a543066fc60d5b63478cc85ba082524d4", null ], + [ "w", "unionIFSR__Type.html#ae31262477d14b86f30c3bef90a3fc371", null ] + ] ], + [ "__get_IFSR", "group__CMSIS__IFSR.html#ga9350226159749b673afd56a3b24953a0", null ], + [ "__set_IFSR", "group__CMSIS__IFSR.html#ga5bd9b703236cf2566eeed0ed59dda8a6", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__IFSR__BITS.html b/docs/Core_A/html/group__CMSIS__IFSR__BITS.html new file mode 100644 index 0000000..947fe4f --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__IFSR__BITS.html @@ -0,0 +1,289 @@ + + + + + +IFSR Bits +CMSIS-Core (Cortex-A): IFSR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
IFSR Bits
Instruction Fault Status Register (IFSR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IFSR_ExT_Pos   12U
 IFSR: ExT Position. More...
 
#define IFSR_ExT_Msk   (1UL << IFSR_ExT_Pos)
 IFSR: ExT Mask. More...
 
#define IFSR_LPAE_Pos   9U
 IFSR: LPAE Position. More...
 
#define IFSR_LPAE_Msk   (0x1UL << IFSR_LPAE_Pos)
 IFSR: LPAE Mask. More...
 
#define IFSR_FS1_Pos   10U
 IFSR: FS1 Position. More...
 
#define IFSR_FS1_Msk   (1UL << IFSR_FS1_Pos)
 IFSR: FS1 Mask. More...
 
#define IFSR_FS0_Pos   0U
 IFSR: FS0 Position. More...
 
#define IFSR_FS0_Msk   (0xFUL << IFSR_FS0_Pos)
 IFSR: FS0 Mask. More...
 
#define IFSR_STATUS_Pos   0U
 IFSR: STATUS Position. More...
 
#define IFSR_STATUS_Msk   (0x3FUL << IFSR_STATUS_Pos)
 IFSR: STATUS Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define IFSR_ExT_Msk   (1UL << IFSR_ExT_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IFSR_ExT_Pos   12U
+
+ +
+
+ +
+
+ + + + +
#define IFSR_FS0_Msk   (0xFUL << IFSR_FS0_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IFSR_FS0_Pos   0U
+
+ +
+
+ +
+
+ + + + +
#define IFSR_FS1_Msk   (1UL << IFSR_FS1_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IFSR_FS1_Pos   10U
+
+ +
+
+ +
+
+ + + + +
#define IFSR_LPAE_Msk   (0x1UL << IFSR_LPAE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IFSR_LPAE_Pos   9U
+
+ +
+
+ +
+
+ + + + +
#define IFSR_STATUS_Msk   (0x3FUL << IFSR_STATUS_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IFSR_STATUS_Pos   0U
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__IFSR__BITS.js b/docs/Core_A/html/group__CMSIS__IFSR__BITS.js new file mode 100644 index 0000000..8e90265 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__IFSR__BITS.js @@ -0,0 +1,13 @@ +var group__CMSIS__IFSR__BITS = +[ + [ "IFSR_ExT_Msk", "group__CMSIS__IFSR__BITS.html#gab0083a1d82b370a7e5208e39267bda22", null ], + [ "IFSR_ExT_Pos", "group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8", null ], + [ "IFSR_FS0_Msk", "group__CMSIS__IFSR__BITS.html#gaa17676ff0276b0fe93f92010fe35f6b8", null ], + [ "IFSR_FS0_Pos", "group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72", null ], + [ "IFSR_FS1_Msk", "group__CMSIS__IFSR__BITS.html#ga6fc93a02fbd1c968c70786a84428fca6", null ], + [ "IFSR_FS1_Pos", "group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62", null ], + [ "IFSR_LPAE_Msk", "group__CMSIS__IFSR__BITS.html#ga20639ca32a866d7b021e455b7a5d24c6", null ], + [ "IFSR_LPAE_Pos", "group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4", null ], + [ "IFSR_STATUS_Msk", "group__CMSIS__IFSR__BITS.html#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3", null ], + [ "IFSR_STATUS_Pos", "group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__ISR.html b/docs/Core_A/html/group__CMSIS__ISR.html new file mode 100644 index 0000000..a36eb79 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ISR.html @@ -0,0 +1,189 @@ + + + + + +Interrupt Status Register (ISR) +CMSIS-Core (Cortex-A): Interrupt Status Register (ISR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Functions
+
+
Interrupt Status Register (ISR)
Core Register Access
+
+
+ +

The ISR shows whether an IRQ, FIQ, or external abort is pending. +More...

+ + + + + +

+Content

 ISR Bits
 Bit position and mask macros.
 
+ + + + +

+Data Structures

struct  ISR_Type
 Bit field declaration for ISR layout. More...
 
+ + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_ISR (void)
 Get ISR. More...
 
+

Description

+ + + + + + + + + + + + + +
Bits Name Function
[31:9] - Reserved.
[8] A External abort pending bit.
[7] I IRQ pending bit.
[6] F FIQ pending bit.
[5:0] - Reserved.
+

Consider __get_IFSR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_ISR (void )
+
+
Returns
Interrupt Status Register value
+

This function returns the current value of the Interrupt Status Register (ISR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__ISR.js b/docs/Core_A/html/group__CMSIS__ISR.js new file mode 100644 index 0000000..21c7116 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ISR.js @@ -0,0 +1,12 @@ +var group__CMSIS__ISR = +[ + [ "ISR Bits", "group__CMSIS__ISR__BITS.html", "group__CMSIS__ISR__BITS" ], + [ "ISR_Type", "unionISR__Type.html", [ + [ "A", "unionISR__Type.html#ad4dfcb37f30162fd57c4402ae99ca49e", null ], + [ "b", "unionISR__Type.html#ad01f116d61c2ae79c2469a38a0b2f497", null ], + [ "F", "unionISR__Type.html#ae691a856f7de0f301c60521a7a779dc2", null ], + [ "I", "unionISR__Type.html#ad83ba976f1764c7d3a7954c073c39c22", null ], + [ "w", "unionISR__Type.html#a4fca9c1057aa8a6006f1fb631a28ee30", null ] + ] ], + [ "__get_ISR", "group__CMSIS__ISR.html#ga450229b64b770e8524ed763f53ff62e2", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__ISR__BITS.html b/docs/Core_A/html/group__CMSIS__ISR__BITS.html new file mode 100644 index 0000000..449b58d --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ISR__BITS.html @@ -0,0 +1,229 @@ + + + + + +ISR Bits +CMSIS-Core (Cortex-A): ISR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
ISR Bits
Interrupt Status Register (ISR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + +

+Macros

#define ISR_A_Pos   13U
 ISR: A Position. More...
 
#define ISR_A_Msk   (1UL << ISR_A_Pos)
 ISR: A Mask. More...
 
#define ISR_I_Pos   12U
 ISR: I Position. More...
 
#define ISR_I_Msk   (1UL << ISR_I_Pos)
 ISR: I Mask. More...
 
#define ISR_F_Pos   11U
 ISR: F Position. More...
 
#define ISR_F_Msk   (1UL << ISR_F_Pos)
 ISR: F Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define ISR_A_Msk   (1UL << ISR_A_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ISR_A_Pos   13U
+
+ +
+
+ +
+
+ + + + +
#define ISR_F_Msk   (1UL << ISR_F_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ISR_F_Pos   11U
+
+ +
+
+ +
+
+ + + + +
#define ISR_I_Msk   (1UL << ISR_I_Pos)
+
+ +
+
+ +
+
+ + + + +
#define ISR_I_Pos   12U
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__ISR__BITS.js b/docs/Core_A/html/group__CMSIS__ISR__BITS.js new file mode 100644 index 0000000..c837fe0 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ISR__BITS.js @@ -0,0 +1,9 @@ +var group__CMSIS__ISR__BITS = +[ + [ "ISR_A_Msk", "group__CMSIS__ISR__BITS.html#ga8c6d55d243da46ed7ca05c3941316c8d", null ], + [ "ISR_A_Pos", "group__CMSIS__ISR__BITS.html#gaecf0a2cb278bfd27e0da4ab8126d98af", null ], + [ "ISR_F_Msk", "group__CMSIS__ISR__BITS.html#gac2efaf413c81afab4265515160f6700c", null ], + [ "ISR_F_Pos", "group__CMSIS__ISR__BITS.html#gad8654422bb59e22fb7f1321eeef1b81d", null ], + [ "ISR_I_Msk", "group__CMSIS__ISR__BITS.html#ga7b756c9a406d7dd0a86891656908e98c", null ], + [ "ISR_I_Pos", "group__CMSIS__ISR__BITS.html#ga9f51d4217c1394e52f5223a6cd382136", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__MPIDR.html b/docs/Core_A/html/group__CMSIS__MPIDR.html new file mode 100644 index 0000000..cfd04e3 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__MPIDR.html @@ -0,0 +1,180 @@ + + + + + +Multiprocessor Affinity Register (MPIDR) +CMSIS-Core (Cortex-A): Multiprocessor Affinity Register (MPIDR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Multiprocessor Affinity Register (MPIDR)
Core Register Access
+
+
+ +

In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions. +More...

+ + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_MPIDR (void)
 Get MPIDR. More...
 
+

Description

+ + + + + + + + + + + + + + + + + +
Bits Name Function
[31] MPEA Multiprocessing Extensions Available
[30] U Indicates a Uniprocessor system
[29:25] - Reserved.
[24] MT Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach.
[23:16] Aff2 Affinity level 2.
[15:8] Aff1 Affinity level 1.
[7:0] Aff0 Affinity level 0.
+

Consider __get_MPIDR to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_MPIDR (void )
+
+

This function returns the value of the Multiprocessor Affinity Register.

+
Returns
Multiprocessor Affinity Register value
+

This function returns the value of the Multiprocessor Affinity Register (MPIDR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__MPIDR.js b/docs/Core_A/html/group__CMSIS__MPIDR.js new file mode 100644 index 0000000..3a6421f --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__MPIDR.js @@ -0,0 +1,4 @@ +var group__CMSIS__MPIDR = +[ + [ "__get_MPIDR", "group__CMSIS__MPIDR.html#ga05394b4cb9fb0ba1329ec6521c76e571", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__MVBAR.html b/docs/Core_A/html/group__CMSIS__MVBAR.html new file mode 100644 index 0000000..310992b --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__MVBAR.html @@ -0,0 +1,197 @@ + + + + + +Monitor Vector Base Address Register (MVBAR) +CMSIS-Core (Cortex-A): Monitor Vector Base Address Register (MVBAR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Monitor Vector Base Address Register (MVBAR)
Core Register Access
+
+
+ +

The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode. +More...

+ + + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_MVBAR (void)
 Get MVBAR. More...
 
__STATIC_FORCEINLINE void __set_MVBAR (uint32_t mvbar)
 Set MVBAR. More...
 
+

Description

+ + + + + + + +
Bits Name Function
[31:5] MVBA Bits[31:5] of the base address of the exception vectors for exceptions that are taken to Monitor mode.
[4:0] - Reserved.
+

Consider using __get_MVBAR and __set_MVBAR for accessing this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_MVBAR (void )
+
+

This function returns the value of the Monitor Vector Base Address Register.

+
Returns
Monitor Vector Base Address Register
+

This function returns the value of the Monitor Vector Base Address Register (MVBAR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_MVBAR (uint32_t mvbar)
+
+

This function assigns the given value to the Monitor Vector Base Address Register.

+
Parameters
+ + +
[in]mvbarMonitor Vector Base Address Register value to set
+
+
+

This function assigns the given value to the Monitor Vector Base Address Register (MVBAR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__MVBAR.js b/docs/Core_A/html/group__CMSIS__MVBAR.js new file mode 100644 index 0000000..980f6bb --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__MVBAR.js @@ -0,0 +1,5 @@ +var group__CMSIS__MVBAR = +[ + [ "__get_MVBAR", "group__CMSIS__MVBAR.html#ga3839224facf28080e73ac1bd6e356c30", null ], + [ "__set_MVBAR", "group__CMSIS__MVBAR.html#ga73c9231bcf1669fb34a1ee3f8062ad09", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__SCTLR.html b/docs/Core_A/html/group__CMSIS__SCTLR.html new file mode 100644 index 0000000..45a45dd --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SCTLR.html @@ -0,0 +1,243 @@ + + + + + +System Control Register (SCTLR) +CMSIS-Core (Cortex-A): System Control Register (SCTLR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Functions
+
+
System Control Register (SCTLR)
Core Register Access
+
+
+ +

The SCTLR provides the top level control of the system, including its memory system. +More...

+ + + + + +

+Content

 SCTLR Bits
 Bit position and mask macros.
 
+ + + + +

+Data Structures

struct  SCTLR_Type
 Bit field declaration for SCTLR layout. More...
 
+ + + + + + + +

+Functions

__STATIC_FORCEINLINE void __set_SCTLR (uint32_t sctlr)
 Set SCTLR. More...
 
__STATIC_FORCEINLINE uint32_t __get_SCTLR (void)
 Get SCTLR. More...
 
+

Description

+

In a VMSAv7 implementation, the SCTLR bit assignments are:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31] - Reserved.
[30] TE Thumb Exception enable.
[29] AFE Access flag enable bit.
[28] TRE TEX remap enable bit.
[27:26] - Reserved.
[25] EE Exception Endianness bit.
[24:21] - Reserved.
[20] UWXN Unprivileged write permission implies PL1 Execute Never (XN).
[19] WXN Write permission implies Execute Never (XN).
[18:14] - Reserved.
[13] V Vectors bit.
[12] I Instruction cache enable bit.
[11] Z Branch prediction enable bit.
[10] SW SWP and SWPB enable bit.
[9:3] - Reserved.
[2] C Cache enable bit.
[1] A Alignment bit.
[0] M Address translation enable bit.
+

Consider using __get_SCTLR and __set_SCTLR for accessing this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_SCTLR (void )
+
+
Returns
System Control Register value
+

This function returns the value of the System Control Register (SCTLR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_SCTLR (uint32_t sctlr)
+
+

This function assigns the given value to the System Control Register.

+
Parameters
+ + +
[in]sctlrSystem Control Register value to set
+
+
+

This function assigns the given value to the System Control Register (SCTLR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__SCTLR.js b/docs/Core_A/html/group__CMSIS__SCTLR.js new file mode 100644 index 0000000..5029dc3 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SCTLR.js @@ -0,0 +1,31 @@ +var group__CMSIS__SCTLR = +[ + [ "SCTLR Bits", "group__CMSIS__SCTLR__BITS.html", "group__CMSIS__SCTLR__BITS" ], + [ "SCTLR_Type", "unionSCTLR__Type.html", [ + [ "A", "unionSCTLR__Type.html#a078edcb9c3fc8b46b8cf382ad249bb79", null ], + [ "AFE", "unionSCTLR__Type.html#ae5a729bf64a6de4cbfa42c1a7d254535", null ], + [ "B", "unionSCTLR__Type.html#a805ee3324a333d7a77d9f0d8f0fac9a7", null ], + [ "b", "unionSCTLR__Type.html#a21ec59a37644281456a5f607450951d8", null ], + [ "C", "unionSCTLR__Type.html#a122a4dde5ab1a27855ddad88bb3f9f78", null ], + [ "CP15BEN", "unionSCTLR__Type.html#a98b55213f3bf0a8bd4f1db90512238de", null ], + [ "EE", "unionSCTLR__Type.html#af868e042d01b612649539c151f1aaea5", null ], + [ "FI", "unionSCTLR__Type.html#afe77b6c5d73e64d4ef3c5dc5ce2692dc", null ], + [ "HA", "unionSCTLR__Type.html#aba2a8aac3478cdc34428af7b9726d97f", null ], + [ "I", "unionSCTLR__Type.html#a0a4ed1a41f25a191cf4a500401c3c5db", null ], + [ "M", "unionSCTLR__Type.html#a8cbfde3ba235ebd48e82cb314c9b9cc4", null ], + [ "NMFI", "unionSCTLR__Type.html#a60d589567422115a14d6d0fde342dfce", null ], + [ "RR", "unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055", null ], + [ "SW", "unionSCTLR__Type.html#a6598f817304ccaef4509843ce041de1c", null ], + [ "TE", "unionSCTLR__Type.html#a25d4c4cf4df168a30cc4600a130580ab", null ], + [ "TRE", "unionSCTLR__Type.html#abc3055203ce7f9d117ceb10f146722f3", null ], + [ "U", "unionSCTLR__Type.html#a1ca6569db52bca6250afbbd565d05449", null ], + [ "UWXN", "unionSCTLR__Type.html#a32873e90e6814c3a2fc1b1c79c0bc8c8", null ], + [ "V", "unionSCTLR__Type.html#a9a3885d0e2ba2433d128f62ec2552a00", null ], + [ "VE", "unionSCTLR__Type.html#af29c170c65dd4d076b78c793dc17aa0a", null ], + [ "w", "unionSCTLR__Type.html#a4cb084e09742794f1d040c4e44ee4e0f", null ], + [ "WXN", "unionSCTLR__Type.html#a551d0505856acaef4dd1ecca54cb540d", null ], + [ "Z", "unionSCTLR__Type.html#a37f6910db32361f44a268f93b9ff7b20", null ] + ] ], + [ "__get_SCTLR", "group__CMSIS__SCTLR.html#ga3070304d6180433c91c4e6daef3f3c73", null ], + [ "__set_SCTLR", "group__CMSIS__SCTLR.html#gaf9b8e96ddd2e76c4475cf957600fd57a", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__SCTLR__BITS.html b/docs/Core_A/html/group__CMSIS__SCTLR__BITS.html new file mode 100644 index 0000000..79934d5 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SCTLR__BITS.html @@ -0,0 +1,769 @@ + + + + + +SCTLR Bits +CMSIS-Core (Cortex-A): SCTLR Bits + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
SCTLR Bits
System Control Register (SCTLR)
+
+
+ +

Bit position and mask macros. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define SCTLR_TE_Pos   30U
 SCTLR: TE Position. More...
 
#define SCTLR_TE_Msk   (1UL << SCTLR_TE_Pos)
 SCTLR: TE Mask. More...
 
#define SCTLR_AFE_Pos   29U
 SCTLR: AFE Position. More...
 
#define SCTLR_AFE_Msk   (1UL << SCTLR_AFE_Pos)
 SCTLR: AFE Mask. More...
 
#define SCTLR_TRE_Pos   28U
 SCTLR: TRE Position. More...
 
#define SCTLR_TRE_Msk   (1UL << SCTLR_TRE_Pos)
 SCTLR: TRE Mask. More...
 
#define SCTLR_NMFI_Pos   27U
 SCTLR: NMFI Position. More...
 
#define SCTLR_NMFI_Msk   (1UL << SCTLR_NMFI_Pos)
 SCTLR: NMFI Mask. More...
 
#define SCTLR_EE_Pos   25U
 SCTLR: EE Position. More...
 
#define SCTLR_EE_Msk   (1UL << SCTLR_EE_Pos)
 SCTLR: EE Mask. More...
 
#define SCTLR_VE_Pos   24U
 SCTLR: VE Position. More...
 
#define SCTLR_VE_Msk   (1UL << SCTLR_VE_Pos)
 SCTLR: VE Mask. More...
 
#define SCTLR_U_Pos   22U
 SCTLR: U Position. More...
 
#define SCTLR_U_Msk   (1UL << SCTLR_U_Pos)
 SCTLR: U Mask. More...
 
#define SCTLR_FI_Pos   21U
 SCTLR: FI Position. More...
 
#define SCTLR_FI_Msk   (1UL << SCTLR_FI_Pos)
 SCTLR: FI Mask. More...
 
#define SCTLR_UWXN_Pos   20U
 SCTLR: UWXN Position. More...
 
#define SCTLR_UWXN_Msk   (1UL << SCTLR_UWXN_Pos)
 SCTLR: UWXN Mask. More...
 
#define SCTLR_WXN_Pos   19U
 SCTLR: WXN Position. More...
 
#define SCTLR_WXN_Msk   (1UL << SCTLR_WXN_Pos)
 SCTLR: WXN Mask. More...
 
#define SCTLR_HA_Pos   17U
 SCTLR: HA Position. More...
 
#define SCTLR_HA_Msk   (1UL << SCTLR_HA_Pos)
 SCTLR: HA Mask. More...
 
#define SCTLR_RR_Pos   14U
 SCTLR: RR Position. More...
 
#define SCTLR_RR_Msk   (1UL << SCTLR_RR_Pos)
 SCTLR: RR Mask. More...
 
#define SCTLR_V_Pos   13U
 SCTLR: V Position. More...
 
#define SCTLR_V_Msk   (1UL << SCTLR_V_Pos)
 SCTLR: V Mask. More...
 
#define SCTLR_I_Pos   12U
 SCTLR: I Position. More...
 
#define SCTLR_I_Msk   (1UL << SCTLR_I_Pos)
 SCTLR: I Mask. More...
 
#define SCTLR_Z_Pos   11U
 SCTLR: Z Position. More...
 
#define SCTLR_Z_Msk   (1UL << SCTLR_Z_Pos)
 SCTLR: Z Mask. More...
 
#define SCTLR_SW_Pos   10U
 SCTLR: SW Position. More...
 
#define SCTLR_SW_Msk   (1UL << SCTLR_SW_Pos)
 SCTLR: SW Mask. More...
 
#define SCTLR_B_Pos   7U
 SCTLR: B Position. More...
 
#define SCTLR_B_Msk   (1UL << SCTLR_B_Pos)
 SCTLR: B Mask. More...
 
#define SCTLR_CP15BEN_Pos   5U
 SCTLR: CP15BEN Position. More...
 
#define SCTLR_CP15BEN_Msk   (1UL << SCTLR_CP15BEN_Pos)
 SCTLR: CP15BEN Mask. More...
 
#define SCTLR_C_Pos   2U
 SCTLR: C Position. More...
 
#define SCTLR_C_Msk   (1UL << SCTLR_C_Pos)
 SCTLR: C Mask. More...
 
#define SCTLR_A_Pos   1U
 SCTLR: A Position. More...
 
#define SCTLR_A_Msk   (1UL << SCTLR_A_Pos)
 SCTLR: A Mask. More...
 
#define SCTLR_M_Pos   0U
 SCTLR: M Position. More...
 
#define SCTLR_M_Msk   (1UL << SCTLR_M_Pos)
 SCTLR: M Mask. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define SCTLR_A_Msk   (1UL << SCTLR_A_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_A_Pos   1U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_AFE_Msk   (1UL << SCTLR_AFE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_AFE_Pos   29U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_B_Msk   (1UL << SCTLR_B_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_B_Pos   7U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_C_Msk   (1UL << SCTLR_C_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_C_Pos   2U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_CP15BEN_Msk   (1UL << SCTLR_CP15BEN_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_CP15BEN_Pos   5U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_EE_Msk   (1UL << SCTLR_EE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_EE_Pos   25U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_FI_Msk   (1UL << SCTLR_FI_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_FI_Pos   21U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_HA_Msk   (1UL << SCTLR_HA_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_HA_Pos   17U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_I_Msk   (1UL << SCTLR_I_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_I_Pos   12U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_M_Msk   (1UL << SCTLR_M_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_M_Pos   0U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_NMFI_Msk   (1UL << SCTLR_NMFI_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_NMFI_Pos   27U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_RR_Msk   (1UL << SCTLR_RR_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_RR_Pos   14U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_SW_Msk   (1UL << SCTLR_SW_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_SW_Pos   10U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_TE_Msk   (1UL << SCTLR_TE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_TE_Pos   30U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_TRE_Msk   (1UL << SCTLR_TRE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_TRE_Pos   28U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_U_Msk   (1UL << SCTLR_U_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_U_Pos   22U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_UWXN_Msk   (1UL << SCTLR_UWXN_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_UWXN_Pos   20U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_V_Msk   (1UL << SCTLR_V_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_V_Pos   13U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_VE_Msk   (1UL << SCTLR_VE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_VE_Pos   24U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_WXN_Msk   (1UL << SCTLR_WXN_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_WXN_Pos   19U
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_Z_Msk   (1UL << SCTLR_Z_Pos)
+
+ +
+
+ +
+
+ + + + +
#define SCTLR_Z_Pos   11U
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__SCTLR__BITS.js b/docs/Core_A/html/group__CMSIS__SCTLR__BITS.js new file mode 100644 index 0000000..b292775 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SCTLR__BITS.js @@ -0,0 +1,45 @@ +var group__CMSIS__SCTLR__BITS = +[ + [ "SCTLR_A_Msk", "group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741", null ], + [ "SCTLR_A_Pos", "group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146", null ], + [ "SCTLR_AFE_Msk", "group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957", null ], + [ "SCTLR_AFE_Pos", "group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e", null ], + [ "SCTLR_B_Msk", "group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6", null ], + [ "SCTLR_B_Pos", "group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859", null ], + [ "SCTLR_C_Msk", "group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33", null ], + [ "SCTLR_C_Pos", "group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa", null ], + [ "SCTLR_CP15BEN_Msk", "group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac", null ], + [ "SCTLR_CP15BEN_Pos", "group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b", null ], + [ "SCTLR_EE_Msk", "group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044", null ], + [ "SCTLR_EE_Pos", "group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa", null ], + [ "SCTLR_FI_Msk", "group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc", null ], + [ "SCTLR_FI_Pos", "group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360", null ], + [ "SCTLR_HA_Msk", "group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179", null ], + [ "SCTLR_HA_Pos", "group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52", null ], + [ "SCTLR_I_Msk", "group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666", null ], + [ "SCTLR_I_Pos", "group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c", null ], + [ "SCTLR_M_Msk", "group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e", null ], + [ "SCTLR_M_Pos", "group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810", null ], + [ "SCTLR_NMFI_Msk", "group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279", null ], + [ "SCTLR_NMFI_Pos", "group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9", null ], + [ "SCTLR_RR_Msk", "group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc", null ], + [ "SCTLR_RR_Pos", "group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64", null ], + [ "SCTLR_SW_Msk", "group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8", null ], + [ "SCTLR_SW_Pos", "group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8", null ], + [ "SCTLR_TE_Msk", "group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b", null ], + [ "SCTLR_TE_Pos", "group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1", null ], + [ "SCTLR_TRE_Msk", "group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918", null ], + [ "SCTLR_TRE_Pos", "group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04", null ], + [ "SCTLR_U_Msk", "group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f", null ], + [ "SCTLR_U_Pos", "group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17", null ], + [ "SCTLR_UWXN_Msk", "group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199", null ], + [ "SCTLR_UWXN_Pos", "group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3", null ], + [ "SCTLR_V_Msk", "group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11", null ], + [ "SCTLR_V_Pos", "group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d", null ], + [ "SCTLR_VE_Msk", "group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274", null ], + [ "SCTLR_VE_Pos", "group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f", null ], + [ "SCTLR_WXN_Msk", "group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291", null ], + [ "SCTLR_WXN_Pos", "group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256", null ], + [ "SCTLR_Z_Msk", "group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c", null ], + [ "SCTLR_Z_Pos", "group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__SP.html b/docs/Core_A/html/group__CMSIS__SP.html new file mode 100644 index 0000000..6b78427 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SP.html @@ -0,0 +1,213 @@ + + + + + +Stack Pointer (SP/R13) +CMSIS-Core (Cortex-A): Stack Pointer (SP/R13) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Stack Pointer (SP/R13)
Core Register Access
+
+
+ +

The processor uses SP as a pointer to the active stack. +More...

+ + + + + + + + +

+Functions

__STATIC_INLINE __ASM void __set_SP (uint32_t stack)
 Set Stack Pointer. More...
 
__STATIC_INLINE __ASM void __set_SP_usr (uint32_t topOfProcStack)
 Set USR/SYS Stack Pointer. More...
 
+

Description

+

The Stack Pointer is banked per processor mode. Accessing the active stack pointer actually returns/modifies the stack pointer of the current processor execution mode.

+ + + + + + + + + + + + + + + + + + + +
Mode Actual SP
User/System SP_usr
Hypervisor SP_hyp
Supervisor SP_svc
Abort SP_abt
Undefined SP_und
Monitor SP_mon
IRQ SP_irq
FIQ SP_fiq
+

Consider __set_SP and __set_SP_usr to access this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM void __set_SP (uint32_t stack)
+
+
Parameters
+ + +
[in]stackStack Pointer value to set
+
+
+

This function assigns the given value to the current stack pointer.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM void __set_SP_usr (uint32_t topOfProcStack)
+
+
Parameters
+ + +
[in]topOfProcStackUSR/SYS Stack Pointer value to set
+
+
+

This function assigns the given value to the User/System Stack Pointer (SP_usr).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__SP.js b/docs/Core_A/html/group__CMSIS__SP.js new file mode 100644 index 0000000..12d617d --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SP.js @@ -0,0 +1,5 @@ +var group__CMSIS__SP = +[ + [ "__set_SP", "group__CMSIS__SP.html#ga6af63cb939bd108aef1c0f12622350cb", null ], + [ "__set_SP_usr", "group__CMSIS__SP.html#gabfe36eb17b6ae34633c7e155d132426e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__TLB.html b/docs/Core_A/html/group__CMSIS__TLB.html new file mode 100644 index 0000000..333e1a9 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__TLB.html @@ -0,0 +1,162 @@ + + + + + +TLB maintenance operations +CMSIS-Core (Cortex-A): TLB maintenance operations + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
TLB maintenance operations
Core Register Access
+
+
+ +

This section describes the TLB operations that are implemented on all Armv7-A implementations. +More...

+ + + + + +

+Functions

__STATIC_FORCEINLINE void __set_TLBIALL (uint32_t value)
 Set TLBIALL. More...
 
+

Description

+

TLB maintenance operations provide a mechanism to invalidate entries from a TLB.

+

Consider using Memory Management Unit Functions instead of raw register usage.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_TLBIALL (uint32_t value)
+
+

TLB Invalidate All

+

This function invalidates entire unified TLB.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__TLB.js b/docs/Core_A/html/group__CMSIS__TLB.js new file mode 100644 index 0000000..70b0168 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__TLB.js @@ -0,0 +1,4 @@ +var group__CMSIS__TLB = +[ + [ "__set_TLBIALL", "group__CMSIS__TLB.html#gafe73539914fa96265067bec49a3ed4ea", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__TTBR.html b/docs/Core_A/html/group__CMSIS__TTBR.html new file mode 100644 index 0000000..3aacae2 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__TTBR.html @@ -0,0 +1,229 @@ + + + + + +Translation Table Base Registers (TTBR0/TTBR1) +CMSIS-Core (Cortex-A): Translation Table Base Registers (TTBR0/TTBR1) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Translation Table Base Registers (TTBR0/TTBR1)
Core Register Access
+
+
+ +

TTBRn holds the base address of translation table n, and information about the memory it occupies. +More...

+ + + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_TTBR0 (void)
 Get TTBR0. More...
 
__STATIC_FORCEINLINE void __set_TTBR0 (uint32_t ttbr0)
 Set TTBR0. More...
 
+

Description

+

32-bit TTBR format

+ + + + + + + + + + + + + + + + + + + +
Bits Name Function
[31:x] BADDR Translation table base address, bits[31:x].
[x-1:7] - Reserved.
[6] IRGN[0] Inner region bit 0.
[5] NOS Not Outer Shareable bit.
[4:3] RGN Region bits.
[2] - Reserved.
[1] S Shareable bit.
[0] C/IRGN[1] Cacheable bit. / Inner region bit 1.
+
Note
The width of TTBR0 BADDR field depends on the setting in TTBCR N field, giving x=14-N.
+
+The width of TTBR1 BADDR field is fixed at x=14.
+

64-bit TTBR format

+ + + + + + + + + + + + + +
Bits Name Function
[63:56] - Reserved.
[55:48] ASID An ASID for the translation table base address.
[47:40] - Reserved.
[39:x] BADDR Translation table base address, bits[39:x].
[x-1:0] - Reserved.
+
Note
The width of TBBR0/TBBR1 BADDR fields depends on the settings in TTBCR T0SZ/T1SZ fields respectively, giving x=14-TnSZ.
+

Consider using __get_TTBR0 and __set_TTBR0 for accessing TTBR0 register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_TTBR0 (void )
+
+

This function returns the value of the Translation Table Base Register 0.

+
Returns
Translation Table Base Register 0 value
+

This function returns the value of the Translation Table Base Register 0.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_TTBR0 (uint32_t ttbr0)
+
+

This function assigns the given value to the Translation Table Base Register 0.

+
Parameters
+ + +
[in]ttbr0Translation Table Base Register 0 value to set
+
+
+

This function assigns the given value to the Translation Table Base Register 0.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__TTBR.js b/docs/Core_A/html/group__CMSIS__TTBR.js new file mode 100644 index 0000000..4eb1fbf --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__TTBR.js @@ -0,0 +1,5 @@ +var group__CMSIS__TTBR = +[ + [ "__get_TTBR0", "group__CMSIS__TTBR.html#ga678997bc01f6d8d48b1d407cec24809d", null ], + [ "__set_TTBR0", "group__CMSIS__TTBR.html#gad2ccad052f77c18897c5ceaaf307711e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__VBAR.html b/docs/Core_A/html/group__CMSIS__VBAR.html new file mode 100644 index 0000000..2aa7aa9 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__VBAR.html @@ -0,0 +1,197 @@ + + + + + +Vector Base Address Register (VBAR) +CMSIS-Core (Cortex-A): Vector Base Address Register (VBAR) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Vector Base Address Register (VBAR)
Core Register Access
+
+
+ +

When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode. +More...

+ + + + + + + + +

+Functions

__STATIC_FORCEINLINE uint32_t __get_VBAR (void)
 Get VBAR. More...
 
__STATIC_FORCEINLINE void __set_VBAR (uint32_t vbar)
 Set VBAR. More...
 
+

Description

+ + + + + + + +
Bits Name Function
[31:5] VBA Bits[31:5] of the base address of the low exception vectors.
[4:0] - Reserved.
+

Consider using __get_VBAR and __set_VBAR for accessing this register.

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t __get_VBAR (void )
+
+

This function returns the value of the Vector Base Address Register.

+
Returns
Vector Base Address Register
+

This function returns the value of the Vector Base Address Register (VBAR).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void __set_VBAR (uint32_t vbar)
+
+

This function assigns the given value to the Vector Base Address Register.

+
Parameters
+ + +
[in]vbarVector Base Address Register value to set
+
+
+

This function assigns the given value to the Vector Base Address Register (VBAR).

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__VBAR.js b/docs/Core_A/html/group__CMSIS__VBAR.js new file mode 100644 index 0000000..2a8c2c8 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__VBAR.js @@ -0,0 +1,5 @@ +var group__CMSIS__VBAR = +[ + [ "__get_VBAR", "group__CMSIS__VBAR.html#ga8abf5c92597d8e7d403aa26d8246387c", null ], + [ "__set_VBAR", "group__CMSIS__VBAR.html#ga582f9a60f7b090ae5a4e8f60ef3b79f8", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__CMSIS__core__register.html b/docs/Core_A/html/group__CMSIS__core__register.html new file mode 100644 index 0000000..120f536 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__core__register.html @@ -0,0 +1,207 @@ + + + + + +Core Register Access +CMSIS-Core (Cortex-A): Core Register Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
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+
+ + + +
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+ +
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+ +
+ +
+
+Content
+
+
Core Register Access
+
+
+ +

Functions to access the Cortex-A core registers. +More...

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+Content

 Auxiliary Control Register (ACTLR)
 The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
 
 Cache and branch predictor maintenance operations
 This section describes the cache and branch predictor maintenance operations.
 
 Configuration Base Address Register (CBAR)
 Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13].
 
 Coprocessor Access Control Register (CPACR)
 The CPACR controls access to coprocessors CP0 to CP13.
 
 Current Program Status Register (CPSR)
 The Current Program Status Register (CPSR) holds processor status and control information.
 
 Data Fault Status Register (DFSR)
 The DFSR holds status information about the last data fault.
 
 Domain Access Control Register (DACR)
 DACR defines the access permission for each of the sixteen memory domains.
 
 Floating-Point Exception Control register (FPEXC)
 Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded.
 
 Floating-point Status and Control Register (FPSCR)
 Provides floating-point system status information and control.
 
 Instruction Fault Status Register (IFSR)
 The IFSR holds status information about the last instruction fault.
 
 Interrupt Status Register (ISR)
 The ISR shows whether an IRQ, FIQ, or external abort is pending.
 
 Multiprocessor Affinity Register (MPIDR)
 In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions.
 
 Counter Frequency register (CNTFRQ)
 Indicates the clock frequency of the system counter.
 
 PL1 Physical Timer Control register (CNTP_CTL)
 The control register for the physical timer.
 
 PL1 Physical Timer Compare Value register (CNTP_CVAL)
 Holds the 64-bit compare value for the PL1 physical timer.
 
 PL1 Physical Timer Value register (CNTP_TVAL)
 Holds the timer value for the PL1 physical timer.
 
 PL1 Physical Count register (CNTPCT)
 Holds the 64-bit physical count value.
 
 Stack Pointer (SP/R13)
 The processor uses SP as a pointer to the active stack.
 
 System Control Register (SCTLR)
 The SCTLR provides the top level control of the system, including its memory system.
 
 TLB maintenance operations
 This section describes the TLB operations that are implemented on all Armv7-A implementations.
 
 Translation Table Base Registers (TTBR0/TTBR1)
 TTBRn holds the base address of translation table n, and information about the memory it occupies.
 
 Vector Base Address Register (VBAR)
 When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode.
 
 Monitor Vector Base Address Register (MVBAR)
 The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode.
 
+

Description

+
+
+ + + + diff --git a/docs/Core_A/html/group__CMSIS__core__register.js b/docs/Core_A/html/group__CMSIS__core__register.js new file mode 100644 index 0000000..d076e1a --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__core__register.js @@ -0,0 +1,26 @@ +var group__CMSIS__core__register = +[ + [ "Auxiliary Control Register (ACTLR)", "group__CMSIS__ACTLR.html", "group__CMSIS__ACTLR" ], + [ "Cache and branch predictor maintenance operations", "group__CMSIS__CBPM.html", "group__CMSIS__CBPM" ], + [ "Configuration Base Address Register (CBAR)", "group__CMSIS__CBAR.html", "group__CMSIS__CBAR" ], + [ "Coprocessor Access Control Register (CPACR)", "group__CMSIS__CPACR.html", "group__CMSIS__CPACR" ], + [ "Current Program Status Register (CPSR)", "group__CMSIS__CPSR.html", "group__CMSIS__CPSR" ], + [ "Data Fault Status Register (DFSR)", "group__CMSIS__DFSR.html", "group__CMSIS__DFSR" ], + [ "Domain Access Control Register (DACR)", "group__CMSIS__DACR.html", "group__CMSIS__DACR" ], + [ "Floating-Point Exception Control register (FPEXC)", "group__CMSIS__FPEXC.html", "group__CMSIS__FPEXC" ], + [ "Floating-point Status and Control Register (FPSCR)", "group__CMSIS__FPSCR.html", "group__CMSIS__FPSCR" ], + [ "Instruction Fault Status Register (IFSR)", "group__CMSIS__IFSR.html", "group__CMSIS__IFSR" ], + [ "Interrupt Status Register (ISR)", "group__CMSIS__ISR.html", "group__CMSIS__ISR" ], + [ "Multiprocessor Affinity Register (MPIDR)", "group__CMSIS__MPIDR.html", "group__CMSIS__MPIDR" ], + [ "Counter Frequency register (CNTFRQ)", "group__CMSIS__CNTFRQ.html", "group__CMSIS__CNTFRQ" ], + [ "PL1 Physical Timer Control register (CNTP_CTL)", "group__CMSIS__CNTP__CTL.html", "group__CMSIS__CNTP__CTL" ], + [ "PL1 Physical Timer Compare Value register (CNTP_CVAL)", "group__CMSIS__CNTP__CVAL.html", "group__CMSIS__CNTP__CVAL" ], + [ "PL1 Physical Timer Value register (CNTP_TVAL)", "group__CMSIS__CNTP__TVAL.html", "group__CMSIS__CNTP__TVAL" ], + [ "PL1 Physical Count register (CNTPCT)", "group__CMSIS__CNTPCT.html", "group__CMSIS__CNTPCT" ], + [ "Stack Pointer (SP/R13)", "group__CMSIS__SP.html", "group__CMSIS__SP" ], + [ "System Control Register (SCTLR)", "group__CMSIS__SCTLR.html", "group__CMSIS__SCTLR" ], + [ "TLB maintenance operations", "group__CMSIS__TLB.html", "group__CMSIS__TLB" ], + [ "Translation Table Base Registers (TTBR0/TTBR1)", "group__CMSIS__TTBR.html", "group__CMSIS__TTBR" ], + [ "Vector Base Address Register (VBAR)", "group__CMSIS__VBAR.html", "group__CMSIS__VBAR" ], + [ "Monitor Vector Base Address Register (MVBAR)", "group__CMSIS__MVBAR.html", "group__CMSIS__MVBAR" ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__FPU__functions.html b/docs/Core_A/html/group__FPU__functions.html new file mode 100644 index 0000000..856e1e3 --- /dev/null +++ b/docs/Core_A/html/group__FPU__functions.html @@ -0,0 +1,160 @@ + + + + + +Floating Point Unit Functions +CMSIS-Core (Cortex-A): Floating Point Unit Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
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+
+ +
+
    + +
+
+ + + +
+
+ +
+
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+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Floating Point Unit Functions
Core Peripherals
+
+
+ +

FPU Functions enable the use of Floating Point instructions and extensions.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition. +More...

+ + + + + +

+Functions

__STATIC_INLINE __ASM void __FPU_Enable (void)
 Enable Floating Point Unit. More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM void __FPU_Enable (void )
+
+

Critical section, called from undef handler, so systick is disabled

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__FPU__functions.js b/docs/Core_A/html/group__FPU__functions.js new file mode 100644 index 0000000..920d304 --- /dev/null +++ b/docs/Core_A/html/group__FPU__functions.js @@ -0,0 +1,4 @@ +var group__FPU__functions = +[ + [ "__FPU_Enable", "group__FPU__functions.html#ga1e4728985ee8b4fa89cc01c032f69565", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__GIC__functions.html b/docs/Core_A/html/group__GIC__functions.html new file mode 100644 index 0000000..635803e --- /dev/null +++ b/docs/Core_A/html/group__GIC__functions.html @@ -0,0 +1,996 @@ + + + + + +Generic Interrupt Controller Functions +CMSIS-Core (Cortex-A): Generic Interrupt Controller Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
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+ +
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+
+Data Structures | +Macros | +Functions
+
+
Generic Interrupt Controller Functions
Core Peripherals
+
+
+ +

The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC). +More...

+ + + + + + + + +

+Data Structures

struct  GICInterface_Type
 Structure type to access the Generic Interrupt Controller Interface (GICC) More...
 
struct  GICDistributor_Type
 Structure type to access the Generic Interrupt Controller Distributor (GICD) More...
 
+ + + + + + + +

+Macros

#define GICDistributor   ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )
 GIC Distributor register set access pointer. More...
 
#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE )
 GIC Interface register set access pointer. More...
 
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+Functions

__STATIC_INLINE void GIC_EnableDistributor (void)
 Enable the interrupt distributor using the GIC's CTLR register. More...
 
__STATIC_INLINE void GIC_DisableDistributor (void)
 Disable the interrupt distributor using the GIC's CTLR register. More...
 
__STATIC_INLINE uint32_t GIC_DistributorInfo (void)
 Read the GIC's TYPER register. More...
 
__STATIC_INLINE uint32_t GIC_DistributorImplementer (void)
 Reads the GIC's IIDR register. More...
 
__STATIC_INLINE void GIC_SetTarget (IRQn_Type IRQn, uint32_t cpu_target)
 Sets the GIC's ITARGETSR register for the given interrupt. More...
 
__STATIC_INLINE uint32_t GIC_GetTarget (IRQn_Type IRQn)
 Read the GIC's ITARGETSR register. More...
 
__STATIC_INLINE void GIC_EnableInterface (void)
 Enable the CPU's interrupt interface. More...
 
__STATIC_INLINE void GIC_DisableInterface (void)
 Disable the CPU's interrupt interface. More...
 
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending (void)
 Read the CPU's IAR register. More...
 
__STATIC_INLINE void GIC_EndInterrupt (IRQn_Type IRQn)
 Writes the given interrupt number to the CPU's EOIR register. More...
 
__STATIC_INLINE void GIC_EnableIRQ (IRQn_Type IRQn)
 Enables the given interrupt using GIC's ISENABLER register. More...
 
__STATIC_INLINE void GIC_DisableIRQ (IRQn_Type IRQn)
 Disables the given interrupt using GIC's ICENABLER register. More...
 
__STATIC_INLINE void GIC_SetPendingIRQ (IRQn_Type IRQn)
 Sets the given interrupt as pending using GIC's ISPENDR register. More...
 
__STATIC_INLINE void GIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clears the given interrupt from being pending using GIC's ICPENDR register. More...
 
__STATIC_INLINE void GIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for the given interrupt in the GIC's IPRIORITYR register. More...
 
__STATIC_INLINE uint32_t GIC_GetPriority (IRQn_Type IRQn)
 Read the current interrupt priority from GIC's IPRIORITYR register. More...
 
__STATIC_INLINE void GIC_SetInterfacePriorityMask (uint32_t priority)
 Set the interrupt priority mask using CPU's PMR register. More...
 
__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask (void)
 Read the current interrupt priority mask from CPU's PMR register. More...
 
__STATIC_INLINE void GIC_SetBinaryPoint (uint32_t binary_point)
 Configures the group priority and subpriority split point using CPU's BPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetBinaryPoint (void)
 Read the current group priority and subpriority split point from CPU's BPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetIRQStatus (IRQn_Type IRQn)
 Get the status for a given interrupt. More...
 
__STATIC_INLINE void GIC_SendSGI (IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
 Generate a software interrupt using GIC's SGIR register. More...
 
__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ (void)
 Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. More...
 
__STATIC_INLINE uint32_t GIC_GetInterfaceId (void)
 Provides information about the implementer and revision of the CPU interface. More...
 
__STATIC_INLINE void GIC_DistInit (void)
 Initialize the interrupt distributor. More...
 
__STATIC_INLINE void GIC_CPUInterfaceInit (void)
 Initialize the CPU's interrupt interface. More...
 
__STATIC_INLINE void GIC_Enable (void)
 Initialize and enable the GIC. More...
 
+

Description

+

Reference: Generic Interrupt Controller Architecture Specificaton.

+

The following table shows the register naming of CMSIS in correlation with various technical reference manuals.

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CMSIS Register Name Cortex-A5 TRM Cortex-A7 TRM Cortex-A9 TRM
GIC Distributor
GICDistributor->CTLR ICDDCR GICD_CTLR ICDDCR
GICDistributor->TYPER ICDICTR GICD_TYPER ICDICTR
GICDistributor->IIDR ICDIIDR GICD_IIDR ICDIIDR
GICDistributor->STATUSR
GICDistributor->SETSPI_NSR
GICDistributor->CLRSPI_NSR
GICDistributor->IGROUPR[] ICDISR GICD_IGROUPRn ICDISRn
GICDistributor->ISENABLER[] ICDISER GICD_ISENABLERn ICDISERn
GICDistributor->ICENABLER[] ICDICER GICD_ICENABLERn ICDICERn
GICDistributor->ISPENDR[] ICDISPR GICD_ISPENDRn ICDISPRn
GICDistributor->ICPENDR[] ICDICPR GICD_ICPENDRn ICDICPRn
GICDistributor->ISACTIVER[] ICDABR GICD_ISACTIVERn ICDABRn
GICDistributor->ICACTIVER[] GICD_ICACTIVERn
GICDistributor->IPRIORITYR[] ICDIPR GICD_IPRIORITYRn ICDIPRn
GICDistributor->ITARGETSR[] ICDIPTR GICD_ITARGETSRn ICDIPTRn
GICDistributor->ICFGR[] ICDICFR GICD_ICFGRn ICDICFRn
GICDistributor->IGRPMODR[0] ICDPPIS GICD_PPISR ppi_status
GICDistributor->IGRPMODR[31:1] ICDSPIS GICD_SPISRn spi_status
GICDistributor->NSACR[]
GICDistributor->SGIR ICDSGIR GICD_SGIR ICDSGIR
GICDistributor->CPENDSGIR[] GICD_CPENDSGIRn
GICDistributor->SPENDSGIR[] GICD_SPENDSGIRn
GICDistributor->IROUTER[]
GIC Interface
GICInterface->CTLR ICPICR GICC_CTLR ICCICR
GICInterface->PMR ICCIPMR GICC_PMRn ICCPMR
GICInterface->BPR ICCBPR GICC_BPR ICCBPR
GICInterface->IAR ICCIAR GICC_IAR ICCIAR
GICInterface->EOIR ICCEOIR GICC_EOIR ICCEOIR
GICInterface->RPR ICCRPR GICC_RPR ICCRPR
GICInterface->HPPIR ICCHPIR GICC_HPPIR ICCHPIR
GICInterface->ABPR ICCABPR GICC_ABPR ICCABPR
GICInterface->AIAR GICC_AIAR
GICInterface->AEOIR GICC_AEOIR
GICInterface->AHPPIR GICC_AHPPIR
GICInterface->STATUSR
GICInterface->APR[] GICC_APR0
GICInterface->NSAPR[] GICC_NSAPR0
GICInterface->IIDR ICCIIDR GICC_IIDR ICCIDR
GICInterface->DIR GICC_DIR
+

Macro Definition Documentation

+ +
+
+ + + + +
#define GICDistributor   ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )
+
+

Use GICDistributor to access the GIC Distributor registers.

+

Example:

+
GICDistributor->CTRL |= 1; // Enable group 0 interrupts
+
+
+
+ +
+
+ + + + +
#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE )
+
+

Use GICInterface to access the GIC Interface registers.

+

Example:

+
GICInterface->CTLR |= 1; // Enable interrupt signaling
+
+
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending (void )
+
+
Returns
GICInterface_Type::IAR
+

Provides the interrupt number of the highest priority interrupt pending. A read of this register acts as an acknowledge for the interrupt.

+

The read returns a spurious interrupt number of 1023 if any of the following apply:

+
    +
  • Forwarding of interrupts by the Distributor to the CPU interface is disabled.
    • +
  • Signaling of interrupts by the CPU interface to the connected PE is disabled.
    • +
  • There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.
    • +
+
See Also
GIC_EndInterrupt
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_ClearPendingIRQ (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be enabled.
+
+
+

Removes the pending state from the corresponding interrupt.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_CPUInterfaceInit (void )
+
+

All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be

+
    +
  • disabled
    • +
  • level-sensitive, 1-N model
    • +
  • priority 0x7F and the interrupt interface is enabled.
    • +
+

The binary point is set to zero.

+

The interrupt priority mask is set to 0xFF.

+
See Also
GIC_DisableIRQ
+GIC_SetLevelModel
+GIC_SetPriority
+GIC_EnableInterface
+GIC_SetBinaryPoint
+GIC_SetInterfacePriorityMask
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_DisableDistributor (void )
+
+

Globally disable the forwarding of interrupts to the CPU interfaces.

+
See Also
GIC_EnableDistributor
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_DisableInterface (void )
+
+

Resets the Enable bit in the local CPUs CTLR register. Only the CPU executing the call is affected.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_DisableIRQ (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be disabled.
+
+
+

Disables forwarding of the corresponding interrupt to the CPU interfaces.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_DistInit (void )
+
+

All shared peripheral interrupts (SPIs) are initialized to be

+
    +
  • disabled
    • +
  • level-sensitive, 1-N model
    • +
  • priority 0x7F
    • +
  • targeting CPU0 and the distributor is enabled.
    • +
+
See Also
GIC_DisableIRQ
+GIC_SetLevelModel
+GIC_SetPriority
+GIC_SetTarget
+GIC_EnableDistributor
+ +
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+ +
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+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_DistributorImplementer (void )
+
+
Returns
GICDistributor_Type::IIDR
+

Provides information about the implementer and revision of the Distributor.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_DistributorInfo (void )
+
+
Returns
GICDistributor_Type::TYPER
+

Provides information about the configuration of the GIC. It indicates:

+
    +
  • whether the GIC implements the Security Extensions
    • +
  • the maximum number of interrupt IDs that the GIC supports
    • +
  • the number of CPU interfaces implemented
    • +
  • if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
    • +
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_Enable (void )
+
+

Initializes the distributor and the cpu interface.

+
See Also
GIC_DistInit GIC_CPUInterfaceInit
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_EnableDistributor (void )
+
+

Globally enable the forwarding of interrupts to the CPU interfaces.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_EnableInterface (void )
+
+

Sets the Enable bit in the local CPUs CTLR register. Only the CPU executing the call is affected.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_EnableIRQ (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be enabled.
+
+
+

Enables forwarding of the corresponding interrupt to the CPU interfaces.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_EndInterrupt (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be signaled as finished.
+
+
+

A write to this register performs priority drop for the specified interrupt.

+

For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt acknowledgement, i.e. calls to GIC_AcknowledgePending. Behavior is UNPREDICTABLE if:

+
    +
  • This ordering constraint is not maintained.
    • +
  • The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.
    • +
  • The given interrupt number does not match the last valid interrupt value returned by GIC_AcknowledgePending.
    • +
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetBinaryPoint (void )
+
+
Returns
GICInterface_Type::BPR
+
See Also
GIC_SetBinaryPoint
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ (void )
+
+
Returns
GICInterface_Type::HPPIR
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetInterfaceId (void )
+
+
Returns
GICInterface_Type::IIDR
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask (void )
+
+
Returns
GICInterface_Type::PMR
+
See Also
GIC_SetInterfacePriorityMask
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetIRQStatus (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to get status for.
+
+
+
Returns
0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
+

The return value is a combination of GIC's ISACTIVER and ISPENDR registers.

+

Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts active bit (interrupt is currently handled).

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetPriority (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be queried.
+
+
+

Can be used to retrieve the actual priority depending on the GIC implementation.

+
See Also
GIC_SetPriority
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t GIC_GetTarget (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnInterrupt to acquire the configuration for.
+
+
+
Returns
GICDistributor_Type::ITARGETSR
+

Read the current interrupt to CPU assignment for the given interrupt.

+
See Also
GIC_SetTarget
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void GIC_SendSGI (IRQn_Type IRQn,
uint32_t target_list,
uint32_t filter_list 
)
+
+
Parameters
+ + + + +
[in]IRQnSoftware interrupt to be generated.
[in]target_listList of CPUs the software interrupt should be forwarded to.
[in]filter_listFilter to be applied to determine interrupt receivers.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_SetBinaryPoint (uint32_t binary_point)
+
+
Parameters
+ + +
[in]binary_pointAmount of bits used as subpriority.
+
+
+

The binary point defines the amount of priority bits used as a group priority and subpriorities.

+

Interrupts sharing the same group priority do not preempt each other. But interrupts having a higher group priority (lower value) preempt interrups with a lower group priority.

+

The subpriority defines the execution sequence of interrupts with the same group priority if multiple are pending at time.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_SetInterfacePriorityMask (uint32_t priority)
+
+
Parameters
+ + +
[in]priorityPriority mask to be set.
+
+
+

Only interrupts with a higher priority (lower values) than the value provided are signaled.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void GIC_SetPendingIRQ (IRQn_Type IRQn)
+
+
Parameters
+ + +
[in]IRQnThe interrupt to be enabled.
+
+
+

Adds the pending state to the corresponding interrupt.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void GIC_SetPriority (IRQn_Type IRQn,
uint32_t priority 
)
+
+
Parameters
+ + + +
[in]IRQnThe interrupt to be configured.
[in]priorityThe priority for the interrupt, lower values denote higher priorities.
+
+
+

Configures the priority of the given interrupt.

+

The available interrupt priorities are IMPLEMENTATION DEFINED. In order to query the actual priorities one can

+
GIC_SetPriority(IRQn_TIM1, UINT32_MAX); // try to configure lowest possible priority
+
uint32_t actual = GIC_GetPriority(IRQn_TIM1); // retrieve actual lowest priority usable
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void GIC_SetTarget (IRQn_Type IRQn,
uint32_t cpu_target 
)
+
+
Parameters
+ + + +
[in]IRQnInterrupt to be configured.
[in]cpu_targetCPU interfaces to assign this interrupt to.
+
+
+

The ITARGETSR registers provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority.

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__GIC__functions.js b/docs/Core_A/html/group__GIC__functions.js new file mode 100644 index 0000000..81d4676 --- /dev/null +++ b/docs/Core_A/html/group__GIC__functions.js @@ -0,0 +1,76 @@ +var group__GIC__functions = +[ + [ "GICInterface_Type", "structGICInterface__Type.html", [ + [ "ABPR", "structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d", null ], + [ "AEOIR", "structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89", null ], + [ "AHPPIR", "structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8", null ], + [ "AIAR", "structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6", null ], + [ "APR", "structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8", null ], + [ "BPR", "structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829", null ], + [ "CTLR", "structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9", null ], + [ "DIR", "structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa", null ], + [ "EOIR", "structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb", null ], + [ "HPPIR", "structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6", null ], + [ "IAR", "structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea", null ], + [ "IIDR", "structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf", null ], + [ "NSAPR", "structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4", null ], + [ "PMR", "structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b", null ], + [ "RPR", "structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821", null ], + [ "STATUSR", "structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e", null ] + ] ], + [ "GICDistributor_Type", "structGICDistributor__Type.html", [ + [ "CLRSPI_NSR", "structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168", null ], + [ "CLRSPI_SR", "structGICDistributor__Type.html#ab487e4a8684b8a77357c6c20cf71dead", null ], + [ "CPENDSGIR", "structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b", null ], + [ "CTLR", "structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7", null ], + [ "ICACTIVER", "structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967", null ], + [ "ICENABLER", "structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807", null ], + [ "ICFGR", "structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5", null ], + [ "ICPENDR", "structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6", null ], + [ "IGROUPR", "structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306", null ], + [ "IGRPMODR", "structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689", null ], + [ "IIDR", "structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722", null ], + [ "IPRIORITYR", "structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9", null ], + [ "IROUTER", "structGICDistributor__Type.html#a73e0c679e5f45710deea474ab0d39cdb", null ], + [ "ISACTIVER", "structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4", null ], + [ "ISENABLER", "structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87", null ], + [ "ISPENDR", "structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5", null ], + [ "ITARGETSR", "structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c", null ], + [ "NSACR", "structGICDistributor__Type.html#a644abefb7064e434db20cc6dab5fe5f1", null ], + [ "SETSPI_NSR", "structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25", null ], + [ "SETSPI_SR", "structGICDistributor__Type.html#ad55a8644bc95caf8bf53e1407ec9ed0c", null ], + [ "SGIR", "structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1", null ], + [ "SPENDSGIR", "structGICDistributor__Type.html#ae40b4a50d9766c2bbf57441f68094f41", null ], + [ "STATUSR", "structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2", null ], + [ "TYPER", "structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207", null ] + ] ], + [ "GICDistributor", "group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6", null ], + [ "GICInterface", "group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3", null ], + [ "GIC_AcknowledgePending", "group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8", null ], + [ "GIC_ClearPendingIRQ", "group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d", null ], + [ "GIC_CPUInterfaceInit", "group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9", null ], + [ "GIC_DisableDistributor", "group__GIC__functions.html#ga363311538d4a4d750197b9936505d466", null ], + [ "GIC_DisableInterface", "group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e", null ], + [ "GIC_DisableIRQ", "group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d", null ], + [ "GIC_DistInit", "group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1", null ], + [ "GIC_DistributorImplementer", "group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6", null ], + [ "GIC_DistributorInfo", "group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f", null ], + [ "GIC_Enable", "group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e", null ], + [ "GIC_EnableDistributor", "group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6", null ], + [ "GIC_EnableInterface", "group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce", null ], + [ "GIC_EnableIRQ", "group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3", null ], + [ "GIC_EndInterrupt", "group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd", null ], + [ "GIC_GetBinaryPoint", "group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906", null ], + [ "GIC_GetHighPendingIRQ", "group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1", null ], + [ "GIC_GetInterfaceId", "group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50", null ], + [ "GIC_GetInterfacePriorityMask", "group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728", null ], + [ "GIC_GetIRQStatus", "group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f", null ], + [ "GIC_GetPriority", "group__GIC__functions.html#ga397048004654f792649742f95bf8ae67", null ], + [ "GIC_GetTarget", "group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8", null ], + [ "GIC_SendSGI", "group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9", null ], + [ "GIC_SetBinaryPoint", "group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6", null ], + [ "GIC_SetInterfacePriorityMask", "group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0", null ], + [ "GIC_SetPendingIRQ", "group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c", null ], + [ "GIC_SetPriority", "group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71", null ], + [ "GIC_SetTarget", "group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__L1__cache__functions.html b/docs/Core_A/html/group__L1__cache__functions.html new file mode 100644 index 0000000..91f9d82 --- /dev/null +++ b/docs/Core_A/html/group__L1__cache__functions.html @@ -0,0 +1,445 @@ + + + + + +L1 Cache Functions +CMSIS-Core (Cortex-A): L1 Cache Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
L1 Cache Functions
Core Peripherals
+
+
+ +

L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_FORCEINLINE void L1C_EnableCaches (void)
 Enable Caches by setting I and C bits in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_DisableCaches (void)
 Disable Caches by clearing I and C bits in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_EnableBTAC (void)
 Enable Branch Prediction by setting Z bit in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_DisableBTAC (void)
 Disable Branch Prediction by clearing Z bit in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateBTAC (void)
 Invalidate entire branch predictor array. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateICacheAll (void)
 Invalidate the whole instruction cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanDCacheMVA (void *va)
 Clean data cache line by address. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA (void *va)
 Invalidate data cache line by address. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA (void *va)
 Clean and Invalidate data cache by address. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateCache (uint32_t op)
 Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll (void)
 Invalidate the whole data cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanDCacheAll (void)
 Clean the whole data cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll (void)
 Clean and invalidate the whole data cache. More...
 
CMSIS_DEPRECATED
+__STATIC_FORCEINLINE void 		__L1C_CleanInvalidateCache (uint32_t op)
 Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE __ASM void __L1C_CleanInvalidateCache (uint32_t op)
+
+
Parameters
+ + +
[in]op0 - invalidate, 1 - clean, otherwise - invalidate and clean
+
+
+
Deprecated:
Use generic L1C_CleanInvalidateCache instead.
+

Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.

+

The parameter op defines which cleaning/invalidation strategy should be used:

+
    +
  • 0 - Cache is invalidated using DCISW register.
    • +
  • 1 - Cache is cleaned using DCCSW register.
    • +
  • other - Cache is invalidated and cleaned using DCCISW register.
    • +
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_CleanDCacheAll (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_CleanDCacheMVA (void * va)
+
+
Parameters
+ + +
[in]vaPointer to data to clear the cache for.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_CleanInvalidateCache (uint32_t op)
+
+
Parameters
+ + +
[in]op0 - invalidate, 1 - clean, otherwise - invalidate and clean
+
+
+

Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_CleanInvalidateDCacheAll (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA (void * va)
+
+
Parameters
+ + +
[in]vaPointer to data to invalidate the cache for.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_DisableBTAC (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_DisableCaches (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_EnableBTAC (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_EnableCaches (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_InvalidateBTAC (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_InvalidateDCacheAll (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_InvalidateDCacheMVA (void * va)
+
+
Parameters
+ + +
[in]vaPointer to data to invalidate the cache for.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L1C_InvalidateICacheAll (void )
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__L1__cache__functions.js b/docs/Core_A/html/group__L1__cache__functions.js new file mode 100644 index 0000000..35b7516 --- /dev/null +++ b/docs/Core_A/html/group__L1__cache__functions.js @@ -0,0 +1,17 @@ +var group__L1__cache__functions = +[ + [ "__L1C_CleanInvalidateCache", "group__L1__cache__functions.html#ga722ceb077e491bb4befcfbb3aee9b20b", null ], + [ "L1C_CleanDCacheAll", "group__L1__cache__functions.html#ga70359d824bf26f376e3d7cb9c787da27", null ], + [ "L1C_CleanDCacheMVA", "group__L1__cache__functions.html#ga9eb6f0a7c9c04cc49efd964eb59ba26f", null ], + [ "L1C_CleanInvalidateCache", "group__L1__cache__functions.html#ga30d7632156a30a3b75064f6d15b8f850", null ], + [ "L1C_CleanInvalidateDCacheAll", "group__L1__cache__functions.html#ga92b5babf7317abe3815f61a2731735c3", null ], + [ "L1C_CleanInvalidateDCacheMVA", "group__L1__cache__functions.html#ga7646a5e01b529566968f393e485f46a2", null ], + [ "L1C_DisableBTAC", "group__L1__cache__functions.html#gab8695cf1f4a7f3789b93c41dc4eeb51d", null ], + [ "L1C_DisableCaches", "group__L1__cache__functions.html#ga320ef6fd1dd65f2f82e64c096a4994a6", null ], + [ "L1C_EnableBTAC", "group__L1__cache__functions.html#gaa5fb36b4496e64472849f7811970c581", null ], + [ "L1C_EnableCaches", "group__L1__cache__functions.html#gaff8a4966eff1ada5cba80f2b689446db", null ], + [ "L1C_InvalidateBTAC", "group__L1__cache__functions.html#gad0d732293be6a928db184b59aadc1979", null ], + [ "L1C_InvalidateDCacheAll", "group__L1__cache__functions.html#gae895f75c4f3539058232f555d79e5df3", null ], + [ "L1C_InvalidateDCacheMVA", "group__L1__cache__functions.html#ga9209853937940991daf70edd6bc633fe", null ], + [ "L1C_InvalidateICacheAll", "group__L1__cache__functions.html#gac932810cfe83f087590859010972645e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__L2__cache__functions.html b/docs/Core_A/html/group__L2__cache__functions.html new file mode 100644 index 0000000..8744749 --- /dev/null +++ b/docs/Core_A/html/group__L2__cache__functions.html @@ -0,0 +1,377 @@ + + + + + +L2C-310 Cache Controller Functions +CMSIS-Core (Cortex-A): L2C-310 Cache Controller Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
L2C-310 Cache Controller Functions
Core Peripherals
+
+
+ +

L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.
+Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual. +More...

+ + + + + +

+Data Structures

struct  L2C_310_TypeDef
 Union type to access the L2C_310 Cache Controller. More...
 
+ + + + +

+Macros

#define L2C_310   ((L2C_310_TypeDef *)L2C_310_BASE)
 L2C_310 register set access pointer. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void L2C_Sync (void)
 Cache Sync operation by writing CACHE_SYNC register. More...
 
__STATIC_INLINE int L2C_GetID (void)
 Read cache controller cache ID from CACHE_ID register. More...
 
__STATIC_INLINE int L2C_GetType (void)
 Read cache controller cache type from CACHE_TYPE register. More...
 
__STATIC_INLINE void L2C_InvAllByWay (void)
 Invalidate all cache by way. More...
 
__STATIC_INLINE void L2C_CleanInvAllByWay (void)
 Clean and Invalidate all cache by way. More...
 
__STATIC_INLINE void L2C_Enable (void)
 Enable Level 2 Cache. More...
 
__STATIC_INLINE void L2C_Disable (void)
 Disable Level 2 Cache. More...
 
__STATIC_INLINE void L2C_InvPa (void *pa)
 Invalidate cache by physical address. More...
 
__STATIC_INLINE void L2C_CleanPa (void *pa)
 Clean cache by physical address. More...
 
__STATIC_INLINE void L2C_CleanInvPa (void *pa)
 Clean and invalidate cache by physical address. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define L2C_310   ((L2C_310_TypeDef *)L2C_310_BASE)
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_CleanInvAllByWay (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_CleanInvPa (void * pa)
+
+
Parameters
+ + +
[in]paPointer to data to invalidate cache for.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_CleanPa (void * pa)
+
+
Parameters
+ + +
[in]paPointer to data to invalidate cache for.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_Disable (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_Enable (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE int L2C_GetID (void )
+
+
Returns
L2C_310_TypeDef::CACHE_ID
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE int L2C_GetType (void )
+
+
Returns
L2C_310_TypeDef::CACHE_TYPE
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_InvAllByWay (void )
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_InvPa (void * pa)
+
+
Parameters
+ + +
[in]paPointer to data to invalidate cache for.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void L2C_Sync (void )
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__L2__cache__functions.js b/docs/Core_A/html/group__L2__cache__functions.js new file mode 100644 index 0000000..bf173b3 --- /dev/null +++ b/docs/Core_A/html/group__L2__cache__functions.js @@ -0,0 +1,57 @@ +var group__L2__cache__functions = +[ + [ "L2C_310_TypeDef", "structL2C__310__TypeDef.html", [ + [ "ADDRESS_FILTER_END", "structL2C__310__TypeDef.html#a956e7653f25ae52ac9534eb0e1d94c8c", null ], + [ "ADDRESS_FILTER_START", "structL2C__310__TypeDef.html#ae3f752040cdfcabd337b3f0359216b11", null ], + [ "AUX_CNT", "structL2C__310__TypeDef.html#a4f7bc7277a5baa1d804913e41b8200be", null ], + [ "CACHE_ID", "structL2C__310__TypeDef.html#a87833c2acdf685d6ad6d0811f45677d7", null ], + [ "CACHE_SYNC", "structL2C__310__TypeDef.html#ab9b9d1842b5d9e828a6825533ab80c0f", null ], + [ "CACHE_TYPE", "structL2C__310__TypeDef.html#af19e1fd8a729834557884232c9e50bd2", null ], + [ "CLEAN_INV_LINE_INDEX_WAY", "structL2C__310__TypeDef.html#a2adcc6bff9e527be24076d197368a962", null ], + [ "CLEAN_INV_LINE_PA", "structL2C__310__TypeDef.html#a61615f4a4ac97d5d278000a35100d795", null ], + [ "CLEAN_INV_WAY", "structL2C__310__TypeDef.html#ae27fc13cf14eae85ad7ed2c86fd30f6c", null ], + [ "CLEAN_LINE_INDEX_WAY", "structL2C__310__TypeDef.html#ac79d3397741a3ae8566c878b45d30970", null ], + [ "CLEAN_LINE_PA", "structL2C__310__TypeDef.html#a400d9ededaf12a5193e01d7235f3d65d", null ], + [ "CLEAN_WAY", "structL2C__310__TypeDef.html#a0e6d40fb25420d5cac5be15ad2662e2c", null ], + [ "CONTROL", "structL2C__310__TypeDef.html#a491a4ed1ecdcdf784b180fa13ef46f2f", null ], + [ "DATA_LOCK_0_WAY", "structL2C__310__TypeDef.html#a2dbbc5c93d3ddffe2459c053d30ede2d", null ], + [ "DATA_LOCK_1_WAY", "structL2C__310__TypeDef.html#a6288cc2774812105b52a22daedd0c39f", null ], + [ "DATA_LOCK_2_WAY", "structL2C__310__TypeDef.html#acdbc2d1db5722edc69752fe78a5c477d", null ], + [ "DATA_LOCK_3_WAY", "structL2C__310__TypeDef.html#a331d20510fc27cd593ddfedc88c75240", null ], + [ "DATA_LOCK_4_WAY", "structL2C__310__TypeDef.html#aa0a0f2165e329d514cc91dbf84a44a76", null ], + [ "DATA_LOCK_5_WAY", "structL2C__310__TypeDef.html#a6f777080cbf9426d8476d07f6e583d71", null ], + [ "DATA_LOCK_6_WAY", "structL2C__310__TypeDef.html#ab81366685e54829cae7613f080d69f53", null ], + [ "DATA_LOCK_7_WAY", "structL2C__310__TypeDef.html#aed70f16007d4e7d19818e0931581c5a5", null ], + [ "DEBUG_CONTROL", "structL2C__310__TypeDef.html#a996a2a5c1f311a6f3555844adc28e7f4", null ], + [ "EVENT_CONTROL", "structL2C__310__TypeDef.html#a2bc6f09ea83f8d3c966558598a098995", null ], + [ "EVENT_COUNTER0_CONF", "structL2C__310__TypeDef.html#a1c78032b2b237ee968d6758bddc915ba", null ], + [ "EVENT_COUNTER1_CONF", "structL2C__310__TypeDef.html#a4465c7dd7b45f8f35acde8c6e28cbd17", null ], + [ "INST_LOCK_0_WAY", "structL2C__310__TypeDef.html#a50ed69958acada08cce2c93b609097ad", null ], + [ "INST_LOCK_1_WAY", "structL2C__310__TypeDef.html#acba26dcc19591924d2ad088a0b8302fa", null ], + [ "INST_LOCK_2_WAY", "structL2C__310__TypeDef.html#a98c744b09e490fa49beb452ddbc29ffd", null ], + [ "INST_LOCK_3_WAY", "structL2C__310__TypeDef.html#aca5cecc05dae56be40cb1b0852b78490", null ], + [ "INST_LOCK_4_WAY", "structL2C__310__TypeDef.html#a0a54ef3839f09715962f7cc04879d6b8", null ], + [ "INST_LOCK_5_WAY", "structL2C__310__TypeDef.html#a9464799ec7797bacade9eacd4703bad2", null ], + [ "INST_LOCK_6_WAY", "structL2C__310__TypeDef.html#a990118c9674df74beb6879b3f6dbcbc6", null ], + [ "INST_LOCK_7_WAY", "structL2C__310__TypeDef.html#a6240652959732fbb74bbee91d4b487d0", null ], + [ "INTERRUPT_CLEAR", "structL2C__310__TypeDef.html#a43116dfea74e77e870fd790189a403ec", null ], + [ "INTERRUPT_MASK", "structL2C__310__TypeDef.html#a7c8ff2c17c6f3eb0d951e4cd193fd8e4", null ], + [ "INV_LINE_PA", "structL2C__310__TypeDef.html#a1e7c5255e61ce785f2fd5c767178c098", null ], + [ "INV_WAY", "structL2C__310__TypeDef.html#a78853d391272ff835025e8382c3c88d2", null ], + [ "LOCK_LINE_EN", "structL2C__310__TypeDef.html#a58357795f3cda2b0063411abc5165804", null ], + [ "MASKED_INT_STATUS", "structL2C__310__TypeDef.html#a207e1eb35e13440241db1109790d9740", null ], + [ "RAW_INT_STATUS", "structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637", null ], + [ "UNLOCK_ALL_BY_WAY", "structL2C__310__TypeDef.html#acb39f337a421d0640f39092dc992ef1a", null ] + ] ], + [ "L2C_310", "group__L2__cache__functions.html#ga3b08fba5b9be921c8a971231f75f8764", null ], + [ "L2C_CleanInvAllByWay", "group__L2__cache__functions.html#gabd0a9b10926537fa283c0bb30d54abc7", null ], + [ "L2C_CleanInvPa", "group__L2__cache__functions.html#gaaff11c6afa9eaacb4cdfcfe5c36f57eb", null ], + [ "L2C_CleanPa", "group__L2__cache__functions.html#ga242f6fa13f33e7d5cdd7d92935d52f5f", null ], + [ "L2C_Disable", "group__L2__cache__functions.html#ga66767e7f30f52d72de72231b2d6abd34", null ], + [ "L2C_Enable", "group__L2__cache__functions.html#ga720c36b4cd1d6c070ed0d2c49cffd7e1", null ], + [ "L2C_GetID", "group__L2__cache__functions.html#ga75af64212e1d3d0b3ade860c365e95b3", null ], + [ "L2C_GetType", "group__L2__cache__functions.html#ga0c334fa25720d77e78cfa187bdf833be", null ], + [ "L2C_InvAllByWay", "group__L2__cache__functions.html#ga5b0ea2db52d137b5531ce568479c9d17", null ], + [ "L2C_InvPa", "group__L2__cache__functions.html#ga4cf213e72c97776def35ab8223face82", null ], + [ "L2C_Sync", "group__L2__cache__functions.html#ga164c59c55e2d18bf8a94dc91c0f4ce68", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__MMU__defs__gr.html b/docs/Core_A/html/group__MMU__defs__gr.html new file mode 100644 index 0000000..d4a5089 --- /dev/null +++ b/docs/Core_A/html/group__MMU__defs__gr.html @@ -0,0 +1,1269 @@ + + + + + +MMU Defines and Structs +CMSIS-Core (Cortex-A): MMU Defines and Structs + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Enumerations
+
+
MMU Defines and Structs
Memory Management Unit Functions
+
+
+ +

Defines and structures that relate to the Memory Management Unit. +More...

+ + + + +

+Data Structures

struct  mmu_region_attributes_Type
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define SECTION_DESCRIPTOR   (0x2)
 
#define SECTION_B_SHIFT   (2)
 
#define SECTION_C_SHIFT   (3)
 
#define SECTION_TEX0_SHIFT   (12)
 
#define SECTION_TEX1_SHIFT   (13)
 
#define SECTION_TEX2_SHIFT   (14)
 
#define SECTION_XN_SHIFT   (4)
 
#define SECTION_DOMAIN_SHIFT   (5)
 
#define SECTION_P_SHIFT   (9)
 
#define SECTION_AP_SHIFT   (10)
 
#define SECTION_AP2_SHIFT   (15)
 
#define SECTION_S_SHIFT   (16)
 
#define SECTION_NG_SHIFT   (17)
 
#define SECTION_NS_SHIFT   (19)
 
#define PAGE_L1_DESCRIPTOR   (0x1)
 
#define PAGE_L2_4K_DESC   (0x2)
 
#define PAGE_L2_64K_DESC   (0x1)
 
#define PAGE_4K_B_SHIFT   (2)
 
#define PAGE_4K_C_SHIFT   (3)
 
#define PAGE_4K_TEX0_SHIFT   (6)
 
#define PAGE_4K_TEX1_SHIFT   (7)
 
#define PAGE_4K_TEX2_SHIFT   (8)
 
#define PAGE_64K_B_SHIFT   (2)
 
#define PAGE_64K_C_SHIFT   (3)
 
#define PAGE_64K_TEX0_SHIFT   (12)
 
#define PAGE_64K_TEX1_SHIFT   (13)
 
#define PAGE_64K_TEX2_SHIFT   (14)
 
#define PAGE_B_SHIFT   (2)
 
#define PAGE_C_SHIFT   (3)
 
#define PAGE_TEX_SHIFT   (12)
 
#define PAGE_XN_4K_SHIFT   (0)
 
#define PAGE_XN_64K_SHIFT   (15)
 
#define PAGE_DOMAIN_SHIFT   (5)
 
#define PAGE_P_SHIFT   (9)
 
#define PAGE_AP_SHIFT   (4)
 
#define PAGE_AP2_SHIFT   (9)
 
#define PAGE_S_SHIFT   (10)
 
#define PAGE_NG_SHIFT   (11)
 
#define PAGE_NS_SHIFT   (3)
 
#define OFFSET_1M   (0x00100000)
 
#define OFFSET_64K   (0x00010000)
 
#define OFFSET_4K   (0x00001000)
 
#define DESCRIPTOR_FAULT   (0x00000000)
 
#define section_normal(descriptor_l1, region)
 
#define section_normal_cod(descriptor_l1, region)
 
#define section_normal_ro(descriptor_l1, region)
 
#define section_normal_rw(descriptor_l1, region)
 
#define section_so(descriptor_l1, region)
 
#define section_device_ro(descriptor_l1, region)
 
#define section_device_rw(descriptor_l1, region)
 
#define page4k_device_rw(descriptor_l1, descriptor_l2, region)
 
#define page64k_device_rw(descriptor_l1, descriptor_l2, region)
 
+ + + + + + + + + + + + + + + + + + + +

+Enumerations

enum  mmu_region_size_Type {
+  SECTION, +
+  PAGE_4k, +
+  PAGE_64k +
+ }
 
enum  mmu_memory_Type {
+  NORMAL, +
+  DEVICE, +
+  SHARED_DEVICE, +
+  NON_SHARED_DEVICE, +
+  STRONGLY_ORDERED +
+ }
 
enum  mmu_cacheability_Type {
+  NON_CACHEABLE, +
+  WB_WA, +
+  WT, +
+  WB_NO_WA +
+ }
 
enum  mmu_ecc_check_Type {
+  ECC_DISABLED, +
+  ECC_ENABLED +
+ }
 
enum  mmu_execute_Type {
+  EXECUTE, +
+  NON_EXECUTE +
+ }
 
enum  mmu_global_Type {
+  GLOBAL, +
+  NON_GLOBAL +
+ }
 
enum  mmu_shared_Type {
+  NON_SHARED, +
+  SHARED +
+ }
 
enum  mmu_secure_Type {
+  SECURE, +
+  NON_SECURE +
+ }
 
enum  mmu_access_Type {
+  NO_ACCESS, +
+  RW, +
+  READ +
+ }
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define DESCRIPTOR_FAULT   (0x00000000)
+
+ +
+
+ +
+
+ + + + +
#define OFFSET_1M   (0x00100000)
+
+ +
+
+ +
+
+ + + + +
#define OFFSET_4K   (0x00001000)
+
+ +
+
+ +
+
+ + + + +
#define OFFSET_64K   (0x00010000)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define page4k_device_rw( descriptor_l1,
 descriptor_l2,
 region 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
#define page64k_device_rw( descriptor_l1,
 descriptor_l2,
 region 
)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_4K_B_SHIFT   (2)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_4K_C_SHIFT   (3)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_4K_TEX0_SHIFT   (6)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_4K_TEX1_SHIFT   (7)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_4K_TEX2_SHIFT   (8)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_64K_B_SHIFT   (2)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_64K_C_SHIFT   (3)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_64K_TEX0_SHIFT   (12)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_64K_TEX1_SHIFT   (13)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_64K_TEX2_SHIFT   (14)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_AP2_SHIFT   (9)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_AP_SHIFT   (4)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_B_SHIFT   (2)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_C_SHIFT   (3)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_DOMAIN_SHIFT   (5)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_L1_DESCRIPTOR   (0x1)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_L2_4K_DESC   (0x2)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_L2_64K_DESC   (0x1)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_NG_SHIFT   (11)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_NS_SHIFT   (3)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_P_SHIFT   (9)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_S_SHIFT   (10)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_TEX_SHIFT   (12)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_XN_4K_SHIFT   (0)
+
+ +
+
+ +
+
+ + + + +
#define PAGE_XN_64K_SHIFT   (15)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_AP2_SHIFT   (15)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_AP_SHIFT   (10)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_B_SHIFT   (2)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_C_SHIFT   (3)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_DESCRIPTOR   (0x2)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_device_ro( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_device_rw( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_DOMAIN_SHIFT   (5)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_NG_SHIFT   (17)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_normal( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_normal_cod( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_normal_ro( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_normal_rw( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_NS_SHIFT   (19)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_P_SHIFT   (9)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_S_SHIFT   (16)
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define section_so( descriptor_l1,
 region 
)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_TEX0_SHIFT   (12)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_TEX1_SHIFT   (13)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_TEX2_SHIFT   (14)
+
+ +
+
+ +
+
+ + + + +
#define SECTION_XN_SHIFT   (4)
+
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum mmu_access_Type
+
+ + + + +
Enumerator
NO_ACCESS  +
RW  +
READ  +
+ +
+
+ +
+
+ + + + +
enum mmu_cacheability_Type
+
+ + + + + +
Enumerator
NON_CACHEABLE  +
WB_WA  +
WT  +
WB_NO_WA  +
+ +
+
+ +
+
+ + + + +
enum mmu_ecc_check_Type
+
+ + + +
Enumerator
ECC_DISABLED  +
ECC_ENABLED  +
+ +
+
+ +
+
+ + + + +
enum mmu_execute_Type
+
+ + + +
Enumerator
EXECUTE  +
NON_EXECUTE  +
+ +
+
+ +
+
+ + + + +
enum mmu_global_Type
+
+ + + +
Enumerator
GLOBAL  +
NON_GLOBAL  +
+ +
+
+ +
+
+ + + + +
enum mmu_memory_Type
+
+ + + + + + +
Enumerator
NORMAL  +
DEVICE  +
SHARED_DEVICE  +
NON_SHARED_DEVICE  +
STRONGLY_ORDERED  +
+ +
+
+ +
+
+ + + + +
enum mmu_region_size_Type
+
+ + + + +
Enumerator
SECTION  +
PAGE_4k  +
PAGE_64k  +
+ +
+
+ +
+
+ + + + +
enum mmu_secure_Type
+
+ + + +
Enumerator
SECURE  +
NON_SECURE  +
+ +
+
+ +
+
+ + + + +
enum mmu_shared_Type
+
+ + + +
Enumerator
NON_SHARED  +
SHARED  +
+ +
+
+
+
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+Content | +Functions
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Memory Management Unit Functions
Core Peripherals
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+ +

MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition. +More...

+ + + + + +

+Content

 MMU Defines and Structs
 Defines and structures that relate to the Memory Management Unit.
 
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+Functions

__STATIC_INLINE int MMU_XNSection (uint32_t *descriptor_l1, mmu_execute_Type xn)
 Set section execution-never attribute. More...
 
__STATIC_INLINE int MMU_DomainSection (uint32_t *descriptor_l1, uint8_t domain)
 Set section domain. More...
 
__STATIC_INLINE int MMU_PSection (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 Set section parity check. More...
 
__STATIC_INLINE int MMU_APSection (uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
 Set section access privileges. More...
 
__STATIC_INLINE int MMU_SharedSection (uint32_t *descriptor_l1, mmu_shared_Type s_bit)
 Set section shareability. More...
 
__STATIC_INLINE int MMU_GlobalSection (uint32_t *descriptor_l1, mmu_global_Type g_bit)
 Set section Global attribute. More...
 
__STATIC_INLINE int MMU_SecureSection (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 Set section Security attribute. More...
 
__STATIC_INLINE int MMU_XNPage (uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
 Set 4k/64k page execution-never attribute. More...
 
__STATIC_INLINE int MMU_DomainPage (uint32_t *descriptor_l1, uint8_t domain)
 Set 4k/64k page domain. More...
 
__STATIC_INLINE int MMU_PPage (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 Set 4k/64k page parity check. More...
 
__STATIC_INLINE int MMU_APPage (uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
 Set 4k/64k page access privileges. More...
 
__STATIC_INLINE int MMU_SharedPage (uint32_t *descriptor_l2, mmu_shared_Type s_bit)
 Set 4k/64k page shareability. More...
 
__STATIC_INLINE int MMU_GlobalPage (uint32_t *descriptor_l2, mmu_global_Type g_bit)
 Set 4k/64k page Global attribute. More...
 
__STATIC_INLINE int MMU_SecurePage (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 Set 4k/64k page Security attribute. More...
 
__STATIC_INLINE int MMU_MemorySection (uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
 Set Section memory attributes. More...
 
__STATIC_INLINE int MMU_MemoryPage (uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
 Set 4k/64k page memory attributes. More...
 
__STATIC_INLINE int MMU_GetSectionDescriptor (uint32_t *descriptor, mmu_region_attributes_Type reg)
 Create a L1 section descriptor. More...
 
__STATIC_INLINE int MMU_GetPageDescriptor (uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
 Create a L1 and L2 4k/64k page descriptor. More...
 
__STATIC_INLINE void MMU_TTSection (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
 Create a 1MB Section. More...
 
__STATIC_INLINE void MMU_TTPage4k (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)
 Create a 4k page entry. More...
 
__STATIC_INLINE void MMU_TTPage64k (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)
 Create a 64k page entry. More...
 
__STATIC_INLINE void MMU_Enable (void)
 Enable MMU. More...
 
__STATIC_INLINE void MMU_Disable (void)
 Disable MMU. More...
 
__STATIC_INLINE void MMU_InvalidateTLB (void)
 Invalidate entire unified TLB. More...
 
+

Description

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Function Documentation

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__STATIC_INLINE int MMU_APPage (uint32_t * descriptor_l2,
mmu_access_Type user,
mmu_access_Type priv,
uint32_t afe 
)
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Parameters
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[out]descriptor_l2L2 descriptor.
[in]userUser Level Access: NO_ACCESS, RW, READ
[in]privPrivilege Level Access: NO_ACCESS, RW, READ
[in]afeAccess flag enable
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Returns
0
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The function sets 4k/64k page access privileges

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__STATIC_INLINE int MMU_APSection (uint32_t * descriptor_l1,
mmu_access_Type user,
mmu_access_Type priv,
uint32_t afe 
)
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Parameters
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[out]descriptor_l1L1 descriptor.
[in]userUser Level Access: NO_ACCESS, RW, READ
[in]privPrivilege Level Access: NO_ACCESS, RW, READ
[in]afeAccess flag enable
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Returns
0
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The function sets section access privileges

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__STATIC_INLINE void MMU_Disable (void )
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__STATIC_INLINE int MMU_DomainPage (uint32_t * descriptor_l1,
uint8_t domain 
)
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Parameters
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[out]descriptor_l1L1 descriptor.
[in]domainPage domain
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Returns
0
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The function sets 4k/64k page domain

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__STATIC_INLINE int MMU_DomainSection (uint32_t * descriptor_l1,
uint8_t domain 
)
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Parameters
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[out]descriptor_l1L1 descriptor.
[in]domainSection domain
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Returns
0
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The function sets section domain.

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__STATIC_INLINE void MMU_Enable (void )
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Set M bit 0 to enable the MMU Set AFE bit to enable simplified access permissions model Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking

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__STATIC_INLINE int MMU_GetPageDescriptor (uint32_t * descriptor,
uint32_t * descriptor2,
mmu_region_attributes_Type reg 
)
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Parameters
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[out]descriptorL1 descriptor
[out]descriptor2L2 descriptor
[in]reg4k/64k page attributes
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Returns
0
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The function creates a 4k/64k page descriptor. Assumptions:

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  • TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
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  • Functions always return 0
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__STATIC_INLINE int MMU_GetSectionDescriptor (uint32_t * descriptor,
mmu_region_attributes_Type reg 
)
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Parameters
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[out]descriptorL1 descriptor
[in]regSection attributes
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Returns
0
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The function creates a section descriptor.

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__STATIC_INLINE int MMU_GlobalPage (uint32_t * descriptor_l2,
mmu_global_Type g_bit 
)
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Parameters
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[out]descriptor_l2L2 descriptor.
[in]g_bit4k/64k page attribute: GLOBAL, NON_GLOBAL
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Returns
0
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The function sets 4k/64k page Global attribute

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+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_GlobalSection (uint32_t * descriptor_l1,
mmu_global_Type g_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]g_bitSection attribute: GLOBAL, NON_GLOBAL
+
+
+
Returns
0
+

The function sets section Global attribute

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void MMU_InvalidateTLB (void )
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_MemoryPage (uint32_t * descriptor_l2,
mmu_memory_Type mem,
mmu_cacheability_Type outer,
mmu_cacheability_Type inner,
mmu_region_size_Type page 
)
+
+
Parameters
+ + + + + + +
[out]descriptor_l2L2 descriptor.
[in]mem4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
[in]outerOuter cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
[in]innerInner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
[in]pagePage size
+
+
+
Returns
0
+

The function sets 4k/64k page memory attributes

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_MemorySection (uint32_t * descriptor_l1,
mmu_memory_Type mem,
mmu_cacheability_Type outer,
mmu_cacheability_Type inner 
)
+
+
Parameters
+ + + + + +
[out]descriptor_l1L1 descriptor.
[in]memSection memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
[in]outerOuter cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
[in]innerInner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+
+
Returns
0
+

The function sets section memory attributes

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_PPage (uint32_t * descriptor_l1,
mmu_ecc_check_Type p_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]p_bitParity check: ECC_DISABLED, ECC_ENABLED
+
+
+
Returns
0
+

The function sets 4k/64k page parity check

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_PSection (uint32_t * descriptor_l1,
mmu_ecc_check_Type p_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]p_bitParity check: ECC_DISABLED, ECC_ENABLED
+
+
+
Returns
0
+

The function sets section parity check

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_SecurePage (uint32_t * descriptor_l1,
mmu_secure_Type s_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]s_bit4k/64k page Security attribute: SECURE, NON_SECURE
+
+
+
Returns
0
+

The function sets 4k/64k page Global attribute

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_SecureSection (uint32_t * descriptor_l1,
mmu_secure_Type s_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]s_bitSection Security attribute: SECURE, NON_SECURE
+
+
+
Returns
0
+

The function sets section Global attribute

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_SharedPage (uint32_t * descriptor_l2,
mmu_shared_Type s_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l2L2 descriptor.
[in]s_bit4k/64k page shareability: NON_SHARED, SHARED
+
+
+
Returns
0
+

The function sets 4k/64k page shareability

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_SharedSection (uint32_t * descriptor_l1,
mmu_shared_Type s_bit 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]s_bitSection shareability: NON_SHARED, SHARED
+
+
+
Returns
0
+

The function sets section shareability

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void MMU_TTPage4k (uint32_t * ttb,
uint32_t base_address,
uint32_t count,
uint32_t descriptor_l1,
uint32_t * ttb_l2,
uint32_t descriptor_l2 
)
+
+
Parameters
+ + + + + + + +
[in]ttbL1 table base address
[in]base_address4k base address
[in]countNumber of 4k pages to create
[in]descriptor_l1L1 descriptor (region attributes)
[in]ttb_l2L2 table base address
[in]descriptor_l2L2 descriptor (region attributes)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void MMU_TTPage64k (uint32_t * ttb,
uint32_t base_address,
uint32_t count,
uint32_t descriptor_l1,
uint32_t * ttb_l2,
uint32_t descriptor_l2 
)
+
+
Parameters
+ + + + + + + +
[in]ttbL1 table base address
[in]base_address64k base address
[in]countNumber of 64k pages to create
[in]descriptor_l1L1 descriptor (region attributes)
[in]ttb_l2L2 table base address
[in]descriptor_l2L2 descriptor (region attributes)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void MMU_TTSection (uint32_t * ttb,
uint32_t base_address,
uint32_t count,
uint32_t descriptor_l1 
)
+
+
Parameters
+ + + + + +
[in]ttbTranslation table base address
[in]base_addressSection base address
[in]countNumber of sections to create
[in]descriptor_l1L1 descriptor (region attributes)
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_XNPage (uint32_t * descriptor_l2,
mmu_execute_Type xn,
mmu_region_size_Type page 
)
+
+
Parameters
+ + + + +
[out]descriptor_l2L2 descriptor.
[in]xnPage execution-never attribute : EXECUTE , NON_EXECUTE.
[in]pagePage size: PAGE_4k, PAGE_64k,
+
+
+
Returns
0
+

The function sets 4k/64k page execution-never attribute

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE int MMU_XNSection (uint32_t * descriptor_l1,
mmu_execute_Type xn 
)
+
+
Parameters
+ + + +
[out]descriptor_l1L1 descriptor.
[in]xnSection execution-never attribute : EXECUTE , NON_EXECUTE.
+
+
+
Returns
0
+

The function sets section execution-never attribute

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__MMU__functions.js b/docs/Core_A/html/group__MMU__functions.js new file mode 100644 index 0000000..773413f --- /dev/null +++ b/docs/Core_A/html/group__MMU__functions.js @@ -0,0 +1,28 @@ +var group__MMU__functions = +[ + [ "MMU Defines and Structs", "group__MMU__defs__gr.html", "group__MMU__defs__gr" ], + [ "MMU_APPage", "group__MMU__functions.html#gac7c88d4d613350059b4d77814ea2c7a0", null ], + [ "MMU_APSection", "group__MMU__functions.html#ga946866c84a72690c385ee07545bf8145", null ], + [ "MMU_Disable", "group__MMU__functions.html#ga2a2badd06531e04f559b97fdb2aea154", null ], + [ "MMU_DomainPage", "group__MMU__functions.html#ga45f5389cb1351bb2806a38ac8c32d416", null ], + [ "MMU_DomainSection", "group__MMU__functions.html#gabd88f4c41b74365c38209692785287d0", null ], + [ "MMU_Enable", "group__MMU__functions.html#ga63334cbd77d310d078eb226c7542b96b", null ], + [ "MMU_GetPageDescriptor", "group__MMU__functions.html#gaa2fcfb63c7019665b8a352d54f55d740", null ], + [ "MMU_GetSectionDescriptor", "group__MMU__functions.html#ga4f21eee79309cf8cde694d0d7e1205bd", null ], + [ "MMU_GlobalPage", "group__MMU__functions.html#ga14dfeaf8983de57521aaa66c19dd43c9", null ], + [ "MMU_GlobalSection", "group__MMU__functions.html#ga3ca22117a7f2d3c4d1cd1bf832cc4d2f", null ], + [ "MMU_InvalidateTLB", "group__MMU__functions.html#ga9de65bea1cabf73dc4302e0e727cc8c3", null ], + [ "MMU_MemoryPage", "group__MMU__functions.html#ga9a2946f7c93bcb05cdd20be691a54b8c", null ], + [ "MMU_MemorySection", "group__MMU__functions.html#ga353d3d794bcd1b35b3b5aeb73d6feb08", null ], + [ "MMU_PPage", "group__MMU__functions.html#gab15289c416609cd56dde816b39a4cea4", null ], + [ "MMU_PSection", "group__MMU__functions.html#ga3577aec23189228c9f95abba50c3716d", null ], + [ "MMU_SecurePage", "group__MMU__functions.html#ga2c1887ed6aaff0a51e3effc3db595c94", null ], + [ "MMU_SecureSection", "group__MMU__functions.html#ga84a5a15ee353d70a9b904e3814bd94d8", null ], + [ "MMU_SharedPage", "group__MMU__functions.html#gaaa19560532778e4fdc667e56fd2dd378", null ], + [ "MMU_SharedSection", "group__MMU__functions.html#ga29ea426394746cdd6a4b4c14164ec6b9", null ], + [ "MMU_TTPage4k", "group__MMU__functions.html#ga823cca9649a28bab8a90f8bd9bb92d83", null ], + [ "MMU_TTPage64k", "group__MMU__functions.html#ga48c509501f94a3f7316e79f8ccd34184", null ], + [ "MMU_TTSection", "group__MMU__functions.html#gaaff28ea191391cbbd389d74327961753", null ], + [ "MMU_XNPage", "group__MMU__functions.html#gab0e0fed40d998757147beb8fcf05a890", null ], + [ "MMU_XNSection", "group__MMU__functions.html#ga9132cbfe3b2367de3db27daf4cc82ad7", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__PL1__timer__functions.html b/docs/Core_A/html/group__PL1__timer__functions.html new file mode 100644 index 0000000..946be94 --- /dev/null +++ b/docs/Core_A/html/group__PL1__timer__functions.html @@ -0,0 +1,339 @@ + + + + + +Generic Physical Timer Functions +CMSIS-Core (Cortex-A): Generic Physical Timer Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Functions
+
+
Generic Physical Timer Functions
Core Peripherals
+
+
+ +

Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.
+Reference: Cortex-A7 MPCore Technical Reference Manual. +More...

+ + + + + +

+Data Structures

union  CNTP_CTL_Type
 Physical Timer Control register. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void PL1_SetCounterFrequency (uint32_t value)
 Configures the frequency the timer shall run at. More...
 
__STATIC_INLINE void PL1_SetLoadValue (uint32_t value)
 Sets the reset value of the timer. More...
 
__STATIC_INLINE uint32_t PL1_GetCurrentValue ()
 Get the current counter value. More...
 
__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue (void)
 Get the current physical counter value. More...
 
__STATIC_INLINE void PL1_SetPhysicalCompareValue (uint64_t value)
 Set the physical compare value. More...
 
__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue (void)
 Get the physical compare value. More...
 
__STATIC_INLINE void PL1_SetControl (uint32_t value)
 Configure the timer by setting the control value. More...
 
__STATIC_INLINE uint32_t PL1_GetControl ()
 Get the control value. More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t PL1_GetControl (void )
+
+

Get the timer control value.

+
Returns
CNTP_CTL_Type Timer control value.
+
+Control value.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue (void )
+
+
Returns
Current physical counter value.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t PL1_GetCurrentValue (void )
+
+

Get the current counter value.

+
Returns
Current counter value.
+
+Current counter value.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue (void )
+
+
Returns
Physical compare value.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PL1_SetControl (uint32_t value)
+
+

Configure the timer by setting the control value.

+
Parameters
+ + + +
valueNew timer control value.
[in]valueNew timer control value.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PL1_SetCounterFrequency (uint32_t value)
+
+

Configures the frequency the timer shall run at.

+
Parameters
+ + + +
valueThe timer frequency in Hz.
[in]valueThe timer frequency in Hz.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PL1_SetLoadValue (uint32_t value)
+
+

Sets the reset value of the timer.

+
Parameters
+ + + +
valueThe value the timer is loaded with.
[in]valueThe value the timer is loaded with.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PL1_SetPhysicalCompareValue (uint64_t value)
+
+
Parameters
+ + +
[in]valueNew physical timer compare value.
+
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__PL1__timer__functions.js b/docs/Core_A/html/group__PL1__timer__functions.js new file mode 100644 index 0000000..785f0e2 --- /dev/null +++ b/docs/Core_A/html/group__PL1__timer__functions.js @@ -0,0 +1,20 @@ +var group__PL1__timer__functions = +[ + [ "CNTP_CTL_Type", "unionCNTP__CTL__Type.html", [ + [ "_reserved0", "unionCNTP__CTL__Type.html#a033fc913891068a89b1609af783db8a8", null ], + [ "b", "unionCNTP__CTL__Type.html#acfac7f6bcdcf74d339bea24b437d977e", null ], + [ "b", "unionCNTP__CTL__Type.html#afdd6b14cdb03e4e694ec7db8163916b0", null ], + [ "ENABLE", "unionCNTP__CTL__Type.html#a3b7426f99d1ecdacd172999b4d04b210", null ], + [ "IMASK", "unionCNTP__CTL__Type.html#a07e23afbd292bcb84f15ea27ae2c157d", null ], + [ "ISTATUS", "unionCNTP__CTL__Type.html#acb2f8900c7f6960443df47c1f2f2add3", null ], + [ "w", "unionCNTP__CTL__Type.html#a0e2d443e0447f9b286433220cd288dbf", null ] + ] ], + [ "PL1_GetControl", "group__PL1__timer__functions.html#gaf7fda3fe3452565fbe46cb0ea53a9f8a", null ], + [ "PL1_GetCurrentPhysicalValue", "group__PL1__timer__functions.html#gac66bd336d2353f70aa8ebfc73aa3fc43", null ], + [ "PL1_GetCurrentValue", "group__PL1__timer__functions.html#ga8a212e9457005edfb9f14afbf937ebf9", null ], + [ "PL1_GetPhysicalCompareValue", "group__PL1__timer__functions.html#ga341ae7d1ae29f4dc5dae6310fa453164", null ], + [ "PL1_SetControl", "group__PL1__timer__functions.html#ga2e2ea7eac12a90c6243000172bf774e1", null ], + [ "PL1_SetCounterFrequency", "group__PL1__timer__functions.html#gac09f09327fde6a6adffe0e6298eaa1db", null ], + [ "PL1_SetLoadValue", "group__PL1__timer__functions.html#gae4edcfbdaf901a59a81d1fbf9845d9f7", null ], + [ "PL1_SetPhysicalCompareValue", "group__PL1__timer__functions.html#gab34067824971064a829e17b791070643", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__PTM__timer__functions.html b/docs/Core_A/html/group__PTM__timer__functions.html new file mode 100644 index 0000000..23051df --- /dev/null +++ b/docs/Core_A/html/group__PTM__timer__functions.html @@ -0,0 +1,296 @@ + + + + + +Private Timer Functions +CMSIS-Core (Cortex-A): Private Timer Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Structures | +Macros | +Functions
+
+
Private Timer Functions
Core Peripherals
+
+
+ +

Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.
+References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual. +More...

+ + + + + +

+Data Structures

struct  Timer_Type
 Structure type to access the Private Timer. More...
 
+ + + + +

+Macros

#define PTIM   ((Timer_Type *) TIMER_BASE )
 Timer register struct. More...
 
+ + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void PTIM_SetLoadValue (uint32_t value)
 Set the load value to timers LOAD register. More...
 
__STATIC_INLINE uint32_t PTIM_GetLoadValue (void)
 Get the load value from timers LOAD register. More...
 
__STATIC_INLINE uint32_t PTIM_GetCurrentValue (void)
 Get current counter value from timers COUNTER register. More...
 
__STATIC_INLINE void PTIM_SetControl (uint32_t value)
 Configure the timer using its CONTROL register. More...
 
__STATIC_INLINE uint32_t PTIM_GetControl (void)
 
__STATIC_INLINE void PTIM_ClearEventFlag (void)
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define PTIM   ((Timer_Type *) TIMER_BASE )
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void PTIM_ClearEventFlag (void )
+
+

ref Timer_Type::CONTROL Clears the event flag in timers ISR register.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t PTIM_GetControl (void )
+
+

ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.

+
Returns
Timer_Type::CONTROL
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t PTIM_GetCurrentValue (void )
+
+
Returns
Timer_Type::COUNTER
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t PTIM_GetLoadValue (void )
+
+
Returns
Timer_Type::LOAD
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PTIM_SetControl (uint32_t value)
+
+
Parameters
+ + +
[in]valueThe new configuration value to be set.
+
+
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void PTIM_SetLoadValue (uint32_t value)
+
+
Parameters
+ + +
[in]valueThe load value to be set.
+
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__PTM__timer__functions.js b/docs/Core_A/html/group__PTM__timer__functions.js new file mode 100644 index 0000000..9e97896 --- /dev/null +++ b/docs/Core_A/html/group__PTM__timer__functions.js @@ -0,0 +1,22 @@ +var group__PTM__timer__functions = +[ + [ "Timer_Type", "structTimer__Type.html", [ + [ "CONTROL", "structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4", null ], + [ "COUNTER", "structTimer__Type.html#ac933977724591e6ca87d91848fc7a6b6", null ], + [ "ISR", "structTimer__Type.html#ace17db6ca92940b030ad2ccbc674877e", null ], + [ "LOAD", "structTimer__Type.html#a073457d2d18c2eff93fd12aec81ef20b", null ], + [ "WCONTROL", "structTimer__Type.html#ac04581b452702517bfbfa61f9af4c6dd", null ], + [ "WCOUNTER", "structTimer__Type.html#a7a763d92fbcb506a28a22de548934abc", null ], + [ "WDISABLE", "structTimer__Type.html#a9d577164e0a55ecd6c630a9720f153c3", null ], + [ "WISR", "structTimer__Type.html#a6239a36319b919b809e00dd26db105fc", null ], + [ "WLOAD", "structTimer__Type.html#a6855bbb5d49f336c9f995dcce492455a", null ], + [ "WRESET", "structTimer__Type.html#a775e70c9dbf2b562f9884a9e0dded741", null ] + ] ], + [ "PTIM", "group__PTM__timer__functions.html#gaaaf976e808e92970c4853195f46f86aa", null ], + [ "PTIM_ClearEventFlag", "group__PTM__timer__functions.html#ga59dca62df390bc4bce18559fc7d28578", null ], + [ "PTIM_GetControl", "group__PTM__timer__functions.html#ga34f0ceea142a4be1479cb552bf8bc4d1", null ], + [ "PTIM_GetCurrentValue", "group__PTM__timer__functions.html#gaaccd88ab7931c379817f71d7c0183586", null ], + [ "PTIM_GetLoadValue", "group__PTM__timer__functions.html#gacca3bf92e93c69e538ff4618317f7bfa", null ], + [ "PTIM_SetControl", "group__PTM__timer__functions.html#gaabc1dba029389fe0e2a6297952df7972", null ], + [ "PTIM_SetLoadValue", "group__PTM__timer__functions.html#ga30516fed24977be8eecf3efd8b6a2fea", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__comp__cntrl__gr.html b/docs/Core_A/html/group__comp__cntrl__gr.html new file mode 100644 index 0000000..7454667 --- /dev/null +++ b/docs/Core_A/html/group__comp__cntrl__gr.html @@ -0,0 +1,337 @@ + + + + + +Compiler Control +CMSIS-Core (Cortex-A): Compiler Control + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Compiler Control
+
+
+ +

Compiler agnostic #define symbols for generic C/C++ source code. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define __ARM_ARCH_7A__   1
 Set to 1 when generating code for Armv7-A (Cortex-A7) More...
 
#define __ASM   __asm
 Pass information from the compiler to the assembler. More...
 
#define __INLINE   __inline
 Recommend that function should be inlined by the compiler. More...
 
#define __STATIC_INLINE   static __inline
 Define a static function should be inlined by the compiler. More...
 
#define __NO_RETURN   __declspec(noreturn)
 Inform the compiler that a function does not return. More...
 
#define __USED   __attribute__((used))
 Inform that a variable shall be retained in executable image. More...
 
#define __WEAK   __attribute__((weak))
 Export a function or variable weakly to allow overwrites. More...
 
#define __ALIGNED(x)   __attribute__((aligned(x)))
 Minimum alignment for a variable. More...
 
#define __PACKED   __attribute__((packed))
 Request smallest possible alignment. More...
 
+

Description

+

The CMSIS-Core provides the header file cmsis_compiler.h with consistent #define symbols to generate C or C++ source files that should be compiler agnostic. Each CMSIS compliant compiler should support the functionality described in this section.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + +
#define __ALIGNED( x)   __attribute__((aligned(x)))
+
+

Specifies a minimum alignment for a variable or structure field, measured in bytes.

+

Code Example:

+
uint32_t stack_space[0x100] __ALIGNED(8); // 8-byte alignment required
+
+
+
+ +
+
+ + + + +
#define __ARM_ARCH_7A__   1
+
+

The #define ARM_ARCH_7A is set to 1 when generating code for the Armv7-A architecture. This architecture is for example used by the Cortex-A7 processor.

+ +
+
+ +
+
+ + + + +
#define __ASM   __asm
+
+

The __ASM keyword can declare or define an embedded assembly function or incorporate inline assembly into a function (shown in the code example below).

+

Code Example:

+
// Reverse bit order of value
+
+
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+
{
+
uint32_t result;
+
+
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+
return(result);
+
}
+
+
+
+ +
+
+ + + + +
#define __INLINE   __inline
+
+

Inline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to inline code or not. The __INLINE attribute gives the compiler an hint to inline this function. Still, the compiler may decide not to inline the function. As the function is global an callable function is also generated.

+

Code Example:

+
const uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};
+
+
//------------------------------------------------------------------------------
+
// Switch on LEDs
+
//------------------------------------------------------------------------------
+
__INLINE static void LED_On (uint32_t led) {
+
+
PTD->PCOR = led_mask[led];
+
}
+
+
+
+ +
+
+ + + + +
#define __NO_RETURN   __declspec(noreturn)
+
+

Informs the compiler that the function does not return. The compiler can then perform optimizations by removing code that is never reached.

+

Code Example:

+
// OS idle demon (running when no other thread is ready to run).
+
+
__NO_RETURN void os_idle_demon (void);
+
+
+
+ +
+
+ + + + +
#define __PACKED   __attribute__((packed))
+
+

Specifies that a type must have the smallest possible alignment.

+

Code Example:

+
struct foo {
+
uint8_t u8;
+
uint32_t u32[2] __PACKED;
+
};
+
+
+
+ +
+
+ + + + +
#define __STATIC_INLINE   static __inline
+
+

Defines a static function that may be inlined by the compiler. If the compiler generates inline code for all calls to this functions, no additional function implementation is generated which may further optimize space.

+

Code Example:

+
__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
+
{
+
return((uint32_t)GICDistributor->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)]);
+
}
+
+
+
+ +
+
+ + + + +
#define __USED   __attribute__((used))
+
+

Definitions tagged with __USED in the source code should be not removed by the linker when detected as unused.

+

Code Example:

+
// Export following variables for debugging
+
__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
+
__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
+
__USED uint32_t const os_clockrate = OS_TICK;
+
__USED uint32_t const os_timernum = 0;
+
+
+
+ +
+
+ + + + +
#define __WEAK   __attribute__((weak))
+
+

Functions defined with __WEAK export their symbols weakly. A function defined weak behaves like a normal defined function unless a non-weak function with the same name is linked into the same image. If both a non-weak function and a weak defined function exist in the same image, then all calls to the function resolve to the non-weak function.

+

Functions declared with __WEAK and then defined without __WEAK behave as non-weak functions.

+

Code Example:

+
__WEAK void SystemInit(void)
+
{
+
SystemCoreSetup();
+
SystemCoreClockSetup();
+
}
+
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__comp__cntrl__gr.js b/docs/Core_A/html/group__comp__cntrl__gr.js new file mode 100644 index 0000000..d7eb628 --- /dev/null +++ b/docs/Core_A/html/group__comp__cntrl__gr.js @@ -0,0 +1,12 @@ +var group__comp__cntrl__gr = +[ + [ "__ALIGNED", "group__comp__cntrl__gr.html#gaa65ef8f7a5e8b7a6ea6c1d48b4c78e55", null ], + [ "__ARM_ARCH_7A__", "group__comp__cntrl__gr.html#gaee91bdfb2b6986731af09835bc9c6e74", null ], + [ "__ASM", "group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd", null ], + [ "__INLINE", "group__comp__cntrl__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb", null ], + [ "__NO_RETURN", "group__comp__cntrl__gr.html#ga153a4a31b276a9758959580538720a51", null ], + [ "__PACKED", "group__comp__cntrl__gr.html#gabe8996d3d985ee1529475443cc635bf1", null ], + [ "__STATIC_INLINE", "group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c", null ], + [ "__USED", "group__comp__cntrl__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0", null ], + [ "__WEAK", "group__comp__cntrl__gr.html#gac607bf387b29162be6a9b77fc7999539", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__irq__ctrl__gr.html b/docs/Core_A/html/group__irq__ctrl__gr.html new file mode 100644 index 0000000..6122a40 --- /dev/null +++ b/docs/Core_A/html/group__irq__ctrl__gr.html @@ -0,0 +1,1061 @@ + + + + + +Interrupts and Exceptions +CMSIS-Core (Cortex-A): Interrupts and Exceptions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Functions
+
+
Interrupts and Exceptions
+
+
+ +

Generic functions to access the Interrupt Controller. +More...

+ + + + + + + + +

+Content

 IRQ Mode Bit-Masks
 Configure interrupt line mode.
 
 IRQ Priority Bit-Masks
 Definitions used by interrupt priority functions.
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

int32_t IRQ_Initialize (void)
 Initialize interrupt controller. More...
 
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler)
 Register interrupt handler. More...
 
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn)
 Get the registered interrupt handler. More...
 
int32_t IRQ_Enable (IRQn_ID_t irqn)
 Enable interrupt. More...
 
int32_t IRQ_Disable (IRQn_ID_t irqn)
 Disable interrupt. More...
 
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn)
 Get interrupt enable state. More...
 
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)
 Configure interrupt request mode. More...
 
uint32_t IRQ_GetMode (IRQn_ID_t irqn)
 Get interrupt mode configuration. More...
 
IRQn_ID_t IRQ_GetActiveIRQ (void)
 Get ID number of current interrupt request (IRQ). More...
 
IRQn_ID_t IRQ_GetActiveFIQ (void)
 Get ID number of current fast interrupt request (FIQ). More...
 
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn)
 Signal end of interrupt processing. More...
 
int32_t IRQ_SetPending (IRQn_ID_t irqn)
 Set interrupt pending flag. More...
 
uint32_t IRQ_GetPending (IRQn_ID_t irqn)
 Get interrupt pending flag. More...
 
int32_t IRQ_ClearPending (IRQn_ID_t irqn)
 Clear interrupt pending flag. More...
 
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)
 Set interrupt priority value. More...
 
uint32_t IRQ_GetPriority (IRQn_ID_t irqn)
 Get interrupt priority. More...
 
int32_t IRQ_SetPriorityMask (uint32_t priority)
 Set priority masking threshold. More...
 
uint32_t IRQ_GetPriorityMask (void)
 Get priority masking threshold. More...
 
int32_t IRQ_SetPriorityGroupBits (uint32_t bits)
 Set priority grouping field split point. More...
 
uint32_t IRQ_GetPriorityGroupBits (void)
 Get priority grouping field split point. More...
 
+

Description

+

This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers. The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.

+
Note
The default implementation for Arm GIC (Generic Interrupt Controller) can be found in irq_ctrl_gic.c. It uses weak functions thus it can easily be overwritten by an alternative user implementation if needed.
+

The Armv7-A architecture defines a common set of first level exceptions, see table below.

+ + + + + + + + + + + + + + + + + + + +
Exception CMSIS Handler Offset Description
Reset Reset_Handler 0x0000 First instruction executed after reset.
Undefined Instruction (Undef) Undef_Handler 0x0004 Signals usage of an illegal instructions.
Supervisor Call (SVC) SVC_Handler 0x0008 Issued by software using SVC instruction.
Prefetch Abort (PAbt) PAbt_Handler 0x000C Signals a memory abort on istruction fetch.
Data Abort (DAbt) DAbt_Handler 0x0010 Signals a memory abort on data read or write.
Hyp Trap (NOP) 0x0014 Hypervisor instruction trap, only available with Virtualization Extensions.
IRQ interrupt IRQ_Handler 0x0018 Interrupt Request (typically from Interrupt Controller)
FIQ interrupt FIQ_Handler 0x001C Fast Interrupt Request (typically from Interrupt Controller)
+

By default those handlers are defined as weak empty functions by the device specific startup code. Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using RTX5.

+

The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined as IRQn_Type in Device Header File <device.h>. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes and preemption rules, and register interrupt callbacks.

+

Example:

+
void SGI0_Handler() {
+
/*
+
* Handle Interrupt
+
*/
+
+
IRQ_ClearPending((IRQn_ID_t)SGI0_IRQn);
+
}
+
+
void main() {
+
/* Initialize the Interrupt Controller */
+
IRQ_Initialize();
+
+
/* Register the user defined handler function */
+
IRQ_SetHandler((IRQn_ID_t)SGI0_IRQn, SGI0_Handler);
+
+
/* Set the priority considering the priority grouping */
+
const uint32_t subprio = IRQ_GetPriorityGroupBits();
+
IRQ_SetPriority((IRQn_ID_t)SGI0_IRQn, 1u << subprio);
+
+
/* Set interrupt mode to falling edge */
+
IRQ_SetMode((IRQn_ID_t)SGI0_IRQn, IRQ_MODE_TYPE_IRQ | IRQ_MODE_CPU_0 | IRQ_MODE_TRIG_EDGE | IRQ_MODE_TRIG_EDGE_FALLING);
+
+
IRQ_Enable((IRQn_ID_t)SGI0_IRQn);
+
+
/* Trigger interrupt */
+
IRQ_SetPending((IRQn_ID_t)SGI0_IRQn);
+
+
IRQ_Disable((IRQn_ID_t)SGI0_IRQn);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
int32_t IRQ_ClearPending (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 on success, -1 on error.
+

This function clears the pending status of the interrupt identified by the irqn parameter.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
+
int32_t status;
+
+
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
GIC_ClearPendingIRQ ((IRQn_Type)irqn);
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_Disable (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 on success, -1 on error.
+

This function disables forwarding of the corresponding interrupt to the CPU.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_Disable (IRQn_ID_t irqn) {
+
int32_t status;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
GIC_DisableIRQ ((IRQn_Type)irqn);
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_Enable (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 on success, -1 on error.
+

This function enables forwarding of the corresponding interrupt to the CPU.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_Enable (IRQn_ID_t irqn) {
+
int32_t status;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
GIC_EnableIRQ ((IRQn_Type)irqn);
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 on success, -1 on error.
+

This function informs the interrupt controller that the interrupt service routine processing of the currently active interrupt request is completed.

+

The parameter irqn should specify the value previously returned by the IRQ_GetActiveIRQ or IRQ_GetActiveFIQ functions.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
+
int32_t status;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
GIC_EndInterrupt ((IRQn_Type)irqn);
+
+
if (irqn == 0) {
+
IRQ_ID0 = 0U;
+
}
+
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
IRQn_ID_t IRQ_GetActiveFIQ (void )
+
+
Returns
interrupt ID number.
+

This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.

+

For Arm GIC the default implementation looks like the following example:

+
IRQn_ID_t IRQ_GetActiveFIQ (void) {
+
// FIQ is not supported, return invalid ID
+
return ((IRQn_ID_t)-1);
+
}
+
+
+
+ +
+
+ + + + + + + + +
IRQn_ID_t IRQ_GetActiveIRQ (void )
+
+
Returns
interrupt ID number.
+

This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.

+

For Arm GIC the default implementation looks like the following example:

+
IRQn_ID_t IRQ_GetActiveIRQ (void) {
+
IRQn_ID_t irqn;
+
+
irqn = (IRQn_ID_t)GIC_AcknowledgePending();
+
+
return (irqn);
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 - interrupt is disabled, 1 - interrupt is enabled.
+

This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.

+

Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts which cannot be identified by irqn.

+

For Arm GIC the default implementation looks like the following example:

+
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
+
uint32_t enable;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
+
} else {
+
enable = 0U;
+
}
+
+
return (enable);
+
}
+
+
+
+ +
+
+ + + + + + + + +
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
registered interrupt handler function address.
+

This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt ID number.

+

For Arm GIC the default implementation looks like the following example:

+
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
+
IRQHandler h;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
h = IRQTable[irqn];
+
} else {
+
h = (IRQHandler_t)0;
+
}
+
+
return (h);
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t IRQ_GetMode (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
+

This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter. IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.

+

For Arm GIC the default implementation looks like the following example:

+
uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
+
uint32_t mode;
+
uint32_t val;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
mode = IRQ_MODE_TYPE_IRQ;
+
+
// Get trigger mode
+
val = GIC_GetConfiguration((IRQn_Type)irqn);
+
+
if ((val & 2U) != 0U) {
+
// Corresponding interrupt is edge triggered
+
mode |= IRQ_MODE_TRIG_EDGE;
+
} else {
+
// Corresponding interrupt is level triggered
+
mode |= IRQ_MODE_TRIG_LEVEL;
+
}
+
+
// Get interrupt CPU targets
+
mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
+
+
} else {
+
mode = IRQ_MODE_ERROR;
+
}
+
+
return (mode);
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t IRQ_GetPending (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 - interrupt is not pending, 1 - interrupt is pending.
+

This function retrieves the pending status of the interrupt identified by the irqn parameter.

+

Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which cannot be identified by irqn.

+

For Arm GIC the default implementation looks like the following example:

+
uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
+
uint32_t pending;
+
+
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
+
} else {
+
pending = 0U;
+
}
+
+
return (pending & 1U);
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t IRQ_GetPriority (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
+

This function retrieves the priority of the interrupt identified by the irqn parameter.

+

The valid priority value can be from zero (0) to the value of IRQ_PRIORITY_Msk. IRQ_PRIORITY_ERROR bit is set in returned value for interrupts which cannot be identified by irqn.

+

For Arm GIC the default implementation looks like the following example:

+
uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
+
uint32_t priority;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
priority = GIC_GetPriority ((IRQn_Type)irqn);
+
} else {
+
priority = IRQ_PRIORITY_ERROR;
+
}
+
+
return (priority);
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t IRQ_GetPriorityGroupBits (void )
+
+
Returns
current number of MSB bits included in the group priority field comparison with optional IRQ_PRIORITY_ERROR bit set.
+

This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.

+

IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.

+

For Arm GIC the default implementation looks like the following example:

+
uint32_t IRQ_GetPriorityGroupBits (void) {
+
uint32_t bp;
+
+
bp = GIC_GetBinaryPoint() & 0x07U;
+
+
return (7U - bp);
+
}
+
+
+
+ +
+
+ + + + + + + + +
uint32_t IRQ_GetPriorityMask (void )
+
+
Returns
current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
+

This function retrieves the priority masking threshold for the current processor.

+

IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.

+

For Arm GIC the default implementation looks like the following example:

+
uint32_t IRQ_GetPriorityMask (void) {
+
return GIC_GetInterfacePriorityMask();
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_Initialize (void )
+
+
Returns
0 on success, -1 on error.
+

This function initializes interrupt controller.

+

It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should be set to NULL.

+

For Arm GIC the default implementation looks like the following example:

+
#ifndef IRQ_GIC_LINE_COUNT
+
#define IRQ_GIC_LINE_COUNT (1020U)
+
#endif
+
+
static IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
+
+
int32_t IRQ_Initialize (void) {
+
uint32_t i;
+
+
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
+
IRQTable[i] = (IRQHandler)NULL;
+
}
+
GIC_Enable();
+
return (0);
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t IRQ_SetHandler (IRQn_ID_t irqn,
IRQHandler_t handler 
)
+
+
Parameters
+ + + +
[in]irqninterrupt ID number
[in]handlerinterrupt handler function address
+
+
+
Returns
0 on success, -1 on error.
+

This function registers address of the interrupt handler callback function corresponding to the specified interrupt ID number.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
+
int32_t status;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
IRQTable[irqn] = handler;
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t IRQ_SetMode (IRQn_ID_t irqn,
uint32_t mode 
)
+
+
Parameters
+ + + +
[in]irqninterrupt ID number
[in]modemode configuration
+
+
+
Returns
0 on success, -1 on error.
+

This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt (see IRQ Mode Bit-Masks) identified by the irqn parameter.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
+
int32_t status;
+
uint32_t val;
+
uint8_t cfg;
+
uint8_t secure;
+
uint8_t cpu;
+
+
status = 0;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
// Check triggering mode
+
val = (mode & IRQ_MODE_TRIG_Msk);
+
+
if (val == IRQ_MODE_TRIG_LEVEL) {
+
cfg = 0x00U;
+
} else if (val == IRQ_MODE_TRIG_EDGE) {
+
cfg = 0x02U;
+
} else {
+
status = -1;
+
}
+
+
// Check interrupt type
+
val = mode & IRQ_MODE_TYPE_Msk;
+
+
if (val != IRQ_MODE_TYPE_IRQ) {
+
status = -1;
+
}
+
+
// Check interrupt domain
+
val = mode & IRQ_MODE_DOMAIN_Msk;
+
+
if (val == IRQ_MODE_DOMAIN_NONSECURE) {
+
secure = 0;
+
} else {
+
// Check security extensions support
+
val = GIC_DistributorInfo() & (1UL << 10U);
+
+
if (val != 0U) {
+
// Security extensions are supported
+
secure = 1;
+
} else {
+
status = -1;
+
}
+
}
+
+
// Check interrupt CPU targets
+
val = mode & IRQ_MODE_CPU_Msk;
+
+
if (val == IRQ_MODE_CPU_ALL) {
+
cpu = 0xFF;
+
} else {
+
cpu = val >> IRQ_MODE_CPU_Pos;
+
}
+
+
// Apply configuration if no mode error
+
if (status == 0) {
+
GIC_SetConfiguration((IRQn_Type)irqn, cfg);
+
GIC_SetTarget ((IRQn_Type)irqn, cpu);
+
+
if (secure != 0U) {
+
GIC_SetGroup ((IRQn_Type)irqn, secure);
+
}
+
}
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_SetPending (IRQn_ID_t irqn)
+
+
Parameters
+ + +
[in]irqninterrupt ID number
+
+
+
Returns
0 on success, -1 on error.
+

This function sets the pending status of the interrupt identified by the irqn parameter.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_SetPending (IRQn_ID_t irqn) {
+
int32_t status;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
GIC_SetPendingIRQ ((IRQn_Type)irqn);
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
int32_t IRQ_SetPriority (IRQn_ID_t irqn,
uint32_t priority 
)
+
+
Parameters
+ + + +
[in]irqninterrupt ID number
[in]priorityinterrupt priority value
+
+
+
Returns
0 on success, -1 on error.
+

This function sets the priority of the interrupt identified by the irqn parameter.

+

Higher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value depends on the number of implemented priority levels.

+

The number of implemented priority bits can be determined by setting value IRQ_PRIORITY_Msk to arbitrary irqn and by retrieving the actual stored value with IRQ_GetPriority function.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
+
int32_t status;
+
+
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
+
GIC_SetPriority ((IRQn_Type)irqn, priority);
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_SetPriorityGroupBits (uint32_t bits)
+
+
Parameters
+ + +
[in]bitsnumber of MSB bits included in the group priority field comparison
+
+
+
Returns
0 on success, -1 on error.
+

This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.

+

The number of implemented group priority bits can be determined by setting value IRQ_PRIORITY_Msk and by retrieving the actual stored value with IRQ_GetPriorityGroupBits function. Function returns error status -1 if priority grouping is not supported.

+

For Arm GIC the default implementation looks like the following example:

+
int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
+
int32_t status;
+
+
if (bits == IRQ_PRIORITY_Msk) {
+
bits = 7U;
+
}
+
+
if (bits < 8U) {
+
GIC_SetBinaryPoint (7U - bits);
+
status = 0;
+
} else {
+
status = -1;
+
}
+
+
return (status);
+
}
+
+
+
+ +
+
+ + + + + + + + +
int32_t IRQ_SetPriorityMask (uint32_t priority)
+
+
Parameters
+ + +
[in]prioritypriority masking threshold value
+
+
+
Returns
0 on success, -1 on error.
+

This function sets the priority masking threshold for the current processor.

+

It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor. Function returns error status -1 if priority masking is not supported.

+

For Arm GIC the default implementation looks like the following example:

+
IRQ_SetPriorityMask (uint32_t priority) {
+
GIC_SetInterfacePriorityMask (priority);
+
return (0);
+
}
+
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__irq__ctrl__gr.js b/docs/Core_A/html/group__irq__ctrl__gr.js new file mode 100644 index 0000000..1f962d6 --- /dev/null +++ b/docs/Core_A/html/group__irq__ctrl__gr.js @@ -0,0 +1,25 @@ +var group__irq__ctrl__gr = +[ + [ "IRQ Mode Bit-Masks", "group__irq__mode__defs.html", "group__irq__mode__defs" ], + [ "IRQ Priority Bit-Masks", "group__irq__priority__defs.html", "group__irq__priority__defs" ], + [ "IRQ_ClearPending", "group__irq__ctrl__gr.html#gaad6b03f73b3d3ea2ccbb122484e8bd36", null ], + [ "IRQ_Disable", "group__irq__ctrl__gr.html#ga544cf4ae0159cc17e259d55898528248", null ], + [ "IRQ_Enable", "group__irq__ctrl__gr.html#ga4ad780a3dc23a1b6222de8adcd7c20a7", null ], + [ "IRQ_EndOfInterrupt", "group__irq__ctrl__gr.html#ga55638c35efdc7a197b51165929ef0c10", null ], + [ "IRQ_GetActiveFIQ", "group__irq__ctrl__gr.html#ga1376a5cf6ff38344a9bbbae080af5a0f", null ], + [ "IRQ_GetActiveIRQ", "group__irq__ctrl__gr.html#ga1664e9fc682c3ace4b721906d6ce2b3d", null ], + [ "IRQ_GetEnableState", "group__irq__ctrl__gr.html#ga8913613a9075a35410af0eb7b275d9e2", null ], + [ "IRQ_GetHandler", "group__irq__ctrl__gr.html#gaa2a2df8fbc7bad465ada49bd690f65d5", null ], + [ "IRQ_GetMode", "group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711", null ], + [ "IRQ_GetPending", "group__irq__ctrl__gr.html#gaa399f9169f136b3930f0d50247aa22fc", null ], + [ "IRQ_GetPriority", "group__irq__ctrl__gr.html#ga0a6a18c8fa2bc3183598439b56c507c3", null ], + [ "IRQ_GetPriorityGroupBits", "group__irq__ctrl__gr.html#ga061da812739bdba1e32765ed6501b83c", null ], + [ "IRQ_GetPriorityMask", "group__irq__ctrl__gr.html#ga77632ae73f1ba46c4a9a0c12e6bc4869", null ], + [ "IRQ_Initialize", "group__irq__ctrl__gr.html#ga03ea5d5d67a89acff8a5b02286795a99", null ], + [ "IRQ_SetHandler", "group__irq__ctrl__gr.html#gac1fcc16fb8e488d315cfa496f1d71db3", null ], + [ "IRQ_SetMode", "group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85", null ], + [ "IRQ_SetPending", "group__irq__ctrl__gr.html#ga88aedf1dee1061783e6c05c535e7b6c4", null ], + [ "IRQ_SetPriority", "group__irq__ctrl__gr.html#gaa90aed20ac94420fff4bbbf55c12d4c2", null ], + [ "IRQ_SetPriorityGroupBits", "group__irq__ctrl__gr.html#gabaa4074988ea9e30523f7ed5a86953c2", null ], + [ "IRQ_SetPriorityMask", "group__irq__ctrl__gr.html#ga3a79888f72bd1db45f0b9a59dbaa2337", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__irq__mode__defs.html b/docs/Core_A/html/group__irq__mode__defs.html new file mode 100644 index 0000000..bfa8b83 --- /dev/null +++ b/docs/Core_A/html/group__irq__mode__defs.html @@ -0,0 +1,457 @@ + + + + + +IRQ Mode Bit-Masks +CMSIS-Core (Cortex-A): IRQ Mode Bit-Masks + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
IRQ Mode Bit-Masks
Interrupts and Exceptions
+
+
+ +

Configure interrupt line mode. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IRQ_MODE_TRIG_LEVEL   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: level triggered interrupt. More...
 
#define IRQ_MODE_TRIG_LEVEL_LOW   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: low level triggered interrupt. More...
 
#define IRQ_MODE_TRIG_LEVEL_HIGH   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: high level triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: edge triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: rising edge triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE_FALLING   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: falling edge triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE_BOTH   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: rising and falling edge triggered interrupt. More...
 
#define IRQ_MODE_TYPE_IRQ   (0x00UL << IRQ_MODE_TYPE_Pos)
 Type: interrupt source triggers CPU IRQ line. More...
 
#define IRQ_MODE_TYPE_FIQ   (0x01UL << IRQ_MODE_TYPE_Pos)
 Type: interrupt source triggers CPU FIQ line. More...
 
#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)
 Domain: interrupt is targeting non-secure domain. More...
 
#define IRQ_MODE_DOMAIN_SECURE   (0x01UL << IRQ_MODE_DOMAIN_Pos)
 Domain: interrupt is targeting secure domain. More...
 
#define IRQ_MODE_CPU_ALL   (0x00UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets all CPUs. More...
 
#define IRQ_MODE_CPU_0   (0x01UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 0. More...
 
#define IRQ_MODE_CPU_1   (0x02UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 1. More...
 
#define IRQ_MODE_CPU_2   (0x04UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 2. More...
 
#define IRQ_MODE_CPU_3   (0x08UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 3. More...
 
#define IRQ_MODE_CPU_4   (0x10UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 4. More...
 
#define IRQ_MODE_CPU_5   (0x20UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 5. More...
 
#define IRQ_MODE_CPU_6   (0x40UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 6. More...
 
#define IRQ_MODE_CPU_7   (0x80UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 7. More...
 
#define IRQ_MODE_ERROR   (0x80000000UL)
 Bit indicating mode value error. More...
 
+

Description

+

The following codes are used as values for the parameter mode of the function IRQ_SetMode to configure interrupt line mode. They are also returned by the function IRQ_GetMode when retrieving interrupt line mode.

+

The values of IRQ_MODE_TRIG_x definitions specify The values of IRQ_MODE_TYPE_x definitions specify The values of IRQ_MODE_DOMAIN_x definitions specify The values of IRQ_MODE_CPU_x definitions specify

+

Interrupt mode bit-masks

+

Macro Definition Documentation

+ +
+
+ + + + +
#define IRQ_MODE_CPU_0   (0x01UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_1   (0x02UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_2   (0x04UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_3   (0x08UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_4   (0x10UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_5   (0x20UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_6   (0x40UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_7   (0x80UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_ALL   (0x00UL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_DOMAIN_SECURE   (0x01UL << IRQ_MODE_DOMAIN_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_ERROR   (0x80000000UL)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_EDGE   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_EDGE_BOTH   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_EDGE_FALLING   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_LEVEL   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_LEVEL_HIGH   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_LEVEL_LOW   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TYPE_FIQ   (0x01UL << IRQ_MODE_TYPE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TYPE_IRQ   (0x00UL << IRQ_MODE_TYPE_Pos)
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__irq__mode__defs.js b/docs/Core_A/html/group__irq__mode__defs.js new file mode 100644 index 0000000..c7fa3a2 --- /dev/null +++ b/docs/Core_A/html/group__irq__mode__defs.js @@ -0,0 +1,24 @@ +var group__irq__mode__defs = +[ + [ "IRQ_MODE_CPU_0", "group__irq__mode__defs.html#gacb276aa0488a9bf1aa56e1072d2a15a5", null ], + [ "IRQ_MODE_CPU_1", "group__irq__mode__defs.html#gab09616a5ccd05d75d81ab80a37387a9a", null ], + [ "IRQ_MODE_CPU_2", "group__irq__mode__defs.html#ga3c8c5ec0226d772c3200d9efa2d3bf1a", null ], + [ "IRQ_MODE_CPU_3", "group__irq__mode__defs.html#ga7fe46ac2f03063dc5ed2ca793c9cca85", null ], + [ "IRQ_MODE_CPU_4", "group__irq__mode__defs.html#ga4d428c7ab66cb22eb375a109735e9a3a", null ], + [ "IRQ_MODE_CPU_5", "group__irq__mode__defs.html#ga94faa9eab45bbc6fa6b2a3c9d92bbb37", null ], + [ "IRQ_MODE_CPU_6", "group__irq__mode__defs.html#gadb512fc8a31bc771c3ce0d006b821bb9", null ], + [ "IRQ_MODE_CPU_7", "group__irq__mode__defs.html#gaa66525a1ee05c56f367540b2135e81ed", null ], + [ "IRQ_MODE_CPU_ALL", "group__irq__mode__defs.html#gad3d0505689768247c67495b7359e147f", null ], + [ "IRQ_MODE_DOMAIN_NONSECURE", "group__irq__mode__defs.html#ga7498851a6a7f3e2c5e087041617f5be7", null ], + [ "IRQ_MODE_DOMAIN_SECURE", "group__irq__mode__defs.html#ga15cdeb10ef2b8081c5cd7a87e22e65e6", null ], + [ "IRQ_MODE_ERROR", "group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a", null ], + [ "IRQ_MODE_TRIG_EDGE", "group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d", null ], + [ "IRQ_MODE_TRIG_EDGE_BOTH", "group__irq__mode__defs.html#ga8b0142ff767a9b1b1287e638eacf707b", null ], + [ "IRQ_MODE_TRIG_EDGE_FALLING", "group__irq__mode__defs.html#ga99e0f3f6945991d50e766b19e71e0222", null ], + [ "IRQ_MODE_TRIG_EDGE_RISING", "group__irq__mode__defs.html#ga2dbbbb7100be0fee6e048cd3deb50e28", null ], + [ "IRQ_MODE_TRIG_LEVEL", "group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58", null ], + [ "IRQ_MODE_TRIG_LEVEL_HIGH", "group__irq__mode__defs.html#gafeb539b2a564ca35abc57f87d71e7206", null ], + [ "IRQ_MODE_TRIG_LEVEL_LOW", "group__irq__mode__defs.html#ga326df9e34f6447583895a6f809ee160a", null ], + [ "IRQ_MODE_TYPE_FIQ", "group__irq__mode__defs.html#gaec01a80010bc42b1482388ce3ae4d2a3", null ], + [ "IRQ_MODE_TYPE_IRQ", "group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__irq__priority__defs.html b/docs/Core_A/html/group__irq__priority__defs.html new file mode 100644 index 0000000..e7254ad --- /dev/null +++ b/docs/Core_A/html/group__irq__priority__defs.html @@ -0,0 +1,172 @@ + + + + + +IRQ Priority Bit-Masks +CMSIS-Core (Cortex-A): IRQ Priority Bit-Masks + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
IRQ Priority Bit-Masks
Interrupts and Exceptions
+
+
+ +

Definitions used by interrupt priority functions. +More...

+ + + + + + + + +

+Macros

#define IRQ_PRIORITY_Msk   (0x0000FFFFUL)
 Interrupt priority value bit-mask. More...
 
#define IRQ_PRIORITY_ERROR   (0x80000000UL)
 Bit indicating priority value error. More...
 
+

Description

+

The following values are used by the interrupt priority functions.

+

The value of IRQ_PRIORITY_Msk specifies maximum interrupt priority value and can be used as parameter for the functions IRQ_GetPriority and IRQ_SetPriorityGroupBits to retrieve implementation specific priority values.

+

The value of IRQ_PRIORITY_ERROR is used by functions IRQ_GetPriority, IRQ_GetPriorityMask and IRQ_GetPriorityGroupBits to signal function execution error.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define IRQ_PRIORITY_ERROR   (0x80000000UL)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_PRIORITY_Msk   (0x0000FFFFUL)
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__irq__priority__defs.js b/docs/Core_A/html/group__irq__priority__defs.js new file mode 100644 index 0000000..bccbaeb --- /dev/null +++ b/docs/Core_A/html/group__irq__priority__defs.js @@ -0,0 +1,5 @@ +var group__irq__priority__defs = +[ + [ "IRQ_PRIORITY_ERROR", "group__irq__priority__defs.html#ga47b19866dc05c58c6923c313b371f881", null ], + [ "IRQ_PRIORITY_Msk", "group__irq__priority__defs.html#gabaa4e91ab84dbe5f669080af6d0d81fa", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__peripheral__gr.html b/docs/Core_A/html/group__peripheral__gr.html new file mode 100644 index 0000000..0621ef1 --- /dev/null +++ b/docs/Core_A/html/group__peripheral__gr.html @@ -0,0 +1,360 @@ + + + + + +Peripheral Access +CMSIS-Core (Cortex-A): Peripheral Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Peripheral Access
+
+
+ +

Naming conventions and optional features for accessing peripherals. +More...

+ + + + + + + + +

+Macros

#define _VAL2FLD(field, value)
 Mask and shift a bit field value for assigning the result to a peripheral register. More...
 
#define _FLD2VAL(field, value)
 Extract from a peripheral register value the a bit field value. More...
 
+

Description

+

The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The Device Header File <device.h> contains typically these definition and also includes the core specific header files.

+

The definitions for Peripheral Access can be generated using the CMSIS-SVD System View Description for Peripherals. Refer to SVDConv.exe for more information.

+

Each peripheral provides a data type definition with a name that is composed of:

+
    +
  • an optional prefix <device abbreviation>_
    • +
  • <peripheral name>
    • +
  • postfix _Type or _TypeDef to identify a type definition.
    • +
+

Examples:

+
    +
  • UART_TypeDef for the peripheral UART.
    • +
  • IMX_UART_TypeDef for the device family IMX and the peripheral UART.
    • +
+

The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.

+
    +
  • IO Type Qualifiers are used to specify the access to peripheral variables. + + + + + + + + + + + + + + +
    IO Type Qualifier Type Description
    __IM Struct member Defines 'read only' permissions
    __OM Struct member Defines 'write only' permissions
    __IOM Struct member Defines 'read / write' permissions
    __I Scalar variable Defines 'read only' permissions
    __O Scalar variable Defines 'write only' permissions
    __IO Scalar variable Defines 'read / write' permissions
    +The typedef <device abbreviation>_UART_TypeDef shown below defines the generic register layout for all UART channels in a device.
    • +
+
typedef struct {
+
__O uint32_t UART_CR; // Offset: 0x0000 ( /W) Control Register
+
__IO uint32_t UART_MR; // Offset: 0x0004 (R/W) Mode Register
+
__O uint32_t UART_IER; // Offset: 0x0008 ( /W) Interrupt Enable Register
+
__O uint32_t UART_IDR; // Offset: 0x000C ( /W) Interrupt Disable Register
+
__I uint32_t UART_IMR; // Offset: 0x0010 (R/ ) Interrupt Mask Register
+
__I uint32_t UART_SR; // Offset: 0x0014 (R/ ) Status Register
+
__I uint32_t UART_RHR; // Offset: 0x0018 (R/ ) Receive Holding Register
+
__O uint32_t UART_THR; // Offset: 0x001C ( /W) Transmit Holding Register
+
__IO uint32_t UART_BRGR; // Offset: 0x0020 (R/W) Baud Rate Generator Register
+
__IO uint32_t UART_CMPR; // Offset: 0x0024 (R/W) Comparison Register
+
__IO uint32_t UART_RTOR; // Offset: 0x0028 (R/W) Receiver Time-out Register
+
__I uint32_t RESERVED[46]; // Offset: 0x002C (R/ ) Reserved
+
__IO uint32_t UART_WPMR; // Offset: 0x00E4 (R/W) Write Protection Mode Register
+
} IMX_UART_TypeDef;
+

To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.

+

Example: In this example, IMX_UART2 and IMX_UART3 are two pointers to UARTs defined with above register structure.
+

+
#define IMX_UART2 ((IMX_UART_TypeDef *) IMX_UART2_BASE)
+
#define IMX_UART3 ((IMX_UART_TypeDef *) IMX_UART3_BASE)
+
Note
    +
  • The prefix IMX is optional.
    • +
+
+

The registers in the various UARTs can now be referred in the user code as shown below:
+

+
val = IMX_UART2->SR // is the Status Register of UART2.
+
+

+Minimal Requirements

+

To access the peripheral registers and related function in a device, the files device.h and core_ca.h define as a minimum:
+
+

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
    +
    +Example:
    typedef struct
    +
    {
    +
    __IOM uint32_t C_CTLR; // Offset: 0x0000 (R/W) CPU Interface Control Register
    +
    __IOM uint32_t C_PMR; // Offset: 0x0004 (R/W) Interrupt Priority Mask Register
    +
    __IOM uint32_t C_BPR; // Offset: 0x0008 (R/W) Binary Point Register
    +
    __IM uint32_t C_IAR; // Offset: 0x000C (R/ ) Interrupt Acknowledge Register
    +
    __OM uint32_t C_EOIR; // Offset: 0x0010 ( /W) End Of Interrupt Register
    +
    __IM uint32_t C_RPR; // Offset: 0x0014 (R/ ) Running Priority Register
    +
    __IM uint32_t C_HPPIR; // Offset: 0x0018 (R/ ) Highest Priority Pending Interrupt Register
    +
    __IOM uint32_t C_ABPR; // Offset: 0x001C (R/W) Aliased Binary Point Register
    +
    __IM uint32_t C_AIAR; // Offset: 0x0020 (R/ ) Aliased Interrupt Acknowledge Register
    +
    __OM uint32_t C_AEOIR; // Offset: 0x0024 ( /W) Aliased End Of Interrupt Register
    +
    __IM uint32_t C_AHPPIR; // Offset: 0x0028 (R/ ) Aliased Highest Priority Pending Interrupt Register
    +
    __IOM uint32_t C_STATUSR; // Offset: 0x002C (R/W) Error Reporting Status Register, optional
    +
    __I uint32_t RESERVED1[40]; // Offset: 0x0030 (R/ ) Reserved
    +
    __IOM uint32_t C_APR[4]; // Offset: 0x00D0 (R/W) Active Priority Register
    +
    __IOM uint32_t C_NSAPR[4]; // Offset: 0x00E0 (R/W) Non-secure Active Priority Register
    +
    __I uint32_t RESERVED2[3]; // Offset: 0x00F6 (R/ ) Reserved
    +
    __IM uint32_t C_IIDR; // Offset: 0x00FC (R/ ) CPU Interface Identification Register
    +
    __I uint32_t RESERVED3[960]; // Offset: 0x0100 (R/ ) Reserved
    +
    __OM uint32_t C_DIR; // Offset: 0x1000 ( /W) Deactivate Interrupt Register
    +
    } GICInterface_Type;
    +
    • +
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
    +
    +Example:
    #define GIC_INTERFACE_BASE (0xe8202000UL) // GIC Interface Base Address
    +
    • +
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typedef, multiple access definitions exist.
    +
    +Example:
    #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE) // GIC Interface Access Definition
    +
    • +
+

These definitions allow accessing peripheral registers with simple assignments.

+
    +
  • Example:
    +
    GICInterface->C_CTLR |= 1; // Enable Interface
    +
    • +
+
+

+Optional Features

+

Optionally, the file device.h may define:

+
    +
  • Register Bit Fields and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for #define constants.
    • +
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_.
    • +
+
+

+Register Bit Fields

+

For Core Register, macros define the position and the mask value for a bit field.

+

Example:

+

Bit field definitions for register ACTLR in CP15.

+
// CP15 Register ACTLR
+
#define ACTLR_DDI_Pos 28U
+
#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos)
+
+
#define ACTLR_DDVM_Pos 15U
+
#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos)
+
+
#define ACTLR_L1PCTL_Pos 13U
+
#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos)
+
+
#define ACTLR_L1RADIS_Pos 12U
+
#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos)
+
+
#define ACTLR_L2RADIS_Pos 11U
+
#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos)
+
+
#define ACTLR_DODMBS_Pos 10U
+
#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos)
+
+
#define ACTLR_SMP_Pos 6U
+
#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos)
+

The macros _VAL2FLD(field, value) and _FLD2VAL(field, value) enable access to bit fields.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _FLD2VAL( field,
 value 
)
+
+
Parameters
+ + + +
fieldname of bit field.
valuevalue of the register. This parameter is interpreted as an uint32_t type.
+
+
+

The macro _FLD2VAL uses the #define's _Pos and _Msk of the related bit field to extract the value of a bit field from a register.

+

Example:

+
i = _FLD2VAL(ACTLR_SMP, ACTLR);
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _VAL2FLD( field,
 value 
)
+
+
Parameters
+ + + +
fieldname of bit field.
valuevalue for the bit field. This parameter is interpreted as an uint32_t type.
+
+
+

The macro _VAL2FLD uses the #define's _Pos and _Msk of the related bit field to shift bit-field values for assigning to a register.

+

Example:

+
ACTLR = _VAL2FLD(ACTLR_SMP, 0x1)
+
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__peripheral__gr.js b/docs/Core_A/html/group__peripheral__gr.js new file mode 100644 index 0000000..39b83c7 --- /dev/null +++ b/docs/Core_A/html/group__peripheral__gr.js @@ -0,0 +1,5 @@ +var group__peripheral__gr = +[ + [ "_FLD2VAL", "group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444", null ], + [ "_VAL2FLD", "group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__system__init__gr.html b/docs/Core_A/html/group__system__init__gr.html new file mode 100644 index 0000000..a57dd63 --- /dev/null +++ b/docs/Core_A/html/group__system__init__gr.html @@ -0,0 +1,231 @@ + + + + + +System and Clock Configuration +CMSIS-Core (Cortex-A): System and Clock Configuration + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
System and Clock Configuration
+
+
+ +

Functions for system and clock setup available in system_device.c. +More...

+ + + + + + + + +

+Functions

void SystemInit (void)
 Function to Initialize the system. More...
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock. More...
 
+ + + + +

+Variables

uint32_t SystemCoreClock
 Variable to hold the system core clock value. More...
 
+

Description

+

Arm provides a template file system_device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

+
    +
  • A device-specific system configuration function, SystemInit().
    • +
  • A global variable that contains the system frequency, SystemCoreClock.
    • +
+

The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

+
Note
Please pay special attention to the static variable SystemCoreClock. This variable might be used throughout the whole system initialization and runtime to calculate frequency/time related values. Thus one must assure that the variable always reflects the actual system clock speed. Be aware that a value stored to SystemCoreClock during low level initialization (i.e. SystemInit()) might get overwritten by C library startup code. Thus its highly recommended to call SystemCoreClockUpdate at the beginning of the user main() routine.
+

+Code Example

+

The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an arbitrary Arm Cortex-A9.

+
#include "ARMCA9.h"
+
+
uint32_t coreClock_1 = 0; /* Variables to store core clock values */
+
uint32_t coreClock_2 = 0;
+
+
+
int main (void) {
+
+
coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */
+
+
SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */
+
+
coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */
+
+
if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
void SystemCoreClockUpdate (void )
+
+

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

+ +
+
+ +
+
+ + + + + + + + +
void SystemInit (void )
+
+

Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

+ +
+
+

Variable Documentation

+ +
+
+ + + + +
uint32_t SystemCoreClock
+
+

Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

+
Attention
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__system__init__gr.js b/docs/Core_A/html/group__system__init__gr.js new file mode 100644 index 0000000..1ed21ea --- /dev/null +++ b/docs/Core_A/html/group__system__init__gr.js @@ -0,0 +1,6 @@ +var group__system__init__gr = +[ + [ "SystemCoreClockUpdate", "group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f", null ], + [ "SystemInit", "group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2", null ], + [ "SystemCoreClock", "group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/group__version__ctrl.html b/docs/Core_A/html/group__version__ctrl.html new file mode 100644 index 0000000..38df063 --- /dev/null +++ b/docs/Core_A/html/group__version__ctrl.html @@ -0,0 +1,265 @@ + + + + + +Version Control +CMSIS-Core (Cortex-A): Version Control + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Version Control
+
+
+ +

Version symbols for CMSIS release specific C/C++ source code. +More...

+ + + + + + + + + + + + + + + + + +

+Macros

#define __CA_CMSIS_VERSION_MAIN   (1U)
 [31:16] CMSIS-Core(A) main version More...
 
#define __CA_CMSIS_VERSION_SUB   (1U)
 [15:0] CMSIS-Core(A) sub version More...
 
#define __CA_CMSIS_VERSION
 CMSIS-Core(A) version number. More...
 
#define __CA_REV   0x0000U
 Contains the core revision for a Cortex-A class device. More...
 
#define __CORTEX_A   9U
 Contains the core family for a Cortex-A class device. More...
 
+

Description

+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CA_CMSIS_VERSION
+
+

Use this define to query the full version of CMSIS-Core(A) component.

+ + + + + + + +
Bits Name Function
[31:16] MAIN __CA_CMSIS_VERSION_MAIN
[15:0] SUB __CA_CMSIS_VERSION_SUB
+

Example:

+
#if __CA_CMSIS_VERSION < 0x00050001
+
#error This code needs at least CMSIS-Core(A) version 5.1!
+
#endif
+
+
+
+ +
+
+ + + + +
#define __CA_CMSIS_VERSION_MAIN   (1U)
+
+

Use this define to query the major version of CMSIS-Core(A) component.

+

Example:

+
#if __CA_CMSIS_VERSION_MAIN < 5
+
#error This code needs at least CMSIS-Core(A) version 5!
+
#endif
+
+
+
+ +
+
+ + + + +
#define __CA_CMSIS_VERSION_SUB   (1U)
+
+

Use this define to query the minor version of CMSIS-Core(A) component.

+

Example:

+
#if __CA_CMSIS_VERSION_MAIN < 5
+
#error This code needs at least CMSIS-Core(A) version 5!
+
#else
+
#if __CA_CMSIS_VERSION_SUB < 1
+
#warning Using CMSIS-Core(A) version 5.0 compatibility functions.
+
#endif
+
#endif
+
+
+
+ +
+
+ + + + +
#define __CA_REV   0x0000U
+
+

Use this define to query the core design revision number implemented in the selected device.

+ + + + + + + +
Bits Name Function
[15:8] REV Revision number
[7:0] PATCH Patch number
+

Example:

+
#if __CA_REV < 0x0201
+
#error This code needs at least a core revision r2p1.
+
#endif
+

Core revision r0p0

+ +
+
+ +
+
+ + + + +
#define __CORTEX_A   9U
+
+

Use this define to query the actual Cortex-A class device number implemented in the selected device.

+

Example:

+
#if __CORTEX_A == 5
+
#warning Running on Cortex-A5.
+
#elif __CORTEX_A == 7
+
#warning Running on Cortex-A7.
+
#elif __CORTEX_A == 9
+
#warning Running on Cortex-A9.
+
#endif
+

Cortex-A9 Core

+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/group__version__ctrl.js b/docs/Core_A/html/group__version__ctrl.js new file mode 100644 index 0000000..fecdba1 --- /dev/null +++ b/docs/Core_A/html/group__version__ctrl.js @@ -0,0 +1,8 @@ +var group__version__ctrl = +[ + [ "__CA_CMSIS_VERSION", "group__version__ctrl.html#ga60199f17babba1ac0cf233e59043b23b", null ], + [ "__CA_CMSIS_VERSION_MAIN", "group__version__ctrl.html#ga519092cc80304900838f3d79a1a04e36", null ], + [ "__CA_CMSIS_VERSION_SUB", "group__version__ctrl.html#gaca4690227a53e24645758cdab9a00cdf", null ], + [ "__CA_REV", "group__version__ctrl.html#ga8ebf37d3e9141ccae33bb6b1edf539bd", null ], + [ "__CORTEX_A", "group__version__ctrl.html#ga74d176c89aefe783e9ce0712c4360537", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/index.html b/docs/Core_A/html/index.html new file mode 100644 index 0000000..a6e991b --- /dev/null +++ b/docs/Core_A/html/index.html @@ -0,0 +1,184 @@ + + + + + +Overview +CMSIS-Core (Cortex-A): Overview + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-Core (Cortex-A) implements the basic run-time system for a Cortex-A device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-A processor registers with standardized definitions for the GIC, FPU, MMU, Cache, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-A microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup of the system timers.
    • +
+

The following sections provide details about the CMSIS-Core (Cortex-A):

+ +
+

CMSIS-Core (Cortex-A) in ARM::CMSIS Pack

+

Files relevant to CMSIS-Core (Cortex-A) are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core_A This documentation
CMSIS\Core_A\Include CMSIS-Core (Cortex-A) header files (for example core_ca.h, etc.)
Device Arm reference implementations of Cortex-A devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
+
+

+Processor Support

+

CMSIS supports a selected subset of Cortex-A processors.

+

+Cortex-A Technical Reference Manuals

+

The following Technical Reference Manuals describe the various Arm Cortex-A processors:

+ +
+

+Tested and Verified Toolchains

+

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

+
    +
  • Arm: Arm Compiler 5.06 update 6
    • +
  • Arm: Arm Compiler 6.9
    • +
  • Arm: Arm Compiler 6.6.2
    • +
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • +
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • +
+
+
+
+ + + + diff --git a/docs/Core_A/html/irq__ctrl_8h.html b/docs/Core_A/html/irq__ctrl_8h.html new file mode 100644 index 0000000..28d93bd --- /dev/null +++ b/docs/Core_A/html/irq__ctrl_8h.html @@ -0,0 +1,464 @@ + + + + + +irq_ctrl.h File Reference +CMSIS-Core (Cortex-A): irq_ctrl.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Typedefs | +Functions
+
+
irq_ctrl.h File Reference
+
+
+ +

Interrupt Controller API header file. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define IRQ_CTRL_H_
 
#define IRQHANDLER_T
 
#define IRQN_ID_T
 
#define IRQ_MODE_TRIG_Pos   (0U)
 
#define IRQ_MODE_TRIG_Msk   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
 
#define IRQ_MODE_TRIG_LEVEL   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: level triggered interrupt. More...
 
#define IRQ_MODE_TRIG_LEVEL_LOW   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: low level triggered interrupt. More...
 
#define IRQ_MODE_TRIG_LEVEL_HIGH   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: high level triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: edge triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: rising edge triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE_FALLING   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: falling edge triggered interrupt. More...
 
#define IRQ_MODE_TRIG_EDGE_BOTH   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
 Trigger: rising and falling edge triggered interrupt. More...
 
#define IRQ_MODE_TYPE_Pos   (3U)
 
#define IRQ_MODE_TYPE_Msk   (0x01UL << IRQ_MODE_TYPE_Pos)
 
#define IRQ_MODE_TYPE_IRQ   (0x00UL << IRQ_MODE_TYPE_Pos)
 Type: interrupt source triggers CPU IRQ line. More...
 
#define IRQ_MODE_TYPE_FIQ   (0x01UL << IRQ_MODE_TYPE_Pos)
 Type: interrupt source triggers CPU FIQ line. More...
 
#define IRQ_MODE_DOMAIN_Pos   (4U)
 
#define IRQ_MODE_DOMAIN_Msk   (0x01UL << IRQ_MODE_DOMAIN_Pos)
 
#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)
 Domain: interrupt is targeting non-secure domain. More...
 
#define IRQ_MODE_DOMAIN_SECURE   (0x01UL << IRQ_MODE_DOMAIN_Pos)
 Domain: interrupt is targeting secure domain. More...
 
#define IRQ_MODE_CPU_Pos   (5U)
 
#define IRQ_MODE_CPU_Msk   (0xFFUL << IRQ_MODE_CPU_Pos)
 
#define IRQ_MODE_CPU_ALL   (0x00UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets all CPUs. More...
 
#define IRQ_MODE_CPU_0   (0x01UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 0. More...
 
#define IRQ_MODE_CPU_1   (0x02UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 1. More...
 
#define IRQ_MODE_CPU_2   (0x04UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 2. More...
 
#define IRQ_MODE_CPU_3   (0x08UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 3. More...
 
#define IRQ_MODE_CPU_4   (0x10UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 4. More...
 
#define IRQ_MODE_CPU_5   (0x20UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 5. More...
 
#define IRQ_MODE_CPU_6   (0x40UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 6. More...
 
#define IRQ_MODE_CPU_7   (0x80UL << IRQ_MODE_CPU_Pos)
 CPU: interrupt targets CPU 7. More...
 
#define IRQ_MODE_ERROR   (0x80000000UL)
 Bit indicating mode value error. More...
 
#define IRQ_PRIORITY_Msk   (0x0000FFFFUL)
 Interrupt priority value bit-mask. More...
 
#define IRQ_PRIORITY_ERROR   (0x80000000UL)
 Bit indicating priority value error. More...
 
+ + + + + + + +

+Typedefs

typedef void(* IRQHandler_t )(void)
 Interrupt handler data type. More...
 
typedef int32_t IRQn_ID_t
 Interrupt ID number data type. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

int32_t IRQ_Initialize (void)
 Initialize interrupt controller. More...
 
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler)
 Register interrupt handler. More...
 
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn)
 Get the registered interrupt handler. More...
 
int32_t IRQ_Enable (IRQn_ID_t irqn)
 Enable interrupt. More...
 
int32_t IRQ_Disable (IRQn_ID_t irqn)
 Disable interrupt. More...
 
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn)
 Get interrupt enable state. More...
 
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)
 Configure interrupt request mode. More...
 
uint32_t IRQ_GetMode (IRQn_ID_t irqn)
 Get interrupt mode configuration. More...
 
IRQn_ID_t IRQ_GetActiveIRQ (void)
 Get ID number of current interrupt request (IRQ). More...
 
IRQn_ID_t IRQ_GetActiveFIQ (void)
 Get ID number of current fast interrupt request (FIQ). More...
 
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn)
 Signal end of interrupt processing. More...
 
int32_t IRQ_SetPending (IRQn_ID_t irqn)
 Set interrupt pending flag. More...
 
uint32_t IRQ_GetPending (IRQn_ID_t irqn)
 Get interrupt pending flag. More...
 
int32_t IRQ_ClearPending (IRQn_ID_t irqn)
 Clear interrupt pending flag. More...
 
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)
 Set interrupt priority value. More...
 
uint32_t IRQ_GetPriority (IRQn_ID_t irqn)
 Get interrupt priority. More...
 
int32_t IRQ_SetPriorityMask (uint32_t priority)
 Set priority masking threshold. More...
 
uint32_t IRQ_GetPriorityMask (void)
 Get priority masking threshold. More...
 
int32_t IRQ_SetPriorityGroupBits (uint32_t bits)
 Set priority grouping field split point. More...
 
uint32_t IRQ_GetPriorityGroupBits (void)
 Get priority grouping field split point. More...
 
+

Description

+
Version
V1.0.0
+
Date
23. June 2017
+

Macro Definition Documentation

+ +
+
+ + + + +
#define IRQ_CTRL_H_
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_Msk   (0xFFUL << IRQ_MODE_CPU_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_CPU_Pos   (5U)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_DOMAIN_Msk   (0x01UL << IRQ_MODE_DOMAIN_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_DOMAIN_Pos   (4U)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_Msk   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TRIG_Pos   (0U)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TYPE_Msk   (0x01UL << IRQ_MODE_TYPE_Pos)
+
+ +
+
+ +
+
+ + + + +
#define IRQ_MODE_TYPE_Pos   (3U)
+
+ +
+
+ +
+
+ + + + +
#define IRQHANDLER_T
+
+ +
+
+ +
+
+ + + + +
#define IRQN_ID_T
+
+ +
+
+

Typedef Documentation

+ +
+
+ + + + +
typedef void(* IRQHandler_t)(void)
+
+ +
+
+ +
+
+ + + + +
typedef int32_t IRQn_ID_t
+
+ +
+
+
+
+ + + + diff --git a/docs/Core_A/html/irq__ctrl_8txt.html b/docs/Core_A/html/irq__ctrl_8txt.html new file mode 100644 index 0000000..08d420a --- /dev/null +++ b/docs/Core_A/html/irq__ctrl_8txt.html @@ -0,0 +1,129 @@ + + + + + +irq_ctrl.txt File Reference +CMSIS-Core (Cortex-A): irq_ctrl.txt File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
irq_ctrl.txt File Reference
+
+
+
+
+ + + + diff --git a/docs/Core_A/html/irq__ctrl__gic_8c.html b/docs/Core_A/html/irq__ctrl__gic_8c.html new file mode 100644 index 0000000..bac3ce6 --- /dev/null +++ b/docs/Core_A/html/irq__ctrl__gic_8c.html @@ -0,0 +1,135 @@ + + + + + +irq_ctrl_gic.c File Reference +CMSIS-Core (Cortex-A): irq_ctrl_gic.c File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
irq_ctrl_gic.c File Reference
+
+
+ +

Interrupt controller handling implementation for GIC. +More...

+

Description

+
Version
V1.0.1
+
Date
9. April 2018
+
+
+ + + + diff --git a/docs/Core_A/html/jquery.js b/docs/Core_A/html/jquery.js new file mode 100644 index 0000000..3db33e6 --- /dev/null +++ b/docs/Core_A/html/jquery.js @@ -0,0 +1,72 @@ +/*! + * jQuery JavaScript Library v1.7.1 + * http://jquery.com/ + * + * Copyright 2011, John Resig + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * Includes Sizzle.js + * http://sizzlejs.com/ + * Copyright 2011, The Dojo Foundation + * Released under the MIT, BSD, and GPL Licenses. + * + * Date: Mon Nov 21 21:11:03 2011 -0500 + */ +(function(bb,L){var av=bb.document,bu=bb.navigator,bl=bb.location;var b=(function(){var bF=function(b0,b1){return new bF.fn.init(b0,b1,bD)},bU=bb.jQuery,bH=bb.$,bD,bY=/^(?:[^#<]*(<[\w\W]+>)[^>]*$|#([\w\-]*)$)/,bM=/\S/,bI=/^\s+/,bE=/\s+$/,bA=/^<(\w+)\s*\/?>(?:<\/\1>)?$/,bN=/^[\],:{}\s]*$/,bW=/\\(?:["\\\/bfnrt]|u[0-9a-fA-F]{4})/g,bP=/"[^"\\\n\r]*"|true|false|null|-?\d+(?:\.\d*)?(?:[eE][+\-]?\d+)?/g,bJ=/(?:^|:|,)(?:\s*\[)+/g,by=/(webkit)[ \/]([\w.]+)/,bR=/(opera)(?:.*version)?[ \/]([\w.]+)/,bQ=/(msie) ([\w.]+)/,bS=/(mozilla)(?:.*? rv:([\w.]+))?/,bB=/-([a-z]|[0-9])/ig,bZ=/^-ms-/,bT=function(b0,b1){return(b1+"").toUpperCase()},bX=bu.userAgent,bV,bC,e,bL=Object.prototype.toString,bG=Object.prototype.hasOwnProperty,bz=Array.prototype.push,bK=Array.prototype.slice,bO=String.prototype.trim,bv=Array.prototype.indexOf,bx={};bF.fn=bF.prototype={constructor:bF,init:function(b0,b4,b3){var b2,b5,b1,b6;if(!b0){return this}if(b0.nodeType){this.context=this[0]=b0;this.length=1;return this}if(b0==="body"&&!b4&&av.body){this.context=av;this[0]=av.body;this.selector=b0;this.length=1;return this}if(typeof b0==="string"){if(b0.charAt(0)==="<"&&b0.charAt(b0.length-1)===">"&&b0.length>=3){b2=[null,b0,null]}else{b2=bY.exec(b0)}if(b2&&(b2[1]||!b4)){if(b2[1]){b4=b4 instanceof bF?b4[0]:b4;b6=(b4?b4.ownerDocument||b4:av);b1=bA.exec(b0);if(b1){if(bF.isPlainObject(b4)){b0=[av.createElement(b1[1])];bF.fn.attr.call(b0,b4,true)}else{b0=[b6.createElement(b1[1])]}}else{b1=bF.buildFragment([b2[1]],[b6]);b0=(b1.cacheable?bF.clone(b1.fragment):b1.fragment).childNodes}return bF.merge(this,b0)}else{b5=av.getElementById(b2[2]);if(b5&&b5.parentNode){if(b5.id!==b2[2]){return b3.find(b0)}this.length=1;this[0]=b5}this.context=av;this.selector=b0;return this}}else{if(!b4||b4.jquery){return(b4||b3).find(b0)}else{return this.constructor(b4).find(b0)}}}else{if(bF.isFunction(b0)){return b3.ready(b0)}}if(b0.selector!==L){this.selector=b0.selector;this.context=b0.context}return bF.makeArray(b0,this)},selector:"",jquery:"1.7.1",length:0,size:function(){return this.length},toArray:function(){return bK.call(this,0)},get:function(b0){return b0==null?this.toArray():(b0<0?this[this.length+b0]:this[b0])},pushStack:function(b1,b3,b0){var b2=this.constructor();if(bF.isArray(b1)){bz.apply(b2,b1)}else{bF.merge(b2,b1)}b2.prevObject=this;b2.context=this.context;if(b3==="find"){b2.selector=this.selector+(this.selector?" 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http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(hl.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var k=c(this);k.data("resizable-alsoresize",{width:parseInt(k.width(),10),height:parseInt(k.height(),10),left:parseInt(k.css("left"),10),top:parseInt(k.css("top"),10)})})};if(typeof(i.alsoResize)=="object"&&!i.alsoResize.parentNode){if(i.alsoResize.length){i.alsoResize=i.alsoResize[0];h(i.alsoResize)}else{c.each(i.alsoResize,function(j){h(j)})}}else{h(i.alsoResize)}},resize:function(g,i){var f=c(this).data("resizable"),j=f.options,h=f.originalSize,l=f.originalPosition;var k={height:(f.size.height-h.height)||0,width:(f.size.width-h.width)||0,top:(f.position.top-l.top)||0,left:(f.position.left-l.left)||0},e=function(m,n){c(m).each(function(){var q=c(this),r=c(this).data("resizable-alsoresize"),p={},o=n&&n.length?n:q.parents(i.originalElement[0]).length?["width","height"]:["width","height","top","left"];c.each(o,function(s,u){var t=(r[u]||0)+(k[u]||0);if(t&&t>=0){p[u]=t||null}});q.css(p)})};if(typeof(j.alsoResize)=="object"&&!j.alsoResize.nodeType){c.each(j.alsoResize,function(m,n){e(m,n)})}else{e(j.alsoResize)}},stop:function(e,f){c(this).removeData("resizable-alsoresize")}});c.ui.plugin.add("resizable","animate",{stop:function(i,n){var p=c(this).data("resizable"),j=p.options;var h=p._proportionallyResizeElements,e=h.length&&(/textarea/i).test(h[0].nodeName),f=e&&c.ui.hasScroll(h[0],"left")?0:p.sizeDiff.height,l=e?0:p.sizeDiff.width;var g={width:(p.size.width-l),height:(p.size.height-f)},k=(parseInt(p.element.css("left"),10)+(p.position.left-p.originalPosition.left))||null,m=(parseInt(p.element.css("top"),10)+(p.position.top-p.originalPosition.top))||null; +p.element.animate(c.extend(g,m&&k?{top:m,left:k}:{}),{duration:j.animateDuration,easing:j.animateEasing,step:function(){var o={width:parseInt(p.element.css("width"),10),height:parseInt(p.element.css("height"),10),top:parseInt(p.element.css("top"),10),left:parseInt(p.element.css("left"),10)};if(h&&h.length){c(h[0]).css({width:o.width,height:o.height})}p._updateCache(o);p._propagate("resize",i)}})}});c.ui.plugin.add("resizable","containment",{start:function(f,r){var t=c(this).data("resizable"),j=t.options,l=t.element;var g=j.containment,k=(g instanceof c)?g.get(0):(/parent/.test(g))?l.parent().get(0):g;if(!k){return}t.containerElement=c(k);if(/document/.test(g)||g==document){t.containerOffset={left:0,top:0};t.containerPosition={left:0,top:0};t.parentData={element:c(document),left:0,top:0,width:c(document).width(),height:c(document).height()||document.body.parentNode.scrollHeight}}else{var n=c(k),i=[];c(["Top","Right","Left","Bottom"]).each(function(p,o){i[p]=b(n.css("padding"+o))});t.containerOffset=n.offset();t.containerPosition=n.position();t.containerSize={height:(n.innerHeight()-i[3]),width:(n.innerWidth()-i[1])};var q=t.containerOffset,e=t.containerSize.height,m=t.containerSize.width,h=(c.ui.hasScroll(k,"left")?k.scrollWidth:m),s=(c.ui.hasScroll(k)?k.scrollHeight:e);t.parentData={element:k,left:q.left,top:q.top,width:h,height:s}}},resize:function(g,q){var t=c(this).data("resizable"),i=t.options,f=t.containerSize,p=t.containerOffset,m=t.size,n=t.position,r=t._aspectRatio||g.shiftKey,e={top:0,left:0},h=t.containerElement;if(h[0]!=document&&(/static/).test(h.css("position"))){e=p}if(n.left<(t._helper?p.left:0)){t.size.width=t.size.width+(t._helper?(t.position.left-p.left):(t.position.left-e.left));if(r){t.size.height=t.size.width/i.aspectRatio}t.position.left=i.helper?p.left:0}if(n.top<(t._helper?p.top:0)){t.size.height=t.size.height+(t._helper?(t.position.top-p.top):t.position.top);if(r){t.size.width=t.size.height*i.aspectRatio}t.position.top=t._helper?p.top:0}t.offset.left=t.parentData.left+t.position.left;t.offset.top=t.parentData.top+t.position.top;var l=Math.abs((t._helper?t.offset.left-e.left:(t.offset.left-e.left))+t.sizeDiff.width),s=Math.abs((t._helper?t.offset.top-e.top:(t.offset.top-p.top))+t.sizeDiff.height);var k=t.containerElement.get(0)==t.element.parent().get(0),j=/relative|absolute/.test(t.containerElement.css("position"));if(k&&j){l-=t.parentData.left}if(l+t.size.width>=t.parentData.width){t.size.width=t.parentData.width-l;if(r){t.size.height=t.size.width/t.aspectRatio}}if(s+t.size.height>=t.parentData.height){t.size.height=t.parentData.height-s;if(r){t.size.width=t.size.height*t.aspectRatio}}},stop:function(f,n){var q=c(this).data("resizable"),g=q.options,l=q.position,m=q.containerOffset,e=q.containerPosition,i=q.containerElement;var j=c(q.helper),r=j.offset(),p=j.outerWidth()-q.sizeDiff.width,k=j.outerHeight()-q.sizeDiff.height;if(q._helper&&!g.animate&&(/relative/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}if(q._helper&&!g.animate&&(/static/).test(i.css("position"))){c(this).css({left:r.left-e.left-m.left,width:p,height:k})}}});c.ui.plugin.add("resizable","ghost",{start:function(g,h){var e=c(this).data("resizable"),i=e.options,f=e.size;e.ghost=e.originalElement.clone();e.ghost.css({opacity:0.25,display:"block",position:"relative",height:f.height,width:f.width,margin:0,left:0,top:0}).addClass("ui-resizable-ghost").addClass(typeof i.ghost=="string"?i.ghost:"");e.ghost.appendTo(e.helper)},resize:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost){e.ghost.css({position:"relative",height:e.size.height,width:e.size.width})}},stop:function(f,g){var e=c(this).data("resizable"),h=e.options;if(e.ghost&&e.helper){e.helper.get(0).removeChild(e.ghost.get(0))}}});c.ui.plugin.add("resizable","grid",{resize:function(e,m){var p=c(this).data("resizable"),h=p.options,k=p.size,i=p.originalSize,j=p.originalPosition,n=p.axis,l=h._aspectRatio||e.shiftKey;h.grid=typeof h.grid=="number"?[h.grid,h.grid]:h.grid;var g=Math.round((k.width-i.width)/(h.grid[0]||1))*(h.grid[0]||1),f=Math.round((k.height-i.height)/(h.grid[1]||1))*(h.grid[1]||1);if(/^(se|s|e)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f}else{if(/^(ne)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f;p.position.top=j.top-f}else{if(/^(sw)$/.test(n)){p.size.width=i.width+g;p.size.height=i.height+f;p.position.left=j.left-g}else{p.size.width=i.width+g;p.size.height=i.height+f;p.position.top=j.top-f;p.position.left=j.left-g}}}}});var b=function(e){return parseInt(e,10)||0};var a=function(e){return !isNaN(parseInt(e,10))}})(jQuery);/*! + * jQuery hashchange event - v1.3 - 7/21/2010 + * http://benalman.com/projects/jquery-hashchange-plugin/ + * + * Copyright (c) 2010 "Cowboy" Ben Alman + * Dual licensed under the MIT and GPL licenses. + * http://benalman.com/about/license/ + */ +(function($,e,b){var c="hashchange",h=document,f,g=$.event.special,i=h.documentMode,d="on"+c in e&&(i===b||i>7);function a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+Macros
+
+
mem_ARMCA9.h File Reference
+
+
+ +

Memory base and size definitions (used in scatter file) +More...

+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define __ROM_BASE   0x80000000
 
#define __ROM_SIZE   0x00200000
 
#define __RAM_BASE   0x80200000
 
#define __RAM_SIZE   0x00200000
 
#define __RW_DATA_SIZE   0x00100000
 
#define __ZI_DATA_SIZE   0x000F0000
 
#define __STACK_SIZE   0x00001000
 
#define __HEAP_SIZE   0x00008000
 
#define __UND_STACK_SIZE   0x00000100
 
#define __ABT_STACK_SIZE   0x00000100
 
#define __SVC_STACK_SIZE   0x00000100
 
#define __IRQ_STACK_SIZE   0x00000100
 
#define __FIQ_STACK_SIZE   0x00000100
 
#define __TTB_BASE   0x80500000
 
#define __TTB_SIZE   0x00004000
 
+

Description

+
Version
V1.00
+
Date
10. January 2018
+
Note
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __ABT_STACK_SIZE   0x00000100
+
+ +
+
+ +
+
+ + + + +
#define __FIQ_STACK_SIZE   0x00000100
+
+ +
+
+ +
+
+ + + + +
#define __HEAP_SIZE   0x00008000
+
+ +
+
+ +
+
+ + + + +
#define __IRQ_STACK_SIZE   0x00000100
+
+ +
+
+ +
+
+ + + + +
#define __RAM_BASE   0x80200000
+
+ +
+
+ +
+
+ + + + +
#define __RAM_SIZE   0x00200000
+
+ +
+
+ +
+
+ + + + +
#define __ROM_BASE   0x80000000
+
+ +
+
+ +
+
+ + + + +
#define __ROM_SIZE   0x00200000
+
+ +
+
+ +
+
+ + + + +
#define __RW_DATA_SIZE   0x00100000
+
+ +
+
+ +
+
+ + + + +
#define __STACK_SIZE   0x00001000
+
+ +
+
+ +
+
+ + + + +
#define __SVC_STACK_SIZE   0x00000100
+
+ +
+
+ +
+
+ + + + +
#define __TTB_BASE   0x80500000
+
+ +
+
+ +
+
+ + + + +
#define __TTB_SIZE   0x00004000
+
+ +
+
+ +
+
+ + + + +
#define __UND_STACK_SIZE   0x00000100
+
+ +
+
+ +
+
+ + + + +
#define __ZI_DATA_SIZE   0x000F0000
+
+ +
+
+ + + + + + diff --git a/docs/Core_A/html/mem_h_pg.html b/docs/Core_A/html/mem_h_pg.html new file mode 100644 index 0000000..1966f22 --- /dev/null +++ b/docs/Core_A/html/mem_h_pg.html @@ -0,0 +1,220 @@ + + + + + +Memory Configuration Files mem_<device>.h +CMSIS-Core (Cortex-A): Memory Configuration Files mem_<device>.h + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Memory Configuration Files mem_<device>.h
+
+
+
/**************************************************************************//**
+ * @file     mem_<Device>.h
+ * @brief    CMSIS Cortex-A Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define MEM_<Device>_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x80000000
+#define __ROM_SIZE       0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <h> Stack / Heap Configuration
+//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     <h> Exceptional Modes
+//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//     </h>
+//   </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x80200000
+#define __RAM_SIZE       0x00200000
+
+#define __RW_DATA_SIZE   0x00100000
+#define __ZI_DATA_SIZE   0x000F0000
+
+#define __STACK_SIZE     0x00001000
+#define __HEAP_SIZE      0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x80500000
+#define __TTB_SIZE       0x00004000
+
+#endif /* MEM_<Device>_H */
+
+
+ + + + diff --git a/docs/Core_A/html/mmu_c_pg.html b/docs/Core_A/html/mmu_c_pg.html new file mode 100644 index 0000000..8fcf4fe --- /dev/null +++ b/docs/Core_A/html/mmu_c_pg.html @@ -0,0 +1,361 @@ + + + + + +Memory Management Unit Files mmu_<device>.c +CMSIS-Core (Cortex-A): Memory Management Unit Files mmu_<device>.c + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Memory Management Unit Files mmu_<device>.c
+
+
+
/**************************************************************************//**
+ * @file     system_Device.c
+ * @brief    MMU Configuration
+ *           Device <DeviceAbbreviation>
+ * @version  V1.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description
+
+   ToDo: add in this file your device memory map description
+         following is an example of a Cortex-A9 Arm FVP device
+
+                                                     Memory Type
+0xFFFFFFFF |--------------------------|             ------------
+           |       FLAG SYNC          |             Device Memory
+0xFFFFF000 |--------------------------|             ------------
+           |         Fault            |                Fault
+0xFFF00000 |--------------------------|             ------------
+           |                          |                Normal
+           |                          |
+           |      Daughterboard       |
+           |         memory           |
+           |                          |
+0x80505000 |--------------------------|             ------------
+           |TTB (L2 Sync Flags   ) 4k |                Normal
+0x80504C00 |--------------------------|             ------------
+           |TTB (L2 Peripherals-B) 16k|                Normal
+0x80504800 |--------------------------|             ------------
+           |TTB (L2 Peripherals-A) 16k|                Normal
+0x80504400 |--------------------------|             ------------
+           |TTB (L2 Priv Periphs)  4k |                Normal
+0x80504000 |--------------------------|             ------------
+           |    TTB (L1 Descriptors)  |                Normal
+0x80500000 |--------------------------|             ------------
+           |           Heap           |                Normal
+           |--------------------------|             ------------
+           |          Stack           |                Normal
+0x80400000 |--------------------------|             ------------
+           |         ZI Data          |                Normal
+0x80300000 |--------------------------|             ------------
+           |         RW Data          |                Normal
+0x80200000 |--------------------------|             ------------
+           |         RO Data          |                Normal
+           |--------------------------|             ------------
+           |         RO Code          |              USH Normal
+0x80000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |      HSB AXI buses       |
+0x40000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x2C002000 |--------------------------|             ------------
+           |     Private Address      |            Device Memory
+0x2C000000 |--------------------------|             ------------
+           |      Daughterboard       |                Fault
+           |  test chips peripherals  |
+0x20000000 |--------------------------|             ------------
+           |       Peripherals        |           Device Memory RW/RO
+           |                          |              & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+// Note: You should use the Shareable attribute carefully.
+// For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+// Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+// Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+   
+// Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+// When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+// When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+   
+// Following MMU configuration is expected
+// SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+// SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+// Domain 0 is always the Client domain
+// Descriptors should place all memory in domain 0
+
+#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
+
+// L2 table pointers
+//-----------------------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT             (0x00000000 + 0x1C000000) 
+#define PERIPHERAL_B_FAULT             (0x00100000 + 0x1C000000) 
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC                       0xFFFFF000
+#define F_SYNC_BASE                     0xFFF00000  //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal;        // outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod;    // outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;     // as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;     // as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;     // device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;     // as Sect_Device_RO, but writeable
+                                       
+/* Define global descriptors */        
+static uint32_t Page_L1_4k  = 0x0;  // generic
+static uint32_t Page_L1_64k = 0x0;  // generic
+static uint32_t Page_4k_Device_RW;  // shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+  mmu_region_attributes_Type region;
+
+  // Create 4GB of faulting entries
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+  /*
+   * Generate descriptors. Refer to core_ca.h to get information about attributes
+   *
+   */
+  // Create descriptors for Vectors, RO, RW, ZI sections
+  section_normal(Sect_Normal, region);
+  section_normal_cod(Sect_Normal_Cod, region);
+  section_normal_ro(Sect_Normal_RO, region);
+  section_normal_rw(Sect_Normal_RW, region);
+  // Create descriptors for peripherals
+  section_Device_ro(Sect_Device_RO, region);
+  section_Device_rw(Sect_Device_RW, region);
+  // Create descriptors for 64k pages
+  page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+  // Create descriptors for 4k pages
+  page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+  /*
+   *  Define MMU flat-map regions and attributes
+   *
+   */
+  // Define Image
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base     ,    1U, Sect_Normal_Cod);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base     ,    1U, Sect_Normal_RW);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base     ,    1U, Sect_Normal_RW);
+
+  // All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base     , 2043U, Sect_Normal);
+
+  //--------------------- PERIPHERALS -------------------
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE0    ,   64U, Sect_Device_RO);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE1    ,   64U, Sect_Device_RO);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SRAM_BASE      ,   64U, Sect_Device_RW);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_VRAM_BASE      ,   32U, Sect_Device_RW);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_ETHERNET_BASE  ,   16U, Sect_Device_RW);
+  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_USB_BASE       ,   16U, Sect_Device_RW);
+                                                                                
+  // Create (16 * 64k)=1MB faulting entries to cover peripheral range           
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+  // Define peripheral range                                                    
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DAP_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SYSTEM_REG_BASE ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SERIAL_BASE     ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_AACI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_MMCI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_KMI0_BASE       ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART_BASE       ,    4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_WDT_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+                                                                                
+  // Create (16 * 64k)=1MB faulting entries to cover peripheral range           
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+  // Define peripheral range                                                    
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_TIMER_BASE      ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DVI_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_RTC_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART4_BASE      ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_CLCD_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+  // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()                         ,  256U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+  // Define private address space entry
+  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()                         ,    2U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+  // Define L2CC entry
+  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_L2C_BASE        ,    1U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+  // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE                          ,  256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+  // Define synchronization space entry.                       
+  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC                            ,    1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+  /* Set location of level 1 page table
+  ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+  ; 13:7  - 0x0
+  ; 6     - IRGN[0] 0x0 (Inner WB WA)
+  ; 5     - NOS     0x0 (Non-shared)
+  ; 4:3   - RGN     0x1 (Outer WB WA)
+  ; 2     - IMP     0x0 (Implementation Defined)
+  ; 1     - S       0x0 (Non-shared)
+  ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+  __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9U);
+  __ISB();
+
+  /* Set up domain access control register
+  ; We set domain 0 to Client and all other domains to No Access.
+  ; All translation table entries specify domain 0 */
+  __set_DACR(1);
+  __ISB();
+}
+
+
+ + + + diff --git a/docs/Core_A/html/modules.html b/docs/Core_A/html/modules.html new file mode 100644 index 0000000..406932f --- /dev/null +++ b/docs/Core_A/html/modules.html @@ -0,0 +1,191 @@ + + + + + +Reference +CMSIS-Core (Cortex-A): Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Reference
+
+
+
Here is a list of all modules:
+
[detail level 123]
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
oSystem and Clock ConfigurationFunctions for system and clock setup available in system_device.c
oCore Register AccessFunctions to access the Cortex-A core registers
|oAuxiliary Control Register (ACTLR)The ACTLR provides IMPLEMENTATION DEFINED configuration and control options
||\ACTLR BitsBit position and mask macros
|oCache and branch predictor maintenance operationsThis section describes the cache and branch predictor maintenance operations
|oConfiguration Base Address Register (CBAR)Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13]
||\CBAR BitsBit position and mask macros
|oCoprocessor Access Control Register (CPACR)The CPACR controls access to coprocessors CP0 to CP13
||oCPACR BitsBit position and mask macros
||\CPACR CP field valuesValid values for CPACR CP field
|oCurrent Program Status Register (CPSR)The Current Program Status Register (CPSR) holds processor status and control information
||oCPSR BitsBit position and mask macros
||\CPSR M field valuesValid values for CPSR M field
|oData Fault Status Register (DFSR)The DFSR holds status information about the last data fault
||\ACTLR BitsBit position and mask macros
|oDomain Access Control Register (DACR)DACR defines the access permission for each of the sixteen memory domains
||oDACR BitsBit position and mask macros
||\DACR Dn field valuesValid values for DACR Dn field
|oFloating-Point Exception Control register (FPEXC)Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded
|oFloating-point Status and Control Register (FPSCR)Provides floating-point system status information and control
||\FPSCR BitsBit position and mask macros
|oInstruction Fault Status Register (IFSR)The IFSR holds status information about the last instruction fault
||\IFSR BitsBit position and mask macros
|oInterrupt Status Register (ISR)The ISR shows whether an IRQ, FIQ, or external abort is pending
||\ISR BitsBit position and mask macros
|oMultiprocessor Affinity Register (MPIDR)In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions
|oCounter Frequency register (CNTFRQ)Indicates the clock frequency of the system counter
|oPL1 Physical Timer Control register (CNTP_CTL)The control register for the physical timer
|oPL1 Physical Timer Compare Value register (CNTP_CVAL)Holds the 64-bit compare value for the PL1 physical timer
|oPL1 Physical Timer Value register (CNTP_TVAL)Holds the timer value for the PL1 physical timer
|oPL1 Physical Count register (CNTPCT)Holds the 64-bit physical count value
|oStack Pointer (SP/R13)The processor uses SP as a pointer to the active stack
|oSystem Control Register (SCTLR)The SCTLR provides the top level control of the system, including its memory system
||\SCTLR BitsBit position and mask macros
|oTLB maintenance operationsThis section describes the TLB operations that are implemented on all Armv7-A implementations
|oTranslation Table Base Registers (TTBR0/TTBR1)TTBRn holds the base address of translation table n, and information about the memory it occupies
|oVector Base Address Register (VBAR)When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode
|\Monitor Vector Base Address Register (MVBAR)The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode
oPeripheral AccessNaming conventions and optional features for accessing peripherals
oVersion ControlVersion symbols for CMSIS release specific C/C++ source code
oCore Peripherals
|oGeneric Interrupt Controller FunctionsThe Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC)
|oL1 Cache FunctionsL1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache
|oL2C-310 Cache Controller FunctionsL2C-310 Cache Controller gives access to functions for level 2 cache maintenance.
+Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual
|oGeneric Physical Timer FunctionsGeneric Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.
+Reference: Cortex-A7 MPCore Technical Reference Manual
|oPrivate Timer FunctionsPrivate Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.
+References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual
|oMemory Management Unit FunctionsMMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition
||\MMU Defines and StructsDefines and structures that relate to the Memory Management Unit
|\Floating Point Unit FunctionsFPU Functions enable the use of Floating Point instructions and extensions.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition
oCompiler ControlCompiler agnostic #define symbols for generic C/C++ source code
oIntrinsic FunctionsFunctions that generate specific Cortex-A CPU Instructions
\Interrupts and ExceptionsGeneric functions to access the Interrupt Controller
 oIRQ Mode Bit-MasksConfigure interrupt line mode
 \IRQ Priority Bit-MasksDefinitions used by interrupt priority functions
+
+
+
+ + + + diff --git a/docs/Core_A/html/modules.js b/docs/Core_A/html/modules.js new file mode 100644 index 0000000..372d5a1 --- /dev/null +++ b/docs/Core_A/html/modules.js @@ -0,0 +1,11 @@ +var modules = +[ + [ "System and Clock Configuration", "group__system__init__gr.html", "group__system__init__gr" ], + [ "Core Register Access", "group__CMSIS__core__register.html", "group__CMSIS__core__register" ], + [ "Peripheral Access", "group__peripheral__gr.html", "group__peripheral__gr" ], + [ "Version Control", "group__version__ctrl.html", "group__version__ctrl" ], + [ "Core Peripherals", "group__CMSIS__Core__FunctionInterface.html", "group__CMSIS__Core__FunctionInterface" ], + [ "Compiler Control", "group__comp__cntrl__gr.html", "group__comp__cntrl__gr" ], + [ "Intrinsic Functions", "group__CMSIS__Core__InstructionInterface.html", "group__CMSIS__Core__InstructionInterface" ], + [ "Interrupts and Exceptions", "group__irq__ctrl__gr.html", "group__irq__ctrl__gr" ] +]; \ No newline at end of file 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node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = $(location).attr('hash'); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+ + window.location.hash.substring(1)+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parents().slice(2).prop('tagName')=='TR') { + glowEffect(anchor.parents('div.memitem'),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if 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+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
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+ +
+ + + + +
+ +
+ +
+
+
Usage and Description
+
+
+
Here is a list of all related documentation pages:
+
[detail level 12]
+ + + + + + + + + + + + +
oRevision History of CMSIS-Core (Cortex-A)
oUsing CMSIS in Embedded Applications
|oBasic CMSIS Example
|\Using CMSIS with generic Arm Processors
oCMSIS-Core Device Templates
|oStartup File startup_<device>.c
|oSystem Configuration Files system_<device>.c and system_<device>.h
|oDevice Header File \<device.h>
|oMemory Configuration Files mem_<device>.h
|\Memory Management Unit Files mmu_<device>.c
oMISRA-C Deviations
\Deprecated List
+
+
+
+ + + + diff --git a/docs/Core_A/html/printComponentTabs.js b/docs/Core_A/html/printComponentTabs.js new file mode 100644 index 0000000..8afdb6b --- /dev/null +++ b/docs/Core_A/html/printComponentTabs.js @@ -0,0 +1,39 @@ +var strgURL = location.pathname; // path of current component + +// constuctor for the array of objects +function tabElement(id, folderName, tabTxt ) { + this.id = id; // elementID as needed in html; + this.folderName = folderName; // folder name of the component + this.tabTxt = tabTxt; // Text displayed as menu on the web + this.currentListItem = '
  • ' + this.tabTxt + '
    • '; + this.listItem = '
  • ' + this.tabTxt + '
    • '; +}; + +// array of objects +var arr = []; + +// fill array + arr.push( new tabElement( "GEN", "/General/html/", "General") ); + arr.push( new tabElement( "CORE_A", "/Core_A/html/", "CMSIS-Core(A)") ); + arr.push( new tabElement( "CORE_M", "/Core/html/", "CMSIS-Core(M)") ); + arr.push( new tabElement( "DRV", "/Driver/html/", "Driver") ); + arr.push( new tabElement( "DSP", "/DSP/html/", "DSP") ); + arr.push( new tabElement( "NN", "/NN/html/", "NN") ); + arr.push( new tabElement( "RTOSv1", "/RTOS/html/", "RTOS v1") ); + arr.push( new tabElement( "RTOSv2", "/RTOS2/html/", "RTOS v2") ); + arr.push( new tabElement( "PACK", "/Pack/html/", "Pack") ); + arr.push( new tabElement( "SVD", "/SVD/html/", "SVD") ); + arr.push( new tabElement( "DAP", "/DAP/html/", "DAP") ); + arr.push( new tabElement( "ZONE", "/Zone/html/", "Zone") ); + +// write tabs +// called from the header file. +function writeComponentTabs() { + for ( var i=0; i < arr.length; i++ ) { + if (strgURL.search(arr[i].folderName) > 0) { // if this is the current folder + document.write(arr[i].currentListItem); // then print and hightlight the tab + } else { + document.write(arr[i].listItem); // else, print the tab + } + } +}; diff --git a/docs/Core_A/html/ref__cache_8txt.html b/docs/Core_A/html/ref__cache_8txt.html new file mode 100644 index 0000000..46898e7 --- /dev/null +++ b/docs/Core_A/html/ref__cache_8txt.html @@ -0,0 +1,129 @@ + + + + + +ref_cache.txt File Reference +CMSIS-Core (Cortex-A): ref_cache.txt File Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
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    +
    +
    ref_cache.txt File Reference
    +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/ref__core__register_8txt.html b/docs/Core_A/html/ref__core__register_8txt.html new file mode 100644 index 0000000..beb1a82 --- /dev/null +++ b/docs/Core_A/html/ref__core__register_8txt.html @@ -0,0 +1,129 @@ + + + + + +ref_core_register.txt File Reference +CMSIS-Core (Cortex-A): ref_core_register.txt File Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
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    +
    + +
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    + +
    +
    +
    ref_core_register.txt File Reference
    +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/ref__gic_8txt.html b/docs/Core_A/html/ref__gic_8txt.html new file mode 100644 index 0000000..c22ec06 --- /dev/null +++ b/docs/Core_A/html/ref__gic_8txt.html @@ -0,0 +1,129 @@ + + + + + +ref_gic.txt File Reference +CMSIS-Core (Cortex-A): ref_gic.txt File Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
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    +
    +
    ref_gic.txt File Reference
    +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/ref__mmu_8txt.html b/docs/Core_A/html/ref__mmu_8txt.html new file mode 100644 index 0000000..b3d9ebe --- /dev/null +++ b/docs/Core_A/html/ref__mmu_8txt.html @@ -0,0 +1,129 @@ + + + + + +ref_mmu.txt File Reference +CMSIS-Core (Cortex-A): ref_mmu.txt File Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
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    +
    ref_mmu.txt File Reference
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    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/ref__timer_8txt.html b/docs/Core_A/html/ref__timer_8txt.html new file mode 100644 index 0000000..6f090b5 --- /dev/null +++ b/docs/Core_A/html/ref__timer_8txt.html @@ -0,0 +1,166 @@ + + + + + +ref_timer.txt File Reference +CMSIS-Core (Cortex-A): ref_timer.txt File Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Structures | +Functions
    +
    +
    ref_timer.txt File Reference
    +
    +
    + + + + + +

    +Data Structures

    union  CNTP_CTL_Type
     Physical Timer Control register. More...
     
    + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    __STATIC_INLINE void PL1_SetCounterFrequency (uint32_t value)
     Configures the frequency the timer shall run at. More...
     
    __STATIC_INLINE void PL1_SetLoadValue (uint32_t value)
     Sets the reset value of the timer. More...
     
    __STATIC_INLINE uint32_t PL1_GetCurrentValue ()
     Get the current counter value. More...
     
    __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue (void)
     Get the current physical counter value. More...
     
    __STATIC_INLINE void PL1_SetPhysicalCompareValue (uint64_t value)
     Set the physical compare value. More...
     
    __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue (void)
     Get the physical compare value. More...
     
    __STATIC_INLINE void PL1_SetControl (uint32_t value)
     Configure the timer by setting the control value. More...
     
    __STATIC_INLINE uint32_t PL1_GetControl ()
     Get the control value. More...
     
    +
    +
    + + + + diff --git a/docs/Core_A/html/resize.js b/docs/Core_A/html/resize.js new file mode 100644 index 0000000..304fcb6 --- /dev/null +++ b/docs/Core_A/html/resize.js @@ -0,0 +1,97 @@ +var cookie_namespace = 'doxygen'; +var sidenav,navtree,content,header; + +function readCookie(cookie) +{ + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) + { + var index = document.cookie.indexOf(myCookie); + if (index != -1) + { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) + { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; +} + +function writeCookie(cookie, val, expiration) +{ + if (val==undefined) return; + if (expiration == null) + { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; +} + +function resizeWidth() +{ + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).outerWidth(); + content.css({marginLeft:parseInt(sidenavWidth)+"px"}); + writeCookie('width',sidenavWidth, null); +} + +function restoreWidth(navWidth) +{ + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+6+"px"}); + sidenav.css({width:navWidth + "px"}); +} + +function resizeHeight() +{ + var headerHeight = header.outerHeight(); + var footerHeight = footer.outerHeight(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px",top: headerHeight+"px"}); +} + +function initResizable() +{ + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(window).resize(function() { resizeHeight(); }); + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); + $(document).bind('touchmove',function(e){ + var device = navigator.userAgent.toLowerCase(); + var ios = device.match(/(iphone|ipod|ipad)/); + if (ios) { + try { + var target = e.target; + while (target) { + if ($(target).css('-webkit-overflow-scrolling')=='touch') return; + target = target.parentNode; + } + e.preventDefault(); + } catch(err) { + e.preventDefault(); + } + } + }); +} + + diff --git a/docs/Core_A/html/rev_histCoreA.html b/docs/Core_A/html/rev_histCoreA.html new file mode 100644 index 0000000..acea415 --- /dev/null +++ b/docs/Core_A/html/rev_histCoreA.html @@ -0,0 +1,162 @@ + + + + + +Revision History of CMSIS-Core (Cortex-A) +CMSIS-Core (Cortex-A): Revision History of CMSIS-Core (Cortex-A) + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Revision History of CMSIS-Core (Cortex-A)
    +
    +
    +
    + + + + + + + + + + +
    Version Description
    V1.1.2
      +
    • +Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.
      • +
    • +Fixed co-processor register access macros for Arm Compiler 5.
      • +
    +
    V1.1.1
      +
    • +Refactored L1 cache maintenance to be compiler agnostic.
      • +
    +
    V1.1.0
      +
    • +Added compiler_iccarm.h for IAR compiler.
      • +
    • +Added missing core access functions for Arm Compiler 5.
      • +
    • +Aligned access function to coprocessor 15.
      • +
    • +Additional generic Timer functions.
      • +
    • +Bug fixes and minor enhancements.
      • +
    +
    V1.0.0 Initial Release for Cortex-A5/A7/A9 processors.
    +
    +
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    + + diff --git a/docs/Core_A/html/search/pages_0.js b/docs/Core_A/html/search/pages_0.js new file mode 100644 index 0000000..2ad9451 --- /dev/null +++ b/docs/Core_A/html/search/pages_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['basic_20cmsis_20example',['Basic CMSIS Example',['../using_CMSIS.html',1,'using_pg']]] +]; diff --git a/docs/Core_A/html/search/pages_1.html b/docs/Core_A/html/search/pages_1.html new file mode 100644 index 0000000..2a98fce --- /dev/null +++ b/docs/Core_A/html/search/pages_1.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_1.js b/docs/Core_A/html/search/pages_1.js new file mode 100644 index 0000000..18a701d --- /dev/null +++ b/docs/Core_A/html/search/pages_1.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['cmsis_2dcore_20device_20templates',['CMSIS-Core Device Templates',['../templates_pg.html',1,'']]] +]; diff --git a/docs/Core_A/html/search/pages_2.html b/docs/Core_A/html/search/pages_2.html new file mode 100644 index 0000000..0711a0b --- /dev/null +++ b/docs/Core_A/html/search/pages_2.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_2.js b/docs/Core_A/html/search/pages_2.js new file mode 100644 index 0000000..3df69ab --- /dev/null +++ b/docs/Core_A/html/search/pages_2.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['deprecated_20list',['Deprecated List',['../deprecated.html',1,'']]], + ['device_20header_20file_20_5c_3cdevice_2eh_3e',['Device Header File \<device.h>',['../device_h_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core_A/html/search/pages_3.html b/docs/Core_A/html/search/pages_3.html new file mode 100644 index 0000000..4310311 --- /dev/null +++ b/docs/Core_A/html/search/pages_3.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_3.js b/docs/Core_A/html/search/pages_3.js new file mode 100644 index 0000000..3382b9e --- /dev/null +++ b/docs/Core_A/html/search/pages_3.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['misra_2dc_20deviations',['MISRA-C Deviations',['../coreMISRA_Exceptions_pg.html',1,'']]], + ['memory_20configuration_20files_20mem_5f_3cdevice_3e_2eh',['Memory Configuration Files mem_<device>.h',['../mem_h_pg.html',1,'templates_pg']]], + ['memory_20management_20unit_20files_20mmu_5f_3cdevice_3e_2ec',['Memory Management Unit Files mmu_<device>.c',['../mmu_c_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core_A/html/search/pages_4.html b/docs/Core_A/html/search/pages_4.html new file mode 100644 index 0000000..ae5ce18 --- /dev/null +++ b/docs/Core_A/html/search/pages_4.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_4.js b/docs/Core_A/html/search/pages_4.js new file mode 100644 index 0000000..277cca0 --- /dev/null +++ b/docs/Core_A/html/search/pages_4.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['overview',['Overview',['../index.html',1,'']]] +]; diff --git a/docs/Core_A/html/search/pages_5.html b/docs/Core_A/html/search/pages_5.html new file mode 100644 index 0000000..02c1114 --- /dev/null +++ b/docs/Core_A/html/search/pages_5.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_5.js b/docs/Core_A/html/search/pages_5.js new file mode 100644 index 0000000..ef1e60e --- /dev/null +++ b/docs/Core_A/html/search/pages_5.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['revision_20history_20of_20cmsis_2dcore_20_28cortex_2da_29',['Revision History of CMSIS-Core (Cortex-A)',['../rev_histCoreA.html',1,'']]] +]; diff --git a/docs/Core_A/html/search/pages_6.html b/docs/Core_A/html/search/pages_6.html new file mode 100644 index 0000000..afb70af --- /dev/null +++ b/docs/Core_A/html/search/pages_6.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_6.js b/docs/Core_A/html/search/pages_6.js new file mode 100644 index 0000000..ddb93b3 --- /dev/null +++ b/docs/Core_A/html/search/pages_6.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['startup_20file_20startup_5f_3cdevice_3e_2ec',['Startup File startup_<device>.c',['../startup_c_pg.html',1,'templates_pg']]], + ['system_20configuration_20files_20system_5f_3cdevice_3e_2ec_20and_20system_5f_3cdevice_3e_2eh',['System Configuration Files system_<device>.c and system_<device>.h',['../system_c_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core_A/html/search/pages_7.html b/docs/Core_A/html/search/pages_7.html new file mode 100644 index 0000000..9d7ba25 --- /dev/null +++ b/docs/Core_A/html/search/pages_7.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/pages_7.js b/docs/Core_A/html/search/pages_7.js new file mode 100644 index 0000000..72e25e6 --- /dev/null +++ b/docs/Core_A/html/search/pages_7.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['using_20cmsis_20with_20generic_20arm_20processors',['Using CMSIS with generic Arm Processors',['../using_ARM_pg.html',1,'using_pg']]], + ['using_20cmsis_20in_20embedded_20applications',['Using CMSIS in Embedded Applications',['../using_pg.html',1,'']]] +]; diff --git a/docs/Core_A/html/search/search.css b/docs/Core_A/html/search/search.css new file mode 100644 index 0000000..e01a39c --- /dev/null +++ b/docs/Core_A/html/search/search.css @@ -0,0 +1,271 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 8px; + right: 0px; + width: 170px; + z-index: 102; + background-color: white; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:111px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #8EA4D0; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3A568E; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EDF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #3F5D9A; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #3F5D9A; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +span.SRScope { + padding-left: 4px; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} + +/*---------------- External search page results */ + +.searchresult { + background-color: #F0F3F8; +} + +.pages b { + color: white; + padding: 5px 5px 3px 5px; + background-image: url("../tab_a.png"); + background-repeat: repeat-x; + text-shadow: 0 1px 1px #000000; +} + +.pages { + line-height: 17px; + margin-left: 4px; + text-decoration: none; +} + +.hl { + font-weight: bold; +} + +#searchresults { + margin-bottom: 20px; +} + +.searchpages { + margin-top: 10px; +} + diff --git a/docs/Core_A/html/search/search.js b/docs/Core_A/html/search/search.js new file mode 100644 index 0000000..d7d7665 --- /dev/null +++ b/docs/Core_A/html/search/search.js @@ -0,0 +1,813 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "_abcdefghijklmnopqrstuvwxz", + 1: "acdfgilmst", + 2: "acimorstu", + 3: "_dgilmprsv", + 4: "_abcdefghijlmnopqrstuvwxz", + 5: "i", + 6: "im", + 7: "acdegkmnprstuvw", + 8: "_acfgilprstuv", + 9: "acdfgilmpstv", + 10: "bcdmorsu" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "typedefs", + 6: "enums", + 7: "enumvalues", + 8: "defines", + 9: "groups", + 10: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core_A/html/search/typedefs_0.js b/docs/Core_A/html/search/typedefs_0.js new file mode 100644 index 0000000..ce58f7c --- /dev/null +++ b/docs/Core_A/html/search/typedefs_0.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['irqhandler_5ft',['IRQHandler_t',['../irq__ctrl_8h.html#afbfa2180a9b6208f34891d539e9e2d52',1,'irq_ctrl.h']]], + ['irqn_5fid_5ft',['IRQn_ID_t',['../irq__ctrl_8h.html#ac62964c04a7fed2c84aeea9e34f415e2',1,'irq_ctrl.h']]] +]; diff --git a/docs/Core_A/html/search/variables_0.html b/docs/Core_A/html/search/variables_0.html new file mode 100644 index 0000000..1b8adc9 --- /dev/null +++ b/docs/Core_A/html/search/variables_0.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
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    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Macros | +Functions
    +
    +
    startup_ARMCA9.c File Reference
    +
    +
    + + + + + + + + + + + + + + + + +

    +Macros

    #define USR_MODE   0x10
     
    #define FIQ_MODE   0x11
     
    #define IRQ_MODE   0x12
     
    #define SVC_MODE   0x13
     
    #define ABT_MODE   0x17
     
    #define UND_MODE   0x1B
     
    #define SYS_MODE   0x1F
     
    + + + + + + + + +

    +Functions

    void Vectors (void)
     Exception and Interrupt Handler Jumptable. More...
     
    void Reset_Handler (void)
     
    void Default_Handler (void)
     
    +

    Macro Definition Documentation

    + +
    +
    + + + + +
    #define ABT_MODE   0x17
    +
    + +
    +
    + +
    +
    + + + + +
    #define FIQ_MODE   0x11
    +
    + +
    +
    + +
    +
    + + + + +
    #define IRQ_MODE   0x12
    +
    + +
    +
    + +
    +
    + + + + +
    #define SVC_MODE   0x13
    +
    + +
    +
    + +
    +
    + + + + +
    #define SYS_MODE   0x1F
    +
    + +
    +
    + +
    +
    + + + + +
    #define UND_MODE   0x1B
    +
    + +
    +
    + +
    +
    + + + + +
    #define USR_MODE   0x10
    +
    + +
    +
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void Default_Handler (void )
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void Reset_Handler (void )
    +
    + +
    +
    + +
    +
    + + + + + + + + +
    void Vectors (void )
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/startup_c_pg.html b/docs/Core_A/html/startup_c_pg.html new file mode 100644 index 0000000..cdbba66 --- /dev/null +++ b/docs/Core_A/html/startup_c_pg.html @@ -0,0 +1,284 @@ + + + + + +Startup File startup_<device>.c +CMSIS-Core (Cortex-A): Startup File startup_<device>.c + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Startup File startup_<device>.c
    +
    +
    +

    The Startup File startup_<device>.c contains:

    +
      +
    • Exception vectors of the Cortex-A Processor with weak functions that implement default routines.
      • +
    • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
      • +
    • The setup values for the various stack pointers, i.e. per exceptional mode and main stack.
      • +
    +

    The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.

    +

    +startup_Device.c Template File

    +

    An Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.

    +
    /******************************************************************************
+ * @file     startup_<Device>.c
+ * @brief    CMSIS Cortex-A Device Startup
+ * @version  V1.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((section("RESET")));
+void Reset_Handler (void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+  IMPORT Undef_Handler
+  IMPORT SVC_Handler
+  IMPORT PAbt_Handler
+  IMPORT DAbt_Handler
+  IMPORT IRQ_Handler
+  IMPORT FIQ_Handler
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+
+  // Mask interrupts
+  CPSID   if                           
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5       // Read MPIDR
+  ANDS    R0, R0, #3
+goToSleep
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0       // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1                // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exceptional mode
+  IMPORT |Image$$FIQ_STACK$$ZI$$Limit|
+  IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
+  IMPORT |Image$$SVC_STACK$$ZI$$Limit|
+  IMPORT |Image$$ABT_STACK$$ZI$$Limit|
+  IMPORT |Image$$UND_STACK$$ZI$$Limit|
+  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+  CPS    #0x11
+  LDR    SP, =|Image$$FIQ_STACK$$ZI$$Limit|
+  CPS    #0x12
+  LDR    SP, =|Image$$IRQ_STACK$$ZI$$Limit|
+  CPS    #0x13
+  LDR    SP, =|Image$$SVC_STACK$$ZI$$Limit|
+  CPS    #0x17
+  LDR    SP, =|Image$$ABT_STACK$$ZI$$Limit|
+  CPS    #0x1B
+  LDR    SP, =|Image$$UND_STACK$$ZI$$Limit|
+  CPS    #0x1F
+  LDR    SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+  // Call SystemInit
+  IMPORT SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __main
+  IMPORT __main
+  BL     __main
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
+
    +
    + + + + diff --git a/docs/Core_A/html/structFPSCR__Type.html b/docs/Core_A/html/structFPSCR__Type.html new file mode 100644 index 0000000..55b2918 --- /dev/null +++ b/docs/Core_A/html/structFPSCR__Type.html @@ -0,0 +1,138 @@ + + + + + +FPSCR_Type Struct Reference +CMSIS-Core (Cortex-A): FPSCR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    FPSCR_Type Struct Reference
    Floating-point Status and Control Register (FPSCR)
    +
    +
    + +

    Bit field declaration for FPSCR layout. +

    +
    +
    + + + + diff --git a/docs/Core_A/html/structGICDistributor__Type.html b/docs/Core_A/html/structGICDistributor__Type.html new file mode 100644 index 0000000..55d6f67 --- /dev/null +++ b/docs/Core_A/html/structGICDistributor__Type.html @@ -0,0 +1,822 @@ + + + + + +GICDistributor_Type Struct Reference +CMSIS-Core (Cortex-A): GICDistributor_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    GICDistributor_Type Struct Reference
    Generic Interrupt Controller Functions
    +
    +
    + +

    Structure type to access the Generic Interrupt Controller Distributor (GICD) +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t CTLR
     Offset: 0x000 (R/W) Distributor Control Register. More...
     
    __IM uint32_t TYPER
     Offset: 0x004 (R/ ) Interrupt Controller Type Register. More...
     
    __IM uint32_t IIDR
     Offset: 0x008 (R/ ) Distributor Implementer Identification Register. More...
     
    __IOM uint32_t STATUSR
     Offset: 0x010 (R/W) Error Reporting Status Register, optional. More...
     
    __OM uint32_t SETSPI_NSR
     Offset: 0x040 ( /W) Set SPI Register. More...
     
    __OM uint32_t CLRSPI_NSR
     Offset: 0x048 ( /W) Clear SPI Register. More...
     
    __OM uint32_t SETSPI_SR
     Offset: 0x050 ( /W) Set SPI, Secure Register. More...
     
    __OM uint32_t CLRSPI_SR
     Offset: 0x058 ( /W) Clear SPI, Secure Register. More...
     
    __IOM uint32_t IGROUPR [32]
     Offset: 0x080 (R/W) Interrupt Group Registers. More...
     
    __IOM uint32_t ISENABLER [32]
     Offset: 0x100 (R/W) Interrupt Set-Enable Registers. More...
     
    __IOM uint32_t ICENABLER [32]
     Offset: 0x180 (R/W) Interrupt Clear-Enable Registers. More...
     
    __IOM uint32_t ISPENDR [32]
     Offset: 0x200 (R/W) Interrupt Set-Pending Registers. More...
     
    __IOM uint32_t ICPENDR [32]
     Offset: 0x280 (R/W) Interrupt Clear-Pending Registers. More...
     
    __IOM uint32_t ISACTIVER [32]
     Offset: 0x300 (R/W) Interrupt Set-Active Registers. More...
     
    __IOM uint32_t ICACTIVER [32]
     Offset: 0x380 (R/W) Interrupt Clear-Active Registers. More...
     
    __IOM uint32_t IPRIORITYR [255]
     Offset: 0x400 (R/W) Interrupt Priority Registers. More...
     
    __IOM uint32_t ITARGETSR [255]
     Offset: 0x800 (R/W) Interrupt Targets Registers. More...
     
    __IOM uint32_t ICFGR [64]
     Offset: 0xC00 (R/W) Interrupt Configuration Registers. More...
     
    __IOM uint32_t IGRPMODR [32]
     Offset: 0xD00 (R/W) Interrupt Group Modifier Registers. More...
     
    __IOM uint32_t NSACR [64]
     Offset: 0xE00 (R/W) Non-secure Access Control Registers. More...
     
    __OM uint32_t SGIR
     Offset: 0xF00 ( /W) Software Generated Interrupt Register. More...
     
    __IOM uint32_t CPENDSGIR [4]
     Offset: 0xF10 (R/W) SGI Clear-Pending Registers. More...
     
    __IOM uint32_t SPENDSGIR [4]
     Offset: 0xF20 (R/W) SGI Set-Pending Registers. More...
     
    __IOM uint64_t IROUTER [988]
     Offset: 0x6100(R/W) Interrupt Routing Registers. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IO uint32_t GICDistributor_Type::CLRSPI_NSR
    +
    +

    Clear Non-secure SPI Pending Register

    + + + + + + + +
    Bits Name Function
    [31:10] - Reserved.
    [9:0] INTID The interrupt number to clear pending state from.
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t GICDistributor_Type::CLRSPI_SR
    +
    +

    Clear Secure SPI Pending Register

    + + + + + + + +
    Bits Name Function
    [31:10] - Reserved.
    [9:0] INTID The interrupt number to clear pending state from.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t GICDistributor_Type::CPENDSGIR[16]
    +
    +

    SGI Clear-Pending Registers Each register corresponds to one software generated interrupt (SGI).

    +

    Reading from this register reveals

    +
      +
    • 0 - interrupt is not pending
      • +
    • 1 - interrupt is pending
      • +
    +

    Writing to this register causes

    +
      +
    • 0 - no effect
      • +
    • 1 - removes the pending state
      • +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::CTLR
    +
    +

    Distributor Control Register

    +

    When access is Secure, in a system that supports two Security states:

    + + + + + + + + + + + + + + + + + + + + + + + +
    Bits Name Function
    [31] RWP Indicates whether a register write is in progress or not.
    [30:8] - Reserved.
    [7] EINWF Enable 1 of N Wakeup Functionality, if available.
    [6] DS Disable Security.
    [5] ARE_NS Affinity Routing Enable, Non-secure state.
    [4] ARE_S Affinity Routing Enable, Secure state.
    [3] - Reserved.
    [2] EnableGrp1S Enable Secure Group 1 interrupts.
    [1] EnableGrp1NS Enable Non-secure Group 1 interrupts.
    [0] EnableGrp0 Enable Group 0 interrupts.
    +

    When access is Non-secure, in a system that supports two Security states:

    + + + + + + + + + + + + + + + +
    Bits Name Function
    [31] RWP Indicates whether a register write is in progress or not.
    [30:5] - Reserved.
    [4] ARE_NS Affinity Routing Enable, Non-secure state.
    [3:2] - Reserved.
    [1] EnableGrp1A Enable Non-secure Group 1 interrupts.
    [0] EnableGrp1 Enable Non-secure Group 1 interrupts.
    +

    When in a system that supports only a single Security state:

    + + + + + + + + + + + + + + + + + + + + + +
    Bits Name Function
    [31] RWP Indicates whether a register write is in progress or not.
    [30:8] - Reserved.
    [7] EINWF Enable 1 of N Wakeup Functionality, if available.
    [6] DS Disable Security.
    [5] - Reserved.
    [4] ARE Affinity Routing Enable.
    [3:2] - Reserved.
    [1] EnableGrp1 Enable Group 1 interrupts.
    [0] EnableGrp0 Enable Group 0 interrupts.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ICACTIVER[32]
    +
    +

    Interrupt Clear-Active Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +
    Note
    Bits corresponding to unimplemented interrupts are RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ICENABLER[32]
    +
    +

    Interrupt Clear-Enable Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +
    Note
    Bits corresponding to unimplemented interrupts are RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ICFGR[64]
    +
    +

    Interrupt Configuration Registers

    +

    Each interrupt can be configured by two corresponding bits:

    + + + + + + + +
    Bits Name Function
    [2*INTID%16+1] Edge Interrupt is: 0 - level sensitive, 1 - edge triggered
    [2*INTID%16] Model 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ICPENDR[32]
    +
    +

    Interrupt Clear-Pending Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +
    Note
    Bits corresponding to unimplemented interrupts are RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::IGROUPR[32]
    +
    +

    Interrupt Group Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +

    And the value denotes:

    +
      +
    • 0 When CTLR.DS==1, the corresponding interrupt is Group 0
      + When CTLR.DS==0, the corresponding interrupt is Secure.
      • +
    • 1 When CTLR.DS==1, the corresponding interrupt is Group 1.
      + When CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.
      • +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::IGRPMODR[32]
    +
    +

    Interrupt Group Modifier Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICDistributor_Type::IIDR
    +
    +

    Distributor Implementer Identification Register

    + + + + + + + + + + + + + +
    Bits Name Function
    [31:24] ProductID An IMPLEMENTATION DEFINED product identifier
    [23:20] - Reserved.
    [19:16] Variant An IMPLEMENTATION DEFINED variant number.
    [15:12] Revision An IMPLEMENTATION DEFINED revision number.
    [11:0] Implementer Contains the JEP106 code of the company implemented the GICD.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]
    +
    +

    Interrupt Priority Registers

    +

    A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI.

    +
    Note
    A register field corresponding to an unimplemented interrupt is RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint64_t GICDistributor_Type::IROUTER[988]
    +
    +

    Interrupt Routing Registers

    + + + + + + + + + + + + + + + + + +
    Bits Name Function
    [63:40] - Reserved.
    [39:32] Aff3 Affinity level 3, the least significant affinity level field.
    [31] IRM Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy.
    [30:24] - Reserved.
    [23:16] Aff2 Affinity level 2, an intermediate affinity level field.
    [15:8] Aff1 Affinity level 1, an intermediate affinity level field.
    [7:0] Aff0 Affinity level 0, the most significant affinity level field.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ISACTIVER[32]
    +
    +

    Interrupt Set-Active Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +
    Note
    Bits corresponding to unimplemented interrupts are RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ISENABLER[32]
    +
    +

    Interrupt Set-Enable Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +
    Note
    Bits corresponding to unimplemented interrupts are RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::ISPENDR[32]
    +
    +

    Interrupt Set-Pending Registers

    +

    Each bit corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/32
      • +
    • Bit number is given by INTID%32
      • +
    +
    Note
    Bits corresponding to unimplemented interrupts are RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t GICDistributor_Type::ITARGETSR[1020]
    +
    +

    Interrupt Processor Targets Registers

    +

    Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI.

    + + + + + + + + + + + + + + + + + + + +
    CPU target field value Interrupt targets
    0bxxxxxxx1 CPU interface 0
    0bxxxxxx1x CPU interface 1
    0bxxxxx1xx CPU interface 2
    0bxxxx1xxx CPU interface 3
    0bxxx1xxxx CPU interface 4
    0bxx1xxxxx CPU interface 5
    0bx1xxxxxx CPU interface 6
    0b1xxxxxxx CPU interface 7
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::NSACR[64]
    +
    +

    Non-secure Access Control Registers

    +

    Each two bits corresponds to one interrupt:

    +
      +
    • Register index is given by INTID/16
      • +
    • Bit number is given by 2*INTID%16
      • +
    +

    The possible values of each 2-bit field are:

    +
      +
    • 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
      • +
    • 01 - Non-secure accesses are only permitted to requesting fields.
      • +
    • 10 - As 01, additionally accesses to clearing field are permitted.
      • +
    • 11 - As 10, additionally accesses to target and routing fields are permitted.
      • +
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t GICDistributor_Type::SETSPI_NSR
    +
    +

    Set Non-secure SPI Pending Register

    + + + + + + + +
    Bits Name Function
    [31:10] - Reserved.
    [9:0] INTID The interrupt number to set pending state for.
    + +
    +
    + +
    +
    + + + + +
    __IO uint32_t GICDistributor_Type::SETSPI_SR
    +
    +

    Set Secure SPI Pending Register

    + + + + + + + +
    Bits Name Function
    [31:10] - Reserved.
    [9:0] INTID The interrupt number to set pending state for.
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t GICDistributor_Type::SGIR
    +
    +

    Software Generated Interrupt Register

    + + + + + + + + + + + + + + + +
    Bits Name Function
    [31:26] - Reserved.
    [25:24] TargetFilterList Determines how the Distributor processes the requested SGI.
    [23:16] CPUTargetList When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt.
    [15] NSATT Specifies the required group of the SGI.
    [14:4] - Reserved.
    [3:0] INTID The INTID of the SGI to forward to the specified CPU interfaces.
    +

    Refer to ITARGETSR for details on TargetFilterList field.

    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t GICDistributor_Type::SPENDSGIR[16]
    +
    +

    SGI Set-Pending Registers Each register corresponds to one software generated interrupt (SGI).

    +

    Reading from this register reveals

    +
      +
    • 0 - interrupt is not pending
      • +
    • 1 - interrupt is pending
      • +
    +

    Writing to this register causes

    +
      +
    • 0 - no effect
      • +
    • 1 - adds the pending state
      • +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICDistributor_Type::STATUSR
    +
    +

    Error Reporting Status Register

    + + + + + + + + + + + + + +
    Bits Name Function
    [31:4] - Reserved.
    [3] WROD Write to an RO location.
    [2] RWOD Read of a WO location.
    [1] WRD Write to a reserved location.
    [0] RRD Read of a reserved location.
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICDistributor_Type::TYPER
    +
    +

    Interrupt Controller Type Register

    + + + + + + + + + + + + + + + +
    Bits Name Function
    [31:16] - Reserved.
    [15:11] LSPI Maximum number of lockable shared interrupts.
    [10] SecurityExtn Security Extensions: 0 - not implemented. 1 - implemented.
    [9:8] - Reserved.
    [7:5] CPUNumber Number of implemented CPU interfaces [=CPUNumber+1]
    [4:0] ITLinesNumber Maximum number of interrups supported [=32*(ITLinesNumber+1)].
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/structGICDistributor__Type.js b/docs/Core_A/html/structGICDistributor__Type.js new file mode 100644 index 0000000..f7a6188 --- /dev/null +++ b/docs/Core_A/html/structGICDistributor__Type.js @@ -0,0 +1,27 @@ +var structGICDistributor__Type = +[ + [ "CLRSPI_NSR", "structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168", null ], + [ "CLRSPI_SR", "structGICDistributor__Type.html#ab487e4a8684b8a77357c6c20cf71dead", null ], + [ "CPENDSGIR", "structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b", null ], + [ "CTLR", "structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7", null ], + [ "ICACTIVER", "structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967", null ], + [ "ICENABLER", "structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807", null ], + [ "ICFGR", "structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5", null ], + [ "ICPENDR", "structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6", null ], + [ "IGROUPR", "structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306", null ], + [ "IGRPMODR", "structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689", null ], + [ "IIDR", "structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722", null ], + [ "IPRIORITYR", "structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9", null ], + [ "IROUTER", "structGICDistributor__Type.html#a73e0c679e5f45710deea474ab0d39cdb", null ], + [ "ISACTIVER", "structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4", null ], + [ "ISENABLER", "structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87", null ], + [ "ISPENDR", "structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5", null ], + [ "ITARGETSR", "structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c", null ], + [ "NSACR", "structGICDistributor__Type.html#a644abefb7064e434db20cc6dab5fe5f1", null ], + [ "SETSPI_NSR", "structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25", null ], + [ "SETSPI_SR", "structGICDistributor__Type.html#ad55a8644bc95caf8bf53e1407ec9ed0c", null ], + [ "SGIR", "structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1", null ], + [ "SPENDSGIR", "structGICDistributor__Type.html#ae40b4a50d9766c2bbf57441f68094f41", null ], + [ "STATUSR", "structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2", null ], + [ "TYPER", "structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/structGICInterface__Type.html b/docs/Core_A/html/structGICInterface__Type.html new file mode 100644 index 0000000..a47733e --- /dev/null +++ b/docs/Core_A/html/structGICInterface__Type.html @@ -0,0 +1,503 @@ + + + + + +GICInterface_Type Struct Reference +CMSIS-Core (Cortex-A): GICInterface_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    GICInterface_Type Struct Reference
    Generic Interrupt Controller Functions
    +
    +
    + +

    Structure type to access the Generic Interrupt Controller Interface (GICC) +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t CTLR
     Offset: 0x000 (R/W) CPU Interface Control Register. More...
     
    __IOM uint32_t PMR
     Offset: 0x004 (R/W) Interrupt Priority Mask Register. More...
     
    __IOM uint32_t BPR
     Offset: 0x008 (R/W) Binary Point Register. More...
     
    __IM uint32_t IAR
     Offset: 0x00C (R/ ) Interrupt Acknowledge Register. More...
     
    __OM uint32_t EOIR
     Offset: 0x010 ( /W) End Of Interrupt Register. More...
     
    __IM uint32_t RPR
     Offset: 0x014 (R/ ) Running Priority Register. More...
     
    __IM uint32_t HPPIR
     Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. More...
     
    __IOM uint32_t ABPR
     Offset: 0x01C (R/W) Aliased Binary Point Register. More...
     
    __IM uint32_t AIAR
     Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register. More...
     
    __OM uint32_t AEOIR
     Offset: 0x024 ( /W) Aliased End Of Interrupt Register. More...
     
    __IM uint32_t AHPPIR
     Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register. More...
     
    __IOM uint32_t STATUSR
     Offset: 0x02C (R/W) Error Reporting Status Register, optional. More...
     
    __IOM uint32_t APR [4]
     Offset: 0x0D0 (R/W) Active Priority Register. More...
     
    __IOM uint32_t NSAPR [4]
     Offset: 0x0E0 (R/W) Non-secure Active Priority Register. More...
     
    __IM uint32_t IIDR
     Offset: 0x0FC (R/ ) CPU Interface Identification Register. More...
     
    __OM uint32_t DIR
     Offset: 0x1000( /W) Deactivate Interrupt Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::ABPR
    +
    +

    CPU Interface Aliased Binary Point Register

    +
    See Also
    GICInterface_Type::BPR
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t GICInterface_Type::AEOIR
    +
    +

    CPU Interface Aliased End Of Interrupt Register

    +
    See Also
    GICInterface_Type::EOIR
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICInterface_Type::AHPPIR
    +
    +

    CPU Interface Aliased Highest Priority Pending Interrupt Register

    +
    See Also
    GICInterface_Type::HPPIR
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICInterface_Type::AIAR
    +
    +

    CPU Interface Aliased Interrupt Acknowledge Register

    +
    See Also
    GICInterface_Type::IAR
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::APR[4]
    +
    +

    CPU Interface Active Priorities Registers

    +
    Note
    The register values are IMPLEMENTATION DEFINED.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::BPR
    +
    +

    CPU Interface Binary Point Register

    + + + + + + + +
    Bits Name Function
    [31:3] - Reserved.
    [2:0] Binary_Point Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field.
    +

    The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please refer to the section Interrupt prioritization in the Arm Generic Interrupt Controller Architecture Specificaton for details.

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::CTLR
    +
    +

    CPU Interface Control Register

    +

    Enables the signaling of interrupts by the CPU interface to the connected processor, and provides additional top-level control of the CPU interface. In a GICv2 implementation, this includes control of the end of interrupt (EOI) behavior.

    + + + + + + + +
    Bits Name Function
    [31:1] - Reserved.
    [0] Enable Interrupt signaling: 0 - Disable. 1 - Enable.
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t GICInterface_Type::DIR
    +
    +

    CPU Interface Deactivate Interrupt Register

    + + + + + + + +
    Bits Name Function
    [31:24] - Reserved.
    [23:0] INTID The INTID of the interrupt to be disabled.
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t GICInterface_Type::EOIR
    +
    +

    CPU Interface End Of Interrupt Register

    + + + + + + + +
    Bits Name Function
    [31:24] - Reserved.
    [23:0] INTID The interrupt number of the finished interrupt.
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICInterface_Type::HPPIR
    +
    +

    CPU Interface Highest Priority Pending Interrupt Register

    + + + + + + + +
    Bits Name Function
    [31:24] - Reserved.
    [23:0] INTID The INTID of the signaled interrupt.
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICInterface_Type::IAR
    +
    +

    CPU Interface Interrupt Acknowledge Register

    + + + + + + + +
    Bits Name Function
    [31:24] - Reserved.
    [23:0] INTID The interrupt number of the signaled interrupt.
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICInterface_Type::IIDR
    +
    +

    CPU Interface Identification Register

    + + + + + + + + + + + +
    Bits Name Function
    [31:20] ProductID An IMPLEMENTATION DEFINED product identifier
    [19:16] Arch_version The version of the GIC architecture that is implemented.
    [15:12] Revision An IMPLEMENTATION DEFINED revision number for the CPU interface.
    [11:0] Implementer Contains the JEP106 code of the company that implemented the CPU interface.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::NSAPR[4]
    +
    +

    CPU Interface Non-secure Active Priorities Registers

    +
    Note
    The register values are IMPLEMENTATION DEFINED.
    +
    See Also
    GICInterface_Type::APR[4]
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::PMR
    +
    +

    CPU Interface Priority Mask Register

    + + + + + + + +
    Bits Name Function
    [31:8] - Reserved.
    [7:0] Priority The priority mask level for the CPU interface.
    +
    Note
    IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t GICInterface_Type::RPR
    +
    +

    CPU Interface Running Priority Register

    + + + + + + + +
    Bits Name Function
    [31:8] - Reserved.
    [7:0] Priority The current running priority on the CPU interface.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t GICInterface_Type::STATUSR
    +
    +

    CPU Interface Status Register

    + + + + + + + + + + + + + + + +
    Bits Name Function
    [31:5] - Reserved.
    [4] ASV Attempted security violation.
    [3] WROD Write to an RO location.
    [2] RWOD Read of a WO location.
    [1] WRD Write to a reserved location.
    [0] RRD Read of a reserved location.
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/structGICInterface__Type.js b/docs/Core_A/html/structGICInterface__Type.js new file mode 100644 index 0000000..9a713d8 --- /dev/null +++ b/docs/Core_A/html/structGICInterface__Type.js @@ -0,0 +1,19 @@ +var structGICInterface__Type = +[ + [ "ABPR", "structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d", null ], + [ "AEOIR", "structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89", null ], + [ "AHPPIR", "structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8", null ], + [ "AIAR", "structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6", null ], + [ "APR", "structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8", null ], + [ "BPR", "structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829", null ], + [ "CTLR", "structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9", null ], + [ "DIR", "structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa", null ], + [ "EOIR", "structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb", null ], + [ "HPPIR", "structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6", null ], + [ "IAR", "structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea", null ], + [ "IIDR", "structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf", null ], + [ "NSAPR", "structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4", null ], + [ "PMR", "structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b", null ], + [ "RPR", "structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821", null ], + [ "STATUSR", "structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/structL2C__310__TypeDef.html b/docs/Core_A/html/structL2C__310__TypeDef.html new file mode 100644 index 0000000..752f8b8 --- /dev/null +++ b/docs/Core_A/html/structL2C__310__TypeDef.html @@ -0,0 +1,760 @@ + + + + + +L2C_310_TypeDef Struct Reference +CMSIS-Core (Cortex-A): L2C_310_TypeDef Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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    CMSIS-Core support for Cortex-A processor-based devices
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    +Data Fields
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    L2C_310_TypeDef Struct Reference
    L2C-310 Cache Controller Functions
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    +
    + +

    Union type to access the L2C_310 Cache Controller. +

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    +Data Fields

    __IM uint32_t CACHE_ID
     Offset: 0x0000 (R/ ) Cache ID Register. More...
     
    __IM uint32_t CACHE_TYPE
     Offset: 0x0004 (R/ ) Cache Type Register. More...
     
    __IOM uint32_t CONTROL
     Offset: 0x0100 (R/W) Control Register. More...
     
    __IOM uint32_t AUX_CNT
     Offset: 0x0104 (R/W) Auxiliary Control. More...
     
    __IOM uint32_t EVENT_CONTROL
     Offset: 0x0200 (R/W) Event Counter Control. More...
     
    __IOM uint32_t EVENT_COUNTER1_CONF
     Offset: 0x0204 (R/W) Event Counter 1 Configuration. More...
     
    __IOM uint32_t EVENT_COUNTER0_CONF
     Offset: 0x0208 (R/W) Event Counter 1 Configuration. More...
     
    __IOM uint32_t INTERRUPT_MASK
     Offset: 0x0214 (R/W) Interrupt Mask. More...
     
    __IM uint32_t MASKED_INT_STATUS
     Offset: 0x0218 (R/ ) Masked Interrupt Status. More...
     
    __IM uint32_t RAW_INT_STATUS
     Offset: 0x021c (R/ ) Raw Interrupt Status. More...
     
    __OM uint32_t INTERRUPT_CLEAR
     Offset: 0x0220 ( /W) Interrupt Clear. More...
     
    __IOM uint32_t CACHE_SYNC
     Offset: 0x0730 (R/W) Cache Sync. More...
     
    __IOM uint32_t INV_LINE_PA
     Offset: 0x0770 (R/W) Invalidate Line By PA. More...
     
    __IOM uint32_t INV_WAY
     Offset: 0x077c (R/W) Invalidate by Way. More...
     
    __IOM uint32_t CLEAN_LINE_PA
     Offset: 0x07b0 (R/W) Clean Line by PA. More...
     
    __IOM uint32_t CLEAN_LINE_INDEX_WAY
     Offset: 0x07b8 (R/W) Clean Line by Index/Way. More...
     
    __IOM uint32_t CLEAN_WAY
     Offset: 0x07bc (R/W) Clean by Way. More...
     
    __IOM uint32_t CLEAN_INV_LINE_PA
     Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA. More...
     
    __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY
     Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way. More...
     
    __IOM uint32_t CLEAN_INV_WAY
     Offset: 0x07fc (R/W) Clean and Invalidate by Way. More...
     
    __IOM uint32_t DATA_LOCK_0_WAY
     Offset: 0x0900 (R/W) Data Lockdown 0 by Way. More...
     
    __IOM uint32_t INST_LOCK_0_WAY
     Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way. More...
     
    __IOM uint32_t DATA_LOCK_1_WAY
     Offset: 0x0908 (R/W) Data Lockdown 1 by Way. More...
     
    __IOM uint32_t INST_LOCK_1_WAY
     Offset: 0x090c (R/W) Instruction Lockdown 1 by Way. More...
     
    __IOM uint32_t DATA_LOCK_2_WAY
     Offset: 0x0910 (R/W) Data Lockdown 2 by Way. More...
     
    __IOM uint32_t INST_LOCK_2_WAY
     Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way. More...
     
    __IOM uint32_t DATA_LOCK_3_WAY
     Offset: 0x0918 (R/W) Data Lockdown 3 by Way. More...
     
    __IOM uint32_t INST_LOCK_3_WAY
     Offset: 0x091c (R/W) Instruction Lockdown 3 by Way. More...
     
    __IOM uint32_t DATA_LOCK_4_WAY
     Offset: 0x0920 (R/W) Data Lockdown 4 by Way. More...
     
    __IOM uint32_t INST_LOCK_4_WAY
     Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way. More...
     
    __IOM uint32_t DATA_LOCK_5_WAY
     Offset: 0x0928 (R/W) Data Lockdown 5 by Way. More...
     
    __IOM uint32_t INST_LOCK_5_WAY
     Offset: 0x092c (R/W) Instruction Lockdown 5 by Way. More...
     
    __IOM uint32_t DATA_LOCK_6_WAY
     Offset: 0x0930 (R/W) Data Lockdown 5 by Way. More...
     
    __IOM uint32_t INST_LOCK_6_WAY
     Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way. More...
     
    __IOM uint32_t DATA_LOCK_7_WAY
     Offset: 0x0938 (R/W) Data Lockdown 6 by Way. More...
     
    __IOM uint32_t INST_LOCK_7_WAY
     Offset: 0x093c (R/W) Instruction Lockdown 6 by Way. More...
     
    __IOM uint32_t LOCK_LINE_EN
     Offset: 0x0950 (R/W) Lockdown by Line Enable. More...
     
    __IOM uint32_t UNLOCK_ALL_BY_WAY
     Offset: 0x0954 (R/W) Unlock All Lines by Way. More...
     
    __IOM uint32_t ADDRESS_FILTER_START
     Offset: 0x0c00 (R/W) Address Filtering Start. More...
     
    __IOM uint32_t ADDRESS_FILTER_END
     Offset: 0x0c04 (R/W) Address Filtering End. More...
     
    __IOM uint32_t DEBUG_CONTROL
     Offset: 0x0f40 (R/W) Debug Control Register. More...
     
    +

    Field Documentation

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    L2C_310_TypeDef::ADDRESS_FILTER_END
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    __IOM uint32_t L2C_310_TypeDef::ADDRESS_FILTER_START
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    __IOM uint32_t L2C_310_TypeDef::AUX_CNT
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    __IM uint32_t L2C_310_TypeDef::CACHE_ID
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    __IOM uint32_t L2C_310_TypeDef::CACHE_SYNC
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    __IM uint32_t L2C_310_TypeDef::CACHE_TYPE
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    __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_INDEX_WAY
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    __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_PA
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    __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_WAY
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    __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_INDEX_WAY
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    __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_PA
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    __IOM uint32_t L2C_310_TypeDef::CLEAN_WAY
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    __IOM uint32_t L2C_310_TypeDef::CONTROL
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_0_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_1_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_2_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_3_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_4_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_5_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_6_WAY
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    __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_7_WAY
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    __IOM uint32_t L2C_310_TypeDef::DEBUG_CONTROL
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    __IOM uint32_t L2C_310_TypeDef::EVENT_CONTROL
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    __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER0_CONF
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    __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER1_CONF
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_0_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_1_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_2_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_3_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_4_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_5_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_6_WAY
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    __IOM uint32_t L2C_310_TypeDef::INST_LOCK_7_WAY
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    __OM uint32_t L2C_310_TypeDef::INTERRUPT_CLEAR
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    __IOM uint32_t L2C_310_TypeDef::INTERRUPT_MASK
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    __IOM uint32_t L2C_310_TypeDef::INV_LINE_PA
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    __IOM uint32_t L2C_310_TypeDef::INV_WAY
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    __IOM uint32_t L2C_310_TypeDef::LOCK_LINE_EN
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    __IM uint32_t L2C_310_TypeDef::MASKED_INT_STATUS
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    __IM uint32_t L2C_310_TypeDef::RAW_INT_STATUS
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    __IOM uint32_t L2C_310_TypeDef::UNLOCK_ALL_BY_WAY
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    + + + + diff --git a/docs/Core_A/html/structL2C__310__TypeDef.js b/docs/Core_A/html/structL2C__310__TypeDef.js new file mode 100644 index 0000000..99ea05c --- /dev/null +++ b/docs/Core_A/html/structL2C__310__TypeDef.js @@ -0,0 +1,44 @@ +var structL2C__310__TypeDef = +[ + [ "ADDRESS_FILTER_END", "structL2C__310__TypeDef.html#a956e7653f25ae52ac9534eb0e1d94c8c", null ], + [ "ADDRESS_FILTER_START", "structL2C__310__TypeDef.html#ae3f752040cdfcabd337b3f0359216b11", null ], + [ "AUX_CNT", "structL2C__310__TypeDef.html#a4f7bc7277a5baa1d804913e41b8200be", null ], + [ "CACHE_ID", "structL2C__310__TypeDef.html#a87833c2acdf685d6ad6d0811f45677d7", null ], + [ "CACHE_SYNC", "structL2C__310__TypeDef.html#ab9b9d1842b5d9e828a6825533ab80c0f", null ], + [ "CACHE_TYPE", "structL2C__310__TypeDef.html#af19e1fd8a729834557884232c9e50bd2", null ], + [ "CLEAN_INV_LINE_INDEX_WAY", "structL2C__310__TypeDef.html#a2adcc6bff9e527be24076d197368a962", null ], + [ "CLEAN_INV_LINE_PA", "structL2C__310__TypeDef.html#a61615f4a4ac97d5d278000a35100d795", null ], + [ "CLEAN_INV_WAY", "structL2C__310__TypeDef.html#ae27fc13cf14eae85ad7ed2c86fd30f6c", null ], + [ "CLEAN_LINE_INDEX_WAY", "structL2C__310__TypeDef.html#ac79d3397741a3ae8566c878b45d30970", null ], + [ "CLEAN_LINE_PA", "structL2C__310__TypeDef.html#a400d9ededaf12a5193e01d7235f3d65d", null ], + [ "CLEAN_WAY", "structL2C__310__TypeDef.html#a0e6d40fb25420d5cac5be15ad2662e2c", null ], + [ "CONTROL", "structL2C__310__TypeDef.html#a491a4ed1ecdcdf784b180fa13ef46f2f", null ], + [ "DATA_LOCK_0_WAY", "structL2C__310__TypeDef.html#a2dbbc5c93d3ddffe2459c053d30ede2d", null ], + [ "DATA_LOCK_1_WAY", "structL2C__310__TypeDef.html#a6288cc2774812105b52a22daedd0c39f", null ], + [ "DATA_LOCK_2_WAY", "structL2C__310__TypeDef.html#acdbc2d1db5722edc69752fe78a5c477d", null ], + [ "DATA_LOCK_3_WAY", "structL2C__310__TypeDef.html#a331d20510fc27cd593ddfedc88c75240", null ], + [ "DATA_LOCK_4_WAY", "structL2C__310__TypeDef.html#aa0a0f2165e329d514cc91dbf84a44a76", null ], + [ "DATA_LOCK_5_WAY", "structL2C__310__TypeDef.html#a6f777080cbf9426d8476d07f6e583d71", null ], + [ "DATA_LOCK_6_WAY", "structL2C__310__TypeDef.html#ab81366685e54829cae7613f080d69f53", null ], + [ "DATA_LOCK_7_WAY", "structL2C__310__TypeDef.html#aed70f16007d4e7d19818e0931581c5a5", null ], + [ "DEBUG_CONTROL", "structL2C__310__TypeDef.html#a996a2a5c1f311a6f3555844adc28e7f4", null ], + [ "EVENT_CONTROL", "structL2C__310__TypeDef.html#a2bc6f09ea83f8d3c966558598a098995", null ], + [ "EVENT_COUNTER0_CONF", "structL2C__310__TypeDef.html#a1c78032b2b237ee968d6758bddc915ba", null ], + [ "EVENT_COUNTER1_CONF", "structL2C__310__TypeDef.html#a4465c7dd7b45f8f35acde8c6e28cbd17", null ], + [ "INST_LOCK_0_WAY", "structL2C__310__TypeDef.html#a50ed69958acada08cce2c93b609097ad", null ], + [ "INST_LOCK_1_WAY", "structL2C__310__TypeDef.html#acba26dcc19591924d2ad088a0b8302fa", null ], + [ "INST_LOCK_2_WAY", "structL2C__310__TypeDef.html#a98c744b09e490fa49beb452ddbc29ffd", null ], + [ "INST_LOCK_3_WAY", "structL2C__310__TypeDef.html#aca5cecc05dae56be40cb1b0852b78490", null ], + [ "INST_LOCK_4_WAY", "structL2C__310__TypeDef.html#a0a54ef3839f09715962f7cc04879d6b8", null ], + [ "INST_LOCK_5_WAY", "structL2C__310__TypeDef.html#a9464799ec7797bacade9eacd4703bad2", null ], + [ "INST_LOCK_6_WAY", "structL2C__310__TypeDef.html#a990118c9674df74beb6879b3f6dbcbc6", null ], + [ "INST_LOCK_7_WAY", "structL2C__310__TypeDef.html#a6240652959732fbb74bbee91d4b487d0", null ], + [ "INTERRUPT_CLEAR", "structL2C__310__TypeDef.html#a43116dfea74e77e870fd790189a403ec", null ], + [ "INTERRUPT_MASK", "structL2C__310__TypeDef.html#a7c8ff2c17c6f3eb0d951e4cd193fd8e4", null ], + [ "INV_LINE_PA", "structL2C__310__TypeDef.html#a1e7c5255e61ce785f2fd5c767178c098", null ], + [ "INV_WAY", "structL2C__310__TypeDef.html#a78853d391272ff835025e8382c3c88d2", null ], + [ "LOCK_LINE_EN", "structL2C__310__TypeDef.html#a58357795f3cda2b0063411abc5165804", null ], + [ "MASKED_INT_STATUS", "structL2C__310__TypeDef.html#a207e1eb35e13440241db1109790d9740", null ], + [ "RAW_INT_STATUS", "structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637", null ], + [ "UNLOCK_ALL_BY_WAY", "structL2C__310__TypeDef.html#acb39f337a421d0640f39092dc992ef1a", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/structTimer__Type.html b/docs/Core_A/html/structTimer__Type.html new file mode 100644 index 0000000..54e1a7e --- /dev/null +++ b/docs/Core_A/html/structTimer__Type.html @@ -0,0 +1,368 @@ + + + + + +Timer_Type Struct Reference +CMSIS-Core (Cortex-A): Timer_Type Struct Reference + + + + + + + + + + + + + + +
    +
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    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
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    +Data Fields
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    Timer_Type Struct Reference
    Private Timer Functions
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    +
    + +

    Structure type to access the Private Timer. +

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    +Data Fields

    __IOM uint32_t LOAD
     Offset: 0x000 (R/W) Private Timer Load Register. More...
     
    __IOM uint32_t COUNTER
     Offset: 0x004 (R/W) Private Timer Counter Register. More...
     
    __IOM uint32_t CONTROL
     Offset: 0x008 (R/W) Private Timer Control Register. More...
     
    __IOM uint32_t ISR
     Offset: 0x00C (R/W) Private Timer Interrupt Status Register. More...
     
    __IOM uint32_t WLOAD
     Offset: 0x020 (R/W) Watchdog Load Register. More...
     
    __IOM uint32_t WCOUNTER
     Offset: 0x024 (R/W) Watchdog Counter Register. More...
     
    __IOM uint32_t WCONTROL
     Offset: 0x028 (R/W) Watchdog Control Register. More...
     
    __IOM uint32_t WISR
     Offset: 0x02C (R/W) Watchdog Interrupt Status Register. More...
     
    __IOM uint32_t WRESET
     Offset: 0x030 (R/W) Watchdog Reset Status Register. More...
     
    __OM uint32_t WDISABLE
     Offset: 0x034 ( /W) Watchdog Disable Register. More...
     
    +

    Field Documentation

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    + + + + +
    __IOM uint32_t Timer_Type::CONTROL
    +
    +

    Private Timer Control Register

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    Bits Name Function
    [31:16] - Reserved.
    [15:8] Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register.
    [7:3] - Reserved.
    [2] IRQ Enable If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.
    [1] Auto Reload If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register.
    [0] Time Enabled If set, Timer is enabled and the counter decrements normally.
    + +
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    +
    + + + + +
    __IOM uint32_t Timer_Type::COUNTER
    +
    +

    Private Timer Counter Register The Timer Counter Register is a decrementing counter.

    +

    The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.

    +

    When the Timer Counter Register reaches zero and auto reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.

    +

    When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register.

    +

    Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value.

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t Timer_Type::ISR
    +
    +

    Private Timer Interrupt Status Register

    +

    The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written to 1.

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t Timer_Type::LOAD
    +
    +

    Private Timer Load Register The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register.

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t Timer_Type::WCONTROL
    +
    +

    Watchdog Control Register

    + + + + + + + + + + + + + + + + + +
    Bits Name Function
    [31:16] - Reserved.
    [15:8] Prescaler The prescaler modifies the clock period for the decrementing event for the Counter Register.
    [7:4] - Reserved.
    [3] Watchdog Mode 0 - Timer mode (default), 1 - Watchdog mode
    [2] IT Enable Interrupt enable for timer mode.
    [1] Auto Reload 0 - Single shot mode, 1 - Continuous timer mode
    [0] Watchdog Enable 0 - Watchdog counter disabled, 1 - Watchdog timer enabled
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t Timer_Type::WCOUNTER
    +
    +

    Watchdog Counter Register

    +

    The Watchdog Counter Register is a down counter.

    +

    The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode:

    +
      +
    • Timer mode: The watchdog interrupt status event flag is set and the interrupt is set as pending in the Interrupt Distributor.
      • +
    • Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ reset request output pin is asserted.
      • +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t Timer_Type::WDISABLE
    +
    +

    Watchdog Disable Register

    +

    Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t Timer_Type::WISR
    +
    +

    Watchdog Interrupt Status Register

    + + + + + + + +
    Bits Name Function
    [31:1] - Reserved.
    [0] Event Flag The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode.
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t Timer_Type::WLOAD
    +
    +

    Watchdog Load Register

    +

    The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register.

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t Timer_Type::WRESET
    +
    +

    Watchdog Reset Status Register

    + + + + + + + +
    Bits Name Function
    [31:1] - Reserved.
    [0] Reset Flag The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode)
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/structTimer__Type.js b/docs/Core_A/html/structTimer__Type.js new file mode 100644 index 0000000..e694909 --- /dev/null +++ b/docs/Core_A/html/structTimer__Type.js @@ -0,0 +1,13 @@ +var structTimer__Type = +[ + [ "CONTROL", "structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4", null ], + [ "COUNTER", "structTimer__Type.html#ac933977724591e6ca87d91848fc7a6b6", null ], + [ "ISR", "structTimer__Type.html#ace17db6ca92940b030ad2ccbc674877e", null ], + [ "LOAD", "structTimer__Type.html#a073457d2d18c2eff93fd12aec81ef20b", null ], + [ "WCONTROL", "structTimer__Type.html#ac04581b452702517bfbfa61f9af4c6dd", null ], + [ "WCOUNTER", "structTimer__Type.html#a7a763d92fbcb506a28a22de548934abc", null ], + [ "WDISABLE", "structTimer__Type.html#a9d577164e0a55ecd6c630a9720f153c3", null ], + [ "WISR", "structTimer__Type.html#a6239a36319b919b809e00dd26db105fc", null ], + [ "WLOAD", "structTimer__Type.html#a6855bbb5d49f336c9f995dcce492455a", null ], + [ "WRESET", "structTimer__Type.html#a775e70c9dbf2b562f9884a9e0dded741", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/structmmu__region__attributes__Type.html b/docs/Core_A/html/structmmu__region__attributes__Type.html new file mode 100644 index 0000000..1b34694 --- /dev/null +++ b/docs/Core_A/html/structmmu__region__attributes__Type.html @@ -0,0 +1,310 @@ + + + + + +mmu_region_attributes_Type Struct Reference +CMSIS-Core (Cortex-A): mmu_region_attributes_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    mmu_region_attributes_Type Struct Reference
    MMU Defines and Structs
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    mmu_region_size_Type rg_t
     
    mmu_memory_Type mem_t
     
    uint8_t domain
     
    mmu_cacheability_Type inner_norm_t
     
    mmu_cacheability_Type outer_norm_t
     
    mmu_ecc_check_Type e_t
     
    mmu_execute_Type xn_t
     
    mmu_global_Type g_t
     
    mmu_secure_Type sec_t
     
    mmu_access_Type priv_t
     
    mmu_access_Type user_t
     
    mmu_shared_Type sh_t
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint8_t mmu_region_attributes_Type::domain
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_ecc_check_Type mmu_region_attributes_Type::e_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_global_Type mmu_region_attributes_Type::g_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_cacheability_Type mmu_region_attributes_Type::inner_norm_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_memory_Type mmu_region_attributes_Type::mem_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_cacheability_Type mmu_region_attributes_Type::outer_norm_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_access_Type mmu_region_attributes_Type::priv_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_region_size_Type mmu_region_attributes_Type::rg_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_secure_Type mmu_region_attributes_Type::sec_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_shared_Type mmu_region_attributes_Type::sh_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_access_Type mmu_region_attributes_Type::user_t
    +
    + +
    +
    + +
    +
    + + + + +
    mmu_execute_Type mmu_region_attributes_Type::xn_t
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/structmmu__region__attributes__Type.js b/docs/Core_A/html/structmmu__region__attributes__Type.js new file mode 100644 index 0000000..9fa6e13 --- /dev/null +++ b/docs/Core_A/html/structmmu__region__attributes__Type.js @@ -0,0 +1,15 @@ +var structmmu__region__attributes__Type = +[ + [ "domain", "structmmu__region__attributes__Type.html#a94158b710d212b8ca8105d78a910db39", null ], + [ "e_t", "structmmu__region__attributes__Type.html#a7883ad6e464090150b175a54c68f592e", null ], + [ "g_t", "structmmu__region__attributes__Type.html#a51f1a2a77db791b2bdf012f86605adfc", null ], + [ "inner_norm_t", "structmmu__region__attributes__Type.html#a2088aadb7aa8e9b0d91d2dbad564bf33", null ], + [ "mem_t", "structmmu__region__attributes__Type.html#a0d81c9add0ddd2cc5f89e03fae0a3720", null ], + [ "outer_norm_t", "structmmu__region__attributes__Type.html#a2aebbdf7cfb941d5703d008f02131622", null ], + [ "priv_t", "structmmu__region__attributes__Type.html#afb58787cfcf5b9aaf711794e3bf3e849", null ], + [ "rg_t", "structmmu__region__attributes__Type.html#a3f9d884c340aca62d3287b91809ac262", null ], + [ "sec_t", "structmmu__region__attributes__Type.html#a195e022fa08ec703937fa8175d8371d7", null ], + [ "sh_t", "structmmu__region__attributes__Type.html#ad1962a36e3bf13dfb89bc76862097ed5", null ], + [ "user_t", "structmmu__region__attributes__Type.html#a6b32b61a1ee042a22ae0c8a2bd7de544", null ], + [ "xn_t", "structmmu__region__attributes__Type.html#aa8c562e2d40092a0001f49987c7f4a58", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/sync_off.png b/docs/Core_A/html/sync_off.png new file mode 100644 index 0000000..e8e314d Binary files /dev/null and b/docs/Core_A/html/sync_off.png differ diff --git a/docs/Core_A/html/sync_on.png b/docs/Core_A/html/sync_on.png new file mode 100644 index 0000000..f80906a Binary files /dev/null and b/docs/Core_A/html/sync_on.png differ diff --git a/docs/Core_A/html/system__ARMCA9_8h.html b/docs/Core_A/html/system__ARMCA9_8h.html new file mode 100644 index 0000000..9a4b9e1 --- /dev/null +++ b/docs/Core_A/html/system__ARMCA9_8h.html @@ -0,0 +1,203 @@ + + + + + +system_ARMCA9.h File Reference +CMSIS-Core (Cortex-A): system_ARMCA9.h File Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Functions | +Variables
    +
    +
    system_ARMCA9.h File Reference
    +
    +
    + + + + + + + + + + + +

    +Functions

    void SystemInit (void)
     Setup the microcontroller system. More...
     
    void SystemCoreClockUpdate (void)
     Update SystemCoreClock variable. More...
     
    void MMU_CreateTranslationTable (void)
     Create Translation Table. More...
     
    + + + + +

    +Variables

    uint32_t SystemCoreClock
     Variable to hold the system core clock value. More...
     
    +

    Function Documentation

    + +
    +
    + + + + + + + + +
    void MMU_CreateTranslationTable (void )
    +
    +

    Creates Memory Management Unit Translation Table.

    + +
    +
    + +
    +
    + + + + + + + + +
    void SystemCoreClockUpdate (void )
    +
    +

    Updates the SystemCoreClock with current core Clock retrieved from cpu registers.

    + +
    +
    + +
    +
    + + + + + + + + +
    void SystemInit (void )
    +
    +

    Initialize the System and update the SystemCoreClock variable.

    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/system_c_pg.html b/docs/Core_A/html/system_c_pg.html new file mode 100644 index 0000000..9ca50f1 --- /dev/null +++ b/docs/Core_A/html/system_c_pg.html @@ -0,0 +1,310 @@ + + + + + +System Configuration Files system_<device>.c and system_<device>.h +CMSIS-Core (Cortex-A): System Configuration Files system_<device>.c and system_<device>.h + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    System Configuration Files system_<device>.c and system_<device>.h
    +
    +
    +

    The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.

    +

    For devices with external memory BUS the system_<device>.c also configures the BUS system.

    +

    The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.

    +

    +system_Device.c Template File

    +

    The system_Device.c Template File for the Cortex-M3 is shown below.

    +
    /******************************************************************************
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-A Device Peripheral Access Layer 
+ * @version  V1.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
+#include "irq_ctrl.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization
+         following is an example for different system frequencies */
+#define XTAL            (12000000U)       /* Oscillator frequency             */
+
+#define SYSTEM_CLOCK    (5 * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit() */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Clock Frequency (Core Clock)*/
+
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings. */
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+   Do not use global variables because this function is called before
+   reaching pre-main. RW section may be overwritten afterwards.          */
+  SystemCoreClock = SYSTEM_CLOCK;
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+  
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  // Enable GIC
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}
+

    +system_Device.h Template File

    +

    The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-A Device Peripheral Access Layer
+ * @version  V5.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_<Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */
+
    +
    + + + + diff --git a/docs/Core_A/html/tab_a.png b/docs/Core_A/html/tab_a.png new file mode 100644 index 0000000..fffadc1 Binary files /dev/null and b/docs/Core_A/html/tab_a.png differ diff --git a/docs/Core_A/html/tab_b.png b/docs/Core_A/html/tab_b.png new file mode 100644 index 0000000..b7ce1af Binary files /dev/null and b/docs/Core_A/html/tab_b.png differ diff --git a/docs/Core_A/html/tab_h.png b/docs/Core_A/html/tab_h.png new file mode 100644 index 0000000..5e9188f Binary files /dev/null and b/docs/Core_A/html/tab_h.png differ diff --git a/docs/Core_A/html/tab_s.png b/docs/Core_A/html/tab_s.png new file mode 100644 index 0000000..956e1c2 Binary files /dev/null and b/docs/Core_A/html/tab_s.png differ diff --git a/docs/Core_A/html/tab_topnav.png b/docs/Core_A/html/tab_topnav.png new file mode 100644 index 0000000..b257b77 Binary files /dev/null and b/docs/Core_A/html/tab_topnav.png differ diff --git a/docs/Core_A/html/tabs.css b/docs/Core_A/html/tabs.css new file mode 100644 index 0000000..ffbab50 --- /dev/null +++ b/docs/Core_A/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/docs/Core_A/html/templates_pg.html b/docs/Core_A/html/templates_pg.html new file mode 100644 index 0000000..2978def --- /dev/null +++ b/docs/Core_A/html/templates_pg.html @@ -0,0 +1,212 @@ + + + + + +CMSIS-Core Device Templates +CMSIS-Core (Cortex-A): CMSIS-Core Device Templates + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    CMSIS-Core Device Templates
    +
    +
    +

    Arm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliance.

    +

    These CMSIS-Core device template files include the following:

    +
      +
    • Register names of the Core Peripherals and names of the Core Exception Vectors.
      • +
    • Functions to access core peripherals, cache, MMU and special CPU instructions
      • +
    • Generic startup code and system configuration code.
      • +
    +

    The detailed file structure of the CMSIS-Core device templates is shown in the following picture.

    +

    +CMSIS-Core Processor Files

    +

    The CMSIS-Core processor files provided by Arm are in the directory .\CMSIS\Core_A\Include. These header files define all processor specific attributes do not need any modifications. The core_<cpu>.h defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:

    + + + + + +
    Header File Processor
    core_ca.h generics for all supportet Cortex-A processors
    +

    +Device Examples

    +

    The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\Device\ARM and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file ARM.CMSIS.pdsc:

    + + + + + + + + + +
    Family Device Description
    ARM Cortex-A5 ARMCA5 Cortex-A5 based device
    ARM Cortex-A7 ARMCA7 Cortex-A7 based device
    ARM Cortex-A9 ARMCA9 Cortex-A9 based device
    +

    +Template Files

    +

    To simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add to these template files the following information:

    +
      +
    • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
      • +
    • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
      • +
    • Interrupt vectors in the startup file that are device specific.
      • +
    + + + + + + + + + + + + + + + + + +
    Template File Description
    .\Device\_Template_Vendor\Vendor\Device_A\Source\ARM\startup_Device.c Startup file template for Arm C/C++ Compiler.
    .\Device\_Template_Vendor\Vendor\Device_A\Source\ARM\Device.sct Linker scatter file template for Arm C/C++ Compiler.
    .\Device\_Template_Vendor\Vendor\Device_A\Source\system_Device.c Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).
    .\Device\_Template_Vendor\Vendor\Device_A\Source\mmu_Device.c Sample mmu_Device.c file with memory map description for Memory Management Unit (MMU) configuration.
    .\Device\_Template_Vendor\Vendor\Device_A\Include\Device.h Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.
    .\Device\_Template_Vendor\Vendor\Device_A\Include\system_Device.h Generic system device configuration include file.
    .\Device\_Template_Vendor\Vendor\Device_A\Include\mem_Device.h Generic memory base address and size definitions used in scatter file. Settable via Configuration Wizard.
    +

    Adapt Template Files to a Device

    +

    The following steps describe how to adopt the template files to a specific device or device family. Copy the complete all files in the template directory and replace:

    +
      +
    • directory name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
      • +
    • directory name 'Device' with the specific device name e.g.: LPC17xx.
      • +
    • in the file names 'Device' with the specific device name e.g.: LPC17xx.
      • +
    +

    Each template file contains comments that start with ToDo: that describe a required modification. The template files contain place holders:

    + + + + + + + + + + + +
    Placeholder Replaced with
    <Device> the specific device name or device family name; i.e. LPC17xx.
    <DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1.
    <DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.
    Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.
    +

    The device configuration of the template files is described in detail on the following pages:

    + +
    +
    + + + + diff --git a/docs/Core_A/html/templates_pg.js b/docs/Core_A/html/templates_pg.js new file mode 100644 index 0000000..429e978 --- /dev/null +++ b/docs/Core_A/html/templates_pg.js @@ -0,0 +1,25 @@ +var templates_pg = +[ + [ "CMSIS-Core Processor Files", "templates_pg.html#CMSIS_Processor_files", null ], + [ "Device Examples", "templates_pg.html#device_examples", null ], + [ "Template Files", "templates_pg.html#template_files_sec", null ], + [ "Startup File startup_.c", "startup_c_pg.html", [ + [ "startup_Device.c Template File", "startup_c_pg.html#startup_c_sec", null ] + ] ], + [ "System Configuration Files system_.c and system_.h", "system_c_pg.html", [ + [ "system_Device.c Template File", "system_c_pg.html#system_Device_sec", null ], + [ "system_Device.h Template File", "system_c_pg.html#system_Device_h_sec", null ] + ] ], + [ "Device Header File \\", "device_h_pg.html", [ + [ "Interrupt Number Definition", "device_h_pg.html#irqn_defs", null ], + [ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#config_perifs", null ], + [ "Device Peripheral Access Layer", "device_h_pg.html#access_perifs", null ], + [ "Interrupt Number Definition", "device_h_pg.html#interrupt_number_sec", null ], + [ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#core_config_sect", null ], + [ "CMSIS Version and Processor Information", "device_h_pg.html#core_version_sect", null ], + [ "Device Peripheral Access Layer", "device_h_pg.html#device_access", null ], + [ "Device.h Template File", "device_h_pg.html#device_h_sec", null ] + ] ], + [ "Memory Configuration Files mem_.h", "mem_h_pg.html", null ], + [ "Memory Management Unit Files mmu_.c", "mmu_c_pg.html", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionACTLR__Type.html b/docs/Core_A/html/unionACTLR__Type.html new file mode 100644 index 0000000..51fec7a --- /dev/null +++ b/docs/Core_A/html/unionACTLR__Type.html @@ -0,0 +1,511 @@ + + + + + +ACTLR_Type Struct Reference +CMSIS-Core (Cortex-A): ACTLR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    ACTLR_Type Struct Reference
    Auxiliary Control Register (ACTLR)
    +
    +
    + +

    Bit field declaration for ACTLR layout. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   FW:1
     bit: 0 Cache and TLB maintenance broadcast More...
     
       uint32_t   SMP:1
     bit: 6 Enables coherent requests to the processor More...
     
       uint32_t   EXCL:1
     bit: 7 Exclusive L1/L2 cache control More...
     
       uint32_t   DODMBS:1
     bit: 10 Disable optimized data memory barrier behavior More...
     
       uint32_t   DWBST:1
     bit: 11 AXI data write bursts to Normal memory More...
     
       uint32_t   RADIS:1
     bit: 12 L1 Data Cache read-allocate mode disable More...
     
       uint32_t   L1PCTL:2
     bit:13..14 L1 Data prefetch control More...
     
       uint32_t   BP:2
     bit:16..15 Branch prediction policy More...
     
       uint32_t   RSDIS:1
     bit: 17 Disable return stack operation More...
     
       uint32_t   BTDIS:1
     bit: 18 Disable indirect Branch Target Address Cache (BTAC) More...
     
       uint32_t   DBDI:1
     bit: 28 Disable branch dual issue More...
     
    } b
     Structure used for bit access on Cortex-A5. More...
     
    struct {
       uint32_t   SMP:1
     bit: 6 Enables coherent requests to the processor More...
     
       uint32_t   DODMBS:1
     bit: 10 Disable optimized data memory barrier behavior More...
     
       uint32_t   L2RADIS:1
     bit: 11 L2 Data Cache read-allocate mode disable More...
     
       uint32_t   L1RADIS:1
     bit: 12 L1 Data Cache read-allocate mode disable More...
     
       uint32_t   L1PCTL:2
     bit:13..14 L1 Data prefetch control More...
     
       uint32_t   DDVM:1
     bit: 15 Disable Distributed Virtual Memory (DVM) transactions More...
     
       uint32_t   DDI:1
     bit: 28 Disable dual issue More...
     
    } b
     Structure used for bit access on Cortex-A7. More...
     
    struct {
       uint32_t   FW:1
     bit: 0 Cache and TLB maintenance broadcast More...
     
       uint32_t   L1PE:1
     bit: 2 Dside prefetch More...
     
       uint32_t   WFLZM:1
     bit: 3 Cache and TLB maintenance broadcast More...
     
       uint32_t   SMP:1
     bit: 6 Enables coherent requests to the processor More...
     
       uint32_t   EXCL:1
     bit: 7 Exclusive L1/L2 cache control More...
     
       uint32_t   AOW:1
     bit: 8 Enable allocation in one cache way only More...
     
       uint32_t   PARITY:1
     bit: 9 Support for parity checking, if implemented More...
     
    } b
     Structure used for bit access on Cortex-A9. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t ACTLR_Type::AOW
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } ACTLR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } ACTLR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } ACTLR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::BP
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::BTDIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::DBDI
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::DDI
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::DDVM
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::DODMBS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::DWBST
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::EXCL
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::FW
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::L1PCTL
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::L1PE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::L1RADIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::L2RADIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::PARITY
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::RADIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::RSDIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::SMP
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ACTLR_Type::WFLZM
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionACTLR__Type.js b/docs/Core_A/html/unionACTLR__Type.js new file mode 100644 index 0000000..207d81e --- /dev/null +++ b/docs/Core_A/html/unionACTLR__Type.js @@ -0,0 +1,26 @@ +var unionACTLR__Type = +[ + [ "AOW", "unionACTLR__Type.html#a3f235030777fe4e20477063df416b515", null ], + [ "b", "unionACTLR__Type.html#ac953059faa3a1139f8787d87f58a875d", null ], + [ "b", "unionACTLR__Type.html#a94d750b9b337ce140b04d6e30e7a2ca2", null ], + [ "b", "unionACTLR__Type.html#a5044f19ce5ae1f73dda07f7187e70923", null ], + [ "BP", "unionACTLR__Type.html#ac8ac735e3001442e581ae37e773b5929", null ], + [ "BTDIS", "unionACTLR__Type.html#ad1a121373ae8df19f6d11bde3b3ba9c9", null ], + [ "DBDI", "unionACTLR__Type.html#a19e5f8f1a2ad8634619399b4eb50a449", null ], + [ "DDI", "unionACTLR__Type.html#ab938c32e10162d06ba6b02400e955e01", null ], + [ "DDVM", "unionACTLR__Type.html#a4fe04e95b26e089642bee6952f223f82", null ], + [ "DODMBS", "unionACTLR__Type.html#acfabc61e73fb846970cd6541c5baf7d8", null ], + [ "DWBST", "unionACTLR__Type.html#ad8faaa57629f258c6eba678ba8efc9da", null ], + [ "EXCL", "unionACTLR__Type.html#a10c6d649f67d6ca9029731fc44631e91", null ], + [ "FW", "unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781", null ], + [ "L1PCTL", "unionACTLR__Type.html#a5464ac7b26943d2cb868c154b0b1375c", null ], + [ "L1PE", "unionACTLR__Type.html#aacb87aa6bf093e1ee956342e0cb5903e", null ], + [ "L1RADIS", "unionACTLR__Type.html#a3800bdd7abfab1a51dcfa7069e245d65", null ], + [ "L2RADIS", "unionACTLR__Type.html#a947f73d64ebde186b9416fd6dc66bc26", null ], + [ "PARITY", "unionACTLR__Type.html#a6e8f053d01fb236cc7d002b04d93a19c", null ], + [ "RADIS", "unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3", null ], + [ "RSDIS", "unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3", null ], + [ "SMP", "unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149", null ], + [ "w", "unionACTLR__Type.html#ac65c09d839f8a78340c3b81d3bc90e4d", null ], + [ "WFLZM", "unionACTLR__Type.html#a67e005f7741b6d46cf95d9c477efef36", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionCNTP__CTL__Type.html b/docs/Core_A/html/unionCNTP__CTL__Type.html new file mode 100644 index 0000000..481325a --- /dev/null +++ b/docs/Core_A/html/unionCNTP__CTL__Type.html @@ -0,0 +1,279 @@ + + + + + +CNTP_CTL_Type Union Reference +CMSIS-Core (Cortex-A): CNTP_CTL_Type Union Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CNTP_CTL_Type Union Reference
    Generic Physical Timer Functions
    +
    +
    + +

    Physical Timer Control register. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   ENABLE:1
     bit: 0 Enables the timer. More...
     
       uint32_t   IMASK:1
     bit: 1 Timer output signal mask bit. More...
     
       uint32_t   ISTATUS:1
     bit: 2 The status of the timer. More...
     
       uint32_t   _reserved0:29
     bit: 3..31 Reserved More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    struct {
       uint32_t   ENABLE:1
     bit: 0 Enables the timer. More...
     
       uint32_t   IMASK:1
     bit: 1 Timer output signal mask bit. More...
     
       uint32_t   ISTATUS:1
     bit: 2 The status of the timer. More...
     
    } b
     Structure used for bit access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t CNTP_CTL_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CNTP_CTL_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CNTP_CTL_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CNTP_CTL_Type::ENABLE
    +
    +

    Enables the timer.

    +

    Permitted values are:

    +
      +
    • 0 - Timer disabled.
      • +
    • 1 - Timer enabled.
      • +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CNTP_CTL_Type::IMASK
    +
    +

    Timer output signal mask bit.

    +

    Permitted values are:

    +
      +
    • 0 - Timer output signal is not masked.
      • +
    • 1 - Timer output signal is masked.
      • +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CNTP_CTL_Type::ISTATUS
    +
    +

    The status of the timer.

    +

    This bit indicates whether the timer condition is asserted:

    +
      +
    • 0 - Timer condition is not asserted.
      • +
    • 1 - Timer condition is asserted.
      • +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CNTP_CTL_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionCNTP__CTL__Type.js b/docs/Core_A/html/unionCNTP__CTL__Type.js new file mode 100644 index 0000000..2fef421 --- /dev/null +++ b/docs/Core_A/html/unionCNTP__CTL__Type.js @@ -0,0 +1,10 @@ +var unionCNTP__CTL__Type = +[ + [ "_reserved0", "unionCNTP__CTL__Type.html#a033fc913891068a89b1609af783db8a8", null ], + [ "b", "unionCNTP__CTL__Type.html#acfac7f6bcdcf74d339bea24b437d977e", null ], + [ "b", "unionCNTP__CTL__Type.html#afdd6b14cdb03e4e694ec7db8163916b0", null ], + [ "ENABLE", "unionCNTP__CTL__Type.html#a3b7426f99d1ecdacd172999b4d04b210", null ], + [ "IMASK", "unionCNTP__CTL__Type.html#a07e23afbd292bcb84f15ea27ae2c157d", null ], + [ "ISTATUS", "unionCNTP__CTL__Type.html#acb2f8900c7f6960443df47c1f2f2add3", null ], + [ "w", "unionCNTP__CTL__Type.html#a0e2d443e0447f9b286433220cd288dbf", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionCPACR__Type.html b/docs/Core_A/html/unionCPACR__Type.html new file mode 100644 index 0000000..5d0196d --- /dev/null +++ b/docs/Core_A/html/unionCPACR__Type.html @@ -0,0 +1,431 @@ + + + + + +CPACR_Type Struct Reference +CMSIS-Core (Cortex-A): CPACR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CPACR_Type Struct Reference
    Coprocessor Access Control Register (CPACR)
    +
    +
    + +

    Bit field declaration for CPACR layout. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   CP0:2
     bit: 0..1 Access rights for coprocessor 0 More...
     
       uint32_t   CP1:2
     bit: 2..3 Access rights for coprocessor 1 More...
     
       uint32_t   CP2:2
     bit: 4..5 Access rights for coprocessor 2 More...
     
       uint32_t   CP3:2
     bit: 6..7 Access rights for coprocessor 3 More...
     
       uint32_t   CP4:2
     bit: 8..9 Access rights for coprocessor 4 More...
     
       uint32_t   CP5:2
     bit:10..11 Access rights for coprocessor 5 More...
     
       uint32_t   CP6:2
     bit:12..13 Access rights for coprocessor 6 More...
     
       uint32_t   CP7:2
     bit:14..15 Access rights for coprocessor 7 More...
     
       uint32_t   CP8:2
     bit:16..17 Access rights for coprocessor 8 More...
     
       uint32_t   CP9:2
     bit:18..19 Access rights for coprocessor 9 More...
     
       uint32_t   CP10:2
     bit:20..21 Access rights for coprocessor 10 More...
     
       uint32_t   CP11:2
     bit:22..23 Access rights for coprocessor 11 More...
     
       uint32_t   CP12:2
     bit:24..25 Access rights for coprocessor 11 More...
     
       uint32_t   CP13:2
     bit:26..27 Access rights for coprocessor 11 More...
     
       uint32_t   TRCDIS:1
     bit: 28 Disable CP14 access to trace registers More...
     
       uint32_t   D32DIS:1
     bit: 30 Disable use of registers D16-D31 of the VFP register file More...
     
       uint32_t   ASEDIS:1
     bit: 31 Disable Advanced SIMD Functionality More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t CPACR_Type::ASEDIS
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CPACR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP0
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP1
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP10
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP11
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP12
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP13
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP2
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP3
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP4
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP5
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP6
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP7
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP8
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::CP9
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::D32DIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::TRCDIS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPACR_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionCPACR__Type.js b/docs/Core_A/html/unionCPACR__Type.js new file mode 100644 index 0000000..508905f --- /dev/null +++ b/docs/Core_A/html/unionCPACR__Type.js @@ -0,0 +1,22 @@ +var unionCPACR__Type = +[ + [ "ASEDIS", "unionCPACR__Type.html#a792fabd71db2311eefbc9b896db37986", null ], + [ "b", "unionCPACR__Type.html#a7aa1870fa74e00241618df136e04141f", null ], + [ "CP0", "unionCPACR__Type.html#a1a29bc40d708ac1a43153b11f60b8195", null ], + [ "CP1", "unionCPACR__Type.html#acb2055cdbdf2a6c9b8279dc6f7cbc624", null ], + [ "CP10", "unionCPACR__Type.html#a0275dc6b0eb9f906ebc5c6431b03dc4e", null ], + [ "CP11", "unionCPACR__Type.html#ac54b8897f9358f37e0046b010c334e87", null ], + [ "CP12", "unionCPACR__Type.html#a68d69635225dd479d3035cc51b4c40ce", null ], + [ "CP13", "unionCPACR__Type.html#a45d9be266fc37a6ff9f31c2bef897f90", null ], + [ "CP2", "unionCPACR__Type.html#a2553fcdfd94ffc09407db9da9db9d586", null ], + [ "CP3", "unionCPACR__Type.html#af245b8dabfea0bf7dc06f5d4de7bfa79", null ], + [ "CP4", "unionCPACR__Type.html#a6424b7a81a440217aab8e51e4b623adb", null ], + [ "CP5", "unionCPACR__Type.html#ad5c0b15cd6a01a6f1db398e020809573", null ], + [ "CP6", "unionCPACR__Type.html#ad898cab7c89a07b80068d141ced869e3", null ], + [ "CP7", "unionCPACR__Type.html#a12002991719fb1af7a5db9a73deb323d", null ], + [ "CP8", "unionCPACR__Type.html#a5a6f694264518a813bdbc202ff47664f", null ], + [ "CP9", "unionCPACR__Type.html#a4de69636eb450fcc3f5f3e4a19a869f5", null ], + [ "D32DIS", "unionCPACR__Type.html#a6206695a548b18ce0e2ea5276d1eef1d", null ], + [ "TRCDIS", "unionCPACR__Type.html#ac6f2f67dd0250b9dc9a8271a05655bbe", null ], + [ "w", "unionCPACR__Type.html#ae2d9d724aff1f8f0060738f5d4527c33", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionCPSR__Type.html b/docs/Core_A/html/unionCPSR__Type.html new file mode 100644 index 0000000..b55576f --- /dev/null +++ b/docs/Core_A/html/unionCPSR__Type.html @@ -0,0 +1,401 @@ + + + + + +CPSR_Type Struct Reference +CMSIS-Core (Cortex-A): CPSR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CPSR_Type Struct Reference
    Current Program Status Register (CPSR)
    +
    +
    + +

    Bit field declaration for CPSR layout. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   M:5
     bit: 0.. 4 Mode field More...
     
       uint32_t   T:1
     bit: 5 Thumb execution state bit More...
     
       uint32_t   F:1
     bit: 6 FIQ mask bit More...
     
       uint32_t   I:1
     bit: 7 IRQ mask bit More...
     
       uint32_t   A:1
     bit: 8 Asynchronous abort mask bit More...
     
       uint32_t   E:1
     bit: 9 Endianness execution state bit More...
     
       uint32_t   IT1:6
     bit: 10..15 If-Then execution state bits 2-7 More...
     
       uint32_t   GE:4
     bit: 16..19 Greater than or Equal flags More...
     
       uint32_t   J:1
     bit: 24 Jazelle bit More...
     
       uint32_t   IT0:2
     bit: 25..26 If-Then execution state bits 0-1 More...
     
       uint32_t   Q:1
     bit: 27 Saturation condition flag More...
     
       uint32_t   V:1
     bit: 28 Overflow condition code flag More...
     
       uint32_t   C:1
     bit: 29 Carry condition code flag More...
     
       uint32_t   Z:1
     bit: 30 Zero condition code flag More...
     
       uint32_t   N:1
     bit: 31 Negative condition code flag More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t CPSR_Type::A
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CPSR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::C
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::E
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::F
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::GE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::I
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::IT0
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::IT1
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::J
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::M
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::N
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::Q
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::T
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::V
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CPSR_Type::Z
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionCPSR__Type.js b/docs/Core_A/html/unionCPSR__Type.js new file mode 100644 index 0000000..ac6d17d --- /dev/null +++ b/docs/Core_A/html/unionCPSR__Type.js @@ -0,0 +1,20 @@ +var unionCPSR__Type = +[ + [ "A", "unionCPSR__Type.html#a8dc2435a7c376c9b8dfdd9748c091458", null ], + [ "b", "unionCPSR__Type.html#a2e735da6b6156874d12aaceb2017da06", null ], + [ "C", "unionCPSR__Type.html#aa967d0e42ed00bd886b2c6df6f49a7e2", null ], + [ "E", "unionCPSR__Type.html#a96bd175ed9927279dba40e76259dcfa7", null ], + [ "F", "unionCPSR__Type.html#a20bbf5d5ba32cae380b7f181cf306f9e", null ], + [ "GE", "unionCPSR__Type.html#acc18314a4088adfb93a9662c76073704", null ], + [ "I", "unionCPSR__Type.html#a0d277e8b4d2147137407f526aa9e3214", null ], + [ "IT0", "unionCPSR__Type.html#a5299532c92c92babc22517a433686b95", null ], + [ "IT1", "unionCPSR__Type.html#a8bdd87822e3c00b3742c94a42b0654b9", null ], + [ "J", "unionCPSR__Type.html#a5d4e06d8dba8f512c54b16bfa7150d9d", null ], + [ "M", "unionCPSR__Type.html#a2bc38ab81bc2e2fd111526a58f94511f", null ], + [ "N", "unionCPSR__Type.html#a26907b41c086a9f9e7b8c7051481c643", null ], + [ "Q", "unionCPSR__Type.html#a0bdcd0ceaa1ecb8f55ea15075974eb5a", null ], + [ "T", "unionCPSR__Type.html#ac5ec7329b5be4722abc3cef6ef2e9c1b", null ], + [ "V", "unionCPSR__Type.html#aba74c9da04be21f1266d3816af79f8c3", null ], + [ "w", "unionCPSR__Type.html#afd5ed10bab25f324a6fbb3e124d16fc9", null ], + [ "Z", "unionCPSR__Type.html#a790f1950658257a87ac58d132eca9849", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionDFSR__Type.html b/docs/Core_A/html/unionDFSR__Type.html new file mode 100644 index 0000000..0012948 --- /dev/null +++ b/docs/Core_A/html/unionDFSR__Type.html @@ -0,0 +1,324 @@ + + + + + +DFSR_Type Struct Reference +CMSIS-Core (Cortex-A): DFSR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    DFSR_Type Struct Reference
    Data Fault Status Register (DFSR)
    +
    +
    + +

    Bit field declaration for DFSR layout. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   FS0:4
     bit: 0.. 3 Fault Status bits bit 0-3 More...
     
       uint32_t   Domain:4
     bit: 4.. 7 Fault on which domain More...
     
       uint32_t   LPAE:1
     bit: 9 Large Physical Address Extension More...
     
       uint32_t   FS1:1
     bit: 10 Fault Status bits bit 4 More...
     
       uint32_t   WnR:1
     bit: 11 Write not Read bit More...
     
       uint32_t   ExT:1
     bit: 12 External abort type More...
     
       uint32_t   CM:1
     bit: 13 Cache maintenance fault More...
     
    } s
     Structure used for bit access in short format. More...
     
    struct {
       uint32_t   STATUS:5
     bit: 0.. 5 Fault Status bits More...
     
       uint32_t   LPAE:1
     bit: 9 Large Physical Address Extension More...
     
       uint32_t   WnR:1
     bit: 11 Write not Read bit More...
     
       uint32_t   ExT:1
     bit: 12 External abort type More...
     
       uint32_t   CM:1
     bit: 13 Cache maintenance fault More...
     
    } l
     Structure used for bit access in long format. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t DFSR_Type::CM
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::Domain
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::ExT
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::FS0
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::FS1
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } DFSR_Type::l
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::LPAE
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } DFSR_Type::s
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::STATUS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DFSR_Type::WnR
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionDFSR__Type.js b/docs/Core_A/html/unionDFSR__Type.js new file mode 100644 index 0000000..043d9d3 --- /dev/null +++ b/docs/Core_A/html/unionDFSR__Type.js @@ -0,0 +1,14 @@ +var unionDFSR__Type = +[ + [ "CM", "unionDFSR__Type.html#a38562a26cc210ea4c39c6b951c4a5b62", null ], + [ "Domain", "unionDFSR__Type.html#a38982c7088a4069f8a4b347f5eb400e9", null ], + [ "ExT", "unionDFSR__Type.html#aede34079d030df1977646c155a90f445", null ], + [ "FS0", "unionDFSR__Type.html#af29edf59ecfd29848b69e2bbfb7f3082", null ], + [ "FS1", "unionDFSR__Type.html#a869658f432d5e213b8cd55e8e58d1f56", null ], + [ "l", "unionDFSR__Type.html#a583e3138696be655c46f297e083ece52", null ], + [ "LPAE", "unionDFSR__Type.html#add7c7800b87cabdb4a9ecdf41e4469a7", null ], + [ "s", "unionDFSR__Type.html#a54c2eb668436a0f15d781265ceaa8c58", null ], + [ "STATUS", "unionDFSR__Type.html#a4cb3ba7b8c8075bfbff792b7e5b88103", null ], + [ "w", "unionDFSR__Type.html#ad827a36e38ce2dee796835122ae95dd2", null ], + [ "WnR", "unionDFSR__Type.html#a0512860c27723cd35f0abdaa68be9935", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionIFSR__Type.html b/docs/Core_A/html/unionIFSR__Type.html new file mode 100644 index 0000000..93f7ee3 --- /dev/null +++ b/docs/Core_A/html/unionIFSR__Type.html @@ -0,0 +1,273 @@ + + + + + +IFSR_Type Struct Reference +CMSIS-Core (Cortex-A): IFSR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    IFSR_Type Struct Reference
    Instruction Fault Status Register (IFSR)
    +
    +
    + +

    Bit field declaration for IFSR layout. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   FS0:4
     bit: 0.. 3 Fault Status bits bit 0-3 More...
     
       uint32_t   LPAE:1
     bit: 9 Large Physical Address Extension More...
     
       uint32_t   FS1:1
     bit: 10 Fault Status bits bit 4 More...
     
       uint32_t   ExT:1
     bit: 12 External abort type More...
     
    } s
     Structure used for bit access in short format. More...
     
    struct {
       uint32_t   STATUS:6
     bit: 0.. 5 Fault Status bits More...
     
       uint32_t   LPAE:1
     bit: 9 Large Physical Address Extension More...
     
       uint32_t   ExT:1
     bit: 12 External abort type More...
     
    } l
     Structure used for bit access in long format. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t IFSR_Type::ExT
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IFSR_Type::FS0
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IFSR_Type::FS1
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } IFSR_Type::l
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IFSR_Type::LPAE
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } IFSR_Type::s
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IFSR_Type::STATUS
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IFSR_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionIFSR__Type.js b/docs/Core_A/html/unionIFSR__Type.js new file mode 100644 index 0000000..ed9edb0 --- /dev/null +++ b/docs/Core_A/html/unionIFSR__Type.js @@ -0,0 +1,11 @@ +var unionIFSR__Type = +[ + [ "ExT", "unionIFSR__Type.html#aee6fed7525c5125e637acc8e957c8d0f", null ], + [ "FS0", "unionIFSR__Type.html#a9f9ae1ffa89d33e90159eec5c4b7cd6a", null ], + [ "FS1", "unionIFSR__Type.html#adb493acf17881eaf09a2e8629ee2243e", null ], + [ "l", "unionIFSR__Type.html#a8f4e4fe46a9cb9b6c8a6355f9b0938e3", null ], + [ "LPAE", "unionIFSR__Type.html#a40c5236caf0549cc1cc78945b0b0f131", null ], + [ "s", "unionIFSR__Type.html#a4ece60d66e87e10e78aab83ac05e957c", null ], + [ "STATUS", "unionIFSR__Type.html#a543066fc60d5b63478cc85ba082524d4", null ], + [ "w", "unionIFSR__Type.html#ae31262477d14b86f30c3bef90a3fc371", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionISR__Type.html b/docs/Core_A/html/unionISR__Type.html new file mode 100644 index 0000000..9b2e319 --- /dev/null +++ b/docs/Core_A/html/unionISR__Type.html @@ -0,0 +1,221 @@ + + + + + +ISR_Type Struct Reference +CMSIS-Core (Cortex-A): ISR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    ISR_Type Struct Reference
    Interrupt Status Register (ISR)
    +
    +
    + +

    Bit field declaration for ISR layout. +

    + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   F:1
     bit: 6 FIQ pending bit More...
     
       uint32_t   I:1
     bit: 7 IRQ pending bit More...
     
       uint32_t   A:1
     bit: 8 External abort pending bit More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t ISR_Type::A
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } ISR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ISR_Type::F
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ISR_Type::I
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ISR_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionISR__Type.js b/docs/Core_A/html/unionISR__Type.js new file mode 100644 index 0000000..09170d9 --- /dev/null +++ b/docs/Core_A/html/unionISR__Type.js @@ -0,0 +1,8 @@ +var unionISR__Type = +[ + [ "A", "unionISR__Type.html#ad4dfcb37f30162fd57c4402ae99ca49e", null ], + [ "b", "unionISR__Type.html#ad01f116d61c2ae79c2469a38a0b2f497", null ], + [ "F", "unionISR__Type.html#ae691a856f7de0f301c60521a7a779dc2", null ], + [ "I", "unionISR__Type.html#ad83ba976f1764c7d3a7954c073c39c22", null ], + [ "w", "unionISR__Type.html#a4fca9c1057aa8a6006f1fb631a28ee30", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/unionSCTLR__Type.html b/docs/Core_A/html/unionSCTLR__Type.html new file mode 100644 index 0000000..38270e8 --- /dev/null +++ b/docs/Core_A/html/unionSCTLR__Type.html @@ -0,0 +1,491 @@ + + + + + +SCTLR_Type Struct Reference +CMSIS-Core (Cortex-A): SCTLR_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
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      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
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    + +
    + +
    +
    +Data Fields
    +
    +
    SCTLR_Type Struct Reference
    System Control Register (SCTLR)
    +
    +
    + +

    Bit field declaration for SCTLR layout. +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   M:1
     bit: 0 MMU enable More...
     
       uint32_t   A:1
     bit: 1 Alignment check enable More...
     
       uint32_t   C:1
     bit: 2 Cache enable More...
     
       uint32_t   CP15BEN:1
     bit: 5 CP15 barrier enable More...
     
       uint32_t   B:1
     bit: 7 Endianness model More...
     
       uint32_t   SW:1
     bit: 10 SWP and SWPB enable More...
     
       uint32_t   Z:1
     bit: 11 Branch prediction enable More...
     
       uint32_t   I:1
     bit: 12 Instruction cache enable More...
     
       uint32_t   V:1
     bit: 13 Vectors bit More...
     
       uint32_t   RR:1
     bit: 14 Round Robin select More...
     
       uint32_t   HA:1
     bit: 17 Hardware Access flag enable More...
     
       uint32_t   WXN:1
     bit: 19 Write permission implies XN More...
     
       uint32_t   UWXN:1
     bit: 20 Unprivileged write permission implies PL1 XN More...
     
       uint32_t   FI:1
     bit: 21 Fast interrupts configuration enable More...
     
       uint32_t   U:1
     bit: 22 Alignment model More...
     
       uint32_t   VE:1
     bit: 24 Interrupt Vectors Enable More...
     
       uint32_t   EE:1
     bit: 25 Exception Endianness More...
     
       uint32_t   NMFI:1
     bit: 27 Non-maskable FIQ (NMFI) support More...
     
       uint32_t   TRE:1
     bit: 28 TEX remap enable. More...
     
       uint32_t   AFE:1
     bit: 29 Access flag enable More...
     
       uint32_t   TE:1
     bit: 30 Thumb Exception enable More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t SCTLR_Type::A
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::AFE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::B
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } SCTLR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::C
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::CP15BEN
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::EE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::FI
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::HA
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::I
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::M
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::NMFI
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::RR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::SW
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::TE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::TRE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::U
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::UWXN
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::V
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::VE
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::WXN
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCTLR_Type::Z
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core_A/html/unionSCTLR__Type.js b/docs/Core_A/html/unionSCTLR__Type.js new file mode 100644 index 0000000..4df4fd7 --- /dev/null +++ b/docs/Core_A/html/unionSCTLR__Type.js @@ -0,0 +1,26 @@ +var unionSCTLR__Type = +[ + [ "A", "unionSCTLR__Type.html#a078edcb9c3fc8b46b8cf382ad249bb79", null ], + [ "AFE", "unionSCTLR__Type.html#ae5a729bf64a6de4cbfa42c1a7d254535", null ], + [ "B", "unionSCTLR__Type.html#a805ee3324a333d7a77d9f0d8f0fac9a7", null ], + [ "b", "unionSCTLR__Type.html#a21ec59a37644281456a5f607450951d8", null ], + [ "C", "unionSCTLR__Type.html#a122a4dde5ab1a27855ddad88bb3f9f78", null ], + [ "CP15BEN", "unionSCTLR__Type.html#a98b55213f3bf0a8bd4f1db90512238de", null ], + [ "EE", "unionSCTLR__Type.html#af868e042d01b612649539c151f1aaea5", null ], + [ "FI", "unionSCTLR__Type.html#afe77b6c5d73e64d4ef3c5dc5ce2692dc", null ], + [ "HA", "unionSCTLR__Type.html#aba2a8aac3478cdc34428af7b9726d97f", null ], + [ "I", "unionSCTLR__Type.html#a0a4ed1a41f25a191cf4a500401c3c5db", null ], + [ "M", "unionSCTLR__Type.html#a8cbfde3ba235ebd48e82cb314c9b9cc4", null ], + [ "NMFI", "unionSCTLR__Type.html#a60d589567422115a14d6d0fde342dfce", null ], + [ "RR", "unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055", null ], + [ "SW", "unionSCTLR__Type.html#a6598f817304ccaef4509843ce041de1c", null ], + [ "TE", "unionSCTLR__Type.html#a25d4c4cf4df168a30cc4600a130580ab", null ], + [ "TRE", "unionSCTLR__Type.html#abc3055203ce7f9d117ceb10f146722f3", null ], + [ "U", "unionSCTLR__Type.html#a1ca6569db52bca6250afbbd565d05449", null ], + [ "UWXN", "unionSCTLR__Type.html#a32873e90e6814c3a2fc1b1c79c0bc8c8", null ], + [ "V", "unionSCTLR__Type.html#a9a3885d0e2ba2433d128f62ec2552a00", null ], + [ "VE", "unionSCTLR__Type.html#af29c170c65dd4d076b78c793dc17aa0a", null ], + [ "w", "unionSCTLR__Type.html#a4cb084e09742794f1d040c4e44ee4e0f", null ], + [ "WXN", "unionSCTLR__Type.html#a551d0505856acaef4dd1ecca54cb540d", null ], + [ "Z", "unionSCTLR__Type.html#a37f6910db32361f44a268f93b9ff7b20", null ] +]; \ No newline at end of file diff --git a/docs/Core_A/html/using_ARM_pg.html b/docs/Core_A/html/using_ARM_pg.html new file mode 100644 index 0000000..537ab72 --- /dev/null +++ b/docs/Core_A/html/using_ARM_pg.html @@ -0,0 +1,140 @@ + + + + + +Using CMSIS with generic Arm Processors +CMSIS-Core (Cortex-A): Using CMSIS with generic Arm Processors + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Using CMSIS with generic Arm Processors
    +
    +
    +

    Arm provides CMSIS-Core-A files for the supported Arm Processors and for various compiler vendors. These files can be used when standard Arm processors should be used in a project. The table below lists the folder and device names of the Arm processors.

    + + + + + + + + + +
    Folder Processor Description
    ".\Device\ARM\ARMCA5" Cortex-A5 Contains Include and Source template files configured for the Cortex-A5 processor. The device name is ARMCA5 and the name of the Device Header File <device.h> is <ARMCA5.h>.
    ".\Device\ARM\ARMCA7" Cortex-A7 Contains Include and Source template files configured for the Cortex-A7 processor. The device name is ARMCA7 and the name of the Device Header File <device.h> is <ARMCA7.h>.
    ".\Device\ARM\ARMCA9" Cortex-A9 Contains Include and Source template files configured for the Cortex-A9 processor. The device name is ARMCA9 and the name of the Device Header File <device.h> is <ARMCA9.h>.
    +
    +
    + + + + diff --git a/docs/Core_A/html/using_CMSIS.html b/docs/Core_A/html/using_CMSIS.html new file mode 100644 index 0000000..397e885 --- /dev/null +++ b/docs/Core_A/html/using_CMSIS.html @@ -0,0 +1,185 @@ + + + + + +Basic CMSIS Example +CMSIS-Core (Cortex-A): Basic CMSIS Example + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
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    + +
    + + + + +
    + +
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    +
    +
    Basic CMSIS Example
    +
    +
    +

    A typical example for using the CMSIS layer is provided below. The example is based on an unspecific Cortex-A9 Device.

    +
    #include <ARMCA9.h> // File name depends on device used
    +
    +
    static const uint32_t TICK_RATE_HZ = 1000U;
    +
    +
    uint32_t volatile msTicks; // Counter for millisecond Interval
    +
    +
    static void SysTick_Handler( void )
    +
    {
    +
    msTicks++; // Increment Counter
    +
    }
    +
    +
    // We use the Private Tiemer (PTIM) of the Cortex-A9 FVP Model here.
    +
    // In general the available Timers are highly vendor specific for Cortex-A processors.
    +
    void private_timer_init(void) {
    +
    +
    PTIM_SetLoadValue ((SystemCoreClock/TICK_RATE_HZ) - 1U);
    +
    PTIM_SetControl (PTIM_GetControl() | 7U);
    +
    +
    /* Install SysTick_Handler as the interrupt function for PTIM */
    +
    IRQ_SetHandler((IRQn_ID_t)PrivTimer_IRQn, SysTick_Handler);
    +
    +
    /* Determine number of implemented priority bits */
    +
    IRQ_SetPriority ((IRQn_ID_t)PrivTimer_IRQn, IRQ_PRIORITY_Msk);
    +
    +
    /* Set lowest priority -1 */
    +
    IRQ_SetPriority ((IRQn_ID_t)PrivTimer_IRQn, GIC_GetPriority((IRQn_ID_t)PrivTimer_IRQn)-1);
    +
    +
    /* Enable IRQ */
    +
    IRQ_Enable ((IRQn_ID_t)PrivTimer_IRQn);
    +
    }
    +
    +
    /* Delay execution for given amount of ticks */
    +
    void Delay(uint32_t ticks) {
    +
    uint32_t tgtTicks = msTicks + ticks; // target tick count to delay execution to
    +
    while (msTicks == tgtTicks) {
    +
    __WFE (); // Power-Down until next Event/Interrupt
    +
    }
    +
    }
    +
    +
    /* main function */
    +
    int main(void)
    +
    {
    +
    /* Initialize device HAL here */
    +
    private_timer_init();
    +
    +
    static uint8_t ledState = 0;
    +
    +
    /* Infinite loop */
    +
    while (1)
    +
    {
    +
    /* Add application code here */
    +
    ledState = !ledState;
    +
    Delay(500);
    +
    }
    +
    }
    +
    +
    + + + + diff --git a/docs/Core_A/html/using_pg.html b/docs/Core_A/html/using_pg.html new file mode 100644 index 0000000..f406fef --- /dev/null +++ b/docs/Core_A/html/using_pg.html @@ -0,0 +1,165 @@ + + + + + +Using CMSIS in Embedded Applications +CMSIS-Core (Cortex-A): Using CMSIS in Embedded Applications + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-A) +  Version 1.1.2 +
    +
    CMSIS-Core support for Cortex-A processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
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    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Using CMSIS in Embedded Applications
    +
    +
    +

    To use the CMSIS-Core-A the following files are added to the embedded application:

    + +
    Note
    The files Startup File startup_<device>.c, System Configuration Files system_<device>.c and system_<device>.h, Memory Configuration Files mem_<device>.h, and Memory Management Unit Files mmu_<device>.c may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
    +

    The Reset_Handler defined in Startup File startup_<device>.c is executed after reset. The default initialization sequence is

    + +

    After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.c contains a weak default handler implementation for every exception. It may also contain stack and heap configurations for the user application.

    +

    The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock and the initialization of memory caches, memory management unit, generic interrupt interface and floating point unit. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory bus setup and clock re-configuration.

    +

    The Device Header File <device.h> is the central include file that the application programmer is using in the C/C++ source code. It provides the following features:

    +
      +
    • Peripheral Access provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.
      • +
    • Generic Interrupt Controller Functions can be accessed with standardized symbols and functions for the General Interrupt Controller (GIC) are provided.
      • +
    • Intrinsic Functions allow to access special instructions, for example for activating sleep mode or the NOP instruction.
      • +
    • Generic and Private Timer functions to configure and start a periodic timer interrupt.
      • +
    • Level 1 and Level 2 Cache controller functions to enable, disable, clean and invalidate caches.
      • +
    +
    +CMSIS_CORE_A_Files_user.png +
    +CMSIS-Core-A User Files
    +

    The CMSIS-Core-A user files are device specific. In addition, the Startup File startup_<device>.c is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.

    +
    Note
    The silicon vendors create these device-specific CMSIS-Core-A files based on CMSIS-Core Device Templates provide by Arm.
    +

    Thereafter, the functions described under Reference can be used in the application.

    +

    Examples

    + +
    +
    + + + + diff --git a/docs/Core_A/html/using_pg.js b/docs/Core_A/html/using_pg.js new file mode 100644 index 0000000..0b8245b --- /dev/null +++ b/docs/Core_A/html/using_pg.js @@ -0,0 +1,5 @@ +var using_pg = +[ + [ "Basic CMSIS Example", "using_CMSIS.html", null ], + [ "Using CMSIS with generic Arm Processors", "using_ARM_pg.html", null ] +]; \ No newline at end of file -- cgit