From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- docs/Core_A/html/using_pg.html | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'docs/Core_A/html/using_pg.html') diff --git a/docs/Core_A/html/using_pg.html b/docs/Core_A/html/using_pg.html index f406fef..3c7a7e6 100644 --- a/docs/Core_A/html/using_pg.html +++ b/docs/Core_A/html/using_pg.html @@ -32,7 +32,7 @@ Logo
CMSIS-Core (Cortex-A) -  Version 1.1.2 +  Version 1.1.4
CMSIS-Core support for Cortex-A processor-based devices
@@ -124,7 +124,7 @@ $(document).ready(function(){initNavTree('using_pg.html','');});

After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.c contains a weak default handler implementation for every exception. It may also contain stack and heap configurations for the user application.

The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock and the initialization of memory caches, memory management unit, generic interrupt interface and floating point unit. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory bus setup and clock re-configuration.

@@ -136,6 +136,7 @@ $(document).ready(function(){initNavTree('using_pg.html','');});
  • Generic and Private Timer functions to configure and start a periodic timer interrupt.
  • Level 1 and Level 2 Cache controller functions to enable, disable, clean and invalidate caches.
    • +

    CMSIS-Pack provides the #define CMSIS_header_file in RTE_Components.h which gives you access to this device.h file.

    CMSIS_CORE_A_Files_user.png
    @@ -153,7 +154,7 @@ CMSIS-Core-A User Files