From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/unionSCTLR__Type.html | 491 +++++++++++++++++++++++++++++++++ 1 file changed, 491 insertions(+) create mode 100644 docs/Core_A/html/unionSCTLR__Type.html (limited to 'docs/Core_A/html/unionSCTLR__Type.html') diff --git a/docs/Core_A/html/unionSCTLR__Type.html b/docs/Core_A/html/unionSCTLR__Type.html new file mode 100644 index 0000000..38270e8 --- /dev/null +++ b/docs/Core_A/html/unionSCTLR__Type.html @@ -0,0 +1,491 @@ + + + + + +SCTLR_Type Struct Reference +CMSIS-Core (Cortex-A): SCTLR_Type Struct Reference + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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SCTLR_Type Struct Reference
System Control Register (SCTLR)
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Bit field declaration for SCTLR layout. +

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struct {
   uint32_t   M:1
 bit: 0 MMU enable More...
 
   uint32_t   A:1
 bit: 1 Alignment check enable More...
 
   uint32_t   C:1
 bit: 2 Cache enable More...
 
   uint32_t   CP15BEN:1
 bit: 5 CP15 barrier enable More...
 
   uint32_t   B:1
 bit: 7 Endianness model More...
 
   uint32_t   SW:1
 bit: 10 SWP and SWPB enable More...
 
   uint32_t   Z:1
 bit: 11 Branch prediction enable More...
 
   uint32_t   I:1
 bit: 12 Instruction cache enable More...
 
   uint32_t   V:1
 bit: 13 Vectors bit More...
 
   uint32_t   RR:1
 bit: 14 Round Robin select More...
 
   uint32_t   HA:1
 bit: 17 Hardware Access flag enable More...
 
   uint32_t   WXN:1
 bit: 19 Write permission implies XN More...
 
   uint32_t   UWXN:1
 bit: 20 Unprivileged write permission implies PL1 XN More...
 
   uint32_t   FI:1
 bit: 21 Fast interrupts configuration enable More...
 
   uint32_t   U:1
 bit: 22 Alignment model More...
 
   uint32_t   VE:1
 bit: 24 Interrupt Vectors Enable More...
 
   uint32_t   EE:1
 bit: 25 Exception Endianness More...
 
   uint32_t   NMFI:1
 bit: 27 Non-maskable FIQ (NMFI) support More...
 
   uint32_t   TRE:1
 bit: 28 TEX remap enable. More...
 
   uint32_t   AFE:1
 bit: 29 Access flag enable More...
 
   uint32_t   TE:1
 bit: 30 Thumb Exception enable More...
 
} b
 Structure used for bit access. More...
 
uint32_t w
 Type used for word access. More...
 
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Field Documentation

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uint32_t SCTLR_Type::A
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uint32_t SCTLR_Type::AFE
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uint32_t SCTLR_Type::B
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struct { ... } SCTLR_Type::b
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uint32_t SCTLR_Type::C
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uint32_t SCTLR_Type::CP15BEN
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uint32_t SCTLR_Type::EE
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uint32_t SCTLR_Type::FI
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uint32_t SCTLR_Type::HA
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uint32_t SCTLR_Type::I
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uint32_t SCTLR_Type::M
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uint32_t SCTLR_Type::NMFI
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uint32_t SCTLR_Type::RR
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uint32_t SCTLR_Type::SW
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uint32_t SCTLR_Type::TE
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uint32_t SCTLR_Type::TRE
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uint32_t SCTLR_Type::U
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uint32_t SCTLR_Type::UWXN
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uint32_t SCTLR_Type::V
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uint32_t SCTLR_Type::VE
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uint32_t SCTLR_Type::w
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uint32_t SCTLR_Type::WXN
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uint32_t SCTLR_Type::Z
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