From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/structGICDistributor__Type.html | 822 +++++++++++++++++++++++ 1 file changed, 822 insertions(+) create mode 100644 docs/Core_A/html/structGICDistributor__Type.html (limited to 'docs/Core_A/html/structGICDistributor__Type.html') diff --git a/docs/Core_A/html/structGICDistributor__Type.html b/docs/Core_A/html/structGICDistributor__Type.html new file mode 100644 index 0000000..55d6f67 --- /dev/null +++ b/docs/Core_A/html/structGICDistributor__Type.html @@ -0,0 +1,822 @@ + + + + + +GICDistributor_Type Struct Reference +CMSIS-Core (Cortex-A): GICDistributor_Type Struct Reference + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+Data Fields
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GICDistributor_Type Struct Reference
Generic Interrupt Controller Functions
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Structure type to access the Generic Interrupt Controller Distributor (GICD) +

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__IOM uint32_t CTLR
 Offset: 0x000 (R/W) Distributor Control Register. More...
 
__IM uint32_t TYPER
 Offset: 0x004 (R/ ) Interrupt Controller Type Register. More...
 
__IM uint32_t IIDR
 Offset: 0x008 (R/ ) Distributor Implementer Identification Register. More...
 
__IOM uint32_t STATUSR
 Offset: 0x010 (R/W) Error Reporting Status Register, optional. More...
 
__OM uint32_t SETSPI_NSR
 Offset: 0x040 ( /W) Set SPI Register. More...
 
__OM uint32_t CLRSPI_NSR
 Offset: 0x048 ( /W) Clear SPI Register. More...
 
__OM uint32_t SETSPI_SR
 Offset: 0x050 ( /W) Set SPI, Secure Register. More...
 
__OM uint32_t CLRSPI_SR
 Offset: 0x058 ( /W) Clear SPI, Secure Register. More...
 
__IOM uint32_t IGROUPR [32]
 Offset: 0x080 (R/W) Interrupt Group Registers. More...
 
__IOM uint32_t ISENABLER [32]
 Offset: 0x100 (R/W) Interrupt Set-Enable Registers. More...
 
__IOM uint32_t ICENABLER [32]
 Offset: 0x180 (R/W) Interrupt Clear-Enable Registers. More...
 
__IOM uint32_t ISPENDR [32]
 Offset: 0x200 (R/W) Interrupt Set-Pending Registers. More...
 
__IOM uint32_t ICPENDR [32]
 Offset: 0x280 (R/W) Interrupt Clear-Pending Registers. More...
 
__IOM uint32_t ISACTIVER [32]
 Offset: 0x300 (R/W) Interrupt Set-Active Registers. More...
 
__IOM uint32_t ICACTIVER [32]
 Offset: 0x380 (R/W) Interrupt Clear-Active Registers. More...
 
__IOM uint32_t IPRIORITYR [255]
 Offset: 0x400 (R/W) Interrupt Priority Registers. More...
 
__IOM uint32_t ITARGETSR [255]
 Offset: 0x800 (R/W) Interrupt Targets Registers. More...
 
__IOM uint32_t ICFGR [64]
 Offset: 0xC00 (R/W) Interrupt Configuration Registers. More...
 
__IOM uint32_t IGRPMODR [32]
 Offset: 0xD00 (R/W) Interrupt Group Modifier Registers. More...
 
__IOM uint32_t NSACR [64]
 Offset: 0xE00 (R/W) Non-secure Access Control Registers. More...
 
__OM uint32_t SGIR
 Offset: 0xF00 ( /W) Software Generated Interrupt Register. More...
 
__IOM uint32_t CPENDSGIR [4]
 Offset: 0xF10 (R/W) SGI Clear-Pending Registers. More...
 
__IOM uint32_t SPENDSGIR [4]
 Offset: 0xF20 (R/W) SGI Set-Pending Registers. More...
 
__IOM uint64_t IROUTER [988]
 Offset: 0x6100(R/W) Interrupt Routing Registers. More...
 
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Field Documentation

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__IO uint32_t GICDistributor_Type::CLRSPI_NSR
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Clear Non-secure SPI Pending Register

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Bits Name Function
[31:10] - Reserved.
[9:0] INTID The interrupt number to clear pending state from.
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__IO uint32_t GICDistributor_Type::CLRSPI_SR
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Clear Secure SPI Pending Register

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Bits Name Function
[31:10] - Reserved.
[9:0] INTID The interrupt number to clear pending state from.
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__IOM uint8_t GICDistributor_Type::CPENDSGIR[16]
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SGI Clear-Pending Registers Each register corresponds to one software generated interrupt (SGI).

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Reading from this register reveals

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  • 0 - interrupt is not pending
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  • 1 - interrupt is pending
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Writing to this register causes

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  • 0 - no effect
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  • 1 - removes the pending state
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__IOM uint32_t GICDistributor_Type::CTLR
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Distributor Control Register

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When access is Secure, in a system that supports two Security states:

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Bits Name Function
[31] RWP Indicates whether a register write is in progress or not.
[30:8] - Reserved.
[7] EINWF Enable 1 of N Wakeup Functionality, if available.
[6] DS Disable Security.
[5] ARE_NS Affinity Routing Enable, Non-secure state.
[4] ARE_S Affinity Routing Enable, Secure state.
[3] - Reserved.
[2] EnableGrp1S Enable Secure Group 1 interrupts.
[1] EnableGrp1NS Enable Non-secure Group 1 interrupts.
[0] EnableGrp0 Enable Group 0 interrupts.
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When access is Non-secure, in a system that supports two Security states:

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Bits Name Function
[31] RWP Indicates whether a register write is in progress or not.
[30:5] - Reserved.
[4] ARE_NS Affinity Routing Enable, Non-secure state.
[3:2] - Reserved.
[1] EnableGrp1A Enable Non-secure Group 1 interrupts.
[0] EnableGrp1 Enable Non-secure Group 1 interrupts.
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When in a system that supports only a single Security state:

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Bits Name Function
[31] RWP Indicates whether a register write is in progress or not.
[30:8] - Reserved.
[7] EINWF Enable 1 of N Wakeup Functionality, if available.
[6] DS Disable Security.
[5] - Reserved.
[4] ARE Affinity Routing Enable.
[3:2] - Reserved.
[1] EnableGrp1 Enable Group 1 interrupts.
[0] EnableGrp0 Enable Group 0 interrupts.
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__IOM uint32_t GICDistributor_Type::ICACTIVER[32]
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Interrupt Clear-Active Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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Note
Bits corresponding to unimplemented interrupts are RAZ/WI.
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__IOM uint32_t GICDistributor_Type::ICENABLER[32]
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Interrupt Clear-Enable Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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Note
Bits corresponding to unimplemented interrupts are RAZ/WI.
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__IOM uint32_t GICDistributor_Type::ICFGR[64]
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Interrupt Configuration Registers

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Each interrupt can be configured by two corresponding bits:

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Bits Name Function
[2*INTID%16+1] Edge Interrupt is: 0 - level sensitive, 1 - edge triggered
[2*INTID%16] Model 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported
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__IOM uint32_t GICDistributor_Type::ICPENDR[32]
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Interrupt Clear-Pending Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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Bits corresponding to unimplemented interrupts are RAZ/WI.
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__IOM uint32_t GICDistributor_Type::IGROUPR[32]
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Interrupt Group Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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And the value denotes:

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  • 0 When CTLR.DS==1, the corresponding interrupt is Group 0
    + When CTLR.DS==0, the corresponding interrupt is Secure.
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  • 1 When CTLR.DS==1, the corresponding interrupt is Group 1.
    + When CTLR.DS==0, the corresponding interrupt is Non-secure Group 1.
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__IOM uint32_t GICDistributor_Type::IGRPMODR[32]
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Interrupt Group Modifier Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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__IM uint32_t GICDistributor_Type::IIDR
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Distributor Implementer Identification Register

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Bits Name Function
[31:24] ProductID An IMPLEMENTATION DEFINED product identifier
[23:20] - Reserved.
[19:16] Variant An IMPLEMENTATION DEFINED variant number.
[15:12] Revision An IMPLEMENTATION DEFINED revision number.
[11:0] Implementer Contains the JEP106 code of the company implemented the GICD.
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__IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]
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Interrupt Priority Registers

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A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI.

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Note
A register field corresponding to an unimplemented interrupt is RAZ/WI.
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__IOM uint64_t GICDistributor_Type::IROUTER[988]
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Interrupt Routing Registers

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Bits Name Function
[63:40] - Reserved.
[39:32] Aff3 Affinity level 3, the least significant affinity level field.
[31] IRM Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy.
[30:24] - Reserved.
[23:16] Aff2 Affinity level 2, an intermediate affinity level field.
[15:8] Aff1 Affinity level 1, an intermediate affinity level field.
[7:0] Aff0 Affinity level 0, the most significant affinity level field.
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__IOM uint32_t GICDistributor_Type::ISACTIVER[32]
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Interrupt Set-Active Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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Bits corresponding to unimplemented interrupts are RAZ/WI.
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__IOM uint32_t GICDistributor_Type::ISENABLER[32]
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Interrupt Set-Enable Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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__IOM uint32_t GICDistributor_Type::ISPENDR[32]
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Interrupt Set-Pending Registers

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Each bit corresponds to one interrupt:

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  • Register index is given by INTID/32
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  • Bit number is given by INTID%32
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__IOM uint8_t GICDistributor_Type::ITARGETSR[1020]
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Interrupt Processor Targets Registers

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Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI.

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CPU target field value Interrupt targets
0bxxxxxxx1 CPU interface 0
0bxxxxxx1x CPU interface 1
0bxxxxx1xx CPU interface 2
0bxxxx1xxx CPU interface 3
0bxxx1xxxx CPU interface 4
0bxx1xxxxx CPU interface 5
0bx1xxxxxx CPU interface 6
0b1xxxxxxx CPU interface 7
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__IOM uint32_t GICDistributor_Type::NSACR[64]
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Non-secure Access Control Registers

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Each two bits corresponds to one interrupt:

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  • Register index is given by INTID/16
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  • Bit number is given by 2*INTID%16
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The possible values of each 2-bit field are:

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  • 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.
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  • 01 - Non-secure accesses are only permitted to requesting fields.
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  • 10 - As 01, additionally accesses to clearing field are permitted.
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  • 11 - As 10, additionally accesses to target and routing fields are permitted.
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__IO uint32_t GICDistributor_Type::SETSPI_NSR
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Set Non-secure SPI Pending Register

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Bits Name Function
[31:10] - Reserved.
[9:0] INTID The interrupt number to set pending state for.
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__IO uint32_t GICDistributor_Type::SETSPI_SR
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Set Secure SPI Pending Register

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Bits Name Function
[31:10] - Reserved.
[9:0] INTID The interrupt number to set pending state for.
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__OM uint32_t GICDistributor_Type::SGIR
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Software Generated Interrupt Register

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Bits Name Function
[31:26] - Reserved.
[25:24] TargetFilterList Determines how the Distributor processes the requested SGI.
[23:16] CPUTargetList When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt.
[15] NSATT Specifies the required group of the SGI.
[14:4] - Reserved.
[3:0] INTID The INTID of the SGI to forward to the specified CPU interfaces.
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Refer to ITARGETSR for details on TargetFilterList field.

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__IOM uint8_t GICDistributor_Type::SPENDSGIR[16]
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SGI Set-Pending Registers Each register corresponds to one software generated interrupt (SGI).

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Reading from this register reveals

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  • 0 - interrupt is not pending
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  • 1 - interrupt is pending
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Writing to this register causes

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  • 0 - no effect
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  • 1 - adds the pending state
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__IOM uint32_t GICDistributor_Type::STATUSR
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Error Reporting Status Register

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Bits Name Function
[31:4] - Reserved.
[3] WROD Write to an RO location.
[2] RWOD Read of a WO location.
[1] WRD Write to a reserved location.
[0] RRD Read of a reserved location.
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__IM uint32_t GICDistributor_Type::TYPER
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Interrupt Controller Type Register

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Bits Name Function
[31:16] - Reserved.
[15:11] LSPI Maximum number of lockable shared interrupts.
[10] SecurityExtn Security Extensions: 0 - not implemented. 1 - implemented.
[9:8] - Reserved.
[7:5] CPUNumber Number of implemented CPU interfaces [=CPUNumber+1]
[4:0] ITLinesNumber Maximum number of interrups supported [=32*(ITLinesNumber+1)].
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