From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/search/variables_12.js | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 docs/Core_A/html/search/variables_12.js (limited to 'docs/Core_A/html/search/variables_12.js') diff --git a/docs/Core_A/html/search/variables_12.js b/docs/Core_A/html/search/variables_12.js new file mode 100644 index 0000000..94fd92e --- /dev/null +++ b/docs/Core_A/html/search/variables_12.js @@ -0,0 +1,15 @@ +var searchData= +[ + ['s',['s',['../unionDFSR__Type.html#a54c2eb668436a0f15d781265ceaa8c58',1,'DFSR_Type::s()'],['../unionIFSR__Type.html#a4ece60d66e87e10e78aab83ac05e957c',1,'IFSR_Type::s()']]], + ['sec_5ft',['sec_t',['../structmmu__region__attributes__Type.html#a195e022fa08ec703937fa8175d8371d7',1,'mmu_region_attributes_Type']]], + ['setspi_5fnsr',['SETSPI_NSR',['../structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25',1,'GICDistributor_Type']]], + ['setspi_5fsr',['SETSPI_SR',['../structGICDistributor__Type.html#ad55a8644bc95caf8bf53e1407ec9ed0c',1,'GICDistributor_Type']]], + ['sgir',['SGIR',['../structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1',1,'GICDistributor_Type']]], + ['sh_5ft',['sh_t',['../structmmu__region__attributes__Type.html#ad1962a36e3bf13dfb89bc76862097ed5',1,'mmu_region_attributes_Type']]], + ['smp',['SMP',['../unionACTLR__Type.html#afa360e0c6bf79094d72bc78fac300149',1,'ACTLR_Type']]], + ['spendsgir',['SPENDSGIR',['../structGICDistributor__Type.html#ae40b4a50d9766c2bbf57441f68094f41',1,'GICDistributor_Type']]], + ['status',['STATUS',['../unionDFSR__Type.html#a4cb3ba7b8c8075bfbff792b7e5b88103',1,'DFSR_Type::STATUS()'],['../unionIFSR__Type.html#a543066fc60d5b63478cc85ba082524d4',1,'IFSR_Type::STATUS()']]], + ['statusr',['STATUSR',['../structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2',1,'GICDistributor_Type::STATUSR()'],['../structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e',1,'GICInterface_Type::STATUSR()']]], + ['sw',['SW',['../unionSCTLR__Type.html#a6598f817304ccaef4509843ce041de1c',1,'SCTLR_Type']]], + ['systemcoreclock',['SystemCoreClock',['../group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6',1,'SystemCoreClock(): Ref_SystemAndClock.txt'],['../group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6',1,'SystemCoreClock(): Ref_SystemAndClock.txt']]] +]; -- cgit