From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/search/groups_1.js | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 docs/Core_A/html/search/groups_1.js (limited to 'docs/Core_A/html/search/groups_1.js') diff --git a/docs/Core_A/html/search/groups_1.js b/docs/Core_A/html/search/groups_1.js new file mode 100644 index 0000000..96c2513 --- /dev/null +++ b/docs/Core_A/html/search/groups_1.js @@ -0,0 +1,16 @@ +var searchData= +[ + ['configuration_20base_20address_20register_20_28cbar_29',['Configuration Base Address Register (CBAR)',['../group__CMSIS__CBAR.html',1,'']]], + ['cbar_20bits',['CBAR Bits',['../group__CMSIS__CBAR__BITS.html',1,'']]], + ['cache_20and_20branch_20predictor_20maintenance_20operations',['Cache and branch predictor maintenance operations',['../group__CMSIS__CBPM.html',1,'']]], + ['counter_20frequency_20register_20_28cntfrq_29',['Counter Frequency register (CNTFRQ)',['../group__CMSIS__CNTFRQ.html',1,'']]], + ['core_20peripherals',['Core Peripherals',['../group__CMSIS__Core__FunctionInterface.html',1,'']]], + ['core_20register_20access',['Core Register Access',['../group__CMSIS__core__register.html',1,'']]], + ['coprocessor_20access_20control_20register_20_28cpacr_29',['Coprocessor Access Control Register (CPACR)',['../group__CMSIS__CPACR.html',1,'']]], + ['cpacr_20bits',['CPACR Bits',['../group__CMSIS__CPACR__BITS.html',1,'']]], + ['cpacr_20cp_20field_20values',['CPACR CP field values',['../group__CMSIS__CPACR__CP.html',1,'']]], + ['current_20program_20status_20register_20_28cpsr_29',['Current Program Status Register (CPSR)',['../group__CMSIS__CPSR.html',1,'']]], + ['cpsr_20bits',['CPSR Bits',['../group__CMSIS__CPSR__BITS.html',1,'']]], + ['cpsr_20m_20field_20values',['CPSR M field values',['../group__CMSIS__CPSR__M.html',1,'']]], + ['compiler_20control',['Compiler Control',['../group__comp__cntrl__gr.html',1,'']]] +]; -- cgit