From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001
From: Ali Labbene <ali.labbene@st.com>
Date: Wed, 11 Dec 2019 08:59:21 +0100
Subject: Official ARM version: v5.4.0

    Add CMSIS V5.4.0, please refer to index.html available under \docs folder.

    Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
         used in existing projects, and thus avoid projects mass update
    Note: the following components have been removed from ARM original delivery (as not used in ST packages)
        - CMSIS_EW2018.pdf
        - .gitattributes
        - .gitignore
        - \Device
        - \CMSIS
           - \CoreValidation
		   - \DAP
           - \Documentation
           - \DoxyGen
           - \Driver
           - \Pack
           - \RTOS\CMSIS_RTOS_Tutorial.pdf
           - \RTOS\RTX
           - \RTOS\Template
           - \RTOS2\RTX
           - \Utilities
           - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2

Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
---
 docs/Core_A/html/search/all_6.js | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 docs/Core_A/html/search/all_6.js

(limited to 'docs/Core_A/html/search/all_6.js')

diff --git a/docs/Core_A/html/search/all_6.js b/docs/Core_A/html/search/all_6.js
new file mode 100644
index 0000000..9a56916
--- /dev/null
+++ b/docs/Core_A/html/search/all_6.js
@@ -0,0 +1,14 @@
+var searchData=
+[
+  ['floating_2dpoint_20exception_20control_20register_20_28fpexc_29',['Floating-Point Exception Control register (FPEXC)',['../group__CMSIS__FPEXC.html',1,'']]],
+  ['floating_2dpoint_20status_20and_20control_20register_20_28fpscr_29',['Floating-point Status and Control Register (FPSCR)',['../group__CMSIS__FPSCR.html',1,'']]],
+  ['fpscr_20bits',['FPSCR Bits',['../group__CMSIS__FPSCR__BITS.html',1,'']]],
+  ['f',['F',['../unionCPSR__Type.html#a20bbf5d5ba32cae380b7f181cf306f9e',1,'CPSR_Type::F()'],['../unionISR__Type.html#ae691a856f7de0f301c60521a7a779dc2',1,'ISR_Type::F()']]],
+  ['fi',['FI',['../unionSCTLR__Type.html#afe77b6c5d73e64d4ef3c5dc5ce2692dc',1,'SCTLR_Type']]],
+  ['fiq_5fmode',['FIQ_MODE',['../startup__ARMCA9_8c.html#ad53b2deac028f5b71d1cdddda17c4ea0',1,'startup_ARMCA9.c']]],
+  ['fpscr_5ftype',['FPSCR_Type',['../structFPSCR__Type.html',1,'']]],
+  ['floating_20point_20unit_20functions',['Floating Point Unit Functions',['../group__FPU__functions.html',1,'']]],
+  ['fs0',['FS0',['../unionDFSR__Type.html#af29edf59ecfd29848b69e2bbfb7f3082',1,'DFSR_Type::FS0()'],['../unionIFSR__Type.html#a9f9ae1ffa89d33e90159eec5c4b7cd6a',1,'IFSR_Type::FS0()']]],
+  ['fs1',['FS1',['../unionDFSR__Type.html#a869658f432d5e213b8cd55e8e58d1f56',1,'DFSR_Type::FS1()'],['../unionIFSR__Type.html#adb493acf17881eaf09a2e8629ee2243e',1,'IFSR_Type::FS1()']]],
+  ['fw',['FW',['../unionACTLR__Type.html#a55b8e4dd5312f32237dd023032618781',1,'ACTLR_Type']]]
+];
-- 
cgit