From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001
From: Ali Labbene <ali.labbene@st.com>
Date: Wed, 11 Dec 2019 08:59:21 +0100
Subject: Official ARM version: v5.4.0

    Add CMSIS V5.4.0, please refer to index.html available under \docs folder.

    Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
         used in existing projects, and thus avoid projects mass update
    Note: the following components have been removed from ARM original delivery (as not used in ST packages)
        - CMSIS_EW2018.pdf
        - .gitattributes
        - .gitignore
        - \Device
        - \CMSIS
           - \CoreValidation
		   - \DAP
           - \Documentation
           - \DoxyGen
           - \Driver
           - \Pack
           - \RTOS\CMSIS_RTOS_Tutorial.pdf
           - \RTOS\RTX
           - \RTOS\Template
           - \RTOS2\RTX
           - \Utilities
           - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2

Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
---
 docs/Core_A/html/search/all_12.js | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 docs/Core_A/html/search/all_12.js

(limited to 'docs/Core_A/html/search/all_12.js')

diff --git a/docs/Core_A/html/search/all_12.js b/docs/Core_A/html/search/all_12.js
new file mode 100644
index 0000000..fce0120
--- /dev/null
+++ b/docs/Core_A/html/search/all_12.js
@@ -0,0 +1,21 @@
+var searchData=
+[
+  ['radis',['RADIS',['../unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3',1,'ACTLR_Type']]],
+  ['raw_5fint_5fstatus',['RAW_INT_STATUS',['../structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637',1,'L2C_310_TypeDef']]],
+  ['read',['READ',['../core__ca_8h.html#ga2ee598252f996e4f96640b096291d280acb9be765f361bb7efb9073730aac92c6',1,'core_ca.h']]],
+  ['ref_5fcache_2etxt',['ref_cache.txt',['../ref__cache_8txt.html',1,'']]],
+  ['ref_5fcore_5fregister_2etxt',['ref_core_register.txt',['../ref__core__register_8txt.html',1,'']]],
+  ['ref_5fgic_2etxt',['ref_gic.txt',['../ref__gic_8txt.html',1,'']]],
+  ['ref_5fmmu_2etxt',['ref_mmu.txt',['../ref__mmu_8txt.html',1,'']]],
+  ['ref_5fsystemandclock_2etxt',['Ref_SystemAndClock.txt',['../Ref__SystemAndClock_8txt.html',1,'']]],
+  ['ref_5ftimer_2etxt',['ref_timer.txt',['../ref__timer_8txt.html',1,'']]],
+  ['reserved',['RESERVED',['../core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04',1,'core_ca.h']]],
+  ['reset_5fhandler',['Reset_Handler',['../startup__ARMCA9_8c.html#ae7ee340978f5c25f52f0cad1457c6616',1,'startup_ARMCA9.c']]],
+  ['revision_20history_20of_20cmsis_2dcore_20_28cortex_2da_29',['Revision History of CMSIS-Core (Cortex-A)',['../rev_histCoreA.html',1,'']]],
+  ['rg_5ft',['rg_t',['../structmmu__region__attributes__Type.html#a3f9d884c340aca62d3287b91809ac262',1,'mmu_region_attributes_Type']]],
+  ['rpr',['RPR',['../structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821',1,'GICInterface_Type']]],
+  ['rr',['RR',['../unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055',1,'SCTLR_Type']]],
+  ['rsdis',['RSDIS',['../unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3',1,'ACTLR_Type']]],
+  ['rtclock_5firqn',['RTClock_IRQn',['../ARMCA9_8h.html#a7e1129cd8a196f4284d41db3e82ad5c8abdd513b1533957e93fe0d7f26024d28e',1,'ARMCA9.h']]],
+  ['rw',['RW',['../core__ca_8h.html#ga2ee598252f996e4f96640b096291d280aec2497e0c8af01c04bec31ec0d1d7847',1,'core_ca.h']]]
+];
-- 
cgit