From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/group__peripheral__gr.html | 360 ++++++++++++++++++++++++++++ 1 file changed, 360 insertions(+) create mode 100644 docs/Core_A/html/group__peripheral__gr.html (limited to 'docs/Core_A/html/group__peripheral__gr.html') diff --git a/docs/Core_A/html/group__peripheral__gr.html b/docs/Core_A/html/group__peripheral__gr.html new file mode 100644 index 0000000..0621ef1 --- /dev/null +++ b/docs/Core_A/html/group__peripheral__gr.html @@ -0,0 +1,360 @@ + + + + + +Peripheral Access +CMSIS-Core (Cortex-A): Peripheral Access + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+Macros
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Peripheral Access
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Naming conventions and optional features for accessing peripherals. +More...

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+Macros

#define _VAL2FLD(field, value)
 Mask and shift a bit field value for assigning the result to a peripheral register. More...
 
#define _FLD2VAL(field, value)
 Extract from a peripheral register value the a bit field value. More...
 
+

Description

+

The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The Device Header File <device.h> contains typically these definition and also includes the core specific header files.

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The definitions for Peripheral Access can be generated using the CMSIS-SVD System View Description for Peripherals. Refer to SVDConv.exe for more information.

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Each peripheral provides a data type definition with a name that is composed of:

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  • an optional prefix <device abbreviation>_
    • +
  • <peripheral name>
    • +
  • postfix _Type or _TypeDef to identify a type definition.
    • +
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Examples:

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  • UART_TypeDef for the peripheral UART.
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  • IMX_UART_TypeDef for the device family IMX and the peripheral UART.
    • +
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The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.

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    +
  • IO Type Qualifiers are used to specify the access to peripheral variables. + + + + + + + + + + + + + + +
    IO Type Qualifier Type Description
    __IM Struct member Defines 'read only' permissions
    __OM Struct member Defines 'write only' permissions
    __IOM Struct member Defines 'read / write' permissions
    __I Scalar variable Defines 'read only' permissions
    __O Scalar variable Defines 'write only' permissions
    __IO Scalar variable Defines 'read / write' permissions
    +The typedef <device abbreviation>_UART_TypeDef shown below defines the generic register layout for all UART channels in a device.
    • +
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typedef struct {
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__O uint32_t UART_CR; // Offset: 0x0000 ( /W) Control Register
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__IO uint32_t UART_MR; // Offset: 0x0004 (R/W) Mode Register
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__O uint32_t UART_IER; // Offset: 0x0008 ( /W) Interrupt Enable Register
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__O uint32_t UART_IDR; // Offset: 0x000C ( /W) Interrupt Disable Register
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__I uint32_t UART_IMR; // Offset: 0x0010 (R/ ) Interrupt Mask Register
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__I uint32_t UART_SR; // Offset: 0x0014 (R/ ) Status Register
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__I uint32_t UART_RHR; // Offset: 0x0018 (R/ ) Receive Holding Register
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__O uint32_t UART_THR; // Offset: 0x001C ( /W) Transmit Holding Register
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__IO uint32_t UART_BRGR; // Offset: 0x0020 (R/W) Baud Rate Generator Register
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__IO uint32_t UART_CMPR; // Offset: 0x0024 (R/W) Comparison Register
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__IO uint32_t UART_RTOR; // Offset: 0x0028 (R/W) Receiver Time-out Register
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__I uint32_t RESERVED[46]; // Offset: 0x002C (R/ ) Reserved
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__IO uint32_t UART_WPMR; // Offset: 0x00E4 (R/W) Write Protection Mode Register
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} IMX_UART_TypeDef;
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To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.

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Example: In this example, IMX_UART2 and IMX_UART3 are two pointers to UARTs defined with above register structure.
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#define IMX_UART2 ((IMX_UART_TypeDef *) IMX_UART2_BASE)
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#define IMX_UART3 ((IMX_UART_TypeDef *) IMX_UART3_BASE)
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Note
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  • The prefix IMX is optional.
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The registers in the various UARTs can now be referred in the user code as shown below:
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val = IMX_UART2->SR // is the Status Register of UART2.
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+Minimal Requirements

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To access the peripheral registers and related function in a device, the files device.h and core_ca.h define as a minimum:
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  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
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    +Example:
    typedef struct
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    {
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    __IOM uint32_t C_CTLR; // Offset: 0x0000 (R/W) CPU Interface Control Register
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    __IOM uint32_t C_PMR; // Offset: 0x0004 (R/W) Interrupt Priority Mask Register
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    __IOM uint32_t C_BPR; // Offset: 0x0008 (R/W) Binary Point Register
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    __IM uint32_t C_IAR; // Offset: 0x000C (R/ ) Interrupt Acknowledge Register
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    __OM uint32_t C_EOIR; // Offset: 0x0010 ( /W) End Of Interrupt Register
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    __IM uint32_t C_RPR; // Offset: 0x0014 (R/ ) Running Priority Register
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    __IM uint32_t C_HPPIR; // Offset: 0x0018 (R/ ) Highest Priority Pending Interrupt Register
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    __IOM uint32_t C_ABPR; // Offset: 0x001C (R/W) Aliased Binary Point Register
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    __IM uint32_t C_AIAR; // Offset: 0x0020 (R/ ) Aliased Interrupt Acknowledge Register
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    __OM uint32_t C_AEOIR; // Offset: 0x0024 ( /W) Aliased End Of Interrupt Register
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    __IM uint32_t C_AHPPIR; // Offset: 0x0028 (R/ ) Aliased Highest Priority Pending Interrupt Register
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    __IOM uint32_t C_STATUSR; // Offset: 0x002C (R/W) Error Reporting Status Register, optional
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    __I uint32_t RESERVED1[40]; // Offset: 0x0030 (R/ ) Reserved
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    __IOM uint32_t C_APR[4]; // Offset: 0x00D0 (R/W) Active Priority Register
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    __IOM uint32_t C_NSAPR[4]; // Offset: 0x00E0 (R/W) Non-secure Active Priority Register
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    __I uint32_t RESERVED2[3]; // Offset: 0x00F6 (R/ ) Reserved
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    __IM uint32_t C_IIDR; // Offset: 0x00FC (R/ ) CPU Interface Identification Register
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    __I uint32_t RESERVED3[960]; // Offset: 0x0100 (R/ ) Reserved
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    __OM uint32_t C_DIR; // Offset: 0x1000 ( /W) Deactivate Interrupt Register
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    } GICInterface_Type;
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    • +
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
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    +Example:
    #define GIC_INTERFACE_BASE (0xe8202000UL) // GIC Interface Base Address
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    • +
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typedef, multiple access definitions exist.
    +
    +Example:
    #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE) // GIC Interface Access Definition
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    • +
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These definitions allow accessing peripheral registers with simple assignments.

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  • Example:
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    GICInterface->C_CTLR |= 1; // Enable Interface
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    • +
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+Optional Features

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Optionally, the file device.h may define:

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  • Register Bit Fields and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for #define constants.
    • +
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_.
    • +
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+Register Bit Fields

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For Core Register, macros define the position and the mask value for a bit field.

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Example:

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Bit field definitions for register ACTLR in CP15.

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// CP15 Register ACTLR
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#define ACTLR_DDI_Pos 28U
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#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos)
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#define ACTLR_DDVM_Pos 15U
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#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos)
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#define ACTLR_L1PCTL_Pos 13U
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#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos)
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#define ACTLR_L1RADIS_Pos 12U
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#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos)
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#define ACTLR_L2RADIS_Pos 11U
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#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos)
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#define ACTLR_DODMBS_Pos 10U
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#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos)
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#define ACTLR_SMP_Pos 6U
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#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos)
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The macros _VAL2FLD(field, value) and _FLD2VAL(field, value) enable access to bit fields.

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Macro Definition Documentation

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#define _FLD2VAL( field,
 value 
)
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Parameters
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fieldname of bit field.
valuevalue of the register. This parameter is interpreted as an uint32_t type.
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The macro _FLD2VAL uses the #define's _Pos and _Msk of the related bit field to extract the value of a bit field from a register.

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Example:

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i = _FLD2VAL(ACTLR_SMP, ACTLR);
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#define _VAL2FLD( field,
 value 
)
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Parameters
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fieldname of bit field.
valuevalue for the bit field. This parameter is interpreted as an uint32_t type.
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The macro _VAL2FLD uses the #define's _Pos and _Msk of the related bit field to shift bit-field values for assigning to a register.

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Example:

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ACTLR = _VAL2FLD(ACTLR_SMP, 0x1)
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+ + + + -- cgit