From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/group__CMSIS__core__register.html | 207 +++++++++++++++++++++ 1 file changed, 207 insertions(+) create mode 100644 docs/Core_A/html/group__CMSIS__core__register.html (limited to 'docs/Core_A/html/group__CMSIS__core__register.html') diff --git a/docs/Core_A/html/group__CMSIS__core__register.html b/docs/Core_A/html/group__CMSIS__core__register.html new file mode 100644 index 0000000..120f536 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__core__register.html @@ -0,0 +1,207 @@ + + + + + +Core Register Access +CMSIS-Core (Cortex-A): Core Register Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content
+
+
Core Register Access
+
+
+ +

Functions to access the Cortex-A core registers. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Content

 Auxiliary Control Register (ACTLR)
 The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.
 
 Cache and branch predictor maintenance operations
 This section describes the cache and branch predictor maintenance operations.
 
 Configuration Base Address Register (CBAR)
 Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13].
 
 Coprocessor Access Control Register (CPACR)
 The CPACR controls access to coprocessors CP0 to CP13.
 
 Current Program Status Register (CPSR)
 The Current Program Status Register (CPSR) holds processor status and control information.
 
 Data Fault Status Register (DFSR)
 The DFSR holds status information about the last data fault.
 
 Domain Access Control Register (DACR)
 DACR defines the access permission for each of the sixteen memory domains.
 
 Floating-Point Exception Control register (FPEXC)
 Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded.
 
 Floating-point Status and Control Register (FPSCR)
 Provides floating-point system status information and control.
 
 Instruction Fault Status Register (IFSR)
 The IFSR holds status information about the last instruction fault.
 
 Interrupt Status Register (ISR)
 The ISR shows whether an IRQ, FIQ, or external abort is pending.
 
 Multiprocessor Affinity Register (MPIDR)
 In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions.
 
 Counter Frequency register (CNTFRQ)
 Indicates the clock frequency of the system counter.
 
 PL1 Physical Timer Control register (CNTP_CTL)
 The control register for the physical timer.
 
 PL1 Physical Timer Compare Value register (CNTP_CVAL)
 Holds the 64-bit compare value for the PL1 physical timer.
 
 PL1 Physical Timer Value register (CNTP_TVAL)
 Holds the timer value for the PL1 physical timer.
 
 PL1 Physical Count register (CNTPCT)
 Holds the 64-bit physical count value.
 
 Stack Pointer (SP/R13)
 The processor uses SP as a pointer to the active stack.
 
 System Control Register (SCTLR)
 The SCTLR provides the top level control of the system, including its memory system.
 
 TLB maintenance operations
 This section describes the TLB operations that are implemented on all Armv7-A implementations.
 
 Translation Table Base Registers (TTBR0/TTBR1)
 TTBRn holds the base address of translation table n, and information about the memory it occupies.
 
 Vector Base Address Register (VBAR)
 When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode.
 
 Monitor Vector Base Address Register (MVBAR)
 The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode.
 
+

Description

+
+
+ + + + -- cgit