From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/group__CMSIS__TTBR.html | 229 +++++++++++++++++++++++++++++++ 1 file changed, 229 insertions(+) create mode 100644 docs/Core_A/html/group__CMSIS__TTBR.html (limited to 'docs/Core_A/html/group__CMSIS__TTBR.html') diff --git a/docs/Core_A/html/group__CMSIS__TTBR.html b/docs/Core_A/html/group__CMSIS__TTBR.html new file mode 100644 index 0000000..3aacae2 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__TTBR.html @@ -0,0 +1,229 @@ + + + + + +Translation Table Base Registers (TTBR0/TTBR1) +CMSIS-Core (Cortex-A): Translation Table Base Registers (TTBR0/TTBR1) + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+Functions
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Translation Table Base Registers (TTBR0/TTBR1)
Core Register Access
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TTBRn holds the base address of translation table n, and information about the memory it occupies. +More...

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__STATIC_FORCEINLINE uint32_t __get_TTBR0 (void)
 Get TTBR0. More...
 
__STATIC_FORCEINLINE void __set_TTBR0 (uint32_t ttbr0)
 Set TTBR0. More...
 
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Description

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32-bit TTBR format

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Bits Name Function
[31:x] BADDR Translation table base address, bits[31:x].
[x-1:7] - Reserved.
[6] IRGN[0] Inner region bit 0.
[5] NOS Not Outer Shareable bit.
[4:3] RGN Region bits.
[2] - Reserved.
[1] S Shareable bit.
[0] C/IRGN[1] Cacheable bit. / Inner region bit 1.
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Note
The width of TTBR0 BADDR field depends on the setting in TTBCR N field, giving x=14-N.
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+The width of TTBR1 BADDR field is fixed at x=14.
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64-bit TTBR format

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Bits Name Function
[63:56] - Reserved.
[55:48] ASID An ASID for the translation table base address.
[47:40] - Reserved.
[39:x] BADDR Translation table base address, bits[39:x].
[x-1:0] - Reserved.
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Note
The width of TBBR0/TBBR1 BADDR fields depends on the settings in TTBCR T0SZ/T1SZ fields respectively, giving x=14-TnSZ.
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Consider using __get_TTBR0 and __set_TTBR0 for accessing TTBR0 register.

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Function Documentation

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__STATIC_INLINE uint32_t __get_TTBR0 (void )
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This function returns the value of the Translation Table Base Register 0.

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Returns
Translation Table Base Register 0 value
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This function returns the value of the Translation Table Base Register 0.

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__STATIC_INLINE void __set_TTBR0 (uint32_t ttbr0)
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This function assigns the given value to the Translation Table Base Register 0.

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Parameters
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[in]ttbr0Translation Table Base Register 0 value to set
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This function assigns the given value to the Translation Table Base Register 0.

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+ + + + -- cgit