From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/group__CMSIS__SCTLR.html | 243 ++++++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) create mode 100644 docs/Core_A/html/group__CMSIS__SCTLR.html (limited to 'docs/Core_A/html/group__CMSIS__SCTLR.html') diff --git a/docs/Core_A/html/group__CMSIS__SCTLR.html b/docs/Core_A/html/group__CMSIS__SCTLR.html new file mode 100644 index 0000000..45a45dd --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__SCTLR.html @@ -0,0 +1,243 @@ + + + + + +System Control Register (SCTLR) +CMSIS-Core (Cortex-A): System Control Register (SCTLR) + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+Content | +Data Structures | +Functions
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System Control Register (SCTLR)
Core Register Access
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The SCTLR provides the top level control of the system, including its memory system. +More...

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+Content

 SCTLR Bits
 Bit position and mask macros.
 
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+Data Structures

struct  SCTLR_Type
 Bit field declaration for SCTLR layout. More...
 
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+Functions

__STATIC_FORCEINLINE void __set_SCTLR (uint32_t sctlr)
 Set SCTLR. More...
 
__STATIC_FORCEINLINE uint32_t __get_SCTLR (void)
 Get SCTLR. More...
 
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Description

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In a VMSAv7 implementation, the SCTLR bit assignments are:

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Bits Name Function
[31] - Reserved.
[30] TE Thumb Exception enable.
[29] AFE Access flag enable bit.
[28] TRE TEX remap enable bit.
[27:26] - Reserved.
[25] EE Exception Endianness bit.
[24:21] - Reserved.
[20] UWXN Unprivileged write permission implies PL1 Execute Never (XN).
[19] WXN Write permission implies Execute Never (XN).
[18:14] - Reserved.
[13] V Vectors bit.
[12] I Instruction cache enable bit.
[11] Z Branch prediction enable bit.
[10] SW SWP and SWPB enable bit.
[9:3] - Reserved.
[2] C Cache enable bit.
[1] A Alignment bit.
[0] M Address translation enable bit.
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Consider using __get_SCTLR and __set_SCTLR for accessing this register.

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Function Documentation

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__STATIC_INLINE uint32_t __get_SCTLR (void )
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Returns
System Control Register value
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This function returns the value of the System Control Register (SCTLR).

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__STATIC_INLINE void __set_SCTLR (uint32_t sctlr)
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This function assigns the given value to the System Control Register.

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Parameters
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[in]sctlrSystem Control Register value to set
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This function assigns the given value to the System Control Register (SCTLR).

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+ + + + -- cgit