From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- .../group__CMSIS__Core__FunctionInterface.html | 171 +++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html (limited to 'docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html') diff --git a/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html b/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html new file mode 100644 index 0000000..34277fd --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__Core__FunctionInterface.html @@ -0,0 +1,171 @@ + + + + + +Core Peripherals +CMSIS-Core (Cortex-A): Core Peripherals + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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Core Peripherals
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 Generic Interrupt Controller Functions
 The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).
 
 L1 Cache Functions
 L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache.
 
 L2C-310 Cache Controller Functions
 L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.
+Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual.
 
 Generic Physical Timer Functions
 Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.
+Reference: Cortex-A7 MPCore Technical Reference Manual.
 
 Private Timer Functions
 Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.
+References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual.
 
 Memory Management Unit Functions
 MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition.
 
 Floating Point Unit Functions
 FPU Functions enable the use of Floating Point instructions and extensions.
+Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition.
 
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Description

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Hardware Abstraction Layer. The Core-A function interface contains:

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