From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/group__CMSIS__ACTLR__BITS.html | 709 ++++++++++++++++++++++++ 1 file changed, 709 insertions(+) create mode 100644 docs/Core_A/html/group__CMSIS__ACTLR__BITS.html (limited to 'docs/Core_A/html/group__CMSIS__ACTLR__BITS.html') diff --git a/docs/Core_A/html/group__CMSIS__ACTLR__BITS.html b/docs/Core_A/html/group__CMSIS__ACTLR__BITS.html new file mode 100644 index 0000000..e114608 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ACTLR__BITS.html @@ -0,0 +1,709 @@ + + + + + +ACTLR Bits +CMSIS-Core (Cortex-A): ACTLR Bits + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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ACTLR Bits
Auxiliary Control Register (ACTLR)
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Bit position and mask macros. +More...

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+Macros

#define ACTLR_DDI_Pos   28U
 ACTLR: DDI Position. More...
 
#define ACTLR_DDI_Msk   (1UL << ACTLR_DDI_Pos)
 ACTLR: DDI Mask. More...
 
#define ACTLR_DBDI_Pos   28U
 ACTLR: DBDI Position. More...
 
#define ACTLR_DBDI_Msk   (1UL << ACTLR_DBDI_Pos)
 ACTLR: DBDI Mask. More...
 
#define ACTLR_BTDIS_Pos   18U
 ACTLR: BTDIS Position. More...
 
#define ACTLR_BTDIS_Msk   (1UL << ACTLR_BTDIS_Pos)
 ACTLR: BTDIS Mask. More...
 
#define ACTLR_RSDIS_Pos   17U
 ACTLR: RSDIS Position. More...
 
#define ACTLR_RSDIS_Msk   (1UL << ACTLR_RSDIS_Pos)
 ACTLR: RSDIS Mask. More...
 
#define ACTLR_BP_Pos   15U
 ACTLR: BP Position. More...
 
#define ACTLR_BP_Msk   (3UL << ACTLR_BP_Pos)
 ACTLR: BP Mask. More...
 
#define ACTLR_DDVM_Pos   15U
 ACTLR: DDVM Position. More...
 
#define ACTLR_DDVM_Msk   (1UL << ACTLR_DDVM_Pos)
 ACTLR: DDVM Mask. More...
 
#define ACTLR_L1PCTL_Pos   13U
 ACTLR: L1PCTL Position. More...
 
#define ACTLR_L1PCTL_Msk   (3UL << ACTLR_L1PCTL_Pos)
 ACTLR: L1PCTL Mask. More...
 
#define ACTLR_RADIS_Pos   12U
 ACTLR: RADIS Position. More...
 
#define ACTLR_RADIS_Msk   (1UL << ACTLR_RADIS_Pos)
 ACTLR: RADIS Mask. More...
 
#define ACTLR_L1RADIS_Pos   12U
 ACTLR: L1RADIS Position. More...
 
#define ACTLR_L1RADIS_Msk   (1UL << ACTLR_L1RADIS_Pos)
 ACTLR: L1RADIS Mask. More...
 
#define ACTLR_DWBST_Pos   11U
 ACTLR: DWBST Position. More...
 
#define ACTLR_DWBST_Msk   (1UL << ACTLR_DWBST_Pos)
 ACTLR: DWBST Mask. More...
 
#define ACTLR_L2RADIS_Pos   11U
 ACTLR: L2RADIS Position. More...
 
#define ACTLR_L2RADIS_Msk   (1UL << ACTLR_L2RADIS_Pos)
 ACTLR: L2RADIS Mask. More...
 
#define ACTLR_DODMBS_Pos   10U
 ACTLR: DODMBS Position. More...
 
#define ACTLR_DODMBS_Msk   (1UL << ACTLR_DODMBS_Pos)
 ACTLR: DODMBS Mask. More...
 
#define ACTLR_PARITY_Pos   9U
 ACTLR: PARITY Position. More...
 
#define ACTLR_PARITY_Msk   (1UL << ACTLR_PARITY_Pos)
 ACTLR: PARITY Mask. More...
 
#define ACTLR_AOW_Pos   8U
 ACTLR: AOW Position. More...
 
#define ACTLR_AOW_Msk   (1UL << ACTLR_AOW_Pos)
 ACTLR: AOW Mask. More...
 
#define ACTLR_EXCL_Pos   7U
 ACTLR: EXCL Position. More...
 
#define ACTLR_EXCL_Msk   (1UL << ACTLR_EXCL_Pos)
 ACTLR: EXCL Mask. More...
 
#define ACTLR_SMP_Pos   6U
 ACTLR: SMP Position. More...
 
#define ACTLR_SMP_Msk   (1UL << ACTLR_SMP_Pos)
 ACTLR: SMP Mask. More...
 
#define ACTLR_WFLZM_Pos   3U
 ACTLR: WFLZM Position. More...
 
#define ACTLR_WFLZM_Msk   (1UL << ACTLR_WFLZM_Pos)
 ACTLR: WFLZM Mask. More...
 
#define ACTLR_L1PE_Pos   2U
 ACTLR: L1PE Position. More...
 
#define ACTLR_L1PE_Msk   (1UL << ACTLR_L1PE_Pos)
 ACTLR: L1PE Mask. More...
 
#define ACTLR_FW_Pos   0U
 ACTLR: FW Position. More...
 
#define ACTLR_FW_Msk   (1UL << ACTLR_FW_Pos)
 ACTLR: FW Mask. More...
 
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Macro Definition Documentation

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#define ACTLR_AOW_Msk   (1UL << ACTLR_AOW_Pos)
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#define ACTLR_AOW_Pos   8U
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#define ACTLR_BP_Msk   (3UL << ACTLR_BP_Pos)
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#define ACTLR_BP_Pos   15U
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#define ACTLR_BTDIS_Msk   (1UL << ACTLR_BTDIS_Pos)
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#define ACTLR_BTDIS_Pos   18U
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#define ACTLR_DBDI_Msk   (1UL << ACTLR_DBDI_Pos)
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#define ACTLR_DBDI_Pos   28U
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#define ACTLR_DDI_Msk   (1UL << ACTLR_DDI_Pos)
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#define ACTLR_DDI_Pos   28U
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#define ACTLR_DDVM_Msk   (1UL << ACTLR_DDVM_Pos)
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#define ACTLR_DDVM_Pos   15U
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#define ACTLR_DODMBS_Msk   (1UL << ACTLR_DODMBS_Pos)
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#define ACTLR_DODMBS_Pos   10U
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#define ACTLR_DWBST_Msk   (1UL << ACTLR_DWBST_Pos)
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#define ACTLR_DWBST_Pos   11U
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#define ACTLR_EXCL_Msk   (1UL << ACTLR_EXCL_Pos)
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#define ACTLR_EXCL_Pos   7U
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#define ACTLR_FW_Msk   (1UL << ACTLR_FW_Pos)
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#define ACTLR_FW_Pos   0U
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#define ACTLR_L1PCTL_Msk   (3UL << ACTLR_L1PCTL_Pos)
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#define ACTLR_L1PCTL_Pos   13U
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#define ACTLR_L1PE_Msk   (1UL << ACTLR_L1PE_Pos)
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#define ACTLR_L1PE_Pos   2U
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#define ACTLR_L1RADIS_Msk   (1UL << ACTLR_L1RADIS_Pos)
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#define ACTLR_L1RADIS_Pos   12U
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#define ACTLR_L2RADIS_Msk   (1UL << ACTLR_L2RADIS_Pos)
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#define ACTLR_L2RADIS_Pos   11U
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#define ACTLR_PARITY_Msk   (1UL << ACTLR_PARITY_Pos)
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#define ACTLR_PARITY_Pos   9U
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#define ACTLR_RADIS_Msk   (1UL << ACTLR_RADIS_Pos)
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#define ACTLR_RADIS_Pos   12U
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#define ACTLR_RSDIS_Msk   (1UL << ACTLR_RSDIS_Pos)
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#define ACTLR_RSDIS_Pos   17U
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#define ACTLR_SMP_Msk   (1UL << ACTLR_SMP_Pos)
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#define ACTLR_SMP_Pos   6U
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#define ACTLR_WFLZM_Msk   (1UL << ACTLR_WFLZM_Pos)
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#define ACTLR_WFLZM_Pos   3U
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