From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/group__CMSIS__ACTLR.html | 289 ++++++++++++++++++++++++++++++ 1 file changed, 289 insertions(+) create mode 100644 docs/Core_A/html/group__CMSIS__ACTLR.html (limited to 'docs/Core_A/html/group__CMSIS__ACTLR.html') diff --git a/docs/Core_A/html/group__CMSIS__ACTLR.html b/docs/Core_A/html/group__CMSIS__ACTLR.html new file mode 100644 index 0000000..6c0b0c9 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__ACTLR.html @@ -0,0 +1,289 @@ + + + + + +Auxiliary Control Register (ACTLR) +CMSIS-Core (Cortex-A): Auxiliary Control Register (ACTLR) + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-A) +  Version 1.1.2 +
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CMSIS-Core support for Cortex-A processor-based devices
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+Content | +Data Structures | +Functions
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Auxiliary Control Register (ACTLR)
Core Register Access
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The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. +More...

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 ACTLR Bits
 Bit position and mask macros.
 
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+Data Structures

struct  ACTLR_Type
 Bit field declaration for ACTLR layout. More...
 
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+Functions

__STATIC_FORCEINLINE void __set_ACTRL (uint32_t actrl)
 Set ACTRL. More...
 
__STATIC_FORCEINLINE uint32_t __get_ACTLR (void)
 Get ACTLR. More...
 
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Description

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The ACTLR characteristics are differs between various Armv7-A implementations.

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Cortex-A5

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Bits Name Function
[31:29] - Reserved.
[28] DBDI Disable Branch Dual Issue
[27:19] - Reserved.
[18] BTDIS Disable indirect Branch Target Address Cache (BTAC).
[17] RSDIS Disable return stack operation.
[16:15] BP Branch prediction policy.
[14:13] L1PCTL L1 Data prefetch control.
[12] RADIS Disable Data Cache read-allocate mode.
[11] DWBST Disable AXI data write bursts to Normal memory.
[10] DODMBS Disable optimized data memory barrier behavior.
[9:8] - Reserved.
[7] EXCL Exclusive L1/L2 cache control.
[6] SMP Enables coherent requests to the processor.
[5:1] - Reserved.
[0] FW Cache and TLB maintenance broadcast.
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Cortex-A7

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Bits Name Function
[31:29] - Reserved.
[28] DDI Disable Dual Issue
[27:16] - Reserved.
[15] DDVM Disable Distributed Virtual Memory transactions.
[14:13] L1PCTL L1 Data prefetch control.
[12] L1RADIS L1 Data Cache read-allocate mode disable.
[11] L2RADIS L2 Data Cache read-allocate mode disable.
[10] DODMBS Disable optimized data memory barrier behavior.
[9:7] - Reserved.
[6] SMP Enables coherent requests to the processor.
[5:0] - Reserved.
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Cortex-A9

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Bits Name Function
[31:10] - Reserved.
[9] PARITY Support for parity checking, if implemented.
[8] AOW Enable allocation in one cache way only.
[7] EXCL Exclusive L1/L2 cache control.
[6] SMP Enables coherent requests to the processor.
[5:4] - Reserved.
[3] WFLZM Enable write full line of zeros modea.
[2] L1PE Dside prefetch.
[1] - Reserved.
[0] FW Cache and TLB maintenance broadcast.
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Consider using __get_ACTLR and __set_ACTRL to access ACTRL register.

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Function Documentation

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__STATIC_INLINE uint32_t __get_ACTLR (void )
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Returns
Auxiliary Control register value
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This function returns the value of the Auxiliary Control Register (ACTLR).

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__STATIC_INLINE void __set_ACTRL (uint32_t actrl)
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Parameters
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[in]actrlAuxiliary Control Register value to set
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This function assigns the given value to the Auxiliary Control Register (ACTLR).

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+ + + + -- cgit