From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core_A/html/ARMCA9_8h.html | 827 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 827 insertions(+) create mode 100644 docs/Core_A/html/ARMCA9_8h.html (limited to 'docs/Core_A/html/ARMCA9_8h.html') diff --git a/docs/Core_A/html/ARMCA9_8h.html b/docs/Core_A/html/ARMCA9_8h.html new file mode 100644 index 0000000..208e401 --- /dev/null +++ b/docs/Core_A/html/ARMCA9_8h.html @@ -0,0 +1,827 @@ + + + + + +ARMCA9.h File Reference +CMSIS-Core (Cortex-A): ARMCA9.h File Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-A) +  Version 1.1.2 +
+
CMSIS-Core support for Cortex-A processor-based devices
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+Macros | +Enumerations
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+
ARMCA9.h File Reference
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+Macros

#define VE_A9_MP_FLASH_BASE0   (0x00000000UL)
 
#define VE_A9_MP_FLASH_BASE1   (0x08000000UL)
 
#define VE_A9_MP_PERIPH_BASE   (0x18000000UL)
 
#define VE_A9_MP_SRAM_BASE   (0x2E000000UL)
 
#define VE_A9_MP_DRAM_BASE   (0x80000000UL)
 
#define VE_A9_MP_VRAM_BASE   (0x18000000UL)
 
#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE)
 
#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE)
 
#define VE_A9_MP_DAP_BASE   (0x1C000000UL)
 
#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + 0x1C000000UL)
 
#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + 0x1C000000UL)
 
#define VE_A9_MP_AACI_BASE   (0x00040000UL + 0x1C000000UL)
 
#define VE_A9_MP_MMCI_BASE   (0x00050000UL + 0x1C000000UL)
 
#define VE_A9_MP_KMI0_BASE   (0x00060000UL + 0x1C000000UL)
 
#define VE_A9_MP_UART_BASE   (0x00090000UL + 0x1C000000UL)
 
#define VE_A9_MP_WDT_BASE   (0x000F0000UL + 0x1C000000UL)
 
#define VE_A9_MP_TIMER_BASE   (0x00110000UL + 0x1C000000UL)
 
#define VE_A9_MP_DVI_BASE   (0x00160000UL + 0x1C000000UL)
 
#define VE_A9_MP_RTC_BASE   (0x00170000UL + 0x1C000000UL)
 
#define VE_A9_MP_UART4_BASE   (0x001B0000UL + 0x1C000000UL)
 
#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + 0x1C000000UL)
 
#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + 0x2C000000UL)
 
#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + 0x2C000000UL)
 
#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + 0x2C000000UL)
 
#define GIC_DISTRIBUTOR_BASE   VE_A9_MP_GIC_DISTRIBUTOR_BASE
 
#define GIC_INTERFACE_BASE   VE_A9_MP_GIC_INTERFACE_BASE
 
#define TIMER_BASE   VE_A9_MP_PRIVATE_TIMER
 
#define VE_A9_MP_PL310_BASE   (0x1E00A000UL)
 
#define L2C_310_BASE   VE_A9_MP_PL310_BASE
 
#define __CA_REV   0x0000U
 Contains the core revision for a Cortex-A class device. More...
 
#define __CORTEX_A   9U
 Contains the core family for a Cortex-A class device. More...
 
#define __FPU_PRESENT   1U /* FPU present */
 
#define __GIC_PRESENT   1U /* GIC present */
 
#define __TIM_PRESENT   1U /* TIM present */
 
#define __L2C_PRESENT   0U /* L2C present */
 
+ + + +

+Enumerations

enum  IRQn_Type {
+  SGI0_IRQn = 0, +
+  SGI1_IRQn = 1, +
+  SGI2_IRQn = 2, +
+  SGI3_IRQn = 3, +
+  SGI4_IRQn = 4, +
+  SGI5_IRQn = 5, +
+  SGI6_IRQn = 6, +
+  SGI7_IRQn = 7, +
+  SGI8_IRQn = 8, +
+  SGI9_IRQn = 9, +
+  SGI10_IRQn = 10, +
+  SGI11_IRQn = 11, +
+  SGI12_IRQn = 12, +
+  SGI13_IRQn = 13, +
+  SGI14_IRQn = 14, +
+  SGI15_IRQn = 15, +
+  GlobalTimer_IRQn = 27, +
+  PrivTimer_IRQn = 29, +
+  PrivWatchdog_IRQn = 30, +
+  Watchdog_IRQn = 32, +
+  Timer0_IRQn = 34, +
+  Timer1_IRQn = 35, +
+  RTClock_IRQn = 36, +
+  UART0_IRQn = 37, +
+  UART1_IRQn = 38, +
+  UART2_IRQn = 39, +
+  UART3_IRQn = 40, +
+  MCI0_IRQn = 41, +
+  MCI1_IRQn = 42, +
+  AACI_IRQn = 43, +
+  Keyboard_IRQn = 44, +
+  Mouse_IRQn = 45, +
+  CLCD_IRQn = 46, +
+  Ethernet_IRQn = 47, +
+  VFS2_IRQn = 73 +
+ }
 
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __FPU_PRESENT   1U /* FPU present */
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+ + + + +
#define __GIC_PRESENT   1U /* GIC present */
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#define __L2C_PRESENT   0U /* L2C present */
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#define __TIM_PRESENT   1U /* TIM present */
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#define GIC_DISTRIBUTOR_BASE   VE_A9_MP_GIC_DISTRIBUTOR_BASE
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+ +
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+ + + + +
#define GIC_INTERFACE_BASE   VE_A9_MP_GIC_INTERFACE_BASE
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+ +
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+ +
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+ + + + +
#define L2C_310_BASE   VE_A9_MP_PL310_BASE
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#define TIMER_BASE   VE_A9_MP_PRIVATE_TIMER
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+ +
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#define VE_A9_MP_AACI_BASE   (0x00040000UL + 0x1C000000UL)
+
+

(AACI ) Base Address

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#define VE_A9_MP_CLCD_BASE   (0x001F0000UL + 0x1C000000UL)
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+

(CLCD ) Base Address

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#define VE_A9_MP_DAP_BASE   (0x1C000000UL)
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+

(DAP ) Base Address

+ +
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#define VE_A9_MP_DRAM_BASE   (0x80000000UL)
+
+

(DRAM ) Base Address

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#define VE_A9_MP_DVI_BASE   (0x00160000UL + 0x1C000000UL)
+
+

(DVI ) Base Address

+ +
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+ + + + +
#define VE_A9_MP_ETHERNET_BASE   (0x02000000UL + VE_A9_MP_PERIPH_BASE)
+
+

(ETHERNET ) Base Address

+ +
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+ + + + +
#define VE_A9_MP_FLASH_BASE0   (0x00000000UL)
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+

(FLASH0 ) Base Address

+ +
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#define VE_A9_MP_FLASH_BASE1   (0x08000000UL)
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+

(FLASH1 ) Base Address

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#define VE_A9_MP_GIC_DISTRIBUTOR_BASE   (0x00001000UL + 0x2C000000UL)
+
+

(GIC DIST ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_GIC_INTERFACE_BASE   (0x00000100UL + 0x2C000000UL)
+
+

(GIC CPU IF) Base Address

+ +
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+ +
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+ + + + +
#define VE_A9_MP_KMI0_BASE   (0x00060000UL + 0x1C000000UL)
+
+

(KMI0 ) Base Address

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+ +
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#define VE_A9_MP_MMCI_BASE   (0x00050000UL + 0x1C000000UL)
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+

(MMCI ) Base Address

+ +
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#define VE_A9_MP_PERIPH_BASE   (0x18000000UL)
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(Peripheral) Base Address

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#define VE_A9_MP_PL310_BASE   (0x1E00A000UL)
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+

(L2C-310 ) Base Address

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+ +
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#define VE_A9_MP_PRIVATE_TIMER   (0x00000600UL + 0x2C000000UL)
+
+

(PTIM ) Base Address

+ +
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+ +
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+ + + + +
#define VE_A9_MP_RTC_BASE   (0x00170000UL + 0x1C000000UL)
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+

(RTC ) Base Address

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+ +
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#define VE_A9_MP_SERIAL_BASE   (0x00030000UL + 0x1C000000UL)
+
+

(SERIAL ) Base Address

+ +
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+ +
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#define VE_A9_MP_SRAM_BASE   (0x2E000000UL)
+
+

(SRAM ) Base Address

+ +
+
+ +
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+ + + + +
#define VE_A9_MP_SYSTEM_REG_BASE   (0x00010000UL + 0x1C000000UL)
+
+

(SYSTEM REG) Base Address

+ +
+
+ +
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+ + + + +
#define VE_A9_MP_TIMER_BASE   (0x00110000UL + 0x1C000000UL)
+
+

(TIMER ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_UART4_BASE   (0x001B0000UL + 0x1C000000UL)
+
+

(UART4 ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_UART_BASE   (0x00090000UL + 0x1C000000UL)
+
+

(UART ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_USB_BASE   (0x03000000UL + VE_A9_MP_PERIPH_BASE)
+
+

(USB ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_VRAM_BASE   (0x18000000UL)
+
+

(VRAM ) Base Address

+ +
+
+ +
+
+ + + + +
#define VE_A9_MP_WDT_BASE   (0x000F0000UL + 0x1C000000UL)
+
+

(WDT ) Base Address

+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn_Type
+
+

Device specific Interrupt IDs

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Enumerator
SGI0_IRQn  +

Software Generated Interrupt 0

+
SGI1_IRQn  +

Software Generated Interrupt 1

+
SGI2_IRQn  +

Software Generated Interrupt 2

+
SGI3_IRQn  +

Software Generated Interrupt 3

+
SGI4_IRQn  +

Software Generated Interrupt 4

+
SGI5_IRQn  +

Software Generated Interrupt 5

+
SGI6_IRQn  +

Software Generated Interrupt 6

+
SGI7_IRQn  +

Software Generated Interrupt 7

+
SGI8_IRQn  +

Software Generated Interrupt 8

+
SGI9_IRQn  +

Software Generated Interrupt 9

+
SGI10_IRQn  +

Software Generated Interrupt 10

+
SGI11_IRQn  +

Software Generated Interrupt 11

+
SGI12_IRQn  +

Software Generated Interrupt 12

+
SGI13_IRQn  +

Software Generated Interrupt 13

+
SGI14_IRQn  +

Software Generated Interrupt 14

+
SGI15_IRQn  +

Software Generated Interrupt 15

+
GlobalTimer_IRQn  +

Global Timer Interrupt

+
PrivTimer_IRQn  +

Private Timer Interrupt

+
PrivWatchdog_IRQn  +

Private Watchdog Interrupt

+
Watchdog_IRQn  +

SP805 Interrupt

+
Timer0_IRQn  +

SP804 Interrupt

+
Timer1_IRQn  +

SP804 Interrupt

+
RTClock_IRQn  +

PL031 Interrupt

+
UART0_IRQn  +

PL011 Interrupt

+
UART1_IRQn  +

PL011 Interrupt

+
UART2_IRQn  +

PL011 Interrupt

+
UART3_IRQn  +

PL011 Interrupt

+
MCI0_IRQn  +

PL180 Interrupt (1st)

+
MCI1_IRQn  +

PL180 Interrupt (2nd)

+
AACI_IRQn  +

PL041 Interrupt

+
Keyboard_IRQn  +

PL050 Interrupt

+
Mouse_IRQn  +

PL050 Interrupt

+
CLCD_IRQn  +

PL111 Interrupt

+
Ethernet_IRQn  +

SMSC_91C111 Interrupt

+
VFS2_IRQn  +

VFS2 Interrupt

+
+ +
+
+
+
+ + + + -- cgit