From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/CMSIS_CORE_Files.png | Bin 0 -> 26200 bytes docs/Core/html/CMSIS_CORE_Files_user.png | Bin 0 -> 10053 bytes docs/Core/html/CMSIS_Logo_Final.png | Bin 0 -> 12402 bytes docs/Core/html/CMSIS_TZ_files.png | Bin 0 -> 60531 bytes docs/Core/html/MemoryMap_NS.png | Bin 0 -> 65389 bytes docs/Core/html/MemoryMap_S.png | Bin 0 -> 67748 bytes docs/Core/html/Registers.png | Bin 0 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+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
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+
Data Structures
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+
+
Here are the data structures with brief descriptions:
+ + + + + + + + + + + + + + + + +
oCAPSR_TypeUnion type to access the Application Program Status Register (APSR)
oCARM_MPU_Region_tSetup information of a single MPU Region
oCCONTROL_TypeUnion type to access the Control Registers (CONTROL)
oCCoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug)
oCDWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT)
oCFPU_TypeStructure type to access the Floating Point Unit (FPU)
oCIPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR)
oCITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM)
oCMPU_TypeStructure type to access the Memory Protection Unit (MPU)
oCNVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC)
oCSCB_TypeStructure type to access the System Control Block (SCB)
oCSCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB
oCSysTick_TypeStructure type to access the System Timer (SysTick)
oCTPI_TypeStructure type to access the Trace Port Interface Register (TPI)
\CxPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR)
+
+
+
+ + + + diff --git a/docs/Core/html/annotated.js b/docs/Core/html/annotated.js new file mode 100644 index 0000000..323c6b9 --- /dev/null +++ b/docs/Core/html/annotated.js @@ -0,0 +1,18 @@ +var annotated = +[ + [ "APSR_Type", "unionAPSR__Type.html", "unionAPSR__Type" ], + [ "ARM_MPU_Region_t", "structARM__MPU__Region__t.html", "structARM__MPU__Region__t" ], + [ "CONTROL_Type", "unionCONTROL__Type.html", "unionCONTROL__Type" ], + [ "CoreDebug_Type", "structCoreDebug__Type.html", "structCoreDebug__Type" ], + [ "DWT_Type", "structDWT__Type.html", "structDWT__Type" ], + [ "FPU_Type", "structFPU__Type.html", "structFPU__Type" ], + [ "IPSR_Type", "unionIPSR__Type.html", "unionIPSR__Type" ], + [ "ITM_Type", "structITM__Type.html", "structITM__Type" ], + [ "MPU_Type", "structMPU__Type.html", "structMPU__Type" ], + [ "NVIC_Type", "structNVIC__Type.html", "structNVIC__Type" ], + [ "SCB_Type", "structSCB__Type.html", "structSCB__Type" ], + [ "SCnSCB_Type", "structSCnSCB__Type.html", "structSCnSCB__Type" ], + [ "SysTick_Type", "structSysTick__Type.html", "structSysTick__Type" ], + [ "TPI_Type", "structTPI__Type.html", "structTPI__Type" ], + [ "xPSR_Type", "unionxPSR__Type.html", "unionxPSR__Type" ] +]; \ No newline at end of file diff --git a/docs/Core/html/bc_s.png b/docs/Core/html/bc_s.png new file mode 100644 index 0000000..66f8e9a Binary files /dev/null and b/docs/Core/html/bc_s.png differ diff --git a/docs/Core/html/bdwn.png b/docs/Core/html/bdwn.png new file mode 100644 index 0000000..d400769 Binary files /dev/null and b/docs/Core/html/bdwn.png differ diff --git a/docs/Core/html/check.png b/docs/Core/html/check.png new file mode 100644 index 0000000..094e59c Binary files /dev/null and b/docs/Core/html/check.png differ diff --git a/docs/Core/html/classes.html b/docs/Core/html/classes.html new file mode 100644 index 0000000..470e04e --- /dev/null +++ b/docs/Core/html/classes.html @@ -0,0 +1,156 @@ + + + + + +Data Structure Index +CMSIS-Core (Cortex-M): Data Structure Index + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + + +
+
+ +
+
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+ +
+ + + + +
+ +
+ +
+
+
Data Structure Index
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+
+
A | C | D | F | I | M | N | S | T | X
+ + + + + + + + + +
  A  
+		CoreDebug_Type   
  I  
+
  N  
+		SysTick_Type   
  D  
+
  T  
+
APSR_Type   IPSR_Type   NVIC_Type   
ARM_MPU_Region_t   DWT_Type   ITM_Type   
  S  
+		TPI_Type   
  C  
+
  F  
+
  M  
+
  x  
+
SCB_Type   
CONTROL_Type   FPU_Type   MPU_Type   SCnSCB_Type   xPSR_Type   
+
A | C | D | F | I | M | N | S | T | X
+
+
+ + + + diff --git a/docs/Core/html/closed.png b/docs/Core/html/closed.png new file mode 100644 index 0000000..ccbcf62 Binary files /dev/null and b/docs/Core/html/closed.png differ diff --git a/docs/Core/html/cmsis.css b/docs/Core/html/cmsis.css new file mode 100644 index 0000000..bba1010 --- /dev/null +++ b/docs/Core/html/cmsis.css @@ -0,0 +1,1282 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +td.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +span.h2 +{ + font-size: 120%; + font-weight: bold; +} + +div.new +{ + background-color:#ccffcc; /* light green */ +} + +div.mod +{ + background-color:#ffe6cc; /* light amber */ +} + +div.del +{ + background-color:#ffcccc; /* light red */ +} + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #EBEFF6; + color: #000000; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + margin-left: 5px; + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 7px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/docs/Core/html/coreMISRA_Exceptions_pg.html b/docs/Core/html/coreMISRA_Exceptions_pg.html new file mode 100644 index 0000000..d6b95dc --- /dev/null +++ b/docs/Core/html/coreMISRA_Exceptions_pg.html @@ -0,0 +1,174 @@ + + + + + +MISRA-C Deviations +CMSIS-Core (Cortex-M): MISRA-C Deviations + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
MISRA-C Deviations
+
+
+

CMSIS-Core (Cortex-M) uses the common coding rules for CMSIS components that are documented under Introduction.

+

CMSIS-Core (Cortex-M) violates the following MISRA-C:2004 rules:

+
    +
  • Required Rule 8.5, object/function definition in header file.
    + Violated since function definitions in header files are used for function inlining'.
    • +
  • Advisory Rule 12.4, Side effects on right hand side of logical operator.
    + Violated because volatile is used for core register definitions.
    • +
  • Advisory Rule 14.7, Return statement before end of function.
    + Violated to simplify code logic.
    • +
  • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Violated since unions are used for effective representation of core registers.
    • +
  • Advisory Rule 19.4, Disallowed definition for macro.
    + Violated since macros are used for assembler keywords.
    • +
  • Advisory Rule 19.7, Function-like macro defined.
    + Violated since function-like macros are used to generate more efficient code.
    • +
  • Advisory Rule 19.16, all preprocessing directives must be valid.
    + Violated to set default settings for macros.
    • +
+

CMSIS-Core (Cortex-M) violates the following MISRA-C:2012 rules:

+
    +
  • Directive 4.9, function-like macro defined.
    + Violated since function-like macros are used to generate more efficient code.
    • +
  • Rule 1.3, multiple use of '#/##' operators in macro definition.
    + Violated since function-like macros are used to generate more efficient code.
    • +
  • Rule 11.4, conversion between a pointer and integer type.
    + Violated because of core register access.
    • +
  • Rule 11.6, cast from unsigned long to pointer.
    + Violated because of core register access.
    • +
  • Rule 13.5, side effects on right hand side of logical operator.
    + Violated because of shift operand is used in macros and functions.
    • +
  • Rule 14.4, conditional expression should have essentially Boolean type.
    + Violated since macros with several instructions are used.
    • +
  • Rule 15.5, return statement before end of function.
    + Violated to simplify code logic.
    • +
  • Rule 20.10, '#/##' operators used.
    + Violated since function-like macros are used to generate more efficient code.
    • +
  • Rule 21.1, reserved to the compiler.
    + Violated since macros with leading underscores are used.
    • +
+

<device>.h files generated by SVDConv.exe violate the following MISRA-C:2004 rules:

+
    +
  • Advisory Rule 20.2, Re-use of C90 identifier pattern.
    + Violated since CMSIS macros begin with '__'. Since CMSIS is developed and verified with various compilers this approach is acceptable and avoids conflicts with user symbols.
    • +
  • Advisory Rule 19.1, Declaration before #include.
    + Violated since Interrupt Number Definition Type (IRQn_Type) must be defined before including the core header file.
    • +
+
+
+ + + + diff --git a/docs/Core/html/core_revisionHistory.html b/docs/Core/html/core_revisionHistory.html new file mode 100644 index 0000000..0016702 --- /dev/null +++ b/docs/Core/html/core_revisionHistory.html @@ -0,0 +1,274 @@ + + + + + +Revision History of CMSIS-Core (Cortex-M) +CMSIS-Core (Cortex-M): Revision History of CMSIS-Core (Cortex-M) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Revision History of CMSIS-Core (Cortex-M)
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Version Description
V5.1.2 Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.
+ Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.
+ Added support for Cortex-M1 (beta).
+ Removed usage of register keyword.
+ Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.
+ Enhanced MPUv7 API with defines for memory access attributes.
+
V5.1.1 Aligned MSPLIM and PSPLIM access functions along supported compilers.
+
V5.1.0 Added MPU Functions for ARMv8-M for Cortex-M23/M33.
+ Moved __SSAT and __USAT intrinsics to CMSIS-Core.
+ Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.
+
V5.0.2 Added macros __UNALIGNED_UINT16_READ, __UNALIGNED_UINT16_WRITE.
+ Added macros __UNALIGNED_UINT32_READ, __UNALIGNED_UINT32_WRITE.
+ Deprecated macro __UNALIGNED_UINT32.
+ Changed Version Control macros to be core agnostic.
+ Added MPU Functions for Armv7-M for Cortex-M0+/M3/M4/M7.
V5.0.1 Added: macro __PACKED_STRUCT.
+ Added: uVisor support.
+
V5.00 Added: Cortex-M23, Cortex-M33 support.
+ Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.
+ Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.
+ Reworked: SAU register and functions.
+ Added: macro __ALIGNED.
+ Updated: function SCB_EnableICache.
+ Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.
+ Added: macro __PACKED.
+ Updated: compiler specific include files.
+ Updated: core dependant include files.
+ Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.
V5.00
+Beta 6 		Added: SCB_CFSR register bit definitions.
+ Added: function NVIC_GetEnableIRQ.
+ Updated: core instruction macros __NOP, __WFI, __WFE, __SEV for toolchain GCC.
V5.00
+Beta 5 		Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
+ Added: DSP libraries build projects to CMSIS pack.
V5.00
+Beta 4 		Updated: ARMv8M device files.
+ Corrected: ARMv8MBL interrupts.
+ Reworked: NVIC functions.
V5.00
+Beta 2 		Changed: ARMv8M SAU regions to 8.
+ Changed: moved function TZ_SAU_Setup to file partition_<device>.h.
+ Changed: license under Apache-2.0.
+ Added: check if macro is defined before use.
+ Corrected: function SCB_DisableDCache.
+ Corrected: macros _VAL2FLD, _FLD2VAL.
+ Added: NVIC function virtualization with macros CMSIS_NVIC_VIRTUAL and CMSIS_VECTAB_VIRTUAL.
V5.00
+Beta 1 		Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.
+ Renamed: core_*.h to lower case.
+ Added: function SCB_GetFPUType to all CMSIS cores.
+ Added: ARMv8-M support.
V4.30 Corrected: DoxyGen function parameter comments.
+ Corrected: IAR toolchain: removed for NVIC_SystemReset the attribute(noreturn).
+ Corrected: GCC toolchain: suppressed irrelevant compiler warnings.
+ Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).
V4.20 Corrected: MISRA-C:2004 violations.
+ Corrected: predefined macro for TI CCS Compiler.
+ Corrected: function __SHADD16 in arm_math.h.
+ Updated: cache functions for Cortex-M7.
+ Added: macros _VAL2FLD, _FLD2VAL to core_*.h.
+ Updated: functions __QASX, __QSAX, __SHASX, __SHSAX.
+ Corrected: potential bug in function __SHADD16.
V4.10 Corrected: MISRA-C:2004 violations.
+ Corrected: intrinsic functions __DSB, __DMB, __ISB.
+ Corrected: register definitions for ITCMCR register.
+ Corrected: register definitions for CONTROL_Type register.
+ Added: functions SCB_GetFPUType, SCB_InvalidateDCache_by_Addr to core_cm7.h.
+ Added: register definitions for APSR_Type, IPSR_Type, xPSR_Type register.
+ Added: __set_BASEPRI_MAX function to core_cmFunc.h.
+ Added: intrinsic functions __RBIT, __CLZ for Cortex-M0/CortexM0+.
+
V4.00 Added: Cortex-M7 support.
+ Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
+
V3.40 Corrected: C++ include guard settings.
+
V3.30 Added: COSMIC tool chain support.
+ Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
+ Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
+ Corrected: GCC/CLang warnings.
+
V3.20 Added: __BKPT instruction intrinsic.
+ Added: __SMMLA instruction intrinsic for Cortex-M4.
+ Corrected: ITM_SendChar.
+ Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
+ Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.
+ Corrected: rework of in-line assembly functions to remove potential compiler warnings.
+
V3.01 Added support for Cortex-M0+ processor.
+
V3.00 Added support for GNU GCC ARM Embedded Compiler.
+ Added function __ROR.
+ Added Register Mapping for TPIU, DWT.
+ Added support for SC000 and SC300 processors.
+ Corrected ITM_SendChar function.
+ Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
+ Documentation restructured.
V2.10 Updated documentation.
+ Updated CMSIS core include files.
+ Changed CMSIS/Device folder structure.
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
+ Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
+ Added additional Debug Functionality.
+ Changed folder structure.
+ Added doxygen comments.
+ Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
+
+
+ + + + diff --git a/docs/Core/html/deprecated.html b/docs/Core/html/deprecated.html new file mode 100644 index 0000000..f8b5907 --- /dev/null +++ b/docs/Core/html/deprecated.html @@ -0,0 +1,140 @@ + + + + + +Deprecated List +CMSIS-Core (Cortex-M): Deprecated List + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Deprecated List
+
+
+
+
Global __UNALIGNED_UINT32
+

Do not use this macro. It has been superseded by __UNALIGNED_UINT32_READ, __UNALIGNED_UINT32_WRITE and will be removed in the future.

+

+
+
Global __XXX_CMSIS_VERSION
+
Only rely on this define for CMSIS 5.0 and before.
+
Global __XXX_CMSIS_VERSION_MAIN
+
Only rely on this define for CMSIS 5.0 and before.
+
Global __XXX_CMSIS_VERSION_SUB
+
Only rely on this define for CMSIS 5.0 and before.
+
+
+
+ + + + diff --git a/docs/Core/html/device_h_pg.html b/docs/Core/html/device_h_pg.html new file mode 100644 index 0000000..d72aff3 --- /dev/null +++ b/docs/Core/html/device_h_pg.html @@ -0,0 +1,655 @@ + + + + + +Device Header File <device.h> +CMSIS-Core (Cortex-M): Device Header File <device.h> + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Device Header File <device.h>
+
+
+

The Device Header File <device.h> contains the following sections that are device specific:

+
    +
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • +
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • +
  • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • +
+

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

+

+Interrupt Number Definition

+

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

+
    +
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • +
  • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
    • +
+

Example:

+

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
typedef enum IRQn
+
{
+
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+
NonMaskableInt_IRQn = -14,
+
HardFault_IRQn = -13,
+
SVCall_IRQn = -5,
+
PendSV_IRQn = -2,
+
SysTick_IRQn = -1,
+
/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
+
WAKEUP0_IRQn = 0,
+
WAKEUP1_IRQn = 1,
+
WAKEUP2_IRQn = 2,
+
: :
+
: :
+
EINT1_IRQn = 30,
+
EINT0_IRQn = 31,
+
} IRQn_Type;
+

+Configuration of the Processor and Core Peripherals

+

The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

+

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

+

core_cm0.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm0plus.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm3.h

+ + + + + + + + + + + +
#define Value Range Default Description
__CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm4.h

+ + + + + + + + + + + + + +
#define Value Range Default Description
__CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm7.h

+ + + + + + + + + + + + + + + + + + + + + +
#define Value Range Default Description
__CM7_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not. See __FPU_DP description below.
__FPU_DP 0 .. 1 0 The combination of the defines __FPU_PRESENT and __FPU_DP determine the whether the FPU is with single or double precision as shown in the table below.
+
+ + + + + + + + + +
__FPU_PRESENT __FPU_DP Description
0 ignored Processor has no FPU. The value set for __FPU_DP has no influence.
1 0 Processor with FPU with single precision. The file ARMCM7_SP.h has preconfigured settings for this combination.
1 1 Processor with FPU with double precision. The file ARMCM7_DP.h has preconfigured settings for this combination.
+
__ICACHE_PRESENT 0 .. 1 1 Instruction Chache present or not
__DCACHE_PRESENT 0 .. 1 1 Data Chache present or not
__DTCM_PRESENT 0 .. 1 1 Data Tightly Coupled Memory is present or not
+

core_sc000.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_sc300.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_CM23.h or core_ARMv8MBL.h

+ + + + + + + + + + + + + + + +
#define Value Range Default Description
__ARMv8MBL_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__SAUREGION_PRESENT 0 .. 1 0 Defines if SAU regions are present or not
__VTOR_PRESENT 0 .. 1 0 Defines if a VTOR register is present or not
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_CM33.h or core_ARMv8MML.h

+ + + + + + + + + + + + + + + +
#define Value Range Default Description
__ARMv8MML_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__SAUREGION_PRESENT 0 .. 1 0 Defines if SAU regions are present or not
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
__NVIC_PRIO_BITS 2 .. 8 3 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

Example

+

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

+
#define __CM4_REV 0x0001 /* Core revision r0p1 */
+
#define __MPU_PRESENT 1 /* MPU present or not */
+
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
#define __FPU_PRESENT 1 /* FPU present or not */
+
.
+
.
+
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
+

+CMSIS Version and Processor Information

+

Defines in the core_cpu.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

+

core_cm0.h

+
#define __CM0_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM0_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+
__CM0_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (0U) /* Cortex-M Core */
+

core_cm0plus.h

+
#define __CM0PLUS_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM0PLUS_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16U) | \
+
__CM0P_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (0U) /* Cortex-M Core */
+

core_cm3.h

+
#define __CM3_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM3_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+
__CM3_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (3U) /* Cortex-M Core */
+

core_cm4.h

+
#define __CM4_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM4_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+
__CM4_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (4U) /* Cortex-M Core */
+

core_cm7.h

+
#define __CM7_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM7_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+
__CM7_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (7U) /* Cortex-M Core */
+

core_sc000.h

+
#define __SC000_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __SC000_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+
__SC000_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_SC (0U) /* Cortex secure core */
+

core_sc300.h

+
#define __SC300_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __SC300_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+
__SC300_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_SC (300U) /* Cortex secure core */
+

core_ARMv8MBL.h

+
#define __ARMv8MBL_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __ARMv8MBL_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+
__ARMv8MBL_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (tbd) /* Cortex secure core */
+

core_ARMv8MML.h

+
#define __ARMv8MML_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __ARMv8MML_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+
__ARMv8MML_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (tbd) /* Cortex secure core */
+

+Device Peripheral Access Layer

+

The Device Header File <device.h> contains for each peripheral:

+
    +
  • Register Layout Typedef
    • +
  • Base Address
    • +
  • Access Definitions
    • +
+

The section Peripheral Access shows examples for peripheral definitions.

+

+Device.h Template File

+

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

+
/**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V5.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment   */
+/** @addtogroup <Vendor>
+  * @{
+  */
+
+
+/* ToDo: replace '<Device>' with device name; add your doxyGen comment   */
+/** @addtogroup <Device>
+  * @{
+  */
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+typedef enum IRQn
+{
+/* =======================================  ARM Cortex-M# Specific Interrupt Numbers  ======================================== */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M0 / Cortex-M0+ device */
+  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M3 / Cortex-M4 / Cortex-M7 device */
+  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
+                                                          and No Match                                                         */
+  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                          related Fault                                                        */
+  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
+  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
+  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+
+/* ===========================================  <Device> Specific Interrupt Numbers  ========================================= */
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn */
+  <DeviceInterrupt>_IRQn    = 0,                /*!< Device Interrupt                                                          */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================  Configuration of the Arm Cortex-M4 Processor and Core Peripherals  =========================== */
+/* ToDo: set the defines according your Device */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a Cortex-M0 device
+         __CM3_REV if your device is a Cortex-M3 device
+         __CM4_REV if your device is a Cortex-M4 device
+         __CM7_REV if your device is a Cortex-M7 device */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1 */
+/* ToDo: define the correct core features for the <Device> */
+#define __MPU_PRESENT             1         /*!< Set to 1 if MPU is present */
+#define __VTOR_PRESENT            1         /*!< Set to 1 if VTOR is present */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0         /*!< Set to 1 if FPU is present */
+#define __FPU_DP                  0         /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
+#define __ICACHE_PRESENT          0         /*!< Set to 1 if I-Cache is present */
+#define __DCACHE_PRESENT          0         /*!< Set to 1 if D-Cache is present */
+#define __DTCM_PRESENT            0         /*!< Set to 1 if DTCM is present */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device
+         core_cm7.h if your device is a CORTEX-M4 device */
+#include <core_cm#.h>                           /*!< Arm Cortex-M# processor and core peripherals */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name */
+#include "system_<Device>.h"                    /*!< <Device> System */
+
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer */
+
+/* =========================================================================================================================== */
+/* ================                                            TMR                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer (TMR)
+  */
+
+typedef struct
+{                                               /*!< (@ 0x40000000) TIM Structure                                              */
+  __IOM uint32_t   TimerLoad;                   /*!< (@ 0x00000004) Timer Load                                                 */
+  __IM  uint32_t   TimerValue;                  /*!< (@ 0x00000008) Timer Counter Current Value                                */
+  __IOM uint32_t   TimerControl;                /*!< (@ 0x0000000C) Timer Control                                              */
+  __OM  uint32_t   TimerIntClr;                 /*!< (@ 0x00000010) Timer Interrupt Clear                                      */
+  __IM  uint32_t   TimerRIS;                    /*!< (@ 0x00000014) Timer Raw Interrupt Status                                 */
+  __IM  uint32_t   TimerMIS;                    /*!< (@ 0x00000018) Timer Masked Interrupt Status                              */
+  __IM  uint32_t   RESERVED[1];
+  __IOM uint32_t   TimerBGLoad;                 /*!< (@ 0x00000020) Background Load Register                                   */
+} <DeviceAbbreviation>_TMR_TypeDef;
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+
+/* ToDo: add here your device peripherals base addresses
+         following is an example for timer */
+/** @addtogroup Device_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+
+/* ToDo: add here your device peripherals pointer definitions
+         following is an example for timer */
+/** @addtogroup Device_Peripheral_declaration
+  * @{
+  */
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+
+
+/** @} */ /* End of group <Device> */
+
+/** @} */ /* End of group <Vendor> */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
+
+ + + + diff --git a/docs/Core/html/doxygen.css b/docs/Core/html/doxygen.css new file mode 100644 index 0000000..ce5dd28 --- /dev/null +++ b/docs/Core/html/doxygen.css @@ -0,0 +1,1366 @@ +/* The standard CSS for doxygen 1.8.6 */ + +body, table, div, p, dl { + font: 400 14px/22px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font: 400 14px/28px Roboto,sans-serif; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #859DCD; + color: #334C7D; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd { + margin-top: 2px; +} + +p.starttd { + margin-top: 0px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px 6px; + margin: 4px 8px 4px 2px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + min-height: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; 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+ color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fieldname { + padding-top: 3px; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + /*width: 100%;*/ +} + +.fieldtable td.fielddoc p:first-child { + margin-top: 0px; +} + +.fieldtable td.fielddoc p:last-child { + margin-bottom: 2px; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #27395E; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.diagraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +/* tooltip related style info */ + +.ttc { + position: absolute; + display: none; +} + +#powerTip { + cursor: default; + white-space: nowrap; + background-color: white; + border: 1px solid gray; + border-radius: 4px 4px 4px 4px; + box-shadow: 1px 1px 7px gray; + display: none; + font-size: smaller; + max-width: 80%; + opacity: 0.9; + padding: 1ex 1em 1em; + position: absolute; + z-index: 2147483647; +} + +#powerTip div.ttdoc { + color: grey; + font-style: italic; +} + +#powerTip div.ttname a { + font-weight: bold; +} + +#powerTip div.ttname { + font-weight: bold; +} + +#powerTip div.ttdeci { + color: #006318; +} + +#powerTip div { + margin: 0px; + padding: 0px; + font: 12px/16px Roboto,sans-serif; +} + +#powerTip:before, #powerTip:after { + content: ""; + position: absolute; + margin: 0px; +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.s:after, #powerTip.s:before, +#powerTip.w:after, #powerTip.w:before, +#powerTip.e:after, #powerTip.e:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.nw:after, #powerTip.nw:before, +#powerTip.sw:after, #powerTip.sw:before { + border: solid transparent; + content: " "; + height: 0; + width: 0; + position: absolute; +} + +#powerTip.n:after, #powerTip.s:after, +#powerTip.w:after, #powerTip.e:after, +#powerTip.nw:after, #powerTip.ne:after, +#powerTip.sw:after, #powerTip.se:after { + border-color: rgba(255, 255, 255, 0); +} + +#powerTip.n:before, #powerTip.s:before, +#powerTip.w:before, #powerTip.e:before, +#powerTip.nw:before, #powerTip.ne:before, +#powerTip.sw:before, #powerTip.se:before { + border-color: rgba(128, 128, 128, 0); +} + +#powerTip.n:after, #powerTip.n:before, +#powerTip.ne:after, #powerTip.ne:before, +#powerTip.nw:after, #powerTip.nw:before { + top: 100%; +} + +#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after { + border-top-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} +#powerTip.n:before { + border-top-color: #808080; + border-width: 11px; + margin: 0px -11px; +} +#powerTip.n:after, #powerTip.n:before { + left: 50%; +} + +#powerTip.nw:after, #powerTip.nw:before { + right: 14px; +} + +#powerTip.ne:after, #powerTip.ne:before { + left: 14px; +} + +#powerTip.s:after, #powerTip.s:before, +#powerTip.se:after, #powerTip.se:before, +#powerTip.sw:after, #powerTip.sw:before { + bottom: 100%; +} + +#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after { + border-bottom-color: #ffffff; + border-width: 10px; + margin: 0px -10px; +} + +#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before { + border-bottom-color: #808080; + border-width: 11px; + margin: 0px -11px; +} + +#powerTip.s:after, #powerTip.s:before { + left: 50%; +} + +#powerTip.sw:after, #powerTip.sw:before { + right: 14px; +} + +#powerTip.se:after, #powerTip.se:before { + left: 14px; +} + +#powerTip.e:after, #powerTip.e:before { + left: 100%; +} +#powerTip.e:after { + border-left-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.e:before { + border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/docs/Core/html/doxygen.png b/docs/Core/html/doxygen.png new file mode 100644 index 0000000..7765a33 Binary files /dev/null and b/docs/Core/html/doxygen.png differ diff --git a/docs/Core/html/dynsections.js b/docs/Core/html/dynsections.js new file mode 100644 index 0000000..ed092c7 --- /dev/null +++ b/docs/Core/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +Data Fields +CMSIS-Core (Cortex-M): Data Fields + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
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+ + + + + + +
+
+ +
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+ + + + diff --git a/docs/Core/html/functions_vars.html b/docs/Core/html/functions_vars.html new file mode 100644 index 0000000..a5f74d8 --- /dev/null +++ b/docs/Core/html/functions_vars.html @@ -0,0 +1,680 @@ + + + + + +Data Fields - Variables +CMSIS-Core (Cortex-M): Data Fields - Variables + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
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+ + + + + + +
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+ +
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+ + + + diff --git a/docs/Core/html/globals.html b/docs/Core/html/globals.html new file mode 100644 index 0000000..c6085ac --- /dev/null +++ b/docs/Core/html/globals.html @@ -0,0 +1,687 @@ + + + + + +Globals +CMSIS-Core (Cortex-M): Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
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+ + + + + +
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+ +
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+ + + + +
+ +
+ +
+
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+ +

- _ -

+
+
+ + + + diff --git a/docs/Core/html/globals_a.html b/docs/Core/html/globals_a.html new file mode 100644 index 0000000..16c8841 --- /dev/null +++ b/docs/Core/html/globals_a.html @@ -0,0 +1,195 @@ + + + + + +Globals +CMSIS-Core (Cortex-M): Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
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+ +
+
    + +
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+ + + + + +
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+ +
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+ +
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+ +

- a -

+
+
+ + + + diff --git a/docs/Core/html/globals_b.html b/docs/Core/html/globals_b.html new file mode 100644 index 0000000..8bce3b2 --- /dev/null +++ b/docs/Core/html/globals_b.html @@ -0,0 +1,159 @@ + + + + + +Globals +CMSIS-Core (Cortex-M): Globals + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:
+ +

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+
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+ + + + diff --git a/docs/Core/html/globals_c.html b/docs/Core/html/globals_c.html new file mode 100644 index 0000000..e7cddf4 --- /dev/null +++ b/docs/Core/html/globals_c.html @@ -0,0 +1,162 @@ + + + + + +Globals +CMSIS-Core (Cortex-M): Globals + + + + + + + + + + + + + + +
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+Functions
+
+
Core Register Access
+
+
+ +

Functions to access the Cortex-M core registers. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __get_CONTROL (void)
 Read the CONTROL register. More...
 
void __set_CONTROL (uint32_t control)
 Set the CONTROL Register. More...
 
uint32_t __get_IPSR (void)
 Read the IPSR register. More...
 
uint32_t __get_APSR (void)
 Read the APSR register. More...
 
uint32_t __get_xPSR (void)
 Read the xPSR register. More...
 
uint32_t __get_PSP (void)
 Read the PSP register. More...
 
void __set_PSP (uint32_t topOfProcStack)
 Set the PSP register. More...
 
uint32_t __get_MSP (void)
 Read the MSP register. More...
 
void __set_MSP (uint32_t topOfMainStack)
 Set the MSP register. More...
 
uint32_t __get_PRIMASK (void)
 Read the PRIMASK register bit. More...
 
void __set_PRIMASK (uint32_t priMask)
 Set the Priority Mask bit. More...
 
uint32_t __get_BASEPRI (void)
 Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void __set_BASEPRI (uint32_t basePri)
 Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void __set_BASEPRI_MAX (uint32_t basePri)
 Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __get_FAULTMASK (void)
 Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void __set_FAULTMASK (uint32_t faultMask)
 Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __get_FPSCR (void)
 Read the FPSCR register [only Cortex-M4 and Cortex-M7]. More...
 
void __set_FPSCR (uint32_t fpscr)
 Set the FPSC register [only for Cortex-M4 and Cortex-M7]. More...
 
void __enable_irq (void)
 Globally enables interrupts and configurable fault handlers. More...
 
void __disable_irq (void)
 Globally disables interrupts and configurable fault handlers. More...
 
void __enable_fault_irq (void)
 Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void __disable_fault_irq (void)
 Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __get_PSPLIM (void)
 Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. More...
 
void __set_PSPLIM (uint32_t ProcStackPtrLimit)
 Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. More...
 
uint32_t __get_MSPLIM (void)
 Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. More...
 
 __set_MSPLIM (uint32_t MainStackPtrLimit)
 Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. More...
 
+

Description

+

The following functions provide access to Cortex-M core registers.

+

Function Documentation

+ +
+
+ + + + + + + + +
void __disable_fault_irq (void )
+
+

The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction CPSID f.

+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Can be executed in privileged mode only.
    • +
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __disable_irq (void )
+
+

The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction CPSID i.

+
Remarks
    +
  • Can be executed in privileged mode only.
    • +
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __enable_fault_irq (void )
+
+

The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction CPSIE f.

+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Can be executed in privileged mode only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __enable_irq (void )
+
+

The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction CPSIE i.

+
Remarks
    +
  • Can be executed in privileged mode only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_APSR (void )
+
+

The function reads the Application Program Status Register (APSR) using the instruction MRS.
+
+The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:

+
    +
  • N (APSR[31]) (Negative flag)
      +
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • +
    • =0 The instruction result has a positive value or equal zero.
      +
      +
      • +
    +
    • +
  • Z (APSR[30]) (Zero flag)
      +
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
      +
      +
      • +
    +
    • +
  • C (APSR[29]) (Carry or borrow flag)
      +
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • +
    • =inverse of borrow output status For unsigned subtract operations.
      +
      +
      • +
    +
    • +
  • V (APSR[28]) (Overflow flag)
      +
    • =1 A signed overflow occurred (for signed additions or subtractions).
      +
      +
      • +
    +
    • +
  • Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
      +
    • This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.
      • +
    • =1 When saturation or an overflow occurred.
      +
      +
      • +
    +
    • +
  • GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
      +
    • Can be set by the parallel add and subtract instructions.
      • +
    • Are used by the SEL instruction to perform byte-based selection from two registers.
      • +
    +
    • +
+
Returns
APSR register value
+
Remarks
    +
  • Some instructions update all flags; some instructions update a subset of the flags.
    • +
  • If a flag is not updated, the original value is preserved.
    • +
  • Conditional instructions that are not executed have no effect on the flags.
    • +
  • The CMSIS does not provide a function to update this register.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_BASEPRI (void )
+
+

The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
+
+BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Returns
BASEPRI register value
+
Remarks
    +
  • Not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_CONTROL (void )
+
+

The function reads the CONTROL register value using the instruction MRS.
+
+The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+

+
    +
  • CONTROL[2] [only Cortex-M4 and Cortex-M7]
      +
    • =0 FPU not active
      • +
    • =1 FPU active
      +
      +
      • +
    +
    • +
  • CONTROL[1]
      +
    • =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
      • +
    • =0 In thread mode - Default stack pointer MSP is used.
      • +
    • =1 In thread mode - Alternate stack pointer PSP is used.
      +
      +
      • +
    +
    • +
  • CONTROL[0] [not Cortex-M0]
      +
    • =0 In thread mode and privileged state.
      • +
    • =1 In thread mode and user state.
      • +
    +
    • +
+
Returns
CONTROL register value
+
Remarks
    +
  • The processor can be in user state or privileged state when running in thread mode.
    • +
  • Exception handlers always run in privileged state.
    • +
  • On reset, the processor is in thread mode with privileged access rights.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_FAULTMASK (void )
+
+

The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
+
+FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).

+
Returns
FAULTMASK register value
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_FPSCR (void )
+
+

The function reads the Floating-Point Status Control Register (FPSCR) value.
+
+FPSCR provides all necessary User level controls of the floating-point system.

+
Returns
    +
  • FPSCR register value, when __FPU_PRESENT=1
    • +
  • =0, when __FPU_PRESENT=0
    • +
+
+
Remarks
    +
  • Only for Cortex-M4 and Cortex-M7.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_IPSR (void )
+
+

The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
+
+The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:

+
    +
  • ISR_NUMBER (IPSR[8:0])
      +
    • =0 Thread mode
      • +
    • =1 Reserved
      • +
    • =2 NMI
      • +
    • =3 HardFault
      • +
    • =4 MemManage
      • +
    • =5 BusFault
      • +
    • =6 UsageFault
      • +
    • =7-10 Reserved
      • +
    • =11 SVCall
      • +
    • =12 Reserved for Debug
      • +
    • =13 Reserved
      • +
    • =14 PendSV
      • +
    • =15 SysTick
      • +
    • =16 IRQ0
      • +
    • ...
      • +
    • =n+15 IRQ(n-1)
      • +
    +
    • +
+
Returns
ISPR register value
+
Remarks
    +
  • This register is read-only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_MSP (void )
+
+

The function reads the Main Status Pointer (MSP) value using the instruction MRS.
+
+Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Returns
MSP Register value
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_MSPLIM (void )
+
+

Returns the current value of the Main Stack Pointer Limit (MSPLIM).

+
Returns
MSPLIM Register value
+
Note
Only availabe for Armv8-M Architecture.
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PRIMASK (void )
+
+

The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
+
+PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Returns
PRIMASK register value
    +
  • =0 no effect
    • +
  • =1 prevents the activation of all exceptions with configurable priority
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PSP (void )
+
+

The function reads the Program Status Pointer (PSP) value using the instruction MRS.
+
+Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Returns
PSP register value
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PSPLIM (void )
+
+

Returns the current value of the Process Stack Pointer Limit (PSPLIM).

+
Returns
PSPLIM Register value
+
Note
Only availabe for Armv8-M Architecture.
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_xPSR (void )
+
+

The function reads the combined Program Status Register (xPSR) using the instruction MRS.
+
+xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:

+
    +
  • Application Program Status Register (APSR)
    • +
  • Interrupt Program Status Register (IPSR)
    • +
  • Execution Program Status Register (EPSR)
    • +
+

In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:

+
    +
  • IT (xPSR[26:25]) (If-Then condition instruction)
      +
    • Contains up to four instructions following an IT instruction.
      • +
    • Each instruction in the block is conditional.
      • +
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      +
      +
      • +
    +
    • +
  • T (xPSR[24]) (Thumb bit)
      +
    • =1 Indicates that that the processor is in Thumb state.
      • +
    • =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
      • +
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      • +
    +
    • +
+
Returns
xPSR register value
+
Remarks
    +
  • The CMSIS does not provide functions that access EPSR.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_BASEPRI (uint32_t basePri)
+
+

The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
+
+BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Parameters
+ + +
[in]basePriBASEPRI value to set
+
+
+
Remarks
    +
  • Not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Cannot be set in user state.
    • +
  • Useful for changing the masking level or disabling the masking.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_BASEPRI_MAX (uint32_t basePri)
+
+

The function only increases the Base Priority Mask register (BASEPRI) value using the instruction MSR. The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.
+
+BASEPRI defines the minimum priority for exception processing.

+
Parameters
+ + +
[in]basePriBASEPRI value to set
+
+
+
Remarks
    +
  • Not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Cannot be set in user state.
    • +
  • Useful for increasing the masking level.
    • +
  • Has no effect when basePri is lower than the current value of BASEPRI.
    • +
  • Use __set_BASEPRI to lower the Base Priority Mask register.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_CONTROL (uint32_t control)
+
+

The function sets the CONTROL register value using the instruction MSR.
+
+The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+

+
    +
  • CONTROL[2] [only Cortex-M4 and Cortex-M7]
      +
    • =0 FPU not active
      • +
    • =1 FPU active
      +
      +
      • +
    +
    • +
  • CONTROL[1]
      +
    • Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
      • +
    • =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
      • +
    • =0 In thread mode - Default stack pointer MSP is used.
      • +
    • =1 In thread mode - Alternate stack pointer PSP is used.
      +
      +
      • +
    +
    • +
  • CONTROL[0] [not writeable for Cortex-M0]
      +
    • Writeable only when the processor is in privileged state.
      • +
    • Can be used to switch the processor to user state (thread mode).
      • +
    • Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
      • +
    • =0 In thread mode and privileged state.
      • +
    • =1 In thread mode and user state.
      • +
    +
    • +
+
Parameters
+ + +
[in]controlCONTROL register value to set
+
+
+
Remarks
    +
  • The processor can be in user state or privileged state when running in thread mode.
    • +
  • Exception handlers always run in privileged state.
    • +
  • On reset, the processor is in thread mode with privileged access rights.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_FAULTMASK (uint32_t faultMask)
+
+

The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
+
+FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:

+
    +
  1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
    2. +
  2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.
    3. +
+
Parameters
+ + +
[in]faultMaskFAULTMASK register value to set
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • +
  • When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
    • +
  • Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
    • +
  • When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_FPSCR (uint32_t fpscr)
+
+

The function sets the Floating-Point Status Control Register (FPSCR) value.
+
+FPSCR provides all necessary User level control of the floating-point system.
+

+
    +
  • N (FPSC[31]) (Negative flag)
      +
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • +
    • =0 The instruction result has a positive value or equal zero.
      +
      +
      • +
    +
    • +
  • Z (FPSC[30]) (Zero flag)
      +
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
      +
      +
      • +
    +
    • +
  • C (FPSC[29]) (Carry or borrow flag)
      +
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • +
    • =inverse of borrow output status For unsigned subtract operations.
      +
      +
      • +
    +
    • +
  • V (FPSC[28]) (Overflow flag)
      +
    • =1 A signed overflow occurred (for signed additions or subtractions).
      +
      +
      • +
    +
    • +
  • AHP (FPSC[26]) (Alternative half-precision flag)
      +
    • =1 Alternative half-precision format selected.
      • +
    • =0 IEEE half-precision format selected.
      +
      +
      • +
    +
    • +
  • DN (FPSC[25]) (Default NaN mode control flag)
      +
    • =1 Any operation involving one or more NaNs returns the Default NaN.
      • +
    • =0 NaN operands propagate through to the output of a floating-point operation.
      +
      +
      • +
    +
    • +
  • FZ (FPSC[24]) (Flush-to-zero mode control flag)
      +
    • =1 Flush-to-zero mode enabled.
      • +
    • =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
      +
      +
      • +
    +
    • +
  • RMode (FPSC[23:22]) (Rounding Mode control flags)
      +
    • =0b00 Round to Nearest (RN) mode.
      • +
    • =0b01 Round towards Plus Infinity (RP) mode.
      • +
    • =0b10 Round towards Minus Infinity (RM) mode.
      • +
    • =0b11 Round towards Zero (RZ) mode.
      • +
    • The specified rounding mode is used by almost all floating-point instructions.
      +
      +
      • +
    +
    • +
  • IDC (FPSC[7]) (Input Denormal cumulative exception flags)
      +
    • See Cumulative exception bits (FPSC[4:0]).
      +
      +
      • +
    +
    • +
  • IXC (FPSC[4]) (Inexact cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • UFC (FPSC[3]) (Underflow cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • OFC (FPSC[2]) (Overflow cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • DZC (FPSC[1]) (Division by Zero cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      • +
    +
    • +
+
Parameters
+ + +
[in]fpscrFPSCR value to set
+
+
+
Remarks
    +
  • Only for Cortex-M4 and Cortex-M7.
    • +
  • The variable __FPU_PRESENT has to be set to 1.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_MSP (uint32_t topOfMainStack)
+
+

The function sets the Main Status Pointer (MSP) value using the instruction MSR.
+
+Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Parameters
+ + +
[in]topOfMainStackMSP value to set
+
+
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
__set_MSPLIM (uint32_t MainStackPtrLimit)
+
+

Assigns the given value to the Main Stack Pointer Limit (MSPLIM).

+
Parameters
+ + +
[in]MainStackPtrLimitMain Stack Pointer Limit value to set
+
+
+
Note
Only availabe for Armv8-M Architecture.
+ +
+
+ +
+
+ + + + + + + + +
void __set_PRIMASK (uint32_t priMask)
+
+

The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
+
+PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Parameters
+ + +
[in]priMaskPriority Mask
    +
  • =0 no effect
    • +
  • =1 prevents the activation of all exceptions with configurable priority
    • +
+
+
+
+
Remarks
    +
  • When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
    • +
  • When set and a fault occurs, the hard fault handler will be executed.
    • +
  • Useful for temprorarily disabling all interrupts for timing critical tasks.
    • +
  • Does not have the ability to mask BusFault or bypass MPU.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_PSP (uint32_t topOfProcStack)
+
+

The function sets the Program Status Pointer (PSP) value using the instruction MSR.
+
+Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Parameters
+ + +
[in]topOfProcStackPSP value to set
+
+
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_PSPLIM (uint32_t ProcStackPtrLimit)
+
+

Assigns the given value to the Process Stack Pointer Limit (PSPLIM).

+
Parameters
+ + +
[in]ProcStackPtrLimitProcess Stack Pointer Limit value to set
+
+
+
Note
Only availabe for Armv8-M Architecture.
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__Core__Register__gr.js b/docs/Core/html/group__Core__Register__gr.js new file mode 100644 index 0000000..b3641ea --- /dev/null +++ b/docs/Core/html/group__Core__Register__gr.js @@ -0,0 +1,29 @@ +var group__Core__Register__gr = +[ + [ "__disable_fault_irq", "group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939", null ], + [ "__disable_irq", "group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013", null ], + [ "__enable_fault_irq", "group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf", null ], + [ "__enable_irq", "group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27", null ], + [ "__get_APSR", "group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7", null ], + [ "__get_BASEPRI", "group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667", null ], + [ "__get_CONTROL", "group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7", null ], + [ "__get_FAULTMASK", "group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8", null ], + [ "__get_FPSCR", "group__Core__Register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905", null ], + [ "__get_IPSR", "group__Core__Register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8", null ], + [ "__get_MSP", "group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2", null ], + [ "__get_MSPLIM", "group__Core__Register__gr.html#gaf39856ca50fc88cf459031b44eb2521c", null ], + [ "__get_PRIMASK", "group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02", null ], + [ "__get_PSP", "group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9", null ], + [ "__get_PSPLIM", "group__Core__Register__gr.html#ga8b226929264e903c7019e326b42bef47", null ], + [ "__get_xPSR", "group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd", null ], + [ "__set_BASEPRI", "group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882", null ], + [ "__set_BASEPRI_MAX", "group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9", null ], + [ "__set_CONTROL", "group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c", null ], + [ "__set_FAULTMASK", "group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a", null ], + [ "__set_FPSCR", "group__Core__Register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b", null ], + [ "__set_MSP", "group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4", null ], + [ "__set_MSPLIM", "group__Core__Register__gr.html#ga6809a07c5cb7410e361f3fba57f72172", null ], + [ "__set_PRIMASK", "group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f", null ], + [ "__set_PSP", "group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743", null ], + [ "__set_PSPLIM", "group__Core__Register__gr.html#ga4348d14fc5eefbfd34ab8c51be44a81b", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__Dcache__functions__m7.html b/docs/Core/html/group__Dcache__functions__m7.html new file mode 100644 index 0000000..619e877 --- /dev/null +++ b/docs/Core/html/group__Dcache__functions__m7.html @@ -0,0 +1,356 @@ + + + + + +D-Cache Functions +CMSIS-Core (Cortex-M): D-Cache Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
D-Cache Functions
Cache Functions (only Cortex-M7)
+
+
+ +

Functions for the data cache. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void SCB_EnableDCache (void)
 Enable D-Cache. More...
 
__STATIC_INLINE void SCB_DisableDCache (void)
 Disable D-Cache. More...
 
__STATIC_INLINE void SCB_InvalidateDCache (void)
 Invalidate D-Cache. More...
 
__STATIC_INLINE void SCB_CleanDCache (void)
 Clean D-Cache. More...
 
__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
 Clean & Invalidate D-Cache. More...
 
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
 D-Cache Invalidate by address. More...
 
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
 D-Cache Clean by address. More...
 
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
 D-Cache Clean and Invalidate by address. More...
 
+

Description

+

// close ICache functions

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_CleanDCache (void )
+
+

The function cleans the entire data cache.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t * addr,
int32_t dsize 
)
+
+
Parameters
+ + + +
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)
+
+
+

The function cleans a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundry.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_CleanInvalidateDCache (void )
+
+

The function cleans and invalidates the entire data cache.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t * addr,
int32_t dsize 
)
+
+
Parameters
+ + + +
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)
+
+
+

The function invalidates and cleans a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundry.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_DisableDCache (void )
+
+

The function turns off the entire data cache.

+
Note
When disabling the data cache, you must clean (SCB_CleanDCache) the entire cache to ensure that any dirty data is flushed to external memory.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_EnableDCache (void )
+
+

The function turns on the entire data cache.

+
Note
Before enabling the data cache, you must invalidate the entire data cache (SCB_InvalidateDCache), because external memory might have changed from when the cache was disabled.
+
+After reset, you must invalidate (SCB_InvalidateDCache) each cache before enabling it.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_InvalidateDCache (void )
+
+

The function invalidates the entire data cache.

+
Note
After reset, you must invalidate each cache before enabling (SCB_EnableDCache) it.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t * addr,
int32_t dsize 
)
+
+
Parameters
+ + + +
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)
+
+
+

The function invalidates a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundry.

+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__Dcache__functions__m7.js b/docs/Core/html/group__Dcache__functions__m7.js new file mode 100644 index 0000000..e05fce2 --- /dev/null +++ b/docs/Core/html/group__Dcache__functions__m7.js @@ -0,0 +1,11 @@ +var group__Dcache__functions__m7 = +[ + [ "SCB_CleanDCache", "group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c", null ], + [ "SCB_CleanDCache_by_Addr", "group__Dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d", null ], + [ "SCB_CleanInvalidateDCache", "group__Dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c", null ], + [ "SCB_CleanInvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e", null ], + [ "SCB_DisableDCache", "group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe", null ], + [ "SCB_EnableDCache", "group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6", null ], + [ "SCB_InvalidateDCache", "group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6", null ], + [ "SCB_InvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__ITM__Debug__gr.html b/docs/Core/html/group__ITM__Debug__gr.html new file mode 100644 index 0000000..be926f1 --- /dev/null +++ b/docs/Core/html/group__ITM__Debug__gr.html @@ -0,0 +1,278 @@ + + + + + +Debug Access +CMSIS-Core (Cortex-M): Debug Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
Debug Access
+
+
+ +

Debug Access to the Instrumented Trace Macrocell (ITM) +More...

+ + + + + + + + + + + +

+Functions

uint32_t ITM_SendChar (uint32_t ch)
 Transmits a character via channel 0. More...
 
int32_t ITM_ReceiveChar (void)
 ITM Receive Character. More...
 
int32_t ITM_CheckChar (void)
 ITM Check Character. More...
 
+ + + + +

+Variables

volatile int32_t ITM_RxBuffer
 external variable to receive characters More...
 
+

Description

+

CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

+

The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
    • +
+
Remarks
    +
  • ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.
    • +
  • The ITM channel 0 can be enabled for the user task.
    • +
  • ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.
    • +
+
+
+

+ITM Debugger Support

+

A debugger may support a Debug (printf) Viewer window to display data.

+

Direction: Microcontroller –> Debugger:

+
    +
  • Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window.
    • +
+

Direction: Debugger –> Microcontroller:

+
    +
  • Check if ITM_RxBuffer variable is available (only performed once).
    • +
  • Read the character from the Debug (printf) Viewer window.
    • +
  • If ITM_RxBuffer is empty, write character to ITM_RxBuffer.
    • +
+
Note
The current solution does not use a buffer mechanism for transmitting the characters.
+
+

+Example:

+

Example for the usage of the ITM Channel 31 for RTOS Kernels:

+
// check if debugger connected and ITM channel enabled for tracing
+
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+
(ITM->TCR & ITM_TCR_ITMENA) &&
+
(ITM->TER & (1UL >> 31))) {
+
+
// transmit trace data
+
while (ITM->PORT31_U32 == 0);
+
ITM->PORT[31].u8 = task_id; // id of next task
+
while (ITM->PORT[31].u32 == 0);
+
ITM->PORT[31].u32 = task_status; // status information
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
int32_t ITM_CheckChar (void )
+
+

This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.

+
Returns
    +
  • =0 - No character available
    • +
  • =1 - Character available
    • +
+
+ +
+
+ +
+
+ + + + + + + + +
int32_t ITM_ReceiveChar (void )
+
+

This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Returns
    +
  • Received character
    • +
  • =1 - No character received
    • +
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t ITM_SendChar (uint32_t ch)
+
+

This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Parameters
+ + +
[in]chCharacter to transmit
+
+
+
Returns
Character to transmit
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
volatile int32_t ITM_RxBuffer
+
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__ITM__Debug__gr.js b/docs/Core/html/group__ITM__Debug__gr.js new file mode 100644 index 0000000..fd96124 --- /dev/null +++ b/docs/Core/html/group__ITM__Debug__gr.js @@ -0,0 +1,7 @@ +var group__ITM__Debug__gr = +[ + [ "ITM_CheckChar", "group__ITM__Debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535", null ], + [ "ITM_ReceiveChar", "group__ITM__Debug__gr.html#ga37b8f41cae703b5ff6947e271065558c", null ], + [ "ITM_SendChar", "group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1", null ], + [ "ITM_RxBuffer", "group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__Icache__functions__m7.html b/docs/Core/html/group__Icache__functions__m7.html new file mode 100644 index 0000000..f1215a6 --- /dev/null +++ b/docs/Core/html/group__Icache__functions__m7.html @@ -0,0 +1,203 @@ + + + + + +I-Cache Functions +CMSIS-Core (Cortex-M): I-Cache Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
I-Cache Functions
Cache Functions (only Cortex-M7)
+
+
+ +

Functions for the instruction cache. +More...

+ + + + + + + + + + + +

+Functions

__STATIC_INLINE void SCB_EnableICache (void)
 Enable I-Cache. More...
 
__STATIC_INLINE void SCB_DisableICache (void)
 Disable I-Cache. More...
 
__STATIC_INLINE void SCB_InvalidateICache (void)
 Invalidate I-Cache. More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_DisableICache (void )
+
+

The function turns off the instruction cache.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_EnableICache (void )
+
+

The function turns on the instruction cache.

+
Note
Before enabling the instruction cache, you must invalidate (SCB_InvalidateICache) the entire instruction cache if external memory might have changed since the cache was disabled.
+
+After reset, you must invalidate (SCB_InvalidateICache) each cache before enabling it.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_InvalidateICache (void )
+
+

The function invalidates the instruction cache. The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction.

+
Note
After reset, you must invalidate each cache before enabling (SCB_EnableICache) it.
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__Icache__functions__m7.js b/docs/Core/html/group__Icache__functions__m7.js new file mode 100644 index 0000000..3e654b0 --- /dev/null +++ b/docs/Core/html/group__Icache__functions__m7.js @@ -0,0 +1,6 @@ +var group__Icache__functions__m7 = +[ + [ "SCB_DisableICache", "group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8", null ], + [ "SCB_EnableICache", "group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68", null ], + [ "SCB_InvalidateICache", "group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__NVIC__gr.html b/docs/Core/html/group__NVIC__gr.html new file mode 100644 index 0000000..37b03e6 --- /dev/null +++ b/docs/Core/html/group__NVIC__gr.html @@ -0,0 +1,1425 @@ + + + + + +Interrupts and Exceptions (NVIC) +CMSIS-Core (Cortex-M): Interrupts and Exceptions (NVIC) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Enumerations | +Functions
+
+
Interrupts and Exceptions (NVIC)
+
+
+ +

Functions to access the Nested Vector Interrupt Controller (NVIC). +More...

+ + + + + + + + +

+Macros

#define CMSIS_NVIC_VIRTUAL
 Virtualization of the NVIC API. More...
 
#define CMSIS_VECTAB_VIRTUAL
 Virtualization of interrupt vector table access functions. More...
 
+ + + + +

+Enumerations

enum  IRQn_Type {
+  NonMaskableInt_IRQn = -14, +
+  HardFault_IRQn = -13, +
+  MemoryManagement_IRQn = -12, +
+  BusFault_IRQn = -11, +
+  UsageFault_IRQn = -10, +
+  SecureFault_IRQn = -9, +
+  SVCall_IRQn = -5, +
+  DebugMonitor_IRQn = -4, +
+  PendSV_IRQn = -2, +
+  SysTick_IRQn = -1, +
+  WWDG_STM_IRQn = 0, +
+  PVD_STM_IRQn = 1 +
+ }
 Definition of IRQn numbers. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t NVIC_GetPriorityGrouping (void)
 Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable a device specific interrupt. More...
 
uint32_t NVIC_GetEnableIRQ (IRQn_Type IRQn)
 Get a device specific interrupt enable status. More...
 
void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable a device specific interrupt. More...
 
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get the pending device specific interrupt. More...
 
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set a device specific interrupt to pending. More...
 
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear a device specific interrupt from pending. More...
 
uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for an interrupt. More...
 
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get the priority of an interrupt. More...
 
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t NVIC_GetVector (IRQn_Type IRQn)
 Read Interrupt Vector [not for Cortex-M0, SC000]. More...
 
void NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
 Modify Interrupt Vector [not for Cortex-M0, SC000]. More...
 
void NVIC_SystemReset (void)
 Reset the system. More...
 
uint32_t NVIC_GetTargetState (IRQn_Type IRQn)
 Get Interrupt Target State. More...
 
uint32_t NVIC_SetTargetState (IRQn_Type IRQn)
 Set Interrupt Target State. More...
 
uint32_t NVIC_ClearTargetState (IRQn_Type IRQn)
 Clear Interrupt Target State. More...
 
+

Description

+

This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).

+

Arm provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.

+

The table below lists the core exception vectors of the various Cortex-M processors.

+ + + + + + + + + + + + + + + + + + + + + + + +
Exception Vector IRQn
+Value 		M0 M0+ M3 M4 M7 SC000 SC300 Armv8-M
+Baseline 		Armv8-M
+Mainline 		Description
NonMaskableInt_IRQn -14
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Non Maskable Interrupt
HardFault_IRQn -13
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Hard Fault Interrupt
MemoryManagement_IRQn -12    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Memory Management Interrupt
BusFault_IRQn -11    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Bus Fault Interrupt
UsageFault_IRQn -10    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Usage Fault Interrupt
SecureFault_IRQn -9              
+available +
+
+available +
+ 		Secure Fault Interrupt
SVCall_IRQn -5
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		SV Call Interrupt
DebugMonitor_IRQn -4    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Debug Monitor Interrupt
PendSV_IRQn -2
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Pend SV Interrupt
SysTick_IRQn -1
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		System Tick Interrupt
+

Vector Table

+

The Vector Table defines the entry addresses of the processor exceptions and the device specific interrupts. It is typically located at the beginning of the program memory, however Using Interrupt Vector Remap it can be relocated to RAM. The symbol __Vectors is the address of the vector table in the startup code and the register SCB->VTOR holds the start address of the vector table.

+

An Armv8-M implementation with TrustZone provides two vector tables:

+
    +
  • vector table for Secure handlers
    • +
  • vector table for Non-Secure handlers
    • +
+

Refer to Programmers Model with TrustZone for more information.

+

Processor Exceptions

+

At the beginning of the vector table, the initial stack value and the exception vectors of the processor are defined. The vector table below shows the exception vectors of a Armv8-M Mainline processor. Other processor variants may have fewer vectors.

+
__Vectors DCD __initial_sp ; Top of Stack initialization
+
DCD Reset_Handler ; Reset Handler
+
DCD NMI_Handler ; NMI Handler
+
DCD HardFault_Handler ; Hard Fault Handler
+
DCD MemManage_Handler ; MPU Fault Handler
+
DCD BusFault_Handler ; Bus Fault Handler
+
DCD UsageFault_Handler ; Usage Fault Handler
+
DCD SecureFault_Handler ; Secure Fault Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD SVC_Handler ; SVCall Handler
+
DCD DebugMon_Handler ; Debug Monitor Handler
+
DCD 0 ; Reserved
+
DCD PendSV_Handler ; PendSV Handler
+
DCD SysTick_Handler ; SysTick Handler
+

Device Specific Vectors

+

Following the processor exception vectors, the vector table contains also the device specific interrupt vectors.

+
; device specific interrupts
+
DCD WWDG_IRQHandler ; Window Watchdog
+
DCD PVD_IRQHandler ; PVD through EXTI Line detect
+
DCD TAMPER_IRQHandler ; Tamper
+

All device specific interrupts should have a default interrupt handler function that can be overwritten in user code. Below is an example for this default handler function.

+
Default_Handler PROC
+
EXPORT WWDG_IRQHandler [WEAK]
+
EXPORT PVD_IRQHandler [WEAK]
+
EXPORT TAMPER_IRQHandler [WEAK]
+
:
+
:
+
WWDG_IRQHandler
+
PVD_IRQHandler
+
TAMPER_IRQHandler
+
:
+
:
+
B .
+
ENDP
+

The user application may simply define an interrupt handler function by using the handler name as shown below.

+
void WWDG_IRQHandler(void)
+
{
+
...
+
}
+

NVIC Function Usage

+

The code below shows the usage of various CMSIS NVIC functions with an LPC1700 device.

+

Code Example 1

+
#include "LPC17xx.h"
+
+
uint32_t priorityGroup; /* Variables to store priority group and priority */
+
uint32_t priority;
+
uint32_t preemptPriority;
+
uint32_t subPriority;
+
+
int main (void) {
+
NVIC_SetPriorityGrouping(5); /* Set priority group to 5:
+
Bit[7..6] preempt priority Bits,
+
Bit[5..3] subpriority Bits
+
(valid for five priority bits) */
+
+
priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping */
+
+
priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority
+
Note: priority depends on the used priority grouping */
+
NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority */
+
+
priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again */
+
NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
+
+
while(1);
+
}
+

Code Example 2

+
#include "LPC17xx.h"
+
+
uint32_t active; /* Variable to store interrupt active state */
+
+
void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */
+
+
if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occured */
+
LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occured */
+
}
+
active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0 */
+
}
+
+
int main (void) {
+
/* Set match channel register MR0 to 1 millisecond */
+
LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms? */
+
+
LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0 */
+
NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0 */
+
LPC_TIM0->TCR = (1 << 0); /* Enable timer 0 */
+
+
while(1);
+
}
+

NVIC API Virtualization

+

The CMSIS-Core has provisions for overriding NVIC APIs as required for implementing secure systems that control access to peripherals and related interrupts. These overrides allow an operating system to control the access privileges of application code to critical interrupts.

+

The NVIC function virtualization is enabled with the following #define symbols:

+
    +
  • CMSIS_NVIC_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) NVIC functions.
    • +
  • CMSIS_VECTAB_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions.
    • +
+

Macro Definition Documentation

+ +
+
+ + + + +
#define CMSIS_NVIC_VIRTUAL
+
+

When CMSIS_NVIC_VIRTUAL is defined, the NVIC access functions in the table below must be implemented for virtualizing NVIC access. These functions should be implemented in a separate source module. The original CMSIS-Core __NVIC functions are always available independent of CMSIS_NVIC_VIRTUAL.

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NVIC Access Functions CMSIS-Core Functions
NVIC_EnableIRQ __NVIC_EnableIRQ
NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NVIC_DisableIRQ __NVIC_DisableIRQ
NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NVIC_GetActive __NVIC_GetActive
NVIC_SetPriority __NVIC_SetPriority
NVIC_GetPriority __NVIC_GetPriority
NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ +
+
+ +
+
+ + + + +
#define CMSIS_VECTAB_VIRTUAL
+
+

When CMSIS_NVIC_VIRTUAL is defined, the functions in the table below must be replaced to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.

+

The original CMSIS-Core functions are always available, but prefixed with __NVIC.

+ + + + + + + +
Interrupt Vector Table Access CMSIS-Core Functions
NVIC_GetVector __NVIC_GetVector
NVIC_SetVector __NVIC_SetVector
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn_Type
+
+

The core exception enumeration names for IRQn values are defined in the file device.h.

+
    +
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • +
  • Positive IRQn values represent device-specific exceptions (external interrupts).
    • +
  • The first device-specific interrupt has the IRQn value 0.
    • +
+

The table below describes the core exception names and their availability in various Cortex-M cores.

+ + + + + + + + + + + + + +
Enumerator
NonMaskableInt_IRQn  +

Exception 2: Non Maskable Interrupt.

+
HardFault_IRQn  +

Exception 3: Hard Fault Interrupt.

+
MemoryManagement_IRQn  +

Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].

+
BusFault_IRQn  +

Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].

+
UsageFault_IRQn  +

Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].

+
SecureFault_IRQn  +

Exception 7: Secure Fault Interrupt [only on Armv8-M].

+
SVCall_IRQn  +

Exception 11: SV Call Interrupt.

+
DebugMonitor_IRQn  +

Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].

+
PendSV_IRQn  +

Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].

+
SysTick_IRQn  +

Exception 15: System Tick Interrupt.

+
WWDG_STM_IRQn  +

Device Interrupt 0: Window WatchDog Interrupt.

+
PVD_STM_IRQn  +

Device Interrupt 1: PVD through EXTI Line detection Interrupt.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
+
+

This function removes the pending state of the specified device specific interrupt IRQn. IRQn cannot be a negative number.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
  • An interrupt can have the status pending though it is not active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_ClearTargetState (IRQn_Type IRQn)
+
+

Clears the interrupt target field in the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
Returns
    +
  • 0 if interrupt is assigned to Secure
    • +
  • 1 if interrupt is assigned to Non Secure
    • +
+
+
Remarks
    +
  • Only available for Armv8-M in secure state.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void NVIC_DecodePriority (uint32_t Priority,
uint32_t PriorityGroup,
uint32_t * pPreemptPriority,
uint32_t * pSubPriority 
)
+
+

This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + + +
[in]PriorityPriority
[in]PriorityGroupPriority group
[out]*pPreemptPriorityPreemptive priority value (starting from 0)
[out]*pSubPrioritySubpriority value (starting from 0)
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_DisableIRQ (IRQn_Type IRQn)
+
+

This function disables the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnNumber of the external interrupt to disable
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_EnableIRQ (IRQn_Type IRQn)
+
+

This function enables the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
  • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
    + ICTR[4:0]
      +
    • 0 - 32 interrupts supported
      • +
    • 1 - 64 interrupts supported
      • +
    • ...
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
uint32_t PreemptPriority,
uint32_t SubPriority 
)
+
+

This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + +
[in]PriorityGroupPriority group
[in]PreemptPriorityPreemptive priority value (starting from 0)
[in]SubPrioritySubpriority value (starting from 0)
+
+
+
Returns
Encoded priority for the interrupt
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetActive (IRQn_Type IRQn)
+
+

This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • 0 Interrupt is not active
    • +
  • 1 Interrupt is active, or active and pending
    • +
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • IRQn must not be negative.
    • +
  • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
    • +
  • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetEnableIRQ (IRQn_Type IRQn)
+
+

This function returns the interrupt enable status for the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • 0 Interrupt is not enabled
    • +
  • 1 Interrupt is pending
    • +
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
+
+

This function returns the pending status of the specified device specific interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • 0 Interrupt is not pending
    • +
  • 1 Interrupt is pending
    • +
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
+
+

This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device specific interrupt, or processor exception.

+

The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
Interrupt priority
+
Remarks
    +
  • Each external interrupt has an associated priority-level register.
    • +
  • Unimplemented bits are read as zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriorityGrouping (void )
+
+

This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).

+
Returns
Priority grouping field
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetTargetState (IRQn_Type IRQn)
+
+

Reads the interrupt target field from the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
Returns
    +
  • 0 if interrupt is assigned to Secure
    • +
  • 1 if interrupt is assigned to Non Secure
    • +
+
+
Remarks
    +
  • Only available for Armv8-M in secure state.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetVector (IRQn_Type IRQn)
+
+

This function allows to read the address of an interrupt handler function.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
Address of interrupt handler function
+
Remarks
    +
  • For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
+
+

This function sets the pending bit for the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SetPriority (IRQn_Type IRQn,
uint32_t priority 
)
+
+

Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device specific interrupt, or processor exception. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.

+

The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.

+
Parameters
+ + + +
[in]IRQnInterrupt Number
[in]priorityPriority to set
+
+
+
Remarks
    +
  • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
    • +
  • Writes to unimplemented bits are ignored.
    • +
  • For Cortex-M0:
      +
    • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
      • +
    • Supports 0 to 192 priority levels.
      • +
    • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
      • +
    +
    • +
  • For Cortex-M3, Cortex-M4, and Cortex-M7:
      +
    • Dynamic switching of interrupt priority levels is supported.
      • +
    • Supports 0 to 255 priority levels.
      • +
    • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
+
+

The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+
Parameters
+ + +
[in]PriorityGroupPriority group
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_SetTargetState (IRQn_Type IRQn)
+
+

Sets the interrupt target field in the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
Returns
    +
  • 0 if interrupt is assigned to Secure
    • +
  • 1 if interrupt is assigned to Non Secure
    • +
+
+
Remarks
    +
  • Only available for Armv8-M in secure state.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SetVector (IRQn_Type IRQn,
uint32_t vector 
)
+
+

This function allows to change the address of an interrupt handler function.

+
Parameters
+ + + +
[in]IRQnInterrupt number
[in]vectorAddress of new interrupt handler function
+
+
+
Remarks
    +
  • Usage of this function requires vector relocation to RAM. Refer to Using Interrupt Vector Remap for more information.
      +
    • For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SystemReset (void )
+
+

This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.

+
Remarks
    +
  • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
    • +
+
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__NVIC__gr.js b/docs/Core/html/group__NVIC__gr.js new file mode 100644 index 0000000..09a9dd1 --- /dev/null +++ b/docs/Core/html/group__NVIC__gr.js @@ -0,0 +1,38 @@ +var group__NVIC__gr = +[ + [ "CMSIS_NVIC_VIRTUAL", "group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c", null ], + [ "CMSIS_VECTAB_VIRTUAL", "group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d", null ], + [ "IRQn_Type", "group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8", [ + [ "NonMaskableInt_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30", null ], + [ "HardFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85", null ], + [ "MemoryManagement_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa", null ], + [ "BusFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af", null ], + [ "UsageFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf", null ], + [ "SecureFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da", null ], + [ "SVCall_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237", null ], + [ "DebugMonitor_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c", null ], + [ "PendSV_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2", null ], + [ "SysTick_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7", null ], + [ "WWDG_STM_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2", null ], + [ "PVD_STM_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86", null ] + ] ], + [ "NVIC_ClearPendingIRQ", "group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a", null ], + [ "NVIC_ClearTargetState", "group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b", null ], + [ "NVIC_DecodePriority", "group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377", null ], + [ "NVIC_DisableIRQ", "group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c", null ], + [ "NVIC_EnableIRQ", "group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f", null ], + [ "NVIC_EncodePriority", "group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5", null ], + [ "NVIC_GetActive", "group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892", null ], + [ "NVIC_GetEnableIRQ", "group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3", null ], + [ "NVIC_GetPendingIRQ", "group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662", null ], + [ "NVIC_GetPriority", "group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395", null ], + [ "NVIC_GetPriorityGrouping", "group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78", null ], + [ "NVIC_GetTargetState", "group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746", null ], + [ "NVIC_GetVector", "group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af", null ], + [ "NVIC_SetPendingIRQ", "group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2", null ], + [ "NVIC_SetPriority", "group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798", null ], + [ "NVIC_SetPriorityGrouping", "group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354", null ], + [ "NVIC_SetTargetState", "group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a", null ], + [ "NVIC_SetVector", "group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916", null ], + [ "NVIC_SystemReset", "group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__SysTick__gr.html b/docs/Core/html/group__SysTick__gr.html new file mode 100644 index 0000000..2bf6619 --- /dev/null +++ b/docs/Core/html/group__SysTick__gr.html @@ -0,0 +1,192 @@ + + + + + +Systick Timer (SYSTICK) +CMSIS-Core (Cortex-M): Systick Timer (SYSTICK) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Systick Timer (SYSTICK)
+
+
+ +

Initialize and start the SysTick timer. +More...

+ + + + + +

+Functions

uint32_t SysTick_Config (uint32_t ticks)
 System Tick Timer Configuration. More...
 
+

Description

+

The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.

+

+Code Example

+

The code below shows the usage of the function SysTick_Config() with an LPC1700.

+
#include "LPC17xx.h"
+
+
volatile uint32_t msTicks = 0; /* Variable to store millisecond ticks */
+
+
void SysTick_Handler(void) { /* SysTick interrupt Handler. */
+
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
+
}
+
+
int main (void) {
+
uint32_t returnCode;
+
+
returnCode = SysTick_Config(SystemCoreClock / 1000); /* Configure SysTick to generate an interrupt every millisecond */
+
+
if (returnCode != 0) { /* Check return code for errors */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t SysTick_Config (uint32_t ticks)
+
+

Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.

+
Parameters
+ + +
[in]ticksNumber of ticks between two interrupts
+
+
+
Returns
0 - success
+
+1 - failure
+
Note
When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__SysTick__gr.js b/docs/Core/html/group__SysTick__gr.js new file mode 100644 index 0000000..12d20c3 --- /dev/null +++ b/docs/Core/html/group__SysTick__gr.js @@ -0,0 +1,4 @@ +var group__SysTick__gr = +[ + [ "SysTick_Config", "group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__cache__functions__m7.html b/docs/Core/html/group__cache__functions__m7.html new file mode 100644 index 0000000..fb9cf3a --- /dev/null +++ b/docs/Core/html/group__cache__functions__m7.html @@ -0,0 +1,152 @@ + + + + + +Cache Functions (only Cortex-M7) +CMSIS-Core (Cortex-M): Cache Functions (only Cortex-M7) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content
+
+
Cache Functions (only Cortex-M7)
+
+
+ +

Functions for Instruction and Data Cache. +More...

+ + + + + + + + +

+Content

 I-Cache Functions
 Functions for the instruction cache.
 
 D-Cache Functions
 Functions for the data cache.
 
+

Description

+

Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of [0;4;8;16;32;64]KB. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.

+

All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.

+
Note
After reset, you must invalidate each cache before enabling it.
+

The functions are grouped for:

+ +
+
+ + + + diff --git a/docs/Core/html/group__cache__functions__m7.js b/docs/Core/html/group__cache__functions__m7.js new file mode 100644 index 0000000..a1f8eb0 --- /dev/null +++ b/docs/Core/html/group__cache__functions__m7.js @@ -0,0 +1,5 @@ +var group__cache__functions__m7 = +[ + [ "I-Cache Functions", "group__Icache__functions__m7.html", "group__Icache__functions__m7" ], + [ "D-Cache Functions", "group__Dcache__functions__m7.html", "group__Dcache__functions__m7" ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__compiler__conntrol__gr.html b/docs/Core/html/group__compiler__conntrol__gr.html new file mode 100644 index 0000000..ffbe33a --- /dev/null +++ b/docs/Core/html/group__compiler__conntrol__gr.html @@ -0,0 +1,533 @@ + + + + + +Compiler Control +CMSIS-Core (Cortex-M): Compiler Control + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Compiler Control
+
+
+ +

Compiler agnostic #define symbols for generic C/C++ source code. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Macros

#define __ARM_ARCH_6M__
 Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1) More...
 
#define __ARM_ARCH_7M__
 Set to 1 when generating code for Armv7-M (Cortex-M3) More...
 
#define __ARM_ARCH_7EM__
 Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU. More...
 
#define __ARM_ARCH_8M_BASE__
 Set to 1 when generating code for Armv8-M Baseline. More...
 
#define __ARM_ARCH_8M_MAIN__
 Set to 1 when generating code for Armv8-M Mainline. More...
 
#define __ASM
 Pass information from the compiler to the assembler. More...
 
#define __INLINE
 Recommend that function should be inlined by the compiler. More...
 
#define __STATIC_INLINE
 Define a static function should be inlined by the compiler. More...
 
#define __NO_RETURN
 Inform the compiler that a function does not return. More...
 
#define __USED
 Inform that a variable shall be retained in executable image. More...
 
#define __WEAK
 Export a function or variable weakly to allow overwrites. More...
 
#define __PACKED
 Request smallest possible alignment. More...
 
#define __PACKED_STRUCT
 Request smallest possible alignment for a structure. More...
 
#define __UNALIGNED_UINT32
 Pointer for unaligned access of a uint32_t variable. More...
 
#define __UNALIGNED_UINT16_READ
 Pointer for unaligned read of a uint16_t variable. More...
 
#define __UNALIGNED_UINT16_WRITE
 Pointer for unaligned write of a uint16_t variable. More...
 
#define __UNALIGNED_UINT32_READ
 Pointer for unaligned read of a uint32_t variable. More...
 
#define __UNALIGNED_UINT32_WRITE
 Pointer for unaligned write of a uint32_t variable. More...
 
#define __ALIGNED
 Minimum alignment for a variable. More...
 
+

Description

+

The CMSIS-Core provides the header file cmsis_compiler.h with consistent #define symbols for generate C or C++ source files that should be compiler agnostic. Each CMSIS compliant compiler should support the functionality described in this section.

+

The header file cmsis_compiler.h is also included by each Device Header File <device.h> so that these definitions are available.

+

Macro Definition Documentation

+ +
+
+ + + + +
#define __ALIGNED
+
+

Specifies a minimum alignment for a variable or structure field, measured in bytes.

+

Code Example:

+
uint32_t stack_space[0x100] __ALIGNED(8); // 8-byte alignment required
+
+
+
+ +
+
+ + + + +
#define __ARM_ARCH_6M__
+
+

The #define ARM_ARCH_6M is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.

+ +
+
+ +
+
+ + + + +
#define __ARM_ARCH_7EM__
+
+

The #define ARM_ARCH_7EM is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU

+ +
+
+ +
+
+ + + + +
#define __ARM_ARCH_7M__
+
+

The #define ARM_ARCH_7M is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor.

+ +
+
+ +
+
+ + + + +
#define __ARM_ARCH_8M_BASE__
+
+

The #define ARM_ARCH_8M_BASE is set to 1 when generating code for the Armv8-M architecture baseline variant.

+ +
+
+ +
+
+ + + + +
#define __ARM_ARCH_8M_MAIN__
+
+

The #define ARM_ARCH_8M_MAIN is set to 1 when generating code for the Armv8-M architecture mainline variant.

+ +
+
+ +
+
+ + + + +
#define __ASM
+
+

The __ASM keyword can declare or define an embedded assembly function or incorporate inline assembly into a function (shown in the code example below).

+

Code Example:

+
// Reverse bit order of value
+
+
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+
{
+
uint32_t result;
+
+
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+
return(result);
+
}
+
+
+
+ +
+
+ + + + +
#define __INLINE
+
+

Inline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to inline code or not. The __INLINE attribute gives the compiler an hint to inline this function. Still, the compiler may decide not to inline the function. As the function is global an callable function is also generated.

+

Code Example:

+
const uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};
+
+
/*------------------------------------------------------------------------------
+
Switch on LEDs
+
*------------------------------------------------------------------------------*/
+
__INLINE static void LED_On (uint32_t led) {
+
+
PTD->PCOR = led_mask[led];
+
}
+
+
+
+ +
+
+ + + + +
#define __NO_RETURN
+
+

Informs the compiler that the function does not return. The compiler can then perform optimizations by removing code that is never reached.

+

Code Example:

+
// OS idle demon (running when no other thread is ready to run).
+
+
__NO_RETURN void os_idle_demon (void);
+
+
+
+ +
+
+ + + + +
#define __PACKED
+
+

Specifies that a type must have the smallest possible alignment.

+

Code Example:

+
struct foo {
+
uint8_t u8;
+
uint32_t u32[2] __PACKED;
+
};
+
+
+
+ +
+
+ + + + +
#define __PACKED_STRUCT
+
+

Specifies that a structure must have the smallest possible alignment.

+

Code Example:

+
__PACKED_STRUCT foo {
+
uint8_t u8;
+
uint32_t u32;
+
uint16_t u16;
+
};
+
+
+
+ +
+
+ + + + +
#define __STATIC_INLINE
+
+

Defines a static function that may be inlined by the compiler. If the compiler generates inline code for all calls to this functions, no additional function implementation is generated which may further optimize space.

+

Code Example:

+
\\ Get Interrupt Vector
+
__STATIC_INLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)
+
{
+
uint32_t *vectors = (uint32_t *)SCB->VTOR;
+
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
}
+
+
+
+ +
+
+ + + + +
#define __UNALIGNED_UINT16_READ
+
+

Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.

+

Code Example:

+
uint16_t val16;
+
+
void test (uint8_t *ptr) {
+
val16 = __UNALIGNED_UINT16_READ(ptr);
+
}
+
+
+
+ +
+
+ + + + +
#define __UNALIGNED_UINT16_WRITE
+
+

Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.

+

Code Example:

+
uint16_t val16 = 0U;
+
+
void test (uint8_t *ptr) {
+
__UNALIGNED_UINT16_WRITE(ptr, val16);
+
}
+
+
+
+ +
+
+ + + + +
#define __UNALIGNED_UINT32
+
+
Deprecated:
Do not use this macro. It has been superseded by __UNALIGNED_UINT32_READ, __UNALIGNED_UINT32_WRITE and will be removed in the future.
+

Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.

+

Code Example:

+
uint32_t val32;
+
+
void test (uint8_t *ptr) {
+
__UNALIGNED_UINT32(ptr) = val32;
+
}
+
+
+
+ +
+
+ + + + +
#define __UNALIGNED_UINT32_READ
+
+

Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.

+

Code Example:

+
uint32_t val32;
+
+
void test (uint8_t *ptr) {
+
val32 = __UNALIGNED_UINT32_READ(ptr);
+
}
+
+
+
+ +
+
+ + + + +
#define __UNALIGNED_UINT32_WRITE
+
+

Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.

+

Code Example:

+
uint32_t val32 = 0U;
+
+
void test (uint8_t *ptr) {
+
__UNALIGNED_UINT32_WRITE(ptr, val32);
+
}
+
+
+
+ +
+
+ + + + +
#define __USED
+
+

Definitions tagged with __USED in the source code should be not removed by the linker when detected as unused.

+

Code Example:

+
/* Export following variables for debugging */
+
__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
+
__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
+
__USED uint32_t const os_clockrate = OS_TICK;
+
__USED uint32_t const os_timernum = 0;
+
+
+
+ +
+
+ + + + +
#define __WEAK
+
+

Functions defined with __WEAK export their symbols weakly. A weakly defined function behaves like a normally defined function unless a non-weakly defined function of the same name is linked into the same image. If both a non-weakly defined function and a weakly defined function exist in the same image then all calls to the function resolve to call the non-weak function.

+

Functions declared with __WEAK and then defined without __WEAK behave as non-weak functions.

+

Code Example:

+
__WEAK void SystemInit(void)
+
{
+
SystemCoreSetup();
+
SystemCoreClockSetup();
+
}
+
+
+
+
+
+ + + + diff --git a/docs/Core/html/group__compiler__conntrol__gr.js b/docs/Core/html/group__compiler__conntrol__gr.js new file mode 100644 index 0000000..87193e4 --- /dev/null +++ b/docs/Core/html/group__compiler__conntrol__gr.js @@ -0,0 +1,22 @@ +var group__compiler__conntrol__gr = +[ + [ "__ALIGNED", "group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849", null ], + [ "__ARM_ARCH_6M__", "group__compiler__conntrol__gr.html#ga8be4ebde5d4dd91b161d206545ce59aa", null ], + [ "__ARM_ARCH_7EM__", "group__compiler__conntrol__gr.html#ga43ab3e79ec5ecb615f1f2f6e83e7d48a", null ], + [ "__ARM_ARCH_7M__", "group__compiler__conntrol__gr.html#ga43e1af8bedda108dfc4f8584e6b278a2", null ], + [ "__ARM_ARCH_8M_BASE__", "group__compiler__conntrol__gr.html#gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a", null ], + [ "__ARM_ARCH_8M_MAIN__", "group__compiler__conntrol__gr.html#gad424c7143edd08c982dddad0ff65f4cd", null ], + [ "__ASM", "group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd", null ], + [ "__INLINE", "group__compiler__conntrol__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb", null ], + [ "__NO_RETURN", "group__compiler__conntrol__gr.html#ga153a4a31b276a9758959580538720a51", null ], + [ "__PACKED", "group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1", null ], + [ "__PACKED_STRUCT", "group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314", null ], + [ "__STATIC_INLINE", "group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c", null ], + [ "__UNALIGNED_UINT16_READ", "group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9", null ], + [ "__UNALIGNED_UINT16_WRITE", "group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407", null ], + [ "__UNALIGNED_UINT32", "group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268", null ], + [ "__UNALIGNED_UINT32_READ", "group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87", null ], + [ "__UNALIGNED_UINT32_WRITE", "group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b", null ], + [ "__USED", "group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0", null ], + [ "__WEAK", "group__compiler__conntrol__gr.html#gac607bf387b29162be6a9b77fc7999539", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__context__trustzone__functions.html b/docs/Core/html/group__context__trustzone__functions.html new file mode 100644 index 0000000..3bcaf37 --- /dev/null +++ b/docs/Core/html/group__context__trustzone__functions.html @@ -0,0 +1,271 @@ + + + + + +RTOS Context Management +CMSIS-Core (Cortex-M): RTOS Context Management + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
RTOS Context Management
TrustZone for Armv8-M
+
+
+ +

RTOS Thread Context Management for Armv8-M TrustZone. +More...

+ + + + + + + + + + + + + + + + + +

+Functions

uint32_t TZ_InitContextSystem_S (void)
 Initialize secure context memory system. More...
 
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module)
 Allocate context memory for calling secure software modules in TrustZone. More...
 
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id)
 Free context memory that was previously allocated with TZ_AllocModuleContext_S. More...
 
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id)
 Load secure context (called on RTOS thread context switch) More...
 
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id)
 Store secure context (called on RTOS thread context switch) More...
 
+

Description

+

The CMSIS-Core provides the file tz_context.h which defines an API to standardize the context memory system for real-time operating systems. For more information refer to RTOS Thread Context Management.

+

Function Documentation

+ +
+
+ + + + + + + + +
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module)
+
+

Allocates the secure memory regions for thread execution. The parameter module describes the set of secure functions that are called by the non-secure thread. Set module to zero if no secure calls are used/allowed. This leads to no secure memory to be assigned which results in zero being returned as memory id as well. This function should be called by an RTOS kernel at the start of a thread.

+
Parameters
+ + +
[in]moduleA non-zero value identifies software modules called from non-secure mode. zero is used if no secure calls are used/allowed.
+
+
+
Returns
value != 0 id TrustZone memory slot identify
+
+value 0 no memory available or internal error
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id)
+
+

De-allocates the secure memory regions. The parameter id refers to a TrustZone memory slot that has been obtained with TZ_AllocModuleContext_S. This function should be called by an RTOS kernel at the termination of a thread.

+
Parameters
+ + +
[in]idTrustZone memory slot identifier
+
+
+
Returns
execution status (1: success, 0: error)
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_InitContextSystem_S (void )
+
+

Initializes the memory allocation management for the secure memory regions. As a minimum the secure thread mode stack will be provided.

+
Returns
execution status (1: success, 0: error)
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id)
+
+

Prepare the secure context for execution so that a thread in the non-secure state can call secure library modules. The parameter id refers to a TrustZone memory slot that has been obtained with TZ_AllocModuleContext_S which might be zero if not used. This function should be called by an RTOS kernel at thread context switch before running a thread.

+
Parameters
+ + +
[in]idTrustZone memory slot identifier
+
+
+
Returns
execution status (1: success, 0: error)
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id)
+
+

Free the secure context that has been previously loaded with TZ_LoadContext_S. The parameter id refers to a TrustZone memory slot that has been obtained with TZ_AllocModuleContext_S which might be zero if not used. This function should be called by an RTOS kernel at thread context switch after running a thread.

+
Parameters
+ + +
[in]idTrustZone memory slot identifier
+
+
+
Returns
execution status (1: success, 0: error)
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__context__trustzone__functions.js b/docs/Core/html/group__context__trustzone__functions.js new file mode 100644 index 0000000..fa603e0 --- /dev/null +++ b/docs/Core/html/group__context__trustzone__functions.js @@ -0,0 +1,8 @@ +var group__context__trustzone__functions = +[ + [ "TZ_AllocModuleContext_S", "group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90", null ], + [ "TZ_FreeModuleContext_S", "group__context__trustzone__functions.html#gac84f678fbe974f8b02c683e0b8046524", null ], + [ "TZ_InitContextSystem_S", "group__context__trustzone__functions.html#ga926e2ec472535a6d2b8125be1a79e3c0", null ], + [ "TZ_LoadContext_S", "group__context__trustzone__functions.html#ga4748f6bcdd5fed279ac5a6cd7eca2689", null ], + [ "TZ_StoreContext_S", "group__context__trustzone__functions.html#gac106570f4905f82922fd335aeb08a1bf", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__coreregister__trustzone__functions.html b/docs/Core/html/group__coreregister__trustzone__functions.html new file mode 100644 index 0000000..84584ac --- /dev/null +++ b/docs/Core/html/group__coreregister__trustzone__functions.html @@ -0,0 +1,610 @@ + + + + + +Core Register Access Functions +CMSIS-Core (Cortex-M): Core Register Access Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Core Register Access Functions
TrustZone for Armv8-M
+
+
+ +

Core register Access functions related to TrustZone for Armv8-M. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __TZ_get_CONTROL_NS (void)
 Get Control register (non-secure) More...
 
void __TZ_set_CONTROL_NS (uint32_t control)
 Set Control register (non-secure) More...
 
uint32_t __TZ_get_PSP_NS (void)
 Get Process Stack Pointer (non-secure) More...
 
void __TZ_set_PSP_NS (uint32_t topOfProcStack)
 Set Process Stack Pointer (non-secure) More...
 
uint32_t __TZ_get_MSP_NS (void)
 Get Main Stack Pointer (non-secure) More...
 
void __TZ_set_MSP_NS (uint32_t topOfMainStack)
 Set Main Stack Pointer (non-secure) More...
 
uint32_t __TZ_get_SP_NS (void)
 Get Stack Pointer (non-secure) More...
 
void __TZ_set_SP_NS (uint32_t topOfStack)
 Set Stack Pointer (non-secure) More...
 
uint32_t __TZ_get_PRIMASK_NS (void)
 Get Priority Mask (non-secure) More...
 
void __TZ_set_PRIMASK_NS (uint32_t priMask)
 Set Priority Mask (non-secure) More...
 
uint32_t __TZ_get_BASEPRI_NS (void)
 Get Base Priority (non-secure) More...
 
void __TZ_set_BASEPRI_NS (uint32_t basePri)
 Set Base Priority (non-secure) More...
 
uint32_t __TZ_get_FAULTMASK_NS (void)
 Get Fault Mask (non-secure) More...
 
void __TZ_set_FAULTMASK_NS (uint32_t faultMask)
 Set Fault Mask (non-secure) More...
 
uint32_t __TZ_get_PSPLIM_NS (void)
 Get Process Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. More...
 
void __TZ_set_PSPLIM_NS (uint32_t ProcStackPtrLimit)
 Set Process Stack Pointer (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. More...
 
uint32_t __TZ_get_MSPLIM_NS (void)
 Get Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. More...
 
void __TZ_set_MSPLIM_NS (uint32_t MainStackPtrLimit)
 Set Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t __TZ_get_BASEPRI_NS (void )
+
+

Returns the current value of the non-secure Base Priority register when in secure state.

+
Returns
Base Priority register value
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_CONTROL_NS (void )
+
+

Returns the content of the non-secure Control register when in secure mode.

+
Returns
non-secure Control register value
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_FAULTMASK_NS (void )
+
+

Returns the current value of the non-secure Fault Mask register when in secure state.

+
Returns
Fault Mask register value
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_MSP_NS (void )
+
+

Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.

+
Returns
MSP register value
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_MSPLIM_NS (void )
+
+

Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.

+
Returns
MSPLIM register value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_PRIMASK_NS (void )
+
+

Returns the current state of the non-secure priority mask bit from the Priority Mask register when in secure state.

+
Returns
Priority Mask value
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_PSP_NS (void )
+
+

Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.

+
Returns
PSP register value
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_PSPLIM_NS (void )
+
+

Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

+
Returns
PSPLIM register value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __TZ_get_SP_NS (void )
+
+

Returns the current value of the non-secure Stack Pointer (SP) when in secure state.

+
Returns
SP register value
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_BASEPRI_NS (uint32_t basePri)
+
+

Assigns the given value to the non-secure Base Priority register when in secure state.

+
Parameters
+ + +
[in]basePriBase Priority value to set
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_CONTROL_NS (uint32_t control)
+
+

Writes the given value to the non-secure Control register when in secure state.

+
Parameters
+ + +
[in]controlControl register value to set
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_FAULTMASK_NS (uint32_t faultMask)
+
+

Assigns the given value to the non-secure Fault Mask register when in secure state.

+
Parameters
+ + +
[in]faultMaskFault Mask value to set
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_MSP_NS (uint32_t topOfMainStack)
+
+

Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.

+
Parameters
+ + +
[in]topOfMainStackMain Stack Pointer value to set
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_MSPLIM_NS (uint32_t MainStackPtrLimit)
+
+

Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.

+
Parameters
+ + +
[in]MainStackPtrLimitMain Stack Pointer value to set
+
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_PRIMASK_NS (uint32_t priMask)
+
+

Assigns the given value to the non-secure Priority Mask register when in secure state.

+
Parameters
+ + +
[in]priMaskPriority Mask
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_PSP_NS (uint32_t topOfProcStack)
+
+

Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.

+
Parameters
+ + +
[in]topOfProcStackProcess Stack Pointer value to set
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_PSPLIM_NS (uint32_t ProcStackPtrLimit)
+
+

Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.

+
Parameters
+ + +
[in]ProcStackPtrLimitProcess Stack Pointer Limit value to set
+
+
+ +
+
+ +
+
+ + + + + + + + +
void __TZ_set_SP_NS (uint32_t topOfStack)
+
+

Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.

+
Parameters
+ + +
[in]topOfStackStack Pointer value to set
+
+
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__coreregister__trustzone__functions.js b/docs/Core/html/group__coreregister__trustzone__functions.js new file mode 100644 index 0000000..fb1bbd3 --- /dev/null +++ b/docs/Core/html/group__coreregister__trustzone__functions.js @@ -0,0 +1,21 @@ +var group__coreregister__trustzone__functions = +[ + [ "__TZ_get_BASEPRI_NS", "group__coreregister__trustzone__functions.html#ga624509c924d2583f0d4dca6ab270f051", null ], + [ "__TZ_get_CONTROL_NS", "group__coreregister__trustzone__functions.html#ga27bf1f88e794c30808ee73a29d46e358", null ], + [ "__TZ_get_FAULTMASK_NS", "group__coreregister__trustzone__functions.html#ga578b41087f207e1a475daae6cc8a28dc", null ], + [ "__TZ_get_MSP_NS", "group__coreregister__trustzone__functions.html#gab3aa15eb4f352e230b9f7a3e8856a9e9", null ], + [ "__TZ_get_MSPLIM_NS", "group__coreregister__trustzone__functions.html#gada00853d3e49fa8d21f375c53d28fa51", null ], + [ "__TZ_get_PRIMASK_NS", "group__coreregister__trustzone__functions.html#ga7cc3271c79e619f8838e8767df3cb509", null ], + [ "__TZ_get_PSP_NS", "group__coreregister__trustzone__functions.html#ga40ff8336c6d09af6da1081d4e4adc126", null ], + [ "__TZ_get_PSPLIM_NS", "group__coreregister__trustzone__functions.html#ga5da646ec291b6a183f38497ce92be51c", null ], + [ "__TZ_get_SP_NS", "group__coreregister__trustzone__functions.html#gaaaf2aaf904b25ed17fd3e5e63f8e029b", null ], + [ "__TZ_set_BASEPRI_NS", "group__coreregister__trustzone__functions.html#ga92c187f0b4d53627b59e0fd0bda0b0df", null ], + [ "__TZ_set_CONTROL_NS", "group__coreregister__trustzone__functions.html#ga3eb150204e6d389d5b49065179b9cde5", null ], + [ "__TZ_set_FAULTMASK_NS", "group__coreregister__trustzone__functions.html#ga4f0912db7bc65439d23817c1d372a7a4", null ], + [ "__TZ_set_MSP_NS", "group__coreregister__trustzone__functions.html#ga41c3ac2d9af23c40647c053ad7d564e7", null ], + [ "__TZ_set_MSPLIM_NS", "group__coreregister__trustzone__functions.html#gad2013f4d4311d6db253594a12d192617", null ], + [ "__TZ_set_PRIMASK_NS", "group__coreregister__trustzone__functions.html#ga6686c2ab5756b5049fad1644e89b3340", null ], + [ "__TZ_set_PSP_NS", "group__coreregister__trustzone__functions.html#gaea8db21c00cfa4144ee74dc65dbd7580", null ], + [ "__TZ_set_PSPLIM_NS", "group__coreregister__trustzone__functions.html#ga81e0995ee0fd2a9dcd9e9681bc22c76f", null ], + [ "__TZ_set_SP_NS", "group__coreregister__trustzone__functions.html#gab7263167cb006aeeb04b68e579dae015", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__fpu__functions.html b/docs/Core/html/group__fpu__functions.html new file mode 100644 index 0000000..35570b7 --- /dev/null +++ b/docs/Core/html/group__fpu__functions.html @@ -0,0 +1,166 @@ + + + + + +FPU Functions +CMSIS-Core (Cortex-M): FPU Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
FPU Functions
+
+
+ +

Functions that relate to the Floating-Point Arithmetic Unit. +More...

+ + + + + +

+Functions

__STATIC_INLINE uint32_t SCB_GetFPUType (void)
 Get the FPU type. More...
 
+

Description

+

Some Cortex-M processors include optional floating-point arithmetic functionality, with support for single and double-precision arithmetic. The Cortex-M processor with FPU is an implementation of the single-precision and double-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5).

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t SCB_GetFPUType (void )
+
+
Returns
    +
  • 0: No FPU
    • +
  • 1: Single precision FPU
    • +
  • 2: Double + Single precision FPU
    • +
+
+

The function returns the implemented FPU type.

+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__fpu__functions.js b/docs/Core/html/group__fpu__functions.js new file mode 100644 index 0000000..47f9039 --- /dev/null +++ b/docs/Core/html/group__fpu__functions.js @@ -0,0 +1,4 @@ +var group__fpu__functions = +[ + [ "SCB_GetFPUType", "group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__intrinsic__CPU__gr.html b/docs/Core/html/group__intrinsic__CPU__gr.html new file mode 100644 index 0000000..b11dac6 --- /dev/null +++ b/docs/Core/html/group__intrinsic__CPU__gr.html @@ -0,0 +1,1423 @@ + + + + + +Intrinsic Functions for CPU Instructions +CMSIS-Core (Cortex-M): Intrinsic Functions for CPU Instructions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Intrinsic Functions for CPU Instructions
+
+
+ +

Functions that generate specific Cortex-M CPU Instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void __NOP (void)
 No Operation. More...
 
void __WFI (void)
 Wait For Interrupt. More...
 
void __WFE (void)
 Wait For Event. More...
 
void __SEV (void)
 Send Event. More...
 
void __BKPT (uint8_t value)
 Set Breakpoint. More...
 
void __ISB (void)
 Instruction Synchronization Barrier. More...
 
void __DSB (void)
 Data Synchronization Barrier. More...
 
void __DMB (void)
 Data Memory Barrier. More...
 
uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit) More...
 
uint32_t __REV16 (uint32_t value)
 Reverse byte order (16 bit) More...
 
int32_t __REVSH (int32_t value)
 Reverse byte order (16 bit) More...
 
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value. More...
 
uint32_t __ROR (uint32_t value, uint32_t shift)
 Rotate a value right by a number of bits. More...
 
uint8_t __LDREXB (volatile uint8_t *addr)
 LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint16_t __LDREXH (volatile uint16_t *addr)
 LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __LDREXW (volatile uint32_t *addr)
 LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __STREXB (uint8_t value, volatile uint8_t *addr)
 STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __STREXH (uint16_t value, volatile uint16_t *addr)
 STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __STREXW (uint32_t value, volatile uint32_t *addr)
 STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void __CLREX (void)
 Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
int32_t __SSAT (int32_t value, uint32_t sat)
 Signed Saturate [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t __USAT (uint32_t value, uint32_t sat)
 Unsigned Saturate [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint8_t __CLZ (uint32_t value)
 Count leading zeros. More...
 
uint32_t __RRX (uint32_t value)
 Rotate Right with Extend (32 bit) More...
 
uint8_t __LDRBT (uint8_t ptr)
 LDRT Unprivileged (8 bit) More...
 
uint16_t __LDRHT (uint16_t ptr)
 LDRT Unprivileged (16 bit) More...
 
uint32_t __LDRT (uint32_t ptr)
 LDRT Unprivileged (32 bit) More...
 
void __STRBT (uint8_t value, uint8_t ptr)
 STRT Unprivileged (8 bit) More...
 
void __STRHT (uint16_t value, uint16_t ptr)
 STRT Unprivileged (16 bit) More...
 
void __STRT (uint32_t value, uint32_t ptr)
 STRT Unprivileged (32 bit) More...
 
uint8_t __LDAB (volatile uint8_t *ptr)
 Load-Acquire (8 bit) More...
 
uint16_t __LDAH (volatile uint16_t *ptr)
 Load-Acquire (16 bit) More...
 
uint32_t __LDA (volatile uint32_t *ptr)
 Load-Acquire (32 bit) More...
 
void __STLB (uint8_t value, volatile uint8_t *ptr)
 Store-Release (8 bit) More...
 
void __STLH (uint16_t value, volatile uint16_t *ptr)
 Store-Release (16 bit) More...
 
void __STL (uint32_t value, volatile uint32_t *ptr)
 Store-Release (32 bit) More...
 
uint8_t __LDAEXB (volatile uint32_t *ptr)
 Load-Acquire Exclusive (8 bit) More...
 
uint16_t __LDAEXH (volatile uint32_t *ptr)
 Load-Acquire Exclusive (16 bit) More...
 
uint32_t __LDAEX (volatile uint32_t *ptr)
 Load-Acquire Exclusive (32 bit) More...
 
uint32_t __STLEXB (uint8_t value, volatile uint8_t *ptr)
 Store-Release Exclusive (8 bit) More...
 
uint32_t __STLEXH (uint16_t value, volatile uint16_t *ptr)
 Store-Release Exclusive (16 bit) More...
 
uint32_t __STLEX (uint32_t value, volatile uint32_t *ptr)
 Store-Release Exclusive (32 bit) More...
 
+

Description

+

The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. Refer to the Cortex-M Reference Manuals for detailed information about these Cortex-M instructions.

+
Note
When using the Arm Compiler Version 5 Toolchain the following Intrinsic Functions for CPU Instructions are implemented using the Embedded Assembler. As the Embedded Assembler may cause side effects (Refer to Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler for more information) it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the define __NO_EMBEDDED_ASM: +
+

Function Documentation

+ +
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+ + + + + + + + +
void __BKPT (uint8_t value)
+
+

This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

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Parameters
+ + +
[in]valueis ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.
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void __CLREX (void )
+
+

This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000].

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uint8_t __CLZ (uint32_t value)
+
+

This function counts the number of leading zeros of a data value.

+

On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __CLZ is implemented in software.

+
Parameters
+ + +
[in]valueValue to count the leading zeros
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+
+
Returns
number of leading zeros in value
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void __DMB (void )
+
+

This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

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void __DSB (void )
+
+

This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

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void __ISB (void )
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Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

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uint32_t __LDA (volatile uint32_t * ptr)
+
+

Executes a LDA instruction for 32 bit values.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint32_t at (*ptr)
+
Note
Only availabe for Armv8-M Architecture.
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uint8_t __LDAB (volatile uint8_t * ptr)
+
+

Executes a LDAB instruction for 8 bit value.

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Parameters
+ + +
[in]ptrPointer to data
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+
Returns
value of type uint8_t at (*ptr)
+
Note
Only availabe for Armv8-M Architecture.
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uint32_t __LDAEX (volatile uint32_t * ptr)
+
+

Executes a LDA exclusive instruction for 32 bit values.

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Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint32_t at (*ptr)
+
Note
Only availabe for Armv8-M Architecture.
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uint8_t __LDAEXB (volatile uint32_t * ptr)
+
+

Executes a LDAB exclusive instruction for 8 bit value.

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Parameters
+ + +
[in]ptrPointer to data
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+
Returns
value of type uint8_t at (*ptr)
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Note
Only availabe for Armv8-M Architecture.
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uint16_t __LDAEXH (volatile uint32_t * ptr)
+
+

Executes a LDAH exclusive instruction for 16 bit values.

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Parameters
+ + +
[in]ptrPointer to data
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Returns
value of type uint16_t at (*ptr)
+
Note
Only availabe for Armv8-M Architecture.
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uint16_t __LDAH (volatile uint16_t * ptr)
+
+

Executes a LDAH instruction for 16 bit values.

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Parameters
+ + +
[in]ptrPointer to data
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Returns
value of type uint16_t at (*ptr)
+
Note
Only availabe for Armv8-M Architecture.
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uint8_t __LDRBT (uint8_t ptr)
+
+

This function executed an Unprivileged LDRT command for 8 bit value.

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Parameters
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[in]ptrPointer to data
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Returns
value of type uint8_t at (*ptr)
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uint8_t __LDREXB (volatile uint8_t * addr)
+
+

This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]*addrPointer to data
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Returns
value of type uint8_t at (*addr)
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uint16_t __LDREXH (volatile uint16_t * addr)
+
+

This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]*addrPointer to data
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+
Returns
value of type uint16_t at (*addr)
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uint32_t __LDREXW (volatile uint32_t * addr)
+
+

This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]*addrPointer to data
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Returns
value of type uint32_t at (*addr)
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uint16_t __LDRHT (uint16_t ptr)
+
+

This function executed an Unprivileged LDRT command for 16 bit values.

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Parameters
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[in]ptrPointer to data
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+
Returns
value of type uint16_t at (*ptr)
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uint32_t __LDRT (uint32_t ptr)
+
+

This function executed an Unprivileged LDRT command for 32 bit values.

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Parameters
+ + +
[in]ptrPointer to data
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+
Returns
value of type uint32_t at (*ptr)
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void __NOP (void )
+
+

This function does nothing. This instruction can be used for code alignment purposes.

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uint32_t __RBIT (uint32_t value)
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Parameters
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[in]valueValue to reverse
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Returns
Reversed value
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uint32_t __REV (uint32_t value)
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+

Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

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Parameters
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[in]valueValue to reverse
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Returns
Reversed value
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uint32_t __REV16 (uint32_t value)
+
+

Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

+
Parameters
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[in]valueValue to reverse
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Returns
Reversed value
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int32_t __REVSH (int32_t value)
+
+

Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

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Parameters
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[in]valueValue to reverse
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Returns
Reversed value
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uint32_t __ROR (uint32_t value,
uint32_t shift 
)
+
+

This function rotates a value right by a specified number of bits.

+
Parameters
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[in]valueValue to be shifted right
[in]shiftNumber of bits in the range [1..31]
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Returns
Rotated value
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uint32_t __RRX (uint32_t value)
+
+

This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.

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Parameters
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[in]valueValue to rotate
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Returns
Rotated value
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void __SEV (void )
+
+

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

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int32_t __SSAT (int32_t value,
uint32_t sat 
)
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+

This function saturates a signed value [not for Cortex-M0, Cortex-M0+, or SC000].

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Parameters
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[in]valueValue to be saturated
[in]satBit position to saturate to [1..32]
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Returns
Saturated value
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void __STL (uint32_t value,
volatile uint32_t * ptr 
)
+
+

Executes a STL instruction for 32 bit values.

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Parameters
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[in]valueValue to store
[in]ptrPointer to location
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Note
Only availabe for Armv8-M Architecture.
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void __STLB (uint8_t value,
volatile uint8_t * ptr 
)
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+

Executes a STLB instruction for 8 bit values.

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Parameters
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[in]valueValue to store
[in]ptrPointer to location
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Note
Only availabe for Armv8-M Architecture.
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uint32_t __STLEX (uint32_t value,
volatile uint32_t * ptr 
)
+
+

Executes a STL exclusive instruction for 32 bit values.

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Parameters
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[in]valueValue to store
[in]ptrPointer to location
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Returns
0 Function succeeded
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+1 Function failed
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Note
Only availabe for Armv8-M Architecture.
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uint32_t __STLEXB (uint8_t value,
volatile uint8_t * ptr 
)
+
+

Executes a STLB exclusive instruction for 8 bit values.

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Parameters
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[in]valueValue to store
[in]ptrPointer to location
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Returns
0 Function succeeded
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+1 Function failed
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Note
Only availabe for Armv8-M Architecture.
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uint32_t __STLEXH (uint16_t value,
volatile uint16_t * ptr 
)
+
+

Executes a STLH exclusive instruction for 16 bit values.

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Parameters
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[in]valueValue to store
[in]ptrPointer to location
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Returns
0 Function succeeded
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+1 Function failed
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Note
Only availabe for Armv8-M Architecture.
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void __STLH (uint16_t value,
volatile uint16_t * ptr 
)
+
+

Executes a STLH instruction for 16 bit values.

+
Parameters
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[in]valueValue to store
[in]ptrPointer to location
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+
Note
Only availabe for Armv8-M Architecture.
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void __STRBT (uint8_t value,
uint8_t ptr 
)
+
+

This function executed an Unprivileged STRT command for 8 bit values.

+
Parameters
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[in]valueValue to store
[in]ptrPointer to location
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uint32_t __STREXB (uint8_t value,
volatile uint8_t * addr 
)
+
+

This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
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[in]valueValue to store
[in]*addrPointer to location
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Returns
0 Function succeeded
+
+1 Function failed
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uint32_t __STREXH (uint16_t value,
volatile uint16_t * addr 
)
+
+

This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
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[in]valueValue to store
[in]*addrPointer to location
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Returns
0 Function succeeded
+
+1 Function failed
+ +
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+
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uint32_t __STREXW (uint32_t value,
volatile uint32_t * addr 
)
+
+

This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
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[in]valueValue to store
[in]*addrPointer to location
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Returns
0 Function succeeded
+
+1 Function failed
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void __STRHT (uint16_t value,
uint16_t ptr 
)
+
+

This function executed an Unprivileged STRT command for 16 bit values.

+
Parameters
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[in]valueValue to store
[in]ptrPointer to location
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void __STRT (uint32_t value,
uint32_t ptr 
)
+
+

This function executed an Unprivileged STRT command for 32 bit values.

+
Parameters
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[in]valueValue to store
[in]ptrPointer to location
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uint32_t __USAT (uint32_t value,
uint32_t sat 
)
+
+

This function saturates an unsigned value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to [0..31]
+
+
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Returns
Saturated value
+ +
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void __WFE (void )
+
+

Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs:

+
    +
  • If the event register is 0, then WFE suspends execution until one of the following events occurs:
      +
    • An exception, unless masked by the exception mask registers or the current priority level.
      • +
    • An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
      • +
    • A Debug Entry request, if Debug is enabled.
      • +
    • An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
      • +
    +
    • +
+
    +
  • If the event register is 1, then WFE clears it to 0 and returns immediately.
    • +
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void __WFI (void )
+
+

WFI is a hint instruction that suspends execution until one of the following events occurs:

+
    +
  • A non-masked interrupt occurs and is taken.
    • +
  • An interrupt masked by PRIMASK becomes pending.
    • +
  • A Debug Entry request.
    • +
+ +
+
+
+
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+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]
+
+
+ +

Access to dedicated SIMD instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __SADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed addition. More...
 
uint32_t __QADD8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating addition. More...
 
uint32_t __SHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed addition with halved results. More...
 
uint32_t __UADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned addition. More...
 
uint32_t __UQADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating addition. More...
 
uint32_t __UHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned addition with halved results. More...
 
uint32_t __SSUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed subtraction. More...
 
uint32_t __QSUB8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating subtract. More...
 
uint32_t __SHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed subtraction with halved results. More...
 
uint32_t __USUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned subtract. More...
 
uint32_t __UQSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating subtraction. More...
 
uint32_t __UHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned subtraction with halved results. More...
 
uint32_t __SADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed addition. More...
 
uint32_t __QADD16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating addition. More...
 
uint32_t __SHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition with halved results. More...
 
uint32_t __UADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition. More...
 
uint32_t __UQADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition. More...
 
uint32_t __UHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition with halved results. More...
 
uint32_t __SSUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction. More...
 
uint32_t __QSUB16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating subtract. More...
 
uint32_t __SHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction with halved results. More...
 
uint32_t __USUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract. More...
 
uint32_t __UQSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction. More...
 
uint32_t __UHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction with halved results. More...
 
uint32_t __SASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit addition and subtraction with exchange. More...
 
uint32_t __QASX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit add and subtract with exchange. More...
 
uint32_t __SHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition and subtraction with halved results. More...
 
uint32_t __UASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition and subtraction with exchange. More...
 
uint32_t __UQASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition and subtraction with exchange. More...
 
uint32_t __UHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition and subtraction with halved results and exchange. More...
 
uint32_t __SSAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction and addition with exchange. More...
 
uint32_t __QSAX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit subtract and add with exchange. More...
 
uint32_t __SHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction and addition with halved results. More...
 
uint32_t __USAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract and add with exchange. More...
 
uint32_t __UQSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction and addition with exchange. More...
 
uint32_t __UHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction and addition with halved results and exchange. More...
 
uint32_t __USAD8 (uint32_t val1, uint32_t val2)
 Unsigned sum of quad 8-bit unsigned absolute difference. More...
 
uint32_t __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
 Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. More...
 
uint32_t __SSAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit saturate. More...
 
uint32_t __USAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit unsigned saturate. More...
 
uint32_t __UXTB16 (uint32_t val)
 Dual extract 8-bits and zero-extend to 16-bits. More...
 
uint32_t __UXTAB16 (uint32_t val1, uint32_t val2)
 Extracted 16-bit to 32-bit unsigned addition. More...
 
uint32_t __SXTB16 (uint32_t val)
 Dual extract 8-bits and sign extend each to 16-bits. More...
 
uint32_t __SXTAB16 (uint32_t val1, uint32_t val2)
 Dual extracted 8-bit to 16-bit signed addition. More...
 
uint32_t __SMUAD (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply. More...
 
uint32_t __SMUADX (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply with exchange. More...
 
uint32_t __SMMLA (int32_t val1, int32_t val2, int32_t val3)
 32-bit signed multiply with 32-bit truncated accumulator. More...
 
uint32_t __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with single 32-bit accumulator. More...
 
uint32_t __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. More...
 
uint64_t __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
 Dual 16-bit signed multiply with single 64-bit accumulator. More...
 
unsigned long long __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Dual 16-bit signed multiply with exchange with single 64-bit accumulator. More...
 
uint32_t __SMUSD (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply returning difference. More...
 
uint32_t __SMUSDX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply with exchange returning difference. More...
 
uint32_t __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. More...
 
uint32_t __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. More...
 
uint64_t __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
 Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. More...
 
unsigned long long __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. More...
 
uint32_t __SEL (uint32_t val1, uint32_t val2)
 Select bytes based on GE bits. More...
 
uint32_t __QADD (uint32_t val1, uint32_t val2)
 Q setting saturating add. More...
 
uint32_t __QSUB (uint32_t val1, uint32_t val2)
 Q setting saturating subtract. More...
 
uint32_t __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. More...
 
uint32_t __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. More...
 
+

Description

+

Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 and Cortex-M7 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.

+

SIMD Features:

+
    +
  • Simultaneous computation of 2x16-bit or 4x8-bit operands
    • +
  • Fractional arithmetic
    • +
  • User definable saturation modes (arbitrary word-width)
    • +
  • Dual 16x16 multiply-add/subtract 32x32 fractional MAC
    • +
  • Simultaneous 8/16-bit select operations
    • +
  • Performance up to 3.2 GOPS at 800MHz
    • +
  • Performance is achieved with a "near zero" increase in power consumption on a typical implementation
    • +
+

Examples:

+

Addition: Add two values using SIMD function

+
uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+
{
+
return __SADD16(val1, val2);
+
}
+

Subtraction: Subtract two values using SIMD function

+
uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+
{
+
return __SSUB16(val1, val2);
+
}
+

Multiplication: Performing a multiplication using SIMD function

+
uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+
{
+
return __SMUAD(val1, val2);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __PKHBT (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters
+ + + + +
val1first 16-bit operands
val2second 16-bit operands
val3value for left-shifting val2. Value range [0..31].
+
+
+
Returns
the combination of halfwords.
+
Operation:
res[15:0] = val1[15:0]
+
res[31:16] = val2[31:16]<<val3
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __PKHTB (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters
+ + + + +
val1second 16-bit operands
val2first 16-bit operands
val3value for right-shifting val2. Value range [1..32].
+
+
+
Returns
the combination of halfwords.
+
Operation:
res[15:0] = val2[15:0]>>val3
+
res[31:16] = val1[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to obtain the saturating add of two integers.
+ The Q bit is set if the operation saturates.

+
Parameters
+ + + +
val1first summand of the saturating add operation.
val2second summand of the saturating add operation.
+
+
+
Returns
the saturating addition of val1 and val2.
+
Operation:
res[31:0] = SAT(val1 + SAT(val2))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the saturated addition of the low halfwords, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfwords, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the saturated addition of the first byte of each operand in the first byte of the return value.
    • +
  • the saturated addition of the second byte of each operand in the second byte of the return value.
    • +
  • the saturated addition of the third byte of each operand in the third byte of the return value.
    • +
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value.
    • +
  • the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to obtain the saturating subtraction of two integers.
+ The Q bit is set if the operation saturates.

+
Parameters
+ + + +
val1minuend of the saturating subtraction operation.
val2subtrahend of the saturating subtraction operation.
+
+
+
Returns
the saturating subtraction of val1 and val2.
+
Operation:
res[31:0] = SAT(val1 - SAT(val2))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
    • +
  • the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed integer additions.
+ The GE bits in the APSR are set according to the results of the additions.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the addition of the low halfwords in the low halfword of the return value.
    • +
  • the addition of the high halfwords in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the addition of the second bytes of each operand, in the second byte of the return value.
    • +
  • the addition of the third bytes of each operand, in the third byte of the return value.
    • +
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[7:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SASX (uint32_t val1,
uint32_t val2 
)
+
+

This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APRS are set according to the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SEL (uint32_t val1,
uint32_t val2 
)
+
+

This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.

+
Parameters
+ + + +
val1four selectable 8-bit values.
val2four selectable 8-bit values.
+
+
+
Returns
The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria:
    +
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
    • +
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
    • +
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
    • +
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
    • +
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two signed 16-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the halved addition of the low halfwords, in the low halfword of the return value.
    • +
  • the halved addition of the high halfwords, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1
+
res[31:16] = val1[31:16] + val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four signed 8-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1
+
res[15:8] = val1[15:8] + val2[15:8] >> 1
+
res[23:16] = val1[23:16] + val2[23:16] >> 1
+
res[31:24] = val1[31:24] + val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.

+
Parameters
+ + + +
val1first 16-bit operands.
val2second 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.

+
Parameters
+ + + +
val1first 16-bit operands.
val2second 16-bit operands.
+
+
+
Returns
    +
  • the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two signed 16-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
    • +
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1
+
res[31:16] = val1[31:16] - val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four signed 8-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1
+
res[15:8] = val1[15:8] - val2[15:8] >> 1
+
res[23:16] = val1[23:16] - val2[23:16] >> 1
+
res[31:24] = val1[31:24] - val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLAD (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value, as a 32-bit integer.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 + p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLADX (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 + p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint64_t __SMLALD (uint32_t val1,
uint32_t val2,
uint64_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
sum = p1 + p2 + val3[63:32][31:0]
+
res[63:32] = sum[63:32]
+
res[31:0] = sum[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
unsigned long long __SMLALDX (uint32_t val1,
uint32_t val2,
unsigned long long val3 
)
+
+

This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
sum = p1 + p2 + val3[63:32][31:0]
+
res[63:32] = sum[63:32]
+
res[31:0] = sum[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLSD (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.
+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 - p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLSDX (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 - p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint64_t __SMLSLD (uint32_t val1,
uint32_t val2,
uint64_t val3 
)
+
+

This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[63:0] = p1 - p2 + val3[63:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
unsigned long long __SMLSLDX (uint32_t val1,
uint32_t val2,
unsigned long long val3 
)
+
+

This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[63:0] = p1 - p2 + val3[63:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMMLA (int32_t val1,
int32_t val2,
int32_t val3 
)
+
+

This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
+

+
Parameters
+ + + + +
val1first operand for multiplication.
val2second operand for multiplication.
val3accumulate value.
+
+
+
Returns
the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
+
Operation:
p = val1 * val2
+
res[31:0] = p[61:32] + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUAD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, adding the products together.
+ The Q bit is set if the addition overflows.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the sum of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 + p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUADX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.
+ The Q bit is set if the addition overflows.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 + p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUSD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the difference of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 - p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUSDX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the difference of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 - p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAT16 (uint32_t val1,
const uint32_t val2 
)
+
+

This function enables you to saturate two signed 16-bit values to a selected signed range.
+ The Q bit is set if either operation saturates.

+
Parameters
+ + + +
val1two signed 16-bit values to be saturated.
val2bit position for saturation, an integral constant expression in the range 1 to 16.
+
+
+
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value:
    +
  • the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
    • +
  • the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • +
+
+
Operation:
Saturate halfwords in val1 to the signed range specified by the bit position in val2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit operands of each subtraction.
val2second two 16-bit operands of each subtraction.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If
    +
  • res is the return value, then:
    • +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit operands of each subtraction.
val2second four 8-bit operands of each subtraction.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
the results of the operation.
+
If res is the return value, then:
    +
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SXTAB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.

+
Parameters
+ + + +
val1values added to the zero-extended to 16-bit values.
val2two 8-bit values to be extracted and zero-extended.
+
+
+
Returns
the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.
+
Operation:
res[15:0] = val1[15:0] + SignExtended(val2[7:0])
+
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __SXTB16 (uint32_t val)
+
+

This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.

+
Parameters
+ + +
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
+
+
Returns
the 8-bit values sign-extended to 16-bit values.
    +
  • sign-extended value of val[7:0] in the low halfword of the return value.
    • +
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = SignExtended(val[7:0]
+
res[31:16] = SignExtended(val[23:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit unsigned integer additions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit summands for each addition.
val2second two 16-bit summands for each addition.
+
+
+
Returns
    +
  • the addition of the low halfwords in each operand, in the low halfword of the return value.
    • +
  • the addition of the high halfwords in each operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00
    • +
  • if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit summands for each addition.
val2second four 8-bit summands for each addition.
+
+
+
Returns
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the halved addition of the low halfwords in each operand, in the low halfword of the return value.
    • +
  • the halved addition of the high halfwords in each operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1
+
res[31:16] = val1[31:16] + val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1
+
res[15:8] = val1[15:8] + val2[15:8] >> 1
+
res[23:16] = val1[23:16] + val2[23:16] >> 1
+
res[31:24] = val1[31:24] + val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand.
    • +
  • the halved addition of the high halfword in the first operand and the low halfword in the second operand.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] + val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1
+
res[31:16] = val1[31:16] - val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1
+
res[15:8] = val1[15:8] - val2[15:8] >> 1
+
res[23:16] = val1[23:16] - val2[23:16] >> 1
+
res[31:24] = val1[31:24] - val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters
+ + + +
val1first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword.
val2second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands for each subtraction.
val2second two 16-bit operands for each subtraction.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.

+
Parameters
+ + + +
val1first four 8-bit operands for the subtractions.
val2second four 8-bit operands for the subtractions.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • +
+
+
The sum is returned as a single unsigned integer.
+
Operation:
absdiff1 = val1[7:0] - val2[7:0]
+
absdiff2 = val1[15:8] - val2[15:8]
+
absdiff3 = val1[23:16] - val2[23:16]
+
absdiff4 = val1[31:24] - val2[31:24]
+
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __USADA8 (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.

+
Parameters
+ + + + +
val1first four 8-bit operands for the subtractions.
val2second four 8-bit operands for the subtractions.
val3accumulation value.
+
+
+
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value:
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • +
+
+
Operation:
absdiff1 = val1[7:0] - val2[7:0]
+
absdiff2 = val1[15:8] - val2[15:8]
+
absdiff3 = val1[23:16] - val2[23:16]
+
absdiff4 = val1[31:24] - val2[31:24]
+
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
res[31:0] = sum[31:0] + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAT16 (uint32_t val1,
const uint32_t val2 
)
+
+

This function enables you to saturate two signed 16-bit values to a selected unsigned range.
+ The Q bit is set if either operation saturates.

+
Parameters
+ + + +
val1two 16-bit values that are to be saturated.
val2bit position for saturation, and must be an integral constant expression in the range 0 to 15.
+
+
+
Returns
the saturation of the two signed 16-bit values, as non-negative values.
    +
  • the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
    • +
  • the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • +
+
+
Operation:
Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit unsigned integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UXTAB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.

+
Parameters
+ + + +
val1value added to the zero-extended to 16-bit values.
val2two 8-bit values to be extracted and zero-extended.
+
+
+
Returns
the 8-bit values in val2, zero-extended to 16-bit values and added to val1.
+
Operation:
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0]
+
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __UXTB16 (uint32_t val)
+
+

This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.

+
Parameters
+ + +
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
+
+
Returns
the 8-bit values zero-extended to 16-bit values.
    +
  • zero-extended value of val[7:0] in the low halfword of the return value.
    • +
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = ZeroExtended(val[7:0] )
+
res[31:16] = ZeroExtended(val[23:16])
+
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__intrinsic__SIMD__gr.js b/docs/Core/html/group__intrinsic__SIMD__gr.js new file mode 100644 index 0000000..54073bc --- /dev/null +++ b/docs/Core/html/group__intrinsic__SIMD__gr.js @@ -0,0 +1,65 @@ +var group__intrinsic__SIMD__gr = +[ + [ "__PKHBT", "group__intrinsic__SIMD__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5", null ], + [ "__PKHTB", "group__intrinsic__SIMD__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666", null ], + [ "__QADD", "group__intrinsic__SIMD__gr.html#ga17b873f246c9f5e9355760ffef3dad4a", null ], + [ "__QADD16", "group__intrinsic__SIMD__gr.html#gae83a53ec04b496304bed6d9fe8f7461b", null ], + [ "__QADD8", "group__intrinsic__SIMD__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713", null ], + [ "__QASX", "group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3", null ], + [ "__QSAX", "group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520", null ], + [ "__QSUB", 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+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Define values
MPU Functions for Armv7-M
+
+
+ +

Define values for MPU region setup. +More...

+ + + + + + + + + + + + + + +

+Macros

#define ARM_MPU_REGION_SIZE_xxx
 Size values of a MPU region (in RASR field) More...
 
#define ARM_MPU_AP_xxx
 Values for MPU region access permissions (in RASR field) More...
 
#define ARM_MPU_ACCESS_xxx
 Values for MPU region access attributes (in RASR field) More...
 
#define ARM_MPU_CACHEP_xxx
 Cache policy values for MPU region access attributes (in RASR field) More...
 
+

Description

+

The following define values are used with ARM_MPU_RASR to setup the RASR value field in the MPU region.

+
See Also
ARM_MPU_Region_t, ARM_MPU_SetRegion, ARM_MPU_SetRegionEx.
+

Macro Definition Documentation

+ +
+
+ + + + +
#define ARM_MPU_ACCESS_xxx
+
+

The following define values are used to compose the access attributes for an MPU region:

+ + + + + + + + + +
#define TEX Shareable Cacheable Bufferable Description
ARM_MPU_ACCESS_ORDERED 000b 1 0 0 Strongly ordered memory
ARM_MPU_ACCESS_DEVICE(S) 0s0b S 0 S Memory mapped peripheral device, shared (S=1) or non-shared (S=0)
ARM_MPU_ACCESS_NORMAL(O,I,S) 1BBb S A A Normal memory, with outer/inner cache policy (O/I=ARM_MPU_CACHEP_xxx, shared (S=1) or non-share (S=0)
+ +
+
+ +
+
+ + + + +
#define ARM_MPU_AP_xxx
+
+

The following define values are used to compose the access permission for an MPU region:

+ + + + + + + + + + + + + + + +
#define Value Access permissions
ARM_MPU_AP_NONE 0x0U None: any access generates a permission fault.
ARM_MPU_AP_PRIV 0x1U Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault.
ARM_MPU_AP_URO 0x2U Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault.
ARM_MPU_AP_FULL 0x3U Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated.
ARM_MPU_AP_PRO 0x5U Privileged Read-only: any unprivileged access or privileged write generates a permission fault.
ARM_MPU_AP_RO 0x6U Privileged and Unprivileged Read-only: any write generates a permission fault.
+ +
+
+ +
+
+ + + + +
#define ARM_MPU_CACHEP_xxx
+
+

The following define values are used to compose the cacheability flags within the access attributes for an MPU region:

+ + + + + + + + + + + +
#define Value Cacheability policy
ARM_MPU_CACHEP_NOCACHE 00b Non-cacheable
ARM_MPU_CACHEP_WB_WRA 01b Write-back, write and read allocate
ARM_MPU_CACHEP_WT_NWA 10b Write-through, no write allocate
ARM_MPU_CACHEP_WB_NWA 11b Write-back, no write allocate
+ +
+
+ +
+
+ + + + +
#define ARM_MPU_REGION_SIZE_xxx
+
+

The following define values are used to compose the size information for an MPU region:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#define Value Description
ARM_MPU_REGION_SIZE_32B 0x04U Region size 32 Bytes
ARM_MPU_REGION_SIZE_64B 0x05U Region size 64 Bytes
ARM_MPU_REGION_SIZE_128B 0x06U Region size 128 Bytes
ARM_MPU_REGION_SIZE_256B 0x07U Region size 256 Bytes
ARM_MPU_REGION_SIZE_512B 0x08U Region size 512 Bytes
ARM_MPU_REGION_SIZE_1KB 0x09U Region size 1 KByte
ARM_MPU_REGION_SIZE_2KB 0x0AU Region size 2 KBytes
ARM_MPU_REGION_SIZE_4KB 0x0BU Region size 4 KBytes
ARM_MPU_REGION_SIZE_8KB 0x0CU Region size 8 KBytes
ARM_MPU_REGION_SIZE_16KB 0x0DU Region size 16 KBytes
ARM_MPU_REGION_SIZE_32KB 0x0EU Region size 32 KBytes
ARM_MPU_REGION_SIZE_64KB 0x0FU Region size 64 KBytes
ARM_MPU_REGION_SIZE_128KB 0x10U Region size 128 KBytes
ARM_MPU_REGION_SIZE_256KB 0x11U Region size 256 KBytes
ARM_MPU_REGION_SIZE_512KB 0x12U Region size 512 KBytes
ARM_MPU_REGION_SIZE_1MB 0x13U Region size 1 MByte
ARM_MPU_REGION_SIZE_2MB 0x14U Region size 2 MBytes
ARM_MPU_REGION_SIZE_4MB 0x15U Region size 4 MBytes
ARM_MPU_REGION_SIZE_8MB 0x16U Region size 8 MBytes
ARM_MPU_REGION_SIZE_16MB 0x17U Region size 16 MBytes
ARM_MPU_REGION_SIZE_32MB 0x18U Region size 32 MBytes
ARM_MPU_REGION_SIZE_64MB 0x19U Region size 64 MBytes
ARM_MPU_REGION_SIZE_128MB 0x1AU Region size 128 MBytes
ARM_MPU_REGION_SIZE_256MB 0x1BU Region size 256 MBytes
ARM_MPU_REGION_SIZE_512MB 0x1CU Region size 512 MBytes
ARM_MPU_REGION_SIZE_1GB 0x1DU Region size 1 GByte
ARM_MPU_REGION_SIZE_2GB 0x1EU Region size 2 GBytes
ARM_MPU_REGION_SIZE_4GB 0x1FU Region size 4 GBytes
+ +
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+ + + + diff --git a/docs/Core/html/group__mpu__defines.js b/docs/Core/html/group__mpu__defines.js new file mode 100644 index 0000000..d58eaed --- /dev/null +++ b/docs/Core/html/group__mpu__defines.js @@ -0,0 +1,7 @@ +var group__mpu__defines = +[ + [ "ARM_MPU_ACCESS_xxx", "group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2", null ], + [ "ARM_MPU_AP_xxx", "group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc", null ], + [ "ARM_MPU_CACHEP_xxx", "group__mpu__defines.html#gab23596306119e7831847bd9683de3934", null ], + [ "ARM_MPU_REGION_SIZE_xxx", "group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__mpu__functions.html b/docs/Core/html/group__mpu__functions.html new file mode 100644 index 0000000..0803dee --- /dev/null +++ b/docs/Core/html/group__mpu__functions.html @@ -0,0 +1,576 @@ + + + + + +MPU Functions for Armv7-M +CMSIS-Core (Cortex-M): MPU Functions for Armv7-M + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
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+
+ +
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+ + + + +
+ +
+ +
+
+Content | +Data Structures | +Macros | +Functions
+
+
MPU Functions for Armv7-M
+
+
+ +

Functions that relate to the Memory Protection Unit. +More...

+ + + + + +

+Content

 Define values
 Define values for MPU region setup.
 
+ + + + + + + +

+Data Structures

struct  MPU_Type
 Structure type to access the Memory Protection Unit (MPU). More...
 
struct  ARM_MPU_Region_t
 Setup information of a single MPU Region. More...
 
+ + + + + + + + + + +

+Macros

#define ARM_MPU_RBAR(Region, BaseAddress)
 MPU Region Base Address Register Value. More...
 
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
 MPU Region Attribute and Size Register Value. More...
 
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)
 MPU Region Attribute and Size Register Value. More...
 
+ + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_CTRL)
 Enable the memory protection unit (MPU) and. More...
 
__STATIC_INLINE void ARM_MPU_Disable ()
 
__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rbar, uint32_t rasr)
 
__STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr, uint32_t rbar, uint32_t rasr)
 
__STATIC_INLINE void ARM_MPU_Load (MPU_Region_t const *table, uint32_t cnt)
 
+

Description

+

The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.

+

The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.

+

Example:

+
void main()
+
{
+
// Set Region 0
+
ARM_MPU_SetRegionEx(0UL, 0x08000000UL, MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));
+
+
ARM_MPU_Enable(0);
+
+
// Execute application code that is access protected by the MPU
+
+
ARM_MPU_Disable();
+
}
+

Macro Definition Documentation

+ +
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#define ARM_MPU_RASR( DisableExec,
 AccessPermission,
 TypeExtField,
 IsShareable,
 IsCacheable,
 IsBufferable,
 SubRegionDisable,
 Size 
)
+
+

This macro is used to construct a valid RASR value. The ENABLE bit of the RASR value is implicitly set to 1.

+
Parameters
+ + + + + + + + + +
DisableExecInstruction access disable bit. 1 = disable instruction fetches.
AccessPermissionData access permission configures read/write access for User and Privileged mode. Possible values see ARM_MPU_AP_xxx.
TypeExtFieldType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
IsShareable1 = region is shareable between multiple bus masters.
IsCacheable1 = region is cacheable (values may be kept in cache).
IsBufferable1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy.
SubRegionDisableSub-region disable field (8 bits).
SizeRegion size with values defined under ARM_MPU_REGION_SIZE_xxx.
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#define ARM_MPU_RASR_EX( DisableExec,
 AccessPermission,
 AccessAttributes,
 SubRegionDisable,
 Size 
)
+
+

This macro is used to construct a valid RASR value. The ENABLE bit of the RASR value is implicitly set to 1.

+
Parameters
+ + + + + + +
DisableExecInstruction access disable bit, 1= disable instruction fetches.
AccessPermissionData access permission configures read/write access for User and Privileged mode. Possible values see ARM_MPU_AP_xxx.
AccessAttributesMemory access attribution, see ARM_MPU_ACCESS_xxx.
SubRegionDisableSub-region disable field (8 bits).
SizeRegion size with values defined under ARM_MPU_REGION_SIZE_xxx.
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#define ARM_MPU_RBAR( Region,
 BaseAddress 
)
+
+

This preprocessor function can be used to construct a valid RBAR value. The VALID bit is implicitly set to 1.

+
Parameters
+ + + +
RegionThe region to be configured, number 0 to 15.
BaseAddressThe base address for the region.
+
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
+
+

Clear and disable the given MPU region.

+
Parameters
+ + +
rnrRegion number to be cleared.
+
+
+ +
+
+ +
+
+ + + + + + + +
__STATIC_INLINE void ARM_MPU_Disable ()
+
+

Disable the MPU.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_CTRL)
+
+
Parameters
+ + +
MPU_CTRLAdditional control settings that configure MPU behaviour
+
+
+

The function ARM_MPU_Enable writes to the register MPU->CTRL and sets bit ENABLE. The parameter MPU_CTRL provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an MPU Fault Handler the MemoryManagement_IRQn exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.

+

The following table contains possible values for the parameter MPU_CTRL that set specific bits in register MPU->CTRL.

+ + + + + + + +
Bit MPU_CTRL value When applied When not applied
1 MPU_CTRL_HFNMIENA_Msk Enable MPU during hard fault, NMI, and FAULTMASK handlers execution Disable MPU during hard fault, NMI, and FAULTMASK handler execution
2 MPU_CTRL_PRIVDEFENA_Msk Enable default memory map as a background region for privileged access Use only MPU region settings
+

Example:

+
// enable MPU with all region definitions. Exceptions are not protected by MPU.
+
MPU_Enable (0);
+
+
// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.
+
MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
+
+
+
+ +
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__STATIC_INLINE void ARM_MPU_Load (MPU_Region_t const * table,
uint32_t cnt 
)
+
+

Load the given number of MPU regions from a table.

+
Parameters
+ + + +
tablePointer to the MPU configuration table.
cntNumber of regions to be configured.
+
+
+
Note
only up to 16 regions can be handled as the function ARM_MPU_Load uses the REGION field in MPU->RBAR.
+

Example:

+
const ARM_MPU_Region_t mpuTable[3][4] = {
+
{
+
{ .RBAR = ARM_MPU_RBAR(0UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
+
{ .RBAR = ARM_MPU_RBAR(1UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
+
{ .RBAR = ARM_MPU_RBAR(2UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
+
{ .RBAR = ARM_MPU_RBAR(3UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
+
},
+
{
+
{ .RBAR = ARM_MPU_RBAR(4UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
+
{ .RBAR = ARM_MPU_RBAR(5UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
+
{ .RBAR = ARM_MPU_RBAR(6UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
+
{ .RBAR = ARM_MPU_RBAR(7UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
+
},
+
{
+
{ .RBAR = ARM_MPU_RBAR(4UL, 0x18000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
+
{ .RBAR = ARM_MPU_RBAR(5UL, 0x30000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
+
{ .RBAR = ARM_MPU_RBAR(6UL, 0x50020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
+
{ .RBAR = ARM_MPU_RBAR(7UL, 0x50022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
+
}
+
};
+
+
void UpdateMpu(uint32_t idx)
+
{
+
ARM_MPU_Load(mpuTable[idx], 4);
+
}
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rbar,
uint32_t rasr 
)
+
+

Configure an MPU region.

+

The region number should be contained in the rbar value.

+
Parameters
+ + + +
rbarValue for RBAR register.
rasrValue for RASR register.
+
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__STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr,
uint32_t rbar,
uint32_t rasr 
)
+
+

Configure the given MPU region.

+
Parameters
+ + + + +
rnrRegion number to be configured.
rbarValue for RBAR register.
rasrValue for RASR register.
+
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+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__mpu__functions.js b/docs/Core/html/group__mpu__functions.js new file mode 100644 index 0000000..a7f207f --- /dev/null +++ b/docs/Core/html/group__mpu__functions.js @@ -0,0 +1,30 @@ +var group__mpu__functions = +[ + [ "Define values", "group__mpu__defines.html", "group__mpu__defines" ], + [ "MPU_Type", "structMPU__Type.html", [ + [ "CTRL", "structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f", null ], + [ "RASR", "structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3", null ], + [ "RASR_A1", "structMPU__Type.html#a1658326c6762637eeef8a79bb467445e", null ], + [ "RASR_A2", "structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205", null ], + [ "RASR_A3", "structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd", null ], + [ "RBAR", "structMPU__Type.html#a990c609b26d990b8ba832b110adfd353", null ], + [ "RBAR_A1", "structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066", null ], + [ "RBAR_A2", "structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2", null ], + [ "RBAR_A3", "structMPU__Type.html#a207f6e9c3af753367554cc06df300a55", null ], + [ "RNR", "structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c", null ], + [ "TYPE", "structMPU__Type.html#aba02af87f77577c725cf73879cabb609", null ] + ] ], + [ "ARM_MPU_Region_t", "structARM__MPU__Region__t.html", [ + [ "RASR", "structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d", null ], + [ "RBAR", "structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22", null ] + ] ], + [ "ARM_MPU_RASR", "group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc", null ], + [ "ARM_MPU_RASR_EX", "group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc", null ], + [ "ARM_MPU_RBAR", "group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca", null ], + [ "ARM_MPU_ClrRegion", "group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c", null ], + [ "ARM_MPU_Disable", "group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57", null ], + [ "ARM_MPU_Enable", "group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb", null ], + [ "ARM_MPU_Load", "group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a", null ], + [ "ARM_MPU_SetRegion", "group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d", null ], + [ "ARM_MPU_SetRegionEx", "group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__nvic__trustzone__functions.html b/docs/Core/html/group__nvic__trustzone__functions.html new file mode 100644 index 0000000..8d56623 --- /dev/null +++ b/docs/Core/html/group__nvic__trustzone__functions.html @@ -0,0 +1,488 @@ + + + + + +NVIC Functions +CMSIS-Core (Cortex-M): NVIC Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
NVIC Functions
TrustZone for Armv8-M
+
+
+ +

Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void TZ_NVIC_SetPriorityGrouping_NS (uint32_t PriorityGroup)
 Set Priority Grouping (non-secure) More...
 
uint32_t TZ_NVIC_GetPriorityGrouping_NS (void)
 Get Priority Grouping (non-secure) More...
 
void TZ_NVIC_EnableIRQ_NS (IRQn_Type IRQn)
 Enable External Interrupt (non-secure) More...
 
uint32_t TZ_NVIC_GetEnableIRQ_NS (IRQn_Type IRQn)
 Get Interrupt Enable status (non-secure) More...
 
void TZ_NVIC_DisableIRQ_NS (IRQn_Type IRQn)
 Disable External Interrupt (non-secure) More...
 
uint32_t TZ_NVIC_GetPendingIRQ_NS (IRQn_Type IRQn)
 Get Pending Interrupt (non-secure) More...
 
void TZ_NVIC_SetPendingIRQ_NS (IRQn_Type IRQn)
 Set Pending Interrupt (non-secure) More...
 
void TZ_NVIC_ClearPendingIRQ_NS (IRQn_Type IRQn)
 Clear Pending Interrupt (non-secure) More...
 
uint32_t TZ_NVIC_GetActive_NS (IRQn_Type IRQn)
 Get Active Interrupt (non-secure) More...
 
void TZ_NVIC_SetPriority_NS (IRQn_Type IRQn, uint32_t priority)
 Set Interrupt Priority (non-secure) More...
 
uint32_t TZ_NVIC_GetPriority_NS (IRQn_Type IRQn)
 Get Interrupt Priority (non-secure) More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
void TZ_NVIC_ClearPendingIRQ_NS (IRQn_Type IRQn)
+
+

Clears the pending bit of an non-secure external interrupt when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void TZ_NVIC_DisableIRQ_NS (IRQn_Type IRQn)
+
+

Disables a device-specific interrupt in the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void TZ_NVIC_EnableIRQ_NS (IRQn_Type IRQn)
+
+

Enables a device-specific interrupt in the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_NVIC_GetActive_NS (IRQn_Type IRQn)
+
+

Reads the active register in non-secure NVIC when in secure state and returns the active bit.

+
Parameters
+ + +
[in]IRQnInterrupt number.
+
+
+
Returns
0 Interrupt status is not active.
+
+1 Interrupt status is active.
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_NVIC_GetEnableIRQ_NS (IRQn_Type IRQn)
+
+

Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.

+
Parameters
+ + +
[in]IRQnInterrupt number.
+
+
+
Returns
0 Interrupt is not enabled.
+
+1 Interrupt is enabled.
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_NVIC_GetPendingIRQ_NS (IRQn_Type IRQn)
+
+

Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt.

+
Parameters
+ + +
[in]IRQnInterrupt number.
+
+
+
Returns
0 Interrupt status is not pending.
+
+1 Interrupt status is pending.
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_NVIC_GetPriority_NS (IRQn_Type IRQn)
+
+

Reads the priority of an non-secure interrupt when in secure state. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt.

+
Parameters
+ + +
[in]IRQnInterrupt number.
+
+
+
Returns
Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t TZ_NVIC_GetPriorityGrouping_NS (void )
+
+

Reads the priority grouping field from the non-secure NVIC when in secure state.

+
Returns
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+
Note
Only available for Armv8-M Mainline.
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void TZ_NVIC_SetPendingIRQ_NS (IRQn_Type IRQn)
+
+

Sets the pending bit of an non-secure external interrupt when in secure state.

+
Parameters
+ + +
[in]IRQnInterrupt number. Value cannot be negative.
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void TZ_NVIC_SetPriority_NS (IRQn_Type IRQn,
uint32_t priority 
)
+
+

Sets the priority of an non-secure interrupt when in secure state.

+
Note
The priority cannot be set for every core interrupt.
+
Parameters
+ + + +
[in]IRQnInterrupt number.
[in]priorityPriority to set.
+
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void TZ_NVIC_SetPriorityGrouping_NS (uint32_t PriorityGroup)
+
+

Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+
Parameters
+ + +
[in]PriorityGroupPriority grouping field.
+
+
+
Note
Only available for Armv8-M Mainline.
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__nvic__trustzone__functions.js b/docs/Core/html/group__nvic__trustzone__functions.js new file mode 100644 index 0000000..a5a4bc0 --- /dev/null +++ b/docs/Core/html/group__nvic__trustzone__functions.js @@ -0,0 +1,14 @@ +var group__nvic__trustzone__functions = +[ + [ "TZ_NVIC_ClearPendingIRQ_NS", "group__nvic__trustzone__functions.html#ga3b30f8b602b593a806617b671a50731a", null ], + [ "TZ_NVIC_DisableIRQ_NS", "group__nvic__trustzone__functions.html#gabc58593dea7803c1f1e1ed3b098f497c", null ], + [ "TZ_NVIC_EnableIRQ_NS", "group__nvic__trustzone__functions.html#gaedea4c16dd4a0b792c7e9d1da4c49295", null ], + [ "TZ_NVIC_GetActive_NS", "group__nvic__trustzone__functions.html#ga1bffd79bd6365d83281883b6c4b0f218", null ], + [ "TZ_NVIC_GetEnableIRQ_NS", "group__nvic__trustzone__functions.html#ga57d2a6736704c4a39421ed1a2e7b689b", null ], + [ "TZ_NVIC_GetPendingIRQ_NS", "group__nvic__trustzone__functions.html#gab85bd0d55d746caf0e414be5284afe24", null ], + [ "TZ_NVIC_GetPriority_NS", "group__nvic__trustzone__functions.html#gade6a8784339946fdd50575d7e65a3268", null ], + [ "TZ_NVIC_GetPriorityGrouping_NS", "group__nvic__trustzone__functions.html#gaf5f578628bc8b7154b29577f6f6a87fd", null ], + [ "TZ_NVIC_SetPendingIRQ_NS", "group__nvic__trustzone__functions.html#gaccbc9aa0eacf4d4c3d3046edb9e02edd", null ], + [ "TZ_NVIC_SetPriority_NS", "group__nvic__trustzone__functions.html#ga2caf0df3603378c436c838138e42059a", null ], + [ "TZ_NVIC_SetPriorityGrouping_NS", "group__nvic__trustzone__functions.html#ga0d3b5db0685bd95cc8bd2f7ad0891d39", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__peripheral__gr.html b/docs/Core/html/group__peripheral__gr.html new file mode 100644 index 0000000..36d8415 --- /dev/null +++ b/docs/Core/html/group__peripheral__gr.html @@ -0,0 +1,352 @@ + + + + + +Peripheral Access +CMSIS-Core (Cortex-M): Peripheral Access + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Peripheral Access
+
+
+ +

Naming conventions and optional features for accessing peripherals. +More...

+ + + + + + + + +

+Macros

#define _VAL2FLD(field, value)
 Mask and shift a bit field value for assigning the result to a peripheral register. More...
 
#define _FLD2VAL(field, value)
 Extract from a peripheral register value the a bit field value. More...
 
+

Description

+

The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The Device Header File <device.h> contains typically these definition and also includes the core specific header files.

+

The definitions for Peripheral Access can be generated using the CMSIS-SVD System View Description for Peripherals. Refer to SVDConv.exe for more information.

+

Each peripheral provides a data type definition with a name that is composed of:

+
    +
  • an optional prefix <device abbreviation>_
    • +
  • <peripheral name>
    • +
  • postfix _Type or _TypeDef to identify a type definition.
    • +
+

Examples:

+
    +
  • UART_TypeDef for the peripheral UART.
    • +
  • LPC_UART_TypeDef for the device family LPC and the peripheral UART.
    • +
+

The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.

+
    +
  • IO Type Qualifiers are used to specify the access to peripheral variables. + + + + + + + + + + + + + + +
    IO Type Qualifier Type Description
    __IM Struct member Defines 'read only' permissions
    __OM Struct member Defines 'write only' permissions
    __IOM Struct member Defines 'read / write' permissions
    __I Scalar variable Defines 'read only' permissions
    __O Scalar variable Defines 'write only' permissions
    __IO Scalar variable Defines 'read / write' permissions
    +
    Note
    __IM, __OM, __IOM are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used __I, __O, __IO also for struct member definitions.
    +The typedef <device abbreviation>_UART_TypeDef shown below defines the generic register layout for all UART channels in a device.
    • +
+
typedef struct
+
{
+
union {
+
__IM uint8_t RBR; /* Offset: 0x000 (R/ ) Receiver Buffer Register */
+
__OM uint8_t THR; /* Offset: 0x000 ( /W) Transmit Holding Register */
+
__IOM uint8_t DLL; /* Offset: 0x000 (R/W) Divisor Latch LSB */
+
uint32_t RESERVED0;
+
};
+
union {
+
__IOM uint8_t DLM; /* Offset: 0x004 (R/W) Divisor Latch MSB */
+
__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt Enable Register */
+
};
+
union {
+
__IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt ID Register */
+
__OM uint8_t FCR; /* Offset: 0x008 ( /W) FIFO Control Register */
+
};
+
__IOM uint8_t LCR; /* Offset: 0x00C (R/W) Line Control Register */
+
uint8_t RESERVED1[7];
+
__IM uint8_t LSR; /* Offset: 0x014 (R/ ) Line Status Register */
+
uint8_t RESERVED2[7];
+
__IOM uint8_t SCR; /* Offset: 0x01C (R/W) Scratch Pad Register */
+
uint8_t RESERVED3[3];
+
__IOM uint32_t ACR; /* Offset: 0x020 (R/W) Autobaud Control Register */
+
__IOM uint8_t ICR; /* Offset: 0x024 (R/W) IrDA Control Register */
+
uint8_t RESERVED4[3];
+
__IOM uint8_t FDR; /* Offset: 0x028 (R/W) Fractional Divider Register */
+
uint8_t RESERVED5[7];
+
__IOM uint8_t TER; /* Offset: 0x030 (R/W) Transmit Enable Register */
+
uint8_t RESERVED6[39];
+
__IM uint8_t FIFOLVL; /* Offset: 0x058 (R/ ) FIFO Level Register */
+
} LPC_UART_TypeDef;
+

To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.

+

Example: In this example LPC_UART2 and LPC_UART3 are two pointers to UARTs defined with above register structure.
+

+
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+
Note
    +
  • The prefix LPC is optional.
    • +
+
+

The registers in the various UARTs can now be referred in the user code as shown below:
+

+
val = LPC_UART2->DR // is the data register of UART1.
+
+

+Minimal Requirements

+

To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum:
+
+

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
    +
    +Example:
    typedef struct
    +
    {
    +
    __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) SysTick Control and Status Register */
    +
    __IOM uint32_t LOAD; /* Offset: 0x004 (R/W) SysTick Reload Value Register */
    +
    __IOM uint32_t VAL; /* Offset: 0x008 (R/W) SysTick Current Value Register */
    +
    __IM uint32_t CALIB; /* Offset: 0x00C (R/ ) SysTick Calibration Register */
    +
    } SysTick_Type;
    +
    • +
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
    +
    +Example:
    #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
    +
    • +
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2).
    +
    +Example:
    #define SysTick ((SysTick_Type *) Systick_BASE) /* SysTick access definition */
    +
    • +
+

These definitions allow accessing peripheral registers with simple assignments.

+
    +
  • Example:
    +
    SysTick->CTRL = 0;
    +
    • +
+
+

+Optional Features

+

Optionally, the file device.h may define:

+
    +
  • Register Bit Fields and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for #define constants.
    • +
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_.
    • +
+
+

+Register Bit Fields

+

For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.

+

Example:

+

Bit field definitions for register CPUID in SCB (System Control Block).

+
/* SCB CPUID Register Definitions */
+
#define SCB_CPUID_IMPLEMENTER_Pos 24U
+
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
+
#define SCB_CPUID_VARIANT_Pos 20U
+
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
+
#define SCB_CPUID_ARCHITECTURE_Pos 16U
+
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
+
#define SCB_CPUID_PARTNO_Pos 4U
+
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
+
#define SCB_CPUID_REVISION_Pos 0U
+
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
+

The macros _VAL2FLD(field, value) and _FLD2VAL(field, value) enable access to bit fields.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _FLD2VAL( field,
 value 
)
+
+
Parameters
+ + + +
fieldname of bit field.
valuevalue of the register. This parameter is interpreted as an uint32_t type.
+
+
+

The macro _FLD2VAL uses the #define's _Pos and _Msk of the related bit field to extract the value of a bit field from a register.

+

Example:

+
id = _FLD2VAL(SCB_CPUID_REVISION, SCB->CPUID);
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _VAL2FLD( field,
 value 
)
+
+
Parameters
+ + + +
fieldname of bit field.
valuevalue for the bit field. This parameter is interpreted as an uint32_t type.
+
+
+

The macro _VAL2FLD uses the #define's _Pos and _Msk of the related bit field to shift bit-field values for assigning to a register.

+

Example:

+
SCB->CPUID = _VAL2FLD(SCB_CPUID_REVISION, 0x3) | _VAL2FLD(SCB_CPUID_VARIANT, 0x3);
+
+
+
+
+
+ + + + diff --git a/docs/Core/html/group__peripheral__gr.js b/docs/Core/html/group__peripheral__gr.js new file mode 100644 index 0000000..39b83c7 --- /dev/null +++ b/docs/Core/html/group__peripheral__gr.js @@ -0,0 +1,5 @@ +var group__peripheral__gr = +[ + [ "_FLD2VAL", "group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444", null ], + [ "_VAL2FLD", "group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__sau__trustzone__functions.html b/docs/Core/html/group__sau__trustzone__functions.html new file mode 100644 index 0000000..c1cb706 --- /dev/null +++ b/docs/Core/html/group__sau__trustzone__functions.html @@ -0,0 +1,201 @@ + + + + + +SAU Functions +CMSIS-Core (Cortex-M): SAU Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
SAU Functions
TrustZone for Armv8-M
+
+
+ +

Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M. +More...

+ + + + + + + + + + + +

+Functions

void TZ_SAU_Setup (void)
 Setup Secure Attribute Unit (SAU) and non-secure interrupts. More...
 
void TZ_SAU_Enable (void)
 Enable Security Attribution Unit (SAU) More...
 
void TZ_SAU_Disable (void)
 Disable Security Attribution Unit (SAU) More...
 
+

Description

+

The Secure Attribution Unit (SAU) functions SAU

+
Note
A SAU is always present if the security extension is available. The functionality differs if the SAU contains SAU regions. If SAU regions are available is configured with the macro __SAUREGION_PRESENT (see Configuration of the Processor and Core Peripherals).
+

Function Documentation

+ +
+
+ + + + + + + + +
void TZ_SAU_Disable (void )
+
+

Disables the Security Attribution Unit (SAU).

+ +
+
+ +
+
+ + + + + + + + +
void TZ_SAU_Enable (void )
+
+

Enables the Security Attribution Unit (SAU).

+ +
+
+ +
+
+ + + + + + + + +
void TZ_SAU_Setup (void )
+
+

The function TZ_SAU_Setup uses the settings in the System Partition Header File partition_<device>.h to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts. It is called from the function SystemInit.

+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__sau__trustzone__functions.js b/docs/Core/html/group__sau__trustzone__functions.js new file mode 100644 index 0000000..12263bf --- /dev/null +++ b/docs/Core/html/group__sau__trustzone__functions.js @@ -0,0 +1,6 @@ +var group__sau__trustzone__functions = +[ + [ "TZ_SAU_Disable", "group__sau__trustzone__functions.html#ga42e201cea0a4b09f588a28b751f726fb", null ], + [ "TZ_SAU_Enable", "group__sau__trustzone__functions.html#ga187377409289e34838225ce801fb102c", null ], + [ "TZ_SAU_Setup", "group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__system__init__gr.html b/docs/Core/html/group__system__init__gr.html new file mode 100644 index 0000000..96bf4fe --- /dev/null +++ b/docs/Core/html/group__system__init__gr.html @@ -0,0 +1,231 @@ + + + + + +System and Clock Configuration +CMSIS-Core (Cortex-M): System and Clock Configuration + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
System and Clock Configuration
+
+
+ +

Functions for system and clock setup available in system_device.c. +More...

+ + + + + + + + +

+Functions

void SystemInit (void)
 Function to Initialize the system. More...
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock. More...
 
+ + + + +

+Variables

uint32_t SystemCoreClock
 Variable to hold the system core clock value. More...
 
+

Description

+

Arm provides a template file system_device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

+
    +
  • A device-specific system configuration function, SystemInit().
    • +
  • A global variable that contains the system frequency, SystemCoreClock.
    • +
+

The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

+
Note
Please pay special attention to the static variable SystemCoreClock. This variable might be used throughout the whole system initialization and runtime to calculate frequency/time related values. Thus one must assure that the variable always reflects the actual system clock speed. Be aware that a value stored to SystemCoreClock during low level initializaton (i.e. SystemInit()) might get overwritten by C libray startup code. Thus its highly recommended to call SystemCoreClockUpdate at the beginning of the user main() routine.
+

+Code Example

+

The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t coreClock_1 = 0; /* Variables to store core clock values */
+
uint32_t coreClock_2 = 0;
+
+
+
int main (void) {
+
+
coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */
+
+
SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */
+
+
coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */
+
+
if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
void SystemCoreClockUpdate (void )
+
+

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

+ +
+
+ +
+
+ + + + + + + + +
void SystemInit (void )
+
+

Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

+ +
+
+

Variable Documentation

+ +
+
+ + + + +
uint32_t SystemCoreClock
+
+

Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

+
Attention
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__system__init__gr.js b/docs/Core/html/group__system__init__gr.js new file mode 100644 index 0000000..1ed21ea --- /dev/null +++ b/docs/Core/html/group__system__init__gr.js @@ -0,0 +1,6 @@ +var group__system__init__gr = +[ + [ "SystemCoreClockUpdate", "group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f", null ], + [ "SystemInit", "group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2", null ], + [ "SystemCoreClock", "group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__systick__trustzone__functions.html b/docs/Core/html/group__systick__trustzone__functions.html new file mode 100644 index 0000000..240eb3f --- /dev/null +++ b/docs/Core/html/group__systick__trustzone__functions.html @@ -0,0 +1,173 @@ + + + + + +SysTick Functions +CMSIS-Core (Cortex-M): SysTick Functions + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
SysTick Functions
TrustZone for Armv8-M
+
+
+ +

SysTick functions related to TrustZone for Armv8-M. +More...

+ + + + + +

+Functions

uint32_t TZ_SysTick_Config_NS (uint32_t ticks)
 System Tick Configuration (non-secure) More...
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t TZ_SysTick_Config_NS (uint32_t ticks)
+
+

Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts.

+
Parameters
+ + +
[in]ticksNumber of ticks between two interrupts.
+
+
+
Returns
0 Function succeeded.
+
+1 Function failed.
+
Note
When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function.
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__systick__trustzone__functions.js b/docs/Core/html/group__systick__trustzone__functions.js new file mode 100644 index 0000000..803de1e --- /dev/null +++ b/docs/Core/html/group__systick__trustzone__functions.js @@ -0,0 +1,4 @@ +var group__systick__trustzone__functions = +[ + [ "TZ_SysTick_Config_NS", "group__systick__trustzone__functions.html#gad18a1b1a6796c652f2b35e728f2e2670", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__trustzone__functions.html b/docs/Core/html/group__trustzone__functions.html new file mode 100644 index 0000000..aadc6ba --- /dev/null +++ b/docs/Core/html/group__trustzone__functions.html @@ -0,0 +1,161 @@ + + + + + +TrustZone for Armv8-M +CMSIS-Core (Cortex-M): TrustZone for Armv8-M + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content
+
+
TrustZone for Armv8-M
+
+
+ +

Functions that related to optional Armv8-M security extension. +More...

+ + + + + + + + + + + + + + + + + +

+Content

 Core Register Access Functions
 Core register Access functions related to TrustZone for Armv8-M.
 
 NVIC Functions
 Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M.
 
 SysTick Functions
 SysTick functions related to TrustZone for Armv8-M.
 
 SAU Functions
 Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M.
 
 RTOS Context Management
 RTOS Thread Context Management for Armv8-M TrustZone.
 
+

Description

+

The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology. To access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:

+ +
+
+ + + + diff --git a/docs/Core/html/group__trustzone__functions.js b/docs/Core/html/group__trustzone__functions.js new file mode 100644 index 0000000..d6d489c --- /dev/null +++ b/docs/Core/html/group__trustzone__functions.js @@ -0,0 +1,8 @@ +var group__trustzone__functions = +[ + [ "Core Register Access Functions", "group__coreregister__trustzone__functions.html", "group__coreregister__trustzone__functions" ], + [ "NVIC Functions", "group__nvic__trustzone__functions.html", "group__nvic__trustzone__functions" ], + [ "SysTick Functions", "group__systick__trustzone__functions.html", "group__systick__trustzone__functions" ], + [ "SAU Functions", "group__sau__trustzone__functions.html", "group__sau__trustzone__functions" ], + [ "RTOS Context Management", "group__context__trustzone__functions.html", "group__context__trustzone__functions" ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__version__control__depricated__gr.html b/docs/Core/html/group__version__control__depricated__gr.html new file mode 100644 index 0000000..afbeb0c --- /dev/null +++ b/docs/Core/html/group__version__control__depricated__gr.html @@ -0,0 +1,204 @@ + + + + + +Version Control per Core (Depricated) +CMSIS-Core (Cortex-M): Version Control per Core (Depricated) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Version Control per Core (Depricated)
Version Control
+
+
+ +

Version #define symbols for CMSIS release specific C/C++ source code. +More...

+ + + + + + + + + + + +

+Macros

#define __XXX_CMSIS_VERSION_MAIN
 Contains the CMSIS major version for core of type XXX, i.e. CM0 or SC300. More...
 
#define __XXX_CMSIS_VERSION_SUB
 Contains the CMSIS minor version for core of type XXX, i.e. CM0 or SC300. More...
 
#define __XXX_CMSIS_VERSION
 Contains the CMSIS version for core of type XXX, i.e. CM0 or SC300. More...
 
+

Description

+

Prior CMSIS release 5.1.0 the version information was core specific.

+

Code Example:

+
#if !defined(__CM_CMSIS_VERSION) && defined(__CORTEX_M)
+
#if ((__CORTEX_M == 0) && (__CM0_CMSIS_VERSION >= 0x00050000)) || \
+
((__CORTEX_M == 3) && (__CM3_CMSIS_VERSION >= 0x00050000)) || \
+
((__CORTEX_M == 4) && (__CM4_CMSIS_VERSION >= 0x00050000)) || \
+
((__CORTEX_M == 7) && (__CM7_CMSIS_VERSION >= 0x00050000))
+
#error Yes, we have CMSIS 5!
+
#else
+
#error We need CMSIS 5!
+
#endif
+
#else
+
#error We need a Cortex-M controller!
+
#endif
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __XXX_CMSIS_VERSION
+
+

The CMSIS version is a combination of the __CM_CMSIS_VERSION_MAIN (bits 31..15) and __CM_CMSIS_VERSION_SUB (bits 14..0).

+
Deprecated:
Only rely on this define for CMSIS 5.0 and before.
+ +
+
+ +
+
+ + + + +
#define __XXX_CMSIS_VERSION_MAIN
+
+

The CMSIS major version can be used to differentiate between CMSIS major releases.

+
Deprecated:
Only rely on this define for CMSIS 5.0 and before.
+ +
+
+ +
+
+ + + + +
#define __XXX_CMSIS_VERSION_SUB
+
+

The CMSIS minor version can be used to query a CMSIS release update level.

+
Deprecated:
Only rely on this define for CMSIS 5.0 and before.
+ +
+
+
+
+ + + + diff --git a/docs/Core/html/group__version__control__depricated__gr.js b/docs/Core/html/group__version__control__depricated__gr.js new file mode 100644 index 0000000..02d3c83 --- /dev/null +++ b/docs/Core/html/group__version__control__depricated__gr.js @@ -0,0 +1,6 @@ +var group__version__control__depricated__gr = +[ + [ "__XXX_CMSIS_VERSION", "group__version__control__depricated__gr.html#gabea7df329b150f620ee42f9d82516241", null ], + [ "__XXX_CMSIS_VERSION_MAIN", "group__version__control__depricated__gr.html#ga2ecc1658e18eb1a0be7959e33b836d05", null ], + [ "__XXX_CMSIS_VERSION_SUB", "group__version__control__depricated__gr.html#ga962096f43e0d194f0b79021964c57fbd", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/group__version__control__gr.html b/docs/Core/html/group__version__control__gr.html new file mode 100644 index 0000000..3ac128f --- /dev/null +++ b/docs/Core/html/group__version__control__gr.html @@ -0,0 +1,258 @@ + + + + + +Version Control +CMSIS-Core (Cortex-M): Version Control + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content | +Macros
+
+
Version Control
+
+
+ +

Version #define symbols for CMSIS release specific C/C++ source code. +More...

+ + + + + +

+Content

 Version Control per Core (Depricated)
 Version #define symbols for CMSIS release specific C/C++ source code.
 
+ + + + + + + + + + + + + + + + +

+Macros

#define __CM_CMSIS_VERSION_MAIN
 Contains the CMSIS major version. More...
 
#define __CM_CMSIS_VERSION_SUB
 Contains the CMSIS minor version. More...
 
#define __CM_CMSIS_VERSION
 Contains the CMSIS version. More...
 
#define __CORTEX_M
 Contains the core version for a Cortex-M class controller. More...
 
#define __CORTEX_SC
 Contains the core version for a Cortex Secure Core controller. More...
 
+

Description

+

The header file cmsis_version.h is included by each core header so that these definitions are available.

+

Code Example:

+
#if defined(__CM_CMSIS_VERSION) && \
+
(__CM_CMSIS_VERSION >= 0x00050001)
+
#error Yes, we have CMSIS 5.1 or later
+
#else
+
#error We need CMSIS 5.1 or later!
+
#endif
+

Macro Definition Documentation

+ +
+
+ + + + +
#define __CM_CMSIS_VERSION
+
+

The CMSIS version is a combination of the __CM_CMSIS_VERSION_MAIN (bits 31..15) and __CM_CMSIS_VERSION_SUB (bits 14..0).

+ +
+
+ +
+
+ + + + +
#define __CM_CMSIS_VERSION_MAIN
+
+

The CMSIS major version can be used to differentiate between CMSIS major releases.

+ +
+
+ +
+
+ + + + +
#define __CM_CMSIS_VERSION_SUB
+
+

The CMSIS minor version can be used to query a CMSIS release update level.

+ +
+
+ +
+
+ + + + +
#define __CORTEX_M
+
+

This define can be used to differentiate between the various available Cortex-M controllers. Possible values are:

+
    +
  • 0 for a Cortex-M0 or Cortex-M0+
    • +
  • 3 for a Cortex-M3
    • +
  • 4 for a Cortex-M4
    • +
  • 7 for a Cortex-M7
    • +
  • 23 for a Cortex-M23
    • +
  • 33 for a Cortex-M33
    • +
+

This define is only available for Cortex-M class controllers. Code Example:

+
#if defined(__CORTEX_M) && (__CORTEX_M == 4)
+
#error Yes, we have an Cortex-M4 controller.
+
#else
+
#error We need a Cortex-M4 controller!
+
#endif
+
+
+
+ +
+
+ + + + +
#define __CORTEX_SC
+
+

This define can be used to differentiate between the various available Cortex Secure Core controllers. Possible values are:

+
    +
  • 000 for a Cortex-SC000
    • +
  • 300 for a Cortex-SC300
    • +
+

This define is only available for Cortex Secure Core controllers. Code Example:

+
#if defined(__CORTEX_SC) && (__CORTEX_SC == 300U)
+
#error Yes, we have an Cortex SC300 controller.
+
#else
+
#error We need a Cortex SC300 controller!
+
#endif
+
+
+
+
+
+ + + + diff --git a/docs/Core/html/group__version__control__gr.js b/docs/Core/html/group__version__control__gr.js new file mode 100644 index 0000000..32b6209 --- /dev/null +++ b/docs/Core/html/group__version__control__gr.js @@ -0,0 +1,9 @@ +var group__version__control__gr = +[ + [ "Version Control per Core (Depricated)", "group__version__control__depricated__gr.html", "group__version__control__depricated__gr" ], + [ "__CM_CMSIS_VERSION", "group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89", null ], + [ "__CM_CMSIS_VERSION_MAIN", "group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5", null ], + [ "__CM_CMSIS_VERSION_SUB", "group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608", null ], + [ "__CORTEX_M", "group__version__control__gr.html#ga63ea62503c88acab19fcf3d5743009e3", null ], + [ "__CORTEX_SC", "group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/index.html b/docs/Core/html/index.html new file mode 100644 index 0000000..24643bb --- /dev/null +++ b/docs/Core/html/index.html @@ -0,0 +1,196 @@ + + + + + +Overview +CMSIS-Core (Cortex-M): Overview + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+

The following sections provide details about the CMSIS-Core (Cortex-M):

+ +
+

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

+

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
+
+

+Processor Support

+

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

+

+Cortex-M Reference Manuals

+

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

+ +

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

+ +

+Armv8-M Architecture

+

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

+

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

+
+

+Tested and Verified Toolchains

+

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

+
    +
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • Arm: Arm Compiler 6.9
    • +
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • +
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • +
+
+
+
+ + + + diff --git a/docs/Core/html/jquery.js b/docs/Core/html/jquery.js new file mode 100644 index 0000000..3db33e6 --- /dev/null +++ b/docs/Core/html/jquery.js @@ -0,0 +1,72 @@ +/*! + * jQuery JavaScript Library v1.7.1 + * http://jquery.com/ + * + * Copyright 2011, John Resig + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * Includes Sizzle.js + * http://sizzlejs.com/ + * Copyright 2011, The Dojo Foundation + * Released under the MIT, BSD, and GPL Licenses. + * + * Date: Mon Nov 21 21:11:03 2011 -0500 + */ +(function(bb,L){var av=bb.document,bu=bb.navigator,bl=bb.location;var b=(function(){var bF=function(b0,b1){return new bF.fn.init(b0,b1,bD)},bU=bb.jQuery,bH=bb.$,bD,bY=/^(?:[^#<]*(<[\w\W]+>)[^>]*$|#([\w\-]*)$)/,bM=/\S/,bI=/^\s+/,bE=/\s+$/,bA=/^<(\w+)\s*\/?>(?:<\/\1>)?$/,bN=/^[\],:{}\s]*$/,bW=/\\(?:["\\\/bfnrt]|u[0-9a-fA-F]{4})/g,bP=/"[^"\\\n\r]*"|true|false|null|-?\d+(?:\.\d*)?(?:[eE][+\-]?\d+)?/g,bJ=/(?:^|:|,)(?:\s*\[)+/g,by=/(webkit)[ \/]([\w.]+)/,bR=/(opera)(?:.*version)?[ \/]([\w.]+)/,bQ=/(msie) ([\w.]+)/,bS=/(mozilla)(?:.*? rv:([\w.]+))?/,bB=/-([a-z]|[0-9])/ig,bZ=/^-ms-/,bT=function(b0,b1){return(b1+"").toUpperCase()},bX=bu.userAgent,bV,bC,e,bL=Object.prototype.toString,bG=Object.prototype.hasOwnProperty,bz=Array.prototype.push,bK=Array.prototype.slice,bO=String.prototype.trim,bv=Array.prototype.indexOf,bx={};bF.fn=bF.prototype={constructor:bF,init:function(b0,b4,b3){var b2,b5,b1,b6;if(!b0){return this}if(b0.nodeType){this.context=this[0]=b0;this.length=1;return this}if(b0==="body"&&!b4&&av.body){this.context=av;this[0]=av.body;this.selector=b0;this.length=1;return this}if(typeof b0==="string"){if(b0.charAt(0)==="<"&&b0.charAt(b0.length-1)===">"&&b0.length>=3){b2=[null,b0,null]}else{b2=bY.exec(b0)}if(b2&&(b2[1]||!b4)){if(b2[1]){b4=b4 instanceof bF?b4[0]:b4;b6=(b4?b4.ownerDocument||b4:av);b1=bA.exec(b0);if(b1){if(bF.isPlainObject(b4)){b0=[av.createElement(b1[1])];bF.fn.attr.call(b0,b4,true)}else{b0=[b6.createElement(b1[1])]}}else{b1=bF.buildFragment([b2[1]],[b6]);b0=(b1.cacheable?bF.clone(b1.fragment):b1.fragment).childNodes}return bF.merge(this,b0)}else{b5=av.getElementById(b2[2]);if(b5&&b5.parentNode){if(b5.id!==b2[2]){return b3.find(b0)}this.length=1;this[0]=b5}this.context=av;this.selector=b0;return this}}else{if(!b4||b4.jquery){return(b4||b3).find(b0)}else{return this.constructor(b4).find(b0)}}}else{if(bF.isFunction(b0)){return b3.ready(b0)}}if(b0.selector!==L){this.selector=b0.selector;this.context=b0.context}return bF.makeArray(b0,this)},selector:"",jquery:"1.7.1",length:0,size:function(){return this.length},toArray:function(){return bK.call(this,0)},get:function(b0){return b0==null?this.toArray():(b0<0?this[this.length+b0]:this[b0])},pushStack:function(b1,b3,b0){var b2=this.constructor();if(bF.isArray(b1)){bz.apply(b2,b1)}else{bF.merge(b2,b1)}b2.prevObject=this;b2.context=this.context;if(b3==="find"){b2.selector=this.selector+(this.selector?" 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j=g.nodeName.toLowerCase();if("area"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!=="map"){return false}f=a("img[usemap=#"+h+"]")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:"a"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,"visibility")==="hidden"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[":"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,"tabindex")))},tabbable:function(g){var e=a.attr(g,"tabindex"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement("div"));f.offsetHeight;a.extend(f.style,{minHeight:"100px",height:"auto",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart="onselectstart" in f;e.removeChild(f).style.display="none"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*! + * jQuery UI Widget 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Widget + */ +(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return 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http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+".preventClickEvent",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget("ui.resizable",c.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:false,animate:false,animateDuration:"slow",animateEasing:"swing",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:"e,s,se",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass("ui-resizable");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||"ui-resizable-helper":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('
').css({position:this.element.css("position"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css("top"),left:this.element.css("left")}));this.element=this.element.parent().data("resizable",this.element.data("resizable"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css("marginLeft"),marginTop:this.originalElement.css("marginTop"),marginRight:this.originalElement.css("marginRight"),marginBottom:this.originalElement.css("marginBottom")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css("resize");this.originalElement.css("resize","none");this._proportionallyResizeElements.push(this.originalElement.css({position:"static",zoom:1,display:"block"}));this.originalElement.css({margin:this.originalElement.css("margin")});this._proportionallyResize()}this.handles=k.handles||(!c(".ui-resizable-handle",this.element).length?"e,s,se":{n:".ui-resizable-n",e:".ui-resizable-e",s:".ui-resizable-s",w:".ui-resizable-w",se:".ui-resizable-se",sw:".ui-resizable-sw",ne:".ui-resizable-ne",nw:".ui-resizable-nw"});if(this.handles.constructor==String){if(this.handles=="all"){this.handles="n,e,s,w,se,sw,ne,nw"}var l=this.handles.split(",");this.handles={};for(var g=0;g
');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=["padding",/ne|nw|n/.test(n)?"Top":/se|sw|s/.test(n)?"Bottom":/^e$/.test(n)?"Right":"Left"].join("");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(".ui-resizable-handle",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:"se"}});if(k.autoHide){this._handles.hide();c(this.element).addClass("ui-resizable-autohide").hover(function(){if(k.disabled){return}c(this).removeClass("ui-resizable-autohide");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass("ui-resizable-autohide");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css("position"),width:f.outerWidth(),height:f.outerHeight(),top:f.css("top"),left:f.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(".ui-draggable")||(/absolute/).test(e.css("position"))){e.css({position:"absolute",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css("left")),h=b(this.helper.css("top"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio=="number")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(".ui-resizable-"+this.axis).css("cursor");c("body").css("cursor",i=="auto"?this.axis+"-resize":i);e.addClass("ui-resizable-resizing");this._propagate("start",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate("resize",e);h.css({top:this.position.top+"px",left:this.position.left+"px",width:this.size.width+"px",height:this.size.height+"px"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger("resize",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],"left")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css("left"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css("top"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c("body").css("cursor","auto");this.element.removeClass("ui-resizable-resizing");this._propagate("stop",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(hl.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:"absolute",left:this.elementOffset.left-g+"px",top:this.elementOffset.top-g+"px",zIndex:++i.zIndex});this.helper.appendTo("body").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!="resize"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:"1.8.18"});c.ui.plugin.add("resizable","alsoResize",{start:function(f,g){var e=c(this).data("resizable"),i=e.options;var h=function(j){c(j).each(function(){var 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a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+
Reference
+
+
+
Here is a list of all modules:
+
[detail level 12]
+ + + + + + + + + + + + + + + + + + + + + + + +
oVersion ControlVersion #define symbols for CMSIS release specific C/C++ source code
|\Version Control per Core (Depricated)Version #define symbols for CMSIS release specific C/C++ source code
oCompiler ControlCompiler agnostic #define symbols for generic C/C++ source code
oPeripheral AccessNaming conventions and optional features for accessing peripherals
oSystem and Clock ConfigurationFunctions for system and clock setup available in system_device.c
oInterrupts and Exceptions (NVIC)Functions to access the Nested Vector Interrupt Controller (NVIC)
oCore Register AccessFunctions to access the Cortex-M core registers
oIntrinsic Functions for CPU InstructionsFunctions that generate specific Cortex-M CPU Instructions
oIntrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]Access to dedicated SIMD instructions
oFPU FunctionsFunctions that relate to the Floating-Point Arithmetic Unit
oMPU Functions for Armv7-MFunctions that relate to the Memory Protection Unit
|\Define valuesDefine values for MPU region setup
oSystick Timer (SYSTICK)Initialize and start the SysTick timer
oDebug AccessDebug Access to the Instrumented Trace Macrocell (ITM)
oTrustZone for Armv8-MFunctions that related to optional Armv8-M security extension
|oCore Register Access FunctionsCore register Access functions related to TrustZone for Armv8-M
|oNVIC FunctionsNested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M
|oSysTick FunctionsSysTick functions related to TrustZone for Armv8-M
|oSAU FunctionsSecure Attribution Unit (SAU) functions related to TrustZone for Armv8-M
|\RTOS Context ManagementRTOS Thread Context Management for Armv8-M TrustZone
\Cache Functions (only Cortex-M7)Functions for Instruction and Data Cache
 oI-Cache FunctionsFunctions for the instruction cache
 \D-Cache FunctionsFunctions for the data cache
+ + + + + + + diff --git a/docs/Core/html/modules.js b/docs/Core/html/modules.js new file mode 100644 index 0000000..da3f440 --- /dev/null +++ b/docs/Core/html/modules.js @@ -0,0 +1,17 @@ +var modules = +[ + [ "Version Control", "group__version__control__gr.html", "group__version__control__gr" ], + [ "Compiler Control", "group__compiler__conntrol__gr.html", "group__compiler__conntrol__gr" ], + [ "Peripheral Access", "group__peripheral__gr.html", "group__peripheral__gr" ], + [ "System and Clock Configuration", "group__system__init__gr.html", "group__system__init__gr" ], + [ "Interrupts and Exceptions (NVIC)", "group__NVIC__gr.html", "group__NVIC__gr" ], + [ "Core Register Access", "group__Core__Register__gr.html", "group__Core__Register__gr" ], + [ "Intrinsic Functions for CPU Instructions", "group__intrinsic__CPU__gr.html", "group__intrinsic__CPU__gr" ], + [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]", "group__intrinsic__SIMD__gr.html", "group__intrinsic__SIMD__gr" ], + [ "FPU Functions", "group__fpu__functions.html", "group__fpu__functions" ], + [ "MPU Functions for Armv7-M", "group__mpu__functions.html", "group__mpu__functions" ], + [ "Systick Timer (SYSTICK)", "group__SysTick__gr.html", "group__SysTick__gr" ], + [ "Debug Access", "group__ITM__Debug__gr.html", "group__ITM__Debug__gr" ], + [ "TrustZone for Armv8-M", "group__trustzone__functions.html", "group__trustzone__functions" ], + [ "Cache Functions (only Cortex-M7)", "group__cache__functions__m7.html", "group__cache__functions__m7" ] +]; \ No newline at end of file diff --git a/docs/Core/html/nav_f.png b/docs/Core/html/nav_f.png new file mode 100644 index 0000000..a8f400a Binary files /dev/null and b/docs/Core/html/nav_f.png differ diff --git a/docs/Core/html/nav_g.png b/docs/Core/html/nav_g.png new file mode 100644 index 0000000..2093a23 Binary files /dev/null and b/docs/Core/html/nav_g.png differ diff --git a/docs/Core/html/nav_h.png b/docs/Core/html/nav_h.png new file mode 100644 index 0000000..b6c7f01 Binary files /dev/null and b/docs/Core/html/nav_h.png differ diff --git a/docs/Core/html/navtree.css b/docs/Core/html/navtree.css new file mode 100644 index 0000000..41a9cb9 --- /dev/null +++ b/docs/Core/html/navtree.css @@ -0,0 +1,143 @@ +#nav-tree .children_ul { + margin:0; + padding:4px; +} + +#nav-tree ul { + list-style:none outside none; + margin:0px; + padding:0px; +} + +#nav-tree li { + white-space:nowrap; + margin:0px; + padding:0px; +} + +#nav-tree .plus { + margin:0px; +} + +#nav-tree .selected { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; + font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 250px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background:url("ftv2splitbar.png") repeat scroll right center transparent; + cursor:e-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#nav-sync { + position:absolute; + top:5px; + right:24px; + z-index:0; +} + +#nav-sync img { + opacity:0.3; +} + +#nav-sync img:hover { + opacity:0.9; +} + +@media print +{ + #nav-tree { display: none; } + div.ui-resizable-handle { display: none; position: relative; } +} + diff --git a/docs/Core/html/navtree.js b/docs/Core/html/navtree.js new file mode 100644 index 0000000..c916273 --- /dev/null +++ b/docs/Core/html/navtree.js @@ -0,0 +1,558 @@ +var NAVTREE = +[ + [ "CMSIS-Core (Cortex-M)", "index.html", [ + [ "Overview", "index.html", [ + [ "Processor Support", "index.html#ref_v6-v8M", [ + [ "Cortex-M Reference Manuals", "index.html#ref_man_sec", null ], + [ "Armv8-M Architecture", "index.html#ARMv8M", null ] + ] ], + [ "Tested and Verified Toolchains", "index.html#tested_tools_sec", null ] + ] ], + [ "Revision History of CMSIS-Core (Cortex-M)", "core_revisionHistory.html", null ], + [ "Using CMSIS in Embedded Applications", "using_pg.html", "using_pg" ], + [ "Using TrustZone for Armv8-M", "using_TrustZone_pg.html", [ + [ "Simplified Use Case with TrustZone", "using_TrustZone_pg.html#useCase_TrustZone", [ + [ "Program Examples", "using_TrustZone_pg.html#Example_TrustZone", null ] + ] ], + [ "Programmers Model with TrustZone", "using_TrustZone_pg.html#Model_TrustZone", null ], + [ "CMSIS Files for TrustZone", "using_TrustZone_pg.html#CMSIS_Files_TrustZone", [ + [ "RTOS Thread Context Management", "using_TrustZone_pg.html#RTOS_TrustZone", null ] + ] ] + ] ], + [ "CMSIS-Core Device Templates", "templates_pg.html", "templates_pg" ], + [ "MISRA-C Deviations", "coreMISRA_Exceptions_pg.html", null ], + [ "Register Mapping", "regMap_pg.html", null ], + [ "Deprecated List", "deprecated.html", null ], + [ "Reference", "modules.html", "modules" ], + [ "Data Structures", "annotated.html", "annotated" ], + [ "Data Fields", "functions.html", [ + [ "All", "functions.html", null ], + [ "Variables", "functions_vars.html", null ] + ] ] + ] ] +]; + +var NAVTREEINDEX = +[ +"annotated.html", +"group__mpu__defines.html#gab23596306119e7831847bd9683de3934", +"unionxPSR__Type.html#af14df16ea0690070c45b95f2116b7a0a" +]; + +var SYNCONMSG = 'click to disable panel synchronisation'; +var SYNCOFFMSG = 'click to enable panel synchronisation'; +var SYNCONMSG = 'click to disable panel synchronisation'; +var SYNCOFFMSG = 'click to enable panel synchronisation'; +var navTreeSubIndices = new Array(); + +function getData(varName) +{ + var i = varName.lastIndexOf('/'); + var n = i>=0 ? varName.substring(i+1) : varName; + return eval(n.replace(/\-/g,'_')); +} + +function stripPath(uri) +{ + return uri.substring(uri.lastIndexOf('/')+1); +} + +function stripPath2(uri) +{ + var i = uri.lastIndexOf('/'); + var s = uri.substring(i+1); + var m = uri.substring(0,i+1).match(/\/d\w\/d\w\w\/$/); + return m ? uri.substring(i-6) : s; +} + +function localStorageSupported() +{ + try { + return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem; + } + catch(e) { + return false; + } +} + + +function storeLink(link) +{ + if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) { + window.localStorage.setItem('navpath',link); + } +} + +function deleteLink() +{ + if (localStorageSupported()) { + window.localStorage.setItem('navpath',''); + } +} + +function cachedLink() +{ + if (localStorageSupported()) { + return window.localStorage.getItem('navpath'); + } else { + return ''; + } +} + +function getScript(scriptName,func,show) +{ + var head = document.getElementsByTagName("head")[0]; + var script = document.createElement('script'); + script.id = scriptName; + script.type = 'text/javascript'; + script.onload = func; + script.src = scriptName+'.js'; + if ($.browser.msie && $.browser.version<=8) { + // script.onload does not work with older versions of IE + script.onreadystatechange = function() { + if (script.readyState=='complete' || script.readyState=='loaded') { + func(); if (show) showRoot(); + } + } + } + head.appendChild(script); +} + +function createIndent(o,domNode,node,level) +{ + var level=-1; + var n = node; + while (n.parentNode) { level++; n=n.parentNode; } + if (node.childrenData) { + var imgNode = document.createElement("img"); + imgNode.style.paddingLeft=(16*level).toString()+'px'; + imgNode.width = 16; + imgNode.height = 22; + imgNode.border = 0; + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() { + if (node.expanded) { + $(node.getChildrenUL()).slideUp("fast"); + node.plus_img.src = node.relpath+"ftv2pnode.png"; + node.expanded = false; + } else { + expandNode(o, node, false, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + imgNode.src = node.relpath+"ftv2pnode.png"; + } else { + var span = document.createElement("span"); + span.style.display = 'inline-block'; + span.style.width = 16*(level+1)+'px'; + span.style.height = '22px'; + span.innerHTML = ' '; + domNode.appendChild(span); + } +} + +var animationInProgress = false; + +function gotoAnchor(anchor,aname,updateLocation) +{ + var pos, docContent = $('#doc-content'); + if (anchor.parent().attr('class')=='memItemLeft' || + anchor.parent().attr('class')=='fieldtype' || + anchor.parent().is(':header')) + { + pos = anchor.parent().position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath($(location).attr('pathname')); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : "javascript:void(0)"; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var anchor = $(aname); + gotoAnchor(anchor,aname,true); + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, 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+"using_CMSIS.html":[2,0], +"using_TrustZone_pg.html":[3], +"using_TrustZone_pg.html#CMSIS_Files_TrustZone":[3,2], +"using_TrustZone_pg.html#Example_TrustZone":[3,0,0], +"using_TrustZone_pg.html#Model_TrustZone":[3,1], +"using_TrustZone_pg.html#RTOS_TrustZone":[3,2,0], +"using_TrustZone_pg.html#useCase_TrustZone":[3,0], +"using_VTOR_pg.html":[2,1], +"using_pg.html":[2] +}; diff --git a/docs/Core/html/open.png b/docs/Core/html/open.png new file mode 100644 index 0000000..3c4e2e0 Binary files /dev/null and b/docs/Core/html/open.png differ diff --git a/docs/Core/html/pages.html b/docs/Core/html/pages.html new file mode 100644 index 0000000..46722d2 --- /dev/null +++ b/docs/Core/html/pages.html @@ -0,0 +1,146 @@ + + + + + +Usage and Description +CMSIS-Core (Cortex-M): Usage and Description + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Usage and Description
+
+
+
Here is a list of all related documentation pages:
+
[detail level 12]
+ + + + + + + + + + + + + + +
oRevision History of CMSIS-Core (Cortex-M)
oUsing CMSIS in Embedded Applications
|oBasic CMSIS Example
|oUsing Interrupt Vector Remap
|\Using CMSIS with generic Arm Processors
oUsing TrustZone for Armv8-M
oCMSIS-Core Device Templates
|oStartup File startup_<device>.s
|oSystem Configuration Files system_<device>.c and system_<device>.h
|oDevice Header File <device.h>
|\System Partition Header File partition_<device>.h
oMISRA-C Deviations
oRegister Mapping
\Deprecated List
+
+
+
+ + + + diff --git a/docs/Core/html/partition_h_pg.html b/docs/Core/html/partition_h_pg.html new file mode 100644 index 0000000..f41a311 --- /dev/null +++ b/docs/Core/html/partition_h_pg.html @@ -0,0 +1,277 @@ + + + + + +System Partition Header File partition_<device>.h +CMSIS-Core (Cortex-M): System Partition Header File partition_<device>.h + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
System Partition Header File partition_<device>.h
+
+
+

The System Partition Header File partition_<device>.h contains the initial setup of the TrustZone hardware in an Armv8-M system. The function TZ_SAU_Setup is call from SystemInit and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:

+ +

+SAU CTRL register settings

+ + + + + + + + + +
#define Value Range Default Description
SAU_INIT_CTRL 0 .. 1 0 Initialize SAU CTRL register or not
    +
  • 0: do not initialize SAU CTRL register
    • +
  • 1: initialize SAU CTRL register
    • +
+
SAU_INIT_CTRL_ENABLE 0 .. 1 0 enable/disable the SAU
    +
  • 0: disable SAU
    • +
  • 1: enable SAU
    • +
+
SAU_INIT_CTRL_ALLNS 0 .. 1 0 value for SAU_CTRL register bit ALLNS
    +
  • 0: all Memory is Secure
    • +
  • 1: all Memory is Non-Secure
    • +
+
+

+Configuration of the SAU Address Regions

+ + + + + + + + + + + + + +
#define Value Range Default Description
SAU_REGIONS_MAX 0 .. tbd 8 maximum number of SAU regions
SAU_INIT_REGION<number> 0 .. 1 0 initialize SAU region or not
    +
  • 0: do not initialize SAU region
    • +
  • 1: initialize SAU region
    • +
+
SAU_INIT_START<number> 0x00000000 .. 0xFFFFFFE0
+ [in steps of 32] 		0x00000000 region start address
SAU_INIT_END<number> 0x00000000 .. 0xFFFFFFE0
+ [in steps of 32] 		0x00000000 region start address
SAU_INIT_NSC<number> 0 .. 1 0 SAU region attribute
    +
  • 0: Non-Secure
    • +
  • 1: Secure, Non-Secure callable
    • +
+
+

The range of <number> is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each <number>.

+

The following example shows a set of SAU region macros.

+
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+
#define SAU_INIT_REGION0 1
+
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
#define SAU_INIT_END0 0x001FFFE0 /* end address of SAU region 0 */
+
#define SAU_INIT_NSC0 1
+
+
#define SAU_INIT_REGION1 1
+
#define SAU_INIT_START1 0x00200000 /* start address of SAU region 1 */
+
#define SAU_INIT_END1 0x003FFFE0 /* end address of SAU region 1 */
+
#define SAU_INIT_NSC1 0
+
+
#define SAU_INIT_REGION2 1
+
#define SAU_INIT_START2 0x20200000 /* start address of SAU region 2 */
+
#define SAU_INIT_END2 0x203FFFE0 /* end address of SAU region 2 */
+
#define SAU_INIT_NSC2 0
+
+
#define SAU_INIT_REGION3 1
+
#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
+
#define SAU_INIT_END3 0x40040000 /* end address of SAU region 3 */
+
#define SAU_INIT_NSC3 0
+
+
#define SAU_INIT_REGION4 0
+
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
#define SAU_INIT_NSC4 0
+
+
#define SAU_INIT_REGION5 0
+
#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
+
#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
+
#define SAU_INIT_NSC5 0
+
+
#define SAU_INIT_REGION6 0
+
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
+
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
+
#define SAU_INIT_NSC6 0
+
+
#define SAU_INIT_REGION7 0
+
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
+
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
+
#define SAU_INIT_NSC7 0
+

+Configuration of Sleep and Exception behaviour

+ + + + + + + + + + + +
#define Value Range Default Description
CSR_INIT_DEEPSLEEPS 0 .. 1 0 value for SCB_CSR register bit DEEPSLEEPS
    +
  • 0: Deep Sleep can be enabled by Secure and Non-Secure state
    • +
  • 1: Deep Sleep can be enabled by Secure state only
    • +
+
AIRCR_INIT_SYSRESETREQS 0 .. 1 0 value for SCB_AIRCR register bit SYSRESETREQS
    +
  • 0: System reset request accessible from Secure and Non-Secure state
    • +
  • 1: System reset request accessible from Secure state only
    • +
+
AIRCR_INIT_PRIS 0 .. 1 0 value for SCB_AIRCR register bit PRIS
    +
  • 0: Priority of Non-Secure exceptions is Not altered
    • +
  • 1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF
    • +
+
AIRCR_INIT_BFHFNMINS 0 .. 1 0 value for SCB_AIRCR register bit BFHFNMINS
    +
  • 0: BusFault, HardFault, and NMI target are Secure state
    • +
  • 1: BusFault, HardFault, and NMI target are Non-Secure state
    • +
+
+

+Configuration of Interrupt Target settings

+

Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to Programmers Model with TrustZone for more information.

+ + + + + +
#define Value Range Default Description
NVIC_INIT_ITNS<number> 0x00000000 .. 0xFFFFFFFF
+ [each bit represents an interrupt] 		0x00000000 Interrupt vector target
    +
  • 0: Secure state
    • +
  • 1: Non-Secure state
    • +
+
+

The range of <number> is 0 .. (<number of external interrupts> + 31) / 32.

+

The following example shows the configuration for a maximum of 64 external interrupts.

+
#define NVIC_INIT_ITNS0 0x0000122B
+
#define NVIC_INIT_ITNS1 0x0000003A
+
+
+ + + + diff --git a/docs/Core/html/printComponentTabs.js b/docs/Core/html/printComponentTabs.js new file mode 100644 index 0000000..8afdb6b --- /dev/null +++ b/docs/Core/html/printComponentTabs.js @@ -0,0 +1,39 @@ +var strgURL = location.pathname; // path of current component + +// constuctor for the array of objects +function tabElement(id, folderName, tabTxt ) { + this.id = id; // elementID as needed in html; + this.folderName = folderName; // folder name of the component + this.tabTxt = tabTxt; // Text displayed as menu on the web + this.currentListItem = '
  • ' + this.tabTxt + '
    • '; + this.listItem = '
  • ' + this.tabTxt + '
    • '; +}; + +// array of objects +var arr = []; + +// fill array + arr.push( new tabElement( "GEN", "/General/html/", "General") ); + arr.push( new tabElement( "CORE_A", "/Core_A/html/", "CMSIS-Core(A)") ); + arr.push( new tabElement( "CORE_M", "/Core/html/", "CMSIS-Core(M)") ); + arr.push( new tabElement( "DRV", "/Driver/html/", "Driver") ); + arr.push( new tabElement( "DSP", "/DSP/html/", "DSP") ); + arr.push( new tabElement( "NN", "/NN/html/", "NN") ); + arr.push( new tabElement( "RTOSv1", "/RTOS/html/", "RTOS v1") ); + arr.push( new tabElement( "RTOSv2", "/RTOS2/html/", "RTOS v2") ); + arr.push( new tabElement( "PACK", "/Pack/html/", "Pack") ); + arr.push( new tabElement( "SVD", "/SVD/html/", "SVD") ); + arr.push( new tabElement( "DAP", "/DAP/html/", "DAP") ); + arr.push( new tabElement( "ZONE", "/Zone/html/", "Zone") ); + +// write tabs +// called from the header file. +function writeComponentTabs() { + for ( var i=0; i < arr.length; i++ ) { + if (strgURL.search(arr[i].folderName) > 0) { // if this is the current folder + document.write(arr[i].currentListItem); // then print and hightlight the tab + } else { + document.write(arr[i].listItem); // else, print the tab + } + } +}; diff --git a/docs/Core/html/regMap_pg.html b/docs/Core/html/regMap_pg.html new file mode 100644 index 0000000..a53a4a6 --- /dev/null +++ b/docs/Core/html/regMap_pg.html @@ -0,0 +1,303 @@ + + + + + +Register Mapping +CMSIS-Core (Cortex-M): Register Mapping + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Register Mapping
    +
    +
    +

    The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMSIS Register Name Cortex-M3, Cortex-M4, and Cortex-M7 Cortex-M0 and Cortex-M0+ Register Name
    Nested Vectored Interrupt Controller (NVIC) Register Access
    NVIC->ISER[] NVIC_ISER0..7 ISER Interrupt Set-Enable Registers
    NVIC->ICER[] NVIC_ICER0..7 ICER Interrupt Clear-Enable Registers
    NVIC->ISPR[] NVIC_ISPR0..7 ISPR Interrupt Set-Pending Registers
    NVIC->ICPR[] NVIC_ICPR0..7 ICPR Interrupt Clear-Pending Registers
    NVIC->IABR[] NVIC_IABR0..7 - Interrupt Active Bit Register
    NVIC->IP[] NVIC_IPR0..59 IPR0..7 Interrupt Priority Register
    NVIC->STIR STIR - Software Triggered Interrupt Register
    System Control Block (SCB) Register Access
    SCB->CPUID CPUID CPUID CPUID Base Register
    SCB->ICSR ICSR ICSR Interrupt Control and State Register
    SCB->VTOR VTOR - Vector Table Offset Register
    SCB->AIRCR AIRCR AIRCR Application Interrupt and Reset Control Register
    SCB->SCR SCR SCR System Control Register
    SCB->CCR CCR CCR Configuration and Control Register
    SCB->SHP[] SHPR1..3 SHPR2..3 System Handler Priority Registers
    SCB->SHCSR SHCSR SHCSR System Handler Control and State Register
    SCB->CFSR CFSR - Configurable Fault Status Registers
    SCB->HFSR HFSR - HardFault Status Register
    SCB->DFSR DFSR - Debug Fault Status Register
    SCB->MMFAR MMFAR - MemManage Fault Address Register
    SCB->BFAR BFAR - BusFault Address Register
    SCB->AFSR AFSR - Auxiliary Fault Status Register
    SCB->PFR[] ID_PFR0..1 - Processor Feature Registers
    SCB->DFR ID_DFR0 - Debug Feature Register
    SCB->ADR ID_AFR0 - Auxiliary Feature Register
    SCB->MMFR[] ID_MMFR0..3 - Memory Model Feature Registers
    SCB->ISAR[] ID_ISAR0..4 - Instruction Set Attributes Registers
    SCB->CPACR CPACR - Coprocessor Access Control Register
    System Control and ID Registers not in the SCB (SCnSCB) Register Access
    SCnSCB->ICTR ICTR - Interrupt Controller Type Register
    SCnSCB->ACTLR ACTLR - Auxiliary Control Register
    System Timer (SysTick) Control and Status Register Access
    SysTick->CTRL STCSR SYST_CSR SysTick Control and Status Register
    SysTick->LOAD STRVR SYST_RVR SysTick Reload Value Register
    SysTick->VAL STCVR SYST_CVR SysTick Current Value Register
    SysTick->CALIB STCR SYST_CALIB SysTick Calibaration Value Register
    Data Watchpoint and Trace (DWT) Register Access
    DWT->CTRL DWT_CTRL - Control Register
    DWT->CYCCNT DWT_CYCCNT - Cycle Count Register
    DWT->CPICNT DWT_CPICNT - CPI Count Register
    DWT->EXCCNT DWT_EXCCNT - Exception Overhead Count Register
    DWT->SLEEPCNT DWT_SLEEPCNT - Sleep Count Register
    DWT->LSUCNT DWT_LSUCNT - LSU Count Register
    DWT->FOLDCNT DWT_FOLDCNT - Folded-instruction Count Register
    DWT->PCSR DWT_PCSR - Program Counter Sample Register
    DWT->COMP0..3 DWT_COMP0..3 - Comparator Register 0..3
    DWT->MASK0..3 DWT_MASK0..3 - Mask Register 0..3
    DWT->FUNCTION0..3 DWT_FUNCTION0..3 - Function Register 0..3
    Instrumentation Trace Macrocell (ITM) Register Access
    ITM->PORT[] ITM_STIM0..31 - Stimulus Port Registers
    ITM->TER ITM_TER - Trace Enable Register
    ITM->TPR ITM_TPR - ITM Trace Privilege Register
    ITM->TCR ITM_TCR - Trace Control Register
    Trace Port Interface (TPIU) Register Access
    TPI->SSPSR TPIU_SSPR - Supported Parallel Port Size Register
    TPI->CSPSR TPIU_CSPSR - Current Parallel Port Size Register
    TPI->ACPR TPIU_ACPR - Asynchronous Clock Prescaler Register
    TPI->SPPR TPIU_SPPR - Selected Pin Protocol Register
    TPI->FFSR TPIU_FFSR - Formatter and Flush Status Register
    TPI->FFCR TPIU_FFCR - Formatter and Flush Control Register
    TPI->FSCR TPIU_FSCR - Formatter Synchronization Counter Register
    TPI->TRIGGER TRIGGER - TRIGGER
    TPI->FIFO0 FIFO data 0 - Integration ETM Data
    TPI->ITATBCTR2 ITATBCTR2 - ITATBCTR2
    TPI->ITATBCTR0 ITATBCTR0 - ITATBCTR0
    TPI->FIFO1 FIFO data 1 - Integration ITM Data
    TPI->ITCTRL TPIU_ITCTRL - Integration Mode Control
    TPI->CLAIMSET CLAIMSET - Claim tag set
    TPI->CLAIMCLR CLAIMCLR - Claim tag clear
    TPI->DEVID TPIU_DEVID - TPIU_DEVID
    TPI->DEVTYPE TPIU_DEVTYPE - TPIU_DEVTYPE
    Memory Protection Unit (MPU) Register Access
    MPU->TYPE MPU_TYPE - MPU Type Register
    MPU->CTRL MPU_CTRL - MPU Control Register
    MPU->RNR MPU_RNR - MPU Region Number Register
    MPU->RBAR MPU_RBAR - MPU Region Base Address Register
    MPU->RASR MPU_RASR - MPU Region Attribute and Size Register
    MPU->RBAR_A1..3 MPU_RBAR_A1..3 - MPU alias Register
    MPU->RSAR_A1..3 MPU_RSAR_A1..3 - MPU alias Register
    Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]
    FPU->FPCCR FPCCR - FP Context Control Register
    FPU->FPCAR FPCAR - FP Context Address Register
    FPU->FPDSCR FPDSCR - FP Default Status Control Register
    FPU->MVFR0..1 MVFR0..1 - Media and VFP Feature Registers
    +
    +
    + + + + diff --git a/docs/Core/html/resize.js b/docs/Core/html/resize.js new file mode 100644 index 0000000..304fcb6 --- /dev/null +++ b/docs/Core/html/resize.js @@ -0,0 +1,97 @@ +var cookie_namespace = 'doxygen'; +var sidenav,navtree,content,header; + +function readCookie(cookie) +{ + var myCookie = cookie_namespace+"_"+cookie+"="; + if (document.cookie) + { + var index = document.cookie.indexOf(myCookie); + if (index != -1) + { + var valStart = index + myCookie.length; + var valEnd = document.cookie.indexOf(";", valStart); + if (valEnd == -1) + { + valEnd = document.cookie.length; + } + var val = document.cookie.substring(valStart, valEnd); + return val; + } + } + return 0; +} + +function writeCookie(cookie, val, expiration) +{ + if (val==undefined) return; + if (expiration == null) + { + var date = new Date(); + date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week + expiration = date.toGMTString(); + } + document.cookie = cookie_namespace + "_" + cookie + "=" + val + "; expires=" + expiration+"; path=/"; +} + +function resizeWidth() +{ + var windowWidth = $(window).width() + "px"; + var sidenavWidth = $(sidenav).outerWidth(); + content.css({marginLeft:parseInt(sidenavWidth)+"px"}); + writeCookie('width',sidenavWidth, null); +} + +function restoreWidth(navWidth) +{ + var windowWidth = $(window).width() + "px"; + content.css({marginLeft:parseInt(navWidth)+6+"px"}); + sidenav.css({width:navWidth + "px"}); +} + +function resizeHeight() +{ + var headerHeight = header.outerHeight(); + var footerHeight = footer.outerHeight(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + content.css({height:windowHeight + "px"}); + navtree.css({height:windowHeight + "px"}); + sidenav.css({height:windowHeight + "px",top: headerHeight+"px"}); +} + +function initResizable() +{ + header = $("#top"); + sidenav = $("#side-nav"); + content = $("#doc-content"); + navtree = $("#nav-tree"); + footer = $("#nav-path"); + $(".side-nav-resizable").resizable({resize: function(e, ui) { resizeWidth(); } }); + $(window).resize(function() { resizeHeight(); }); + var width = readCookie('width'); + if (width) { restoreWidth(width); } else { resizeWidth(); } + resizeHeight(); + var url = location.href; + var i=url.indexOf("#"); + if (i>=0) window.location.hash=url.substr(i); + var _preventDefault = function(evt) { evt.preventDefault(); }; + $("#splitbar").bind("dragstart", _preventDefault).bind("selectstart", _preventDefault); + $(document).bind('touchmove',function(e){ + var device = navigator.userAgent.toLowerCase(); + var ios = device.match(/(iphone|ipod|ipad)/); + if (ios) { + try { + var target = e.target; + while (target) { + if ($(target).css('-webkit-overflow-scrolling')=='touch') return; + target = target.parentNode; + } + e.preventDefault(); + } catch(err) { + e.preventDefault(); + } + } + }); +} + + diff --git a/docs/Core/html/search.css b/docs/Core/html/search.css new file mode 100644 index 0000000..1746d13 --- /dev/null +++ b/docs/Core/html/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/docs/Core/html/search/all_0.html b/docs/Core/html/search/all_0.html new file mode 100644 index 0000000..17b6da8 --- /dev/null +++ b/docs/Core/html/search/all_0.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
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    + + diff --git a/docs/Core/html/search/groups_3.js b/docs/Core/html/search/groups_3.js new file mode 100644 index 0000000..bf5d5d2 --- /dev/null +++ b/docs/Core/html/search/groups_3.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['i_2dcache_20functions',['I-Cache Functions',['../group__Icache__functions__m7.html',1,'']]], + ['intrinsic_20functions_20for_20cpu_20instructions',['Intrinsic Functions for CPU Instructions',['../group__intrinsic__CPU__gr.html',1,'']]], + ['intrinsic_20functions_20for_20simd_20instructions_20_5bonly_20cortex_2dm4_20and_20cortex_2dm7_5d',['Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]',['../group__intrinsic__SIMD__gr.html',1,'']]], + ['interrupts_20and_20exceptions_20_28nvic_29',['Interrupts and Exceptions (NVIC)',['../group__NVIC__gr.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_4.html b/docs/Core/html/search/groups_4.html new file mode 100644 index 0000000..b07fdf9 --- /dev/null +++ b/docs/Core/html/search/groups_4.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    + +
    + + diff --git a/docs/Core/html/search/groups_4.js b/docs/Core/html/search/groups_4.js new file mode 100644 index 0000000..882b2d9 --- /dev/null +++ b/docs/Core/html/search/groups_4.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['mpu_20functions_20for_20armv7_2dm',['MPU Functions for Armv7-M',['../group__mpu__functions.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_5.html b/docs/Core/html/search/groups_5.html new file mode 100644 index 0000000..35324c0 --- /dev/null +++ b/docs/Core/html/search/groups_5.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
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    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/groups_5.js b/docs/Core/html/search/groups_5.js new file mode 100644 index 0000000..0bf9297 --- /dev/null +++ b/docs/Core/html/search/groups_5.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['nvic_20functions',['NVIC Functions',['../group__nvic__trustzone__functions.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_6.html b/docs/Core/html/search/groups_6.html new file mode 100644 index 0000000..3231402 --- /dev/null +++ b/docs/Core/html/search/groups_6.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/groups_6.js b/docs/Core/html/search/groups_6.js new file mode 100644 index 0000000..46a7250 --- /dev/null +++ b/docs/Core/html/search/groups_6.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['peripheral_20access',['Peripheral Access',['../group__peripheral__gr.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_7.html b/docs/Core/html/search/groups_7.html new file mode 100644 index 0000000..27334b6 --- /dev/null +++ b/docs/Core/html/search/groups_7.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/groups_7.js b/docs/Core/html/search/groups_7.js new file mode 100644 index 0000000..0bdfdb7 --- /dev/null +++ b/docs/Core/html/search/groups_7.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['rtos_20context_20management',['RTOS Context Management',['../group__context__trustzone__functions.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_8.html b/docs/Core/html/search/groups_8.html new file mode 100644 index 0000000..863d136 --- /dev/null +++ b/docs/Core/html/search/groups_8.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
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    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/groups_8.js b/docs/Core/html/search/groups_8.js new file mode 100644 index 0000000..cca49fa --- /dev/null +++ b/docs/Core/html/search/groups_8.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['sau_20functions',['SAU Functions',['../group__sau__trustzone__functions.html',1,'']]], + ['system_20and_20clock_20configuration',['System and Clock Configuration',['../group__system__init__gr.html',1,'']]], + ['systick_20timer_20_28systick_29',['Systick Timer (SYSTICK)',['../group__SysTick__gr.html',1,'']]], + ['systick_20functions',['SysTick Functions',['../group__systick__trustzone__functions.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_9.html b/docs/Core/html/search/groups_9.html new file mode 100644 index 0000000..e42b280 --- /dev/null +++ b/docs/Core/html/search/groups_9.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
    + +
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    +
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    + +
    + + diff --git a/docs/Core/html/search/groups_9.js b/docs/Core/html/search/groups_9.js new file mode 100644 index 0000000..ff00e91 --- /dev/null +++ b/docs/Core/html/search/groups_9.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['trustzone_20for_20armv8_2dm',['TrustZone for Armv8-M',['../group__trustzone__functions.html',1,'']]] +]; diff --git a/docs/Core/html/search/groups_a.html b/docs/Core/html/search/groups_a.html new file mode 100644 index 0000000..dc8d8cd --- /dev/null +++ b/docs/Core/html/search/groups_a.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/groups_a.js b/docs/Core/html/search/groups_a.js new file mode 100644 index 0000000..04ba1fc --- /dev/null +++ b/docs/Core/html/search/groups_a.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['version_20control_20per_20core_20_28depricated_29',['Version Control per Core (Depricated)',['../group__version__control__depricated__gr.html',1,'']]], + ['version_20control',['Version Control',['../group__version__control__gr.html',1,'']]] +]; diff --git a/docs/Core/html/search/mag_sel.png b/docs/Core/html/search/mag_sel.png new file mode 100644 index 0000000..81f6040 Binary files /dev/null and b/docs/Core/html/search/mag_sel.png differ diff --git a/docs/Core/html/search/nomatches.html b/docs/Core/html/search/nomatches.html new file mode 100644 index 0000000..b1ded27 --- /dev/null +++ b/docs/Core/html/search/nomatches.html @@ -0,0 +1,12 @@ + + + + + + + +
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    No Matches
    +
    + + diff --git a/docs/Core/html/search/pages_0.html b/docs/Core/html/search/pages_0.html new file mode 100644 index 0000000..c51c834 --- /dev/null +++ b/docs/Core/html/search/pages_0.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_0.js b/docs/Core/html/search/pages_0.js new file mode 100644 index 0000000..2ad9451 --- /dev/null +++ b/docs/Core/html/search/pages_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['basic_20cmsis_20example',['Basic CMSIS Example',['../using_CMSIS.html',1,'using_pg']]] +]; diff --git a/docs/Core/html/search/pages_1.html b/docs/Core/html/search/pages_1.html new file mode 100644 index 0000000..2a98fce --- /dev/null +++ b/docs/Core/html/search/pages_1.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
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    Searching...
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    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_1.js b/docs/Core/html/search/pages_1.js new file mode 100644 index 0000000..18a701d --- /dev/null +++ b/docs/Core/html/search/pages_1.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['cmsis_2dcore_20device_20templates',['CMSIS-Core Device Templates',['../templates_pg.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_2.html b/docs/Core/html/search/pages_2.html new file mode 100644 index 0000000..0711a0b --- /dev/null +++ b/docs/Core/html/search/pages_2.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_2.js b/docs/Core/html/search/pages_2.js new file mode 100644 index 0000000..339548f --- /dev/null +++ b/docs/Core/html/search/pages_2.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['deprecated_20list',['Deprecated List',['../deprecated.html',1,'']]], + ['device_20header_20file_20_3cdevice_2eh_3e',['Device Header File <device.h>',['../device_h_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core/html/search/pages_3.html b/docs/Core/html/search/pages_3.html new file mode 100644 index 0000000..4310311 --- /dev/null +++ b/docs/Core/html/search/pages_3.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_3.js b/docs/Core/html/search/pages_3.js new file mode 100644 index 0000000..b1e934d --- /dev/null +++ b/docs/Core/html/search/pages_3.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['misra_2dc_20deviations',['MISRA-C Deviations',['../coreMISRA_Exceptions_pg.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_4.html b/docs/Core/html/search/pages_4.html new file mode 100644 index 0000000..ae5ce18 --- /dev/null +++ b/docs/Core/html/search/pages_4.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_4.js b/docs/Core/html/search/pages_4.js new file mode 100644 index 0000000..277cca0 --- /dev/null +++ b/docs/Core/html/search/pages_4.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['overview',['Overview',['../index.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_5.html b/docs/Core/html/search/pages_5.html new file mode 100644 index 0000000..02c1114 --- /dev/null +++ b/docs/Core/html/search/pages_5.html @@ -0,0 +1,26 @@ + + + + + + + + + +
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    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_5.js b/docs/Core/html/search/pages_5.js new file mode 100644 index 0000000..8247a57 --- /dev/null +++ b/docs/Core/html/search/pages_5.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['revision_20history_20of_20cmsis_2dcore_20_28cortex_2dm_29',['Revision History of CMSIS-Core (Cortex-M)',['../core_revisionHistory.html',1,'']]], + ['register_20mapping',['Register Mapping',['../regMap_pg.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_6.html b/docs/Core/html/search/pages_6.html new file mode 100644 index 0000000..afb70af --- /dev/null +++ b/docs/Core/html/search/pages_6.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_6.js b/docs/Core/html/search/pages_6.js new file mode 100644 index 0000000..80ddf96 --- /dev/null +++ b/docs/Core/html/search/pages_6.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['system_20partition_20header_20file_20partition_5f_3cdevice_3e_2eh',['System Partition Header File partition_<device>.h',['../partition_h_pg.html',1,'templates_pg']]], + ['startup_20file_20startup_5f_3cdevice_3e_2es',['Startup File startup_<device>.s',['../startup_s_pg.html',1,'templates_pg']]], + ['system_20configuration_20files_20system_5f_3cdevice_3e_2ec_20and_20system_5f_3cdevice_3e_2eh',['System Configuration Files system_<device>.c and system_<device>.h',['../system_c_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core/html/search/pages_7.html b/docs/Core/html/search/pages_7.html new file mode 100644 index 0000000..9d7ba25 --- /dev/null +++ b/docs/Core/html/search/pages_7.html @@ -0,0 +1,26 @@ + + + + + + + + + +
    +
    Loading...
    +
    + +
    Searching...
    +
    No Matches
    + +
    + + diff --git a/docs/Core/html/search/pages_7.js b/docs/Core/html/search/pages_7.js new file mode 100644 index 0000000..7812e12 --- /dev/null +++ b/docs/Core/html/search/pages_7.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['using_20cmsis_20with_20generic_20arm_20processors',['Using CMSIS with generic Arm Processors',['../using_ARM_pg.html',1,'using_pg']]], + ['using_20cmsis_20in_20embedded_20applications',['Using CMSIS in Embedded Applications',['../using_pg.html',1,'']]], + ['using_20trustzone_20for_20armv8_2dm',['Using TrustZone for Armv8-M',['../using_TrustZone_pg.html',1,'']]], + ['using_20interrupt_20vector_20remap',['Using Interrupt Vector Remap',['../using_VTOR_pg.html',1,'using_pg']]] +]; diff --git a/docs/Core/html/search/search.css b/docs/Core/html/search/search.css new file mode 100644 index 0000000..1746d13 --- /dev/null +++ b/docs/Core/html/search/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/docs/Core/html/search/search.js b/docs/Core/html/search/search.js new file mode 100644 index 0000000..54b1a2a --- /dev/null +++ b/docs/Core/html/search/search.js @@ -0,0 +1,809 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "_abcdefhilmnopqrstuvwxz", + 1: "acdfimnstx", + 2: "cmortu", + 3: "_ainst", + 4: "_abcdefhilmnpqrstuvwz", + 5: "i", + 6: "bdhmnpsuw", + 7: "cdfimnprstv", + 8: "bcdmorsu" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "enums", + 6: "enumvalues", + 7: "groups", + 8: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? 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    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Startup File startup_<device>.s
    +
    +
    +

    The Startup File startup_<device>.s contains:

    +
      +
    • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
      • +
    • The setup values for the Main Stack Pointer (MSP).
      • +
    • Exception vectors of the Cortex-M Processor with weak functions that implement default routines.
      • +
    • Interrupt vectors that are device specific with weak functions that implement default routines.
      • +
    +

    The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.

    +

    To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.

    +

    Example:

    +

    The following example shows the extension of the interrupt vector table for the LPC1100 device family.

    +
    ; External Interrupts
    +
    DCD WAKEUP0_IRQHandler ; 16+ 0: Wakeup PIO0.0
    +
    DCD WAKEUP1_IRQHandler ; 16+ 1: Wakeup PIO0.1
    +
    DCD WAKEUP2_IRQHandler ; 16+ 2: Wakeup PIO0.2
    +
    : :
    +
    : :
    +
    DCD EINT1_IRQHandler ; 16+30: PIO INT1
    +
    DCD EINT0_IRQHandler ; 16+31: PIO INT0
    +
    :
    +
    :
    +
    EXPORT WAKEUP0_IRQHandler [WEAK]
    +
    EXPORT WAKEUP1_IRQHandler [WEAK]
    +
    EXPORT WAKEUP2_IRQHandler [WEAK]
    +
    : :
    +
    : :
    +
    EXPORT EINT1_IRQHandler [WEAK]
    +
    EXPORT EINT0_IRQHandler [WEAK]
    +
    +
    WAKEUP0_IRQHandler
    +
    WAKEUP1_IRQHandler
    +
    WAKEUP1_IRQHandler
    +
    :
    +
    :
    +
    EINT1_IRQHandler
    +
    EINT0_IRQHandler
    +
    B .
    +

    +startup_Device.s Template File

    +

    An Arm Compiler startup_Device.s Template File for an Armv7-M processor like Cortex-M3 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.

    +
    ;/**************************************************************************//**
+; * @file     startup_<Device>.s
+; * @brief    CMSIS Cortex-M ARMv7-M based Core Device Startup File for
+; *           Device <Device>
+; * @version  V5.3.1
+; * @date     09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Stack_Size      EQU      0x00000400
+
+                AREA     STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem       SPACE    Stack_Size
+__initial_sp
+
+
+;<h> Heap Configuration
+;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Heap_Size       EQU      0x00000C00
+
+                IF       Heap_Size != 0                      ; Heap is provided
+                AREA     HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE    Heap_Size
+__heap_limit
+                ENDIF
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+__Vectors       DCD      __initial_sp                        ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      MemManage_Handler                   ; -12 MPU Fault Handler
+                DCD      BusFault_Handler                    ; -11 Bus Fault Handler
+                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD      Interrupt0_Handler                  ;   0 Interrupt 0
+                DCD      Interrupt1_Handler                  ;   1 Interrupt 1
+                DCD      Interrupt2_Handler                  ;   2 Interrupt 2
+                DCD      Interrupt3_Handler                  ;   3 Interrupt 3
+                DCD      Interrupt4_Handler                  ;   4 Interrupt 4
+                DCD      Interrupt5_Handler                  ;   5 Interrupt 5
+                DCD      Interrupt6_Handler                  ;   6 Interrupt 6
+                DCD      Interrupt7_Handler                  ;   7 Interrupt 7
+                DCD      Interrupt8_Handler                  ;   8 Interrupt 8
+                DCD      Interrupt9_Handler                  ;   9 Interrupt 9
+
+                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
+
+
+                AREA     |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   __main
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =__main
+                BX       R0
+                ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
+                ENDP
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  HardFault_Handler
+                Set_Default_Handler  MemManage_Handler
+                Set_Default_Handler  BusFault_Handler
+                Set_Default_Handler  UsageFault_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  DebugMon_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Interrupt0_Handler
+                Set_Default_Handler  Interrupt1_Handler
+                Set_Default_Handler  Interrupt2_Handler
+                Set_Default_Handler  Interrupt3_Handler
+                Set_Default_Handler  Interrupt4_Handler
+                Set_Default_Handler  Interrupt5_Handler
+                Set_Default_Handler  Interrupt6_Handler
+                Set_Default_Handler  Interrupt7_Handler
+                Set_Default_Handler  Interrupt8_Handler
+                Set_Default_Handler  Interrupt9_Handler
+
+                ALIGN
+
+
+; User setup Stack & Heap
+
+                EXPORT   __stack_limit
+                EXPORT   __initial_sp
+                IF       Heap_Size != 0                      ; Heap is provided
+                EXPORT   __heap_base
+                EXPORT   __heap_limit
+                ENDIF
+
+                END
+
    +
    + + + + diff --git a/docs/Core/html/structARM__MPU__Region__t.html b/docs/Core/html/structARM__MPU__Region__t.html new file mode 100644 index 0000000..971f8c0 --- /dev/null +++ b/docs/Core/html/structARM__MPU__Region__t.html @@ -0,0 +1,181 @@ + + + + + +ARM_MPU_Region_t Struct Reference +CMSIS-Core (Cortex-M): ARM_MPU_Region_t Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    ARM_MPU_Region_t Struct Reference
    MPU Functions for Armv7-M
    +
    +
    + +

    Setup information of a single MPU Region. + More...

    + + + + + + + + +

    +Data Fields

    uint32_t RBAR
     The region base address register value (RBAR) More...
     
    uint32_t RASR
     The region attribute and size register value (RASR), see ARM_MPU_RASR. More...
     
    +

    Description

    +

    The typedef ARM_MPU_Region_t allows to define a MPU table (array of MPU regions) with pre-compiled register values. Such tables enable efficient MPU setup using the function ARM_MPU_Load.

    +

    Example: See ARM_MPU_Load

    +

    Field Documentation

    + +
    +
    + + + + +
    ARM_MPU_Region_t::RASR
    +
    +

    This value specifies region attributes and size. Use the ARM_MPU_RASR macro to compose this value.

    + +
    +
    + +
    +
    + + + + +
    ARM_MPU_Region_t::RBAR
    +
    +

    This value specifies the start address of the MPU protected memory region. The address must be a multiple of the region size (size aligned).

    +

    See MPU_Type::RBAR for details about field bit format.

    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structARM__MPU__Region__t.js b/docs/Core/html/structARM__MPU__Region__t.js new file mode 100644 index 0000000..0a08361 --- /dev/null +++ b/docs/Core/html/structARM__MPU__Region__t.js @@ -0,0 +1,5 @@ +var structARM__MPU__Region__t = +[ + [ "RASR", "structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d", null ], + [ "RBAR", "structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structCoreDebug__Type.html b/docs/Core/html/structCoreDebug__Type.html new file mode 100644 index 0000000..3aaaf3a --- /dev/null +++ b/docs/Core/html/structCoreDebug__Type.html @@ -0,0 +1,205 @@ + + + + + +CoreDebug_Type Struct Reference +CMSIS-Core (Cortex-M): CoreDebug_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CoreDebug_Type Struct Reference
    +
    +
    + +

    Structure type to access the Core Debug Register (CoreDebug). +

    + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t DHCSR
     Offset: 0x000 (R/W) Debug Halting Control and Status Register. More...
     
    __OM uint32_t DCRSR
     Offset: 0x004 ( /W) Debug Core Register Selector Register. More...
     
    __IOM uint32_t DCRDR
     Offset: 0x008 (R/W) Debug Core Register Data Register. More...
     
    __IOM uint32_t DEMCR
     Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t CoreDebug_Type::DCRDR
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t CoreDebug_Type::DCRSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t CoreDebug_Type::DEMCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t CoreDebug_Type::DHCSR
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structCoreDebug__Type.js b/docs/Core/html/structCoreDebug__Type.js new file mode 100644 index 0000000..970a8dc --- /dev/null +++ b/docs/Core/html/structCoreDebug__Type.js @@ -0,0 +1,7 @@ +var structCoreDebug__Type = +[ + [ "DCRDR", "structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55", null ], + [ "DCRSR", "structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b", null ], + [ "DEMCR", "structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee", null ], + [ "DHCSR", "structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structDWT__Type.html b/docs/Core/html/structDWT__Type.html new file mode 100644 index 0000000..a02d24b --- /dev/null +++ b/docs/Core/html/structDWT__Type.html @@ -0,0 +1,490 @@ + + + + + +DWT_Type Struct Reference +CMSIS-Core (Cortex-M): DWT_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    DWT_Type Struct Reference
    +
    +
    + +

    Structure type to access the Data Watchpoint and Trace Register (DWT). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t CTRL
     Offset: 0x000 (R/W) Control Register. More...
     
    __IOM uint32_t CYCCNT
     Offset: 0x004 (R/W) Cycle Count Register. More...
     
    __IOM uint32_t CPICNT
     Offset: 0x008 (R/W) CPI Count Register. More...
     
    __IOM uint32_t EXCCNT
     Offset: 0x00C (R/W) Exception Overhead Count Register. More...
     
    __IOM uint32_t SLEEPCNT
     Offset: 0x010 (R/W) Sleep Count Register. More...
     
    __IOM uint32_t LSUCNT
     Offset: 0x014 (R/W) LSU Count Register. More...
     
    __IOM uint32_t FOLDCNT
     Offset: 0x018 (R/W) Folded-instruction Count Register. More...
     
    __IM uint32_t PCSR
     Offset: 0x01C (R/ ) Program Counter Sample Register. More...
     
    __IOM uint32_t COMP0
     Offset: 0x020 (R/W) Comparator Register 0. More...
     
    __IOM uint32_t MASK0
     Offset: 0x024 (R/W) Mask Register 0. More...
     
    __IOM uint32_t FUNCTION0
     Offset: 0x028 (R/W) Function Register 0. More...
     
    uint32_t RESERVED0 [1]
     Reserved. More...
     
    __IOM uint32_t COMP1
     Offset: 0x030 (R/W) Comparator Register 1. More...
     
    __IOM uint32_t MASK1
     Offset: 0x034 (R/W) Mask Register 1. More...
     
    __IOM uint32_t FUNCTION1
     Offset: 0x038 (R/W) Function Register 1. More...
     
    uint32_t RESERVED1 [1]
     Reserved. More...
     
    __IOM uint32_t COMP2
     Offset: 0x040 (R/W) Comparator Register 2. More...
     
    __IOM uint32_t MASK2
     Offset: 0x044 (R/W) Mask Register 2. More...
     
    __IOM uint32_t FUNCTION2
     Offset: 0x048 (R/W) Function Register 2. More...
     
    uint32_t RESERVED2 [1]
     Reserved. More...
     
    __IOM uint32_t COMP3
     Offset: 0x050 (R/W) Comparator Register 3. More...
     
    __IOM uint32_t MASK3
     Offset: 0x054 (R/W) Mask Register 3. More...
     
    __IOM uint32_t FUNCTION3
     Offset: 0x058 (R/W) Function Register 3. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP0
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP3
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::CPICNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::CTRL
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::CYCCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::EXCCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FOLDCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION0
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION3
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::LSUCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK0
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK3
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t DWT_Type::PCSR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED0[1]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED1[1]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED2[1]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::SLEEPCNT
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structDWT__Type.js b/docs/Core/html/structDWT__Type.js new file mode 100644 index 0000000..d8092ba --- /dev/null +++ b/docs/Core/html/structDWT__Type.js @@ -0,0 +1,26 @@ +var structDWT__Type = +[ + [ "COMP0", "structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9", null ], + [ "COMP1", "structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931", null ], + [ "COMP2", "structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46", null ], + [ "COMP3", "structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847", null ], + [ "CPICNT", "structDWT__Type.html#a2c08096c82abe245c0fa97badc458154", null ], + [ "CTRL", "structDWT__Type.html#add790c53410023b3b581919bb681fe2a", null ], + [ "CYCCNT", "structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9", null ], + [ "EXCCNT", "structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1", null ], + [ "FOLDCNT", "structDWT__Type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97", null ], + [ "FUNCTION0", "structDWT__Type.html#a579ae082f58a0317b7ef029b20f52889", null ], + [ "FUNCTION1", "structDWT__Type.html#a8dfcf25675f9606aa305c46e85182e4e", null ], + [ "FUNCTION2", "structDWT__Type.html#ab1b60d6600c38abae515bab8e86a188f", null ], + [ "FUNCTION3", "structDWT__Type.html#a52d4ff278fae6f9216c63b74ce328841", null ], + [ "LSUCNT", "structDWT__Type.html#acc05d89bdb1b4fe2fa499920ec02d0b1", null ], + [ "MASK0", "structDWT__Type.html#a821eb5e71f340ec077efc064cfc567db", null ], + [ "MASK1", "structDWT__Type.html#aabf94936c9340e62fed836dcfb152405", null ], + [ "MASK2", "structDWT__Type.html#a00ac4d830dfe0070a656cda9baed170f", null ], + [ "MASK3", "structDWT__Type.html#a2a509d8505c37a3b64f6b24993df5f3f", null ], + [ "PCSR", "structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113", null ], + [ "RESERVED0", "structDWT__Type.html#addd893d655ed90d40705b20170daac59", null ], + [ "RESERVED1", "structDWT__Type.html#a069871233a8c1df03521e6d7094f1de4", null ], + [ "RESERVED2", "structDWT__Type.html#a8556ca1c32590517602d92fe0cd55738", null ], + [ "SLEEPCNT", "structDWT__Type.html#a416a54e2084ce66e5ca74f152a5ecc70", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structFPU__Type.html b/docs/Core/html/structFPU__Type.html new file mode 100644 index 0000000..a8a2efb --- /dev/null +++ b/docs/Core/html/structFPU__Type.html @@ -0,0 +1,235 @@ + + + + + +FPU_Type Struct Reference +CMSIS-Core (Cortex-M): FPU_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    FPU_Type Struct Reference
    +
    +
    + +

    Structure type to access the Floating Point Unit (FPU). +

    + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    uint32_t RESERVED0 [1]
     Reserved. More...
     
    __IOM uint32_t FPCCR
     Offset: 0x004 (R/W) Floating-Point Context Control Register. More...
     
    __IOM uint32_t FPCAR
     Offset: 0x008 (R/W) Floating-Point Context Address Register. More...
     
    __IOM uint32_t FPDSCR
     Offset: 0x00C (R/W) Floating-Point Default Status Control Register. More...
     
    __IM uint32_t MVFR0
     Offset: 0x010 (R/ ) Media and FP Feature Register 0. More...
     
    __IM uint32_t MVFR1
     Offset: 0x014 (R/ ) Media and FP Feature Register 1. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t FPU_Type::FPCAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t FPU_Type::FPCCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t FPU_Type::FPDSCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t FPU_Type::MVFR0
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t FPU_Type::MVFR1
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t FPU_Type::RESERVED0[1]
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structFPU__Type.js b/docs/Core/html/structFPU__Type.js new file mode 100644 index 0000000..0a8dfde --- /dev/null +++ b/docs/Core/html/structFPU__Type.js @@ -0,0 +1,9 @@ +var structFPU__Type = +[ + [ "FPCAR", "structFPU__Type.html#a55263b468d0f8e11ac77aec9ff87c820", null ], + [ "FPCCR", "structFPU__Type.html#af1b708c5e413739150df3d16ca3b7061", null ], + [ "FPDSCR", "structFPU__Type.html#a58d1989664a06db6ec2e122eefa9f04a", null ], + [ "MVFR0", "structFPU__Type.html#a4f19014defe6033d070b80af19ef627c", null ], + [ "MVFR1", "structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d", null ], + [ "RESERVED0", "structFPU__Type.html#a7b2967b069046c8544adbbc1db143a36", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structITM__Type.html b/docs/Core/html/structITM__Type.html new file mode 100644 index 0000000..b163e30 --- /dev/null +++ b/docs/Core/html/structITM__Type.html @@ -0,0 +1,521 @@ + + + + + +ITM_Type Struct Reference +CMSIS-Core (Cortex-M): ITM_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    ITM_Type Struct Reference
    +
    +
    + +

    Structure type to access the Instrumentation Trace Macrocell Register (ITM). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    union {
       __OM uint8_t   u8
     
       __OM uint16_t   u16
     
       __OM uint32_t   u32
     
    } PORT [32U]
     
    __IOM uint32_t TER
     
    __IOM uint32_t TPR
     
    __IOM uint32_t TCR
     
    __OM uint32_t IWR
     
    __IM uint32_t IRR
     
    __IOM uint32_t IMCR
     
    __OM uint32_t LAR
     
    __IM uint32_t LSR
     
    __IM uint32_t DEVARCH
     
    __IM uint32_t PID4
     
    __IM uint32_t PID5
     
    __IM uint32_t PID6
     
    __IM uint32_t PID7
     
    __IM uint32_t PID0
     
    __IM uint32_t PID1
     
    __IM uint32_t PID2
     
    __IM uint32_t PID3
     
    __IM uint32_t CID0
     
    __IM uint32_t CID1
     
    __IM uint32_t CID2
     
    __IM uint32_t CID3
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::CID0
    +
    +

    Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::CID1
    +
    +

    Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::CID2
    +
    +

    Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::CID3
    +
    +

    Offset: 0xFFC (R/ ) ITM Component Identification Register #3

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::DEVARCH
    +
    +

    Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only)

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::IMCR
    +
    +

    Offset: 0xF00 (R/W) ITM Integration Mode Control Register

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::IRR
    +
    +

    Offset: 0xEFC (R/ ) ITM Integration Read Register

    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t ITM_Type::IWR
    +
    +

    Offset: 0xEF8 ( /W) ITM Integration Write Register

    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t ITM_Type::LAR
    +
    +

    Offset: 0xFB0 ( /W) ITM Lock Access Register

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::LSR
    +
    +

    Offset: 0xFB4 (R/ ) ITM Lock Status Register

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID0
    +
    +

    Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID1
    +
    +

    Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID2
    +
    +

    Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID3
    +
    +

    Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID4
    +
    +

    Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID5
    +
    +

    Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID6
    +
    +

    Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t ITM_Type::PID7
    +
    +

    Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

    + +
    +
    + +
    +
    + + + + +
    __OM { ... } ITM_Type::PORT[32U]
    +
    +

    Offset: 0x000 ( /W) ITM Stimulus Port Registers

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::TCR
    +
    +

    Offset: 0xE80 (R/W) ITM Trace Control Register

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::TER
    +
    +

    Offset: 0xE00 (R/W) ITM Trace Enable Register

    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::TPR
    +
    +

    Offset: 0xE40 (R/W) ITM Trace Privilege Register

    + +
    +
    + +
    +
    + + + + +
    __OM uint16_t ITM_Type::u16
    +
    +

    Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t ITM_Type::u32
    +
    +

    Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

    + +
    +
    + +
    +
    + + + + +
    __OM uint8_t ITM_Type::u8
    +
    +

    Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structITM__Type.js b/docs/Core/html/structITM__Type.js new file mode 100644 index 0000000..8aa3816 --- /dev/null +++ b/docs/Core/html/structITM__Type.js @@ -0,0 +1,28 @@ +var structITM__Type = +[ + [ "CID0", "structITM__Type.html#a30bb2b166b1723867da4a708935677ba", null ], + [ "CID1", "structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f", null ], + [ "CID2", "structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d", null ], + [ "CID3", "structITM__Type.html#a43451f43f514108d9eaed5b017f8d921", null ], + [ "DEVARCH", "structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537", null ], + [ "IMCR", "structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0", null ], + [ "IRR", "structITM__Type.html#a66eb82a070953f09909f39b8e516fb91", null ], + [ "IWR", "structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94", null ], + [ "LAR", "structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5", null ], + [ "LSR", "structITM__Type.html#a3861c67933a24dd6632288c4ed0b80c8", null ], + [ "PID0", "structITM__Type.html#ab4a4cc97ad658e9c46cf17490daffb8a", null ], + [ "PID1", "structITM__Type.html#a89ea1d805a668d6589b22d8e678eb6a4", null ], + [ "PID2", "structITM__Type.html#a8471c4d77b7107cf580587509da69f38", null ], + [ "PID3", "structITM__Type.html#af317d5e2d946d70e6fb67c02b92cc8a3", null ], + [ "PID4", "structITM__Type.html#aad5e11dd4baf6d941bd6c7450f60a158", null ], + [ "PID5", "structITM__Type.html#af9085648bf18f69b5f9d1136d45e1d37", null ], + [ "PID6", "structITM__Type.html#ad34dbe6b1072c77d36281049c8b169f6", null ], + [ "PID7", "structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d", null ], + [ "PORT", "structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e", null ], + [ "TCR", "structITM__Type.html#a04b9fbc83759cb818dfa161d39628426", null ], + [ "TER", "structITM__Type.html#acd03c6858f7b678dab6a6121462e7807", null ], + [ "TPR", "structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2", null ], + [ "u16", "structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3", null ], + [ "u32", "structITM__Type.html#a5834885903a557674f078f3b71fa8bc8", null ], + [ "u8", "structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structMPU__Type.html b/docs/Core/html/structMPU__Type.html new file mode 100644 index 0000000..2e66293 --- /dev/null +++ b/docs/Core/html/structMPU__Type.html @@ -0,0 +1,395 @@ + + + + + +MPU_Type Struct Reference +CMSIS-Core (Cortex-M): MPU_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    MPU_Type Struct Reference
    MPU Functions for Armv7-M
    +
    +
    + +

    Structure type to access the Memory Protection Unit (MPU). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IM uint32_t TYPE
     Offset: 0x000 (R/ ) MPU Type Register. More...
     
    __IOM uint32_t CTRL
     Offset: 0x004 (R/W) MPU Control Register. More...
     
    __IOM uint32_t RNR
     Offset: 0x008 (R/W) MPU Region RNRber Register. More...
     
    __IOM uint32_t RBAR
     Offset: 0x00C (R/W) MPU Region Base Address Register. More...
     
    __IOM uint32_t RASR
     Offset: 0x010 (R/W) MPU Region Attribute and Size Register. More...
     
    __IOM uint32_t RBAR_A1
     Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. More...
     
    __IOM uint32_t RASR_A1
     Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. More...
     
    __IOM uint32_t RBAR_A2
     Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. More...
     
    __IOM uint32_t RASR_A2
     Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. More...
     
    __IOM uint32_t RBAR_A3
     Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. More...
     
    __IOM uint32_t RASR_A3
     Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    MPU_Type::CTRL
    +
    +

    Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.

    + + + + + + + + + + + +
    Bits Name Function
    [31:3] - Reserved.
    [2] PRIVDEFENA 0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access.
    [1] HFNMIENA 0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers.
    [0] ENABLE 0 - The MPU is disabled. 1 - The MPU is enabled.
    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RASR
    +
    +

    Defines the size and access behavior of the region identified by MPU_RNR, and enables that region.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Bits Name Function
    [31:29] - Reserved.
    [28] XN Execute Never.
    [27] - Reserved.
    [26:24] AP Access Permissions, see ARM_MPU_AP_xxx.
    [23:22] - Reserved.
    [21:19] TEX Type Extension.
    [18] S Shareable.
    [17] C Cacheable.
    [16] B Bufferable.
    [15:8] SRD Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1).
    [7:6] - Reserved.
    [5:1] SIZE Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.
    [0] ENABLE 0 - This region is disabled. 1 - This region is enabled.
    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RASR_A1
    +
    +

    Alias for MPU_Type::RASR.

    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RASR_A2
    +
    +

    Alias for MPU_Type::RASR.

    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RASR_A3
    +
    +

    Alias for MPU_Type::RASR.

    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RBAR
    +
    +

    Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.

    + + + + + + + + + +
    Bits Name Function
    [31:5] ADDR Base address of the region.
    [4] VALID 1 - Update MPU_Type::RNR to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.
    [3:0] REGION On writes, can specify the number of the region to update, see VALID field description.
    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RBAR_A1
    +
    +

    Alias for MPU_Type::RBAR.

    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RBAR_A2
    +
    +

    Alias for MPU_Type::RBAR.

    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RBAR_A3
    +
    +

    Alias for MPU_Type::RBAR.

    + +
    +
    + +
    +
    + + + + +
    MPU_Type::RNR
    +
    +

    Selects the region currently accessed by MPU_Type::RBAR and MPU_Type::RASR.

    + + + + + + + +
    Bits Name Function
    [31:8] - Reserved.
    [7:0] REGION Indicates the memory region accessed.
    + +
    +
    + +
    +
    + + + + +
    MPU_Type::TYPE
    +
    +

    The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.

    + + + + + + + + + + + + + +
    Bits Name Function
    [31:24] - Reserved.
    [23:16] IREGION Instruction region. RAZ. Armv7-M only supports a unified MPU.
    [15:8] DREGION Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU.
    [7:1] - Reserved.
    [0] SEPARATE Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU.
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structMPU__Type.js b/docs/Core/html/structMPU__Type.js new file mode 100644 index 0000000..d66b592 --- /dev/null +++ b/docs/Core/html/structMPU__Type.js @@ -0,0 +1,14 @@ +var structMPU__Type = +[ + [ "CTRL", "structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f", null ], + [ "RASR", "structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3", null ], + [ "RASR_A1", "structMPU__Type.html#a1658326c6762637eeef8a79bb467445e", null ], + [ "RASR_A2", "structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205", null ], + [ "RASR_A3", "structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd", null ], + [ "RBAR", "structMPU__Type.html#a990c609b26d990b8ba832b110adfd353", null ], + [ "RBAR_A1", "structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066", null ], + [ "RBAR_A2", "structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2", null ], + [ "RBAR_A3", "structMPU__Type.html#a207f6e9c3af753367554cc06df300a55", null ], + [ "RNR", "structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c", null ], + [ "TYPE", "structMPU__Type.html#aba02af87f77577c725cf73879cabb609", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structNVIC__Type.html b/docs/Core/html/structNVIC__Type.html new file mode 100644 index 0000000..386ca6c --- /dev/null +++ b/docs/Core/html/structNVIC__Type.html @@ -0,0 +1,340 @@ + + + + + +NVIC_Type Struct Reference +CMSIS-Core (Cortex-M): NVIC_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    NVIC_Type Struct Reference
    +
    +
    + +

    Structure type to access the Nested Vectored Interrupt Controller (NVIC). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t ISER [8]
     Offset: 0x000 (R/W) Interrupt Set Enable Register. More...
     
    uint32_t RESERVED0 [24]
     Reserved. More...
     
    __IOM uint32_t ICER [8]
     Offset: 0x080 (R/W) Interrupt Clear Enable Register. More...
     
    uint32_t RSERVED1 [24]
     Reserved. More...
     
    __IOM uint32_t ISPR [8]
     Offset: 0x100 (R/W) Interrupt Set Pending Register. More...
     
    uint32_t RESERVED2 [24]
     Reserved. More...
     
    __IOM uint32_t ICPR [8]
     Offset: 0x180 (R/W) Interrupt Clear Pending Register. More...
     
    uint32_t RESERVED3 [24]
     Reserved. More...
     
    __IOM uint32_t IABR [8]
     Offset: 0x200 (R/W) Interrupt Active bit Register. More...
     
    uint32_t RESERVED4 [56]
     Reserved. More...
     
    __IOM uint8_t IP [240]
     Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) More...
     
    uint32_t RESERVED5 [644]
     Reserved. More...
     
    __OM uint32_t STIR
     Offset: 0xE00 ( /W) Software Trigger Interrupt Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::IABR[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ICER[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ICPR[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t NVIC_Type::IP[240]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ISER[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ISPR[8]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED0[24]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED2[24]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED3[24]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED4[56]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED5[644]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RSERVED1[24]
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t NVIC_Type::STIR
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structNVIC__Type.js b/docs/Core/html/structNVIC__Type.js new file mode 100644 index 0000000..8ba5410 --- /dev/null +++ b/docs/Core/html/structNVIC__Type.js @@ -0,0 +1,16 @@ +var structNVIC__Type = +[ + [ "IABR", "structNVIC__Type.html#a4bca5452748ba84d64536fb6a5d795af", null ], + [ "ICER", "structNVIC__Type.html#a245df8bac1da05c39eadabede9323203", null ], + [ "ICPR", "structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95", null ], + [ "IP", "structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd", null ], + [ "ISER", "structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47", null ], + [ "ISPR", "structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0", null ], + [ "RESERVED0", "structNVIC__Type.html#a2de17698945ea49abd58a2d45bdc9c80", null ], + [ "RESERVED2", "structNVIC__Type.html#a0953af43af8ec7fd5869a1d826ce5b72", null ], + [ "RESERVED3", "structNVIC__Type.html#a9dd330835dbf21471e7b5be8692d77ab", null ], + [ "RESERVED4", "structNVIC__Type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790", null ], + [ "RESERVED5", "structNVIC__Type.html#a4f753b4f824270175af045ac99bc12e8", null ], + [ "RSERVED1", "structNVIC__Type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe", null ], + [ "STIR", "structNVIC__Type.html#a37de89637466e007171c6b135299bc75", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structSCB__Type.html b/docs/Core/html/structSCB__Type.html new file mode 100644 index 0000000..c3facb9 --- /dev/null +++ b/docs/Core/html/structSCB__Type.html @@ -0,0 +1,460 @@ + + + + + +SCB_Type Struct Reference +CMSIS-Core (Cortex-M): SCB_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    SCB_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Control Block (SCB). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IM uint32_t CPUID
     Offset: 0x000 (R/ ) CPUID Base Register. More...
     
    __IOM uint32_t ICSR
     Offset: 0x004 (R/W) Interrupt Control and State Register. More...
     
    __IOM uint32_t VTOR
     Offset: 0x008 (R/W) Vector Table Offset Register. More...
     
    __IOM uint32_t AIRCR
     Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. More...
     
    __IOM uint32_t SCR
     Offset: 0x010 (R/W) System Control Register. More...
     
    __IOM uint32_t CCR
     Offset: 0x014 (R/W) Configuration Control Register. More...
     
    __IOM uint8_t SHP [12]
     Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) More...
     
    __IOM uint32_t SHCSR
     Offset: 0x024 (R/W) System Handler Control and State Register. More...
     
    __IOM uint32_t CFSR
     Offset: 0x028 (R/W) Configurable Fault Status Register. More...
     
    __IOM uint32_t HFSR
     Offset: 0x02C (R/W) HardFault Status Register. More...
     
    __IOM uint32_t DFSR
     Offset: 0x030 (R/W) Debug Fault Status Register. More...
     
    __IOM uint32_t MMFAR
     Offset: 0x034 (R/W) MemManage Fault Address Register. More...
     
    __IOM uint32_t BFAR
     Offset: 0x038 (R/W) BusFault Address Register. More...
     
    __IOM uint32_t AFSR
     Offset: 0x03C (R/W) Auxiliary Fault Status Register. More...
     
    __IM uint32_t PFR [2]
     Offset: 0x040 (R/ ) Processor Feature Register. More...
     
    __IM uint32_t DFR
     Offset: 0x048 (R/ ) Debug Feature Register. More...
     
    __IM uint32_t ADR
     Offset: 0x04C (R/ ) Auxiliary Feature Register. More...
     
    __IM uint32_t MMFR [4]
     Offset: 0x050 (R/ ) Memory Model Feature Register. More...
     
    __IM uint32_t ISAR [5]
     Offset: 0x060 (R/ ) Instruction Set Attributes Register. More...
     
    uint32_t RESERVED0 [5]
     Reserved. More...
     
    __IOM uint32_t CPACR
     Offset: 0x088 (R/W) Coprocessor Access Control Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::ADR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::AFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::AIRCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::BFAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::CCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::CFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::CPACR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::CPUID
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::DFR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::DFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::HFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::ICSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::ISAR[5]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::MMFAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::MMFR[4]
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::PFR[2]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCB_Type::RESERVED0[5]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::SCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::SHCSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t SCB_Type::SHP[12]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::VTOR
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structSCB__Type.js b/docs/Core/html/structSCB__Type.js new file mode 100644 index 0000000..a0ae15a --- /dev/null +++ b/docs/Core/html/structSCB__Type.js @@ -0,0 +1,24 @@ +var structSCB__Type = +[ + [ "ADR", "structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1", null ], + [ "AFSR", "structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e", null ], + [ "AIRCR", "structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380", null ], + [ "BFAR", "structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c", null ], + [ "CCR", "structSCB__Type.html#a2d6653b0b70faac936046a02809b577f", null ], + [ "CFSR", "structSCB__Type.html#a0cda9e061b42373383418663092ad19a", null ], + [ "CPACR", "structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764", null ], + [ "CPUID", "structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46", null ], + [ "DFR", "structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004", null ], + [ "DFSR", "structSCB__Type.html#a191579bde0d21ff51d30a714fd887033", null ], + [ "HFSR", "structSCB__Type.html#a14ad254659362b9752c69afe3fd80934", null ], + [ "ICSR", "structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a", null ], + [ "ISAR", "structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066", null ], + [ "MMFAR", "structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80", null ], + [ "MMFR", "structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c", null ], + [ "PFR", "structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d", null ], + [ "RESERVED0", "structSCB__Type.html#ac89a5d9901e3748d22a7090bfca2bee6", null ], + [ "SCR", "structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34", null ], + [ "SHCSR", "structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4", null ], + [ "SHP", "structSCB__Type.html#a85768f4b3dbbc41fd760041ee1202162", null ], + [ "VTOR", "structSCB__Type.html#a187a4578e920544ed967f98020fb8170", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structSCnSCB__Type.html b/docs/Core/html/structSCnSCB__Type.html new file mode 100644 index 0000000..b6587c7 --- /dev/null +++ b/docs/Core/html/structSCnSCB__Type.html @@ -0,0 +1,190 @@ + + + + + +SCnSCB_Type Struct Reference +CMSIS-Core (Cortex-M): SCnSCB_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    SCnSCB_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Control and ID Register not in the SCB. +

    + + + + + + + + + + + +

    +Data Fields

    uint32_t RESERVED0 [1]
     Reserved. More...
     
    __IM uint32_t ICTR
     Offset: 0x004 (R/ ) Interrupt Controller Type Register. More...
     
    __IOM uint32_t ACTLR
     Offset: 0x008 (R/W) Auxiliary Control Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t SCnSCB_Type::ACTLR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCnSCB_Type::ICTR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCnSCB_Type::RESERVED0[1]
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structSCnSCB__Type.js b/docs/Core/html/structSCnSCB__Type.js new file mode 100644 index 0000000..cb2bdd0 --- /dev/null +++ b/docs/Core/html/structSCnSCB__Type.js @@ -0,0 +1,6 @@ +var structSCnSCB__Type = +[ + [ "ACTLR", "structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23", null ], + [ "ICTR", "structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762", null ], + [ "RESERVED0", "structSCnSCB__Type.html#afe1d5fd2966d5062716613b05c8d0ae1", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structSysTick__Type.html b/docs/Core/html/structSysTick__Type.html new file mode 100644 index 0000000..bcd0dbf --- /dev/null +++ b/docs/Core/html/structSysTick__Type.html @@ -0,0 +1,205 @@ + + + + + +SysTick_Type Struct Reference +CMSIS-Core (Cortex-M): SysTick_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    SysTick_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Timer (SysTick). +

    + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t CTRL
     Offset: 0x000 (R/W) SysTick Control and Status Register. More...
     
    __IOM uint32_t LOAD
     Offset: 0x004 (R/W) SysTick Reload Value Register. More...
     
    __IOM uint32_t VAL
     Offset: 0x008 (R/W) SysTick Current Value Register. More...
     
    __IM uint32_t CALIB
     Offset: 0x00C (R/ ) SysTick Calibration Register. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IM uint32_t SysTick_Type::CALIB
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SysTick_Type::CTRL
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SysTick_Type::LOAD
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SysTick_Type::VAL
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structSysTick__Type.js b/docs/Core/html/structSysTick__Type.js new file mode 100644 index 0000000..3827439 --- /dev/null +++ b/docs/Core/html/structSysTick__Type.js @@ -0,0 +1,7 @@ +var structSysTick__Type = +[ + [ "CALIB", "structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de", null ], + [ "CTRL", "structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e", null ], + [ "LOAD", "structSysTick__Type.html#a4780a489256bb9f54d0ba8ed4de191cd", null ], + [ "VAL", "structSysTick__Type.html#a9b5420d17e8e43104ddd4ae5a610af93", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/structTPI__Type.html b/docs/Core/html/structTPI__Type.html new file mode 100644 index 0000000..b5cf052 --- /dev/null +++ b/docs/Core/html/structTPI__Type.html @@ -0,0 +1,505 @@ + + + + + +TPI_Type Struct Reference +CMSIS-Core (Cortex-M): TPI_Type Struct Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    TPI_Type Struct Reference
    +
    +
    + +

    Structure type to access the Trace Port Interface Register (TPI). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t SSPSR
     Offset: 0x000 (R/ ) Supported Parallel Port Size Register. More...
     
    __IOM uint32_t CSPSR
     Offset: 0x004 (R/W) Current Parallel Port Size Register. More...
     
    uint32_t RESERVED0 [2]
     Reserved. More...
     
    __IOM uint32_t ACPR
     Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. More...
     
    uint32_t RESERVED1 [55]
     Reserved. More...
     
    __IOM uint32_t SPPR
     Offset: 0x0F0 (R/W) Selected Pin Protocol Register. More...
     
    uint32_t RESERVED2 [131]
     Reserved. More...
     
    __IM uint32_t FFSR
     Offset: 0x300 (R/ ) Formatter and Flush Status Register. More...
     
    __IOM uint32_t FFCR
     Offset: 0x304 (R/W) Formatter and Flush Control Register. More...
     
    __IM uint32_t FSCR
     Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. More...
     
    uint32_t RESERVED3 [759]
     Reserved. More...
     
    __IM uint32_t TRIGGER
     Offset: 0xEE8 (R/ ) TRIGGER. More...
     
    __IM uint32_t FIFO0
     Offset: 0xEEC (R/ ) Integration ETM Data. More...
     
    __IM uint32_t ITATBCTR2
     Offset: 0xEF0 (R/ ) ITATBCTR2. More...
     
    uint32_t RESERVED4 [1]
     Reserved. More...
     
    __IM uint32_t ITATBCTR0
     Offset: 0xEF8 (R/ ) ITATBCTR0. More...
     
    __IM uint32_t FIFO1
     Offset: 0xEFC (R/ ) Integration ITM Data. More...
     
    __IOM uint32_t ITCTRL
     Offset: 0xF00 (R/W) Integration Mode Control. More...
     
    uint32_t RESERVED5 [39]
     Reserved. More...
     
    __IOM uint32_t CLAIMSET
     Offset: 0xFA0 (R/W) Claim tag set. More...
     
    __IOM uint32_t CLAIMCLR
     Offset: 0xFA4 (R/W) Claim tag clear. More...
     
    uint32_t RESERVED7 [8]
     Reserved. More...
     
    __IM uint32_t DEVID
     Offset: 0xFC8 (R/ ) TPIU_DEVID. More...
     
    __IM uint32_t DEVTYPE
     Offset: 0xFCC (R/ ) TPIU_DEVTYPE. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::ACPR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::CLAIMCLR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::CLAIMSET
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::CSPSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::DEVID
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::DEVTYPE
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::FFCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FIFO0
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FIFO1
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FSCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::ITATBCTR0
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::ITATBCTR2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::ITCTRL
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED0[2]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED1[55]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED2[131]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED3[759]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED4[1]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED5[39]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED7[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::SPPR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::SSPSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::TRIGGER
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/structTPI__Type.js b/docs/Core/html/structTPI__Type.js new file mode 100644 index 0000000..49365fe --- /dev/null +++ b/docs/Core/html/structTPI__Type.js @@ -0,0 +1,27 @@ +var structTPI__Type = +[ + [ "ACPR", "structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3", null ], + [ "CLAIMCLR", "structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac", null ], + [ "CLAIMSET", "structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a", null ], + [ "CSPSR", "structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f", null ], + [ "DEVID", "structTPI__Type.html#abc0ecda8a5446bc754080276bad77514", null ], + [ "DEVTYPE", "structTPI__Type.html#ad98855854a719bbea33061e71529a472", null ], + [ "FFCR", "structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2", null ], + [ "FFSR", "structTPI__Type.html#a6c47a0b4c7ffc66093ef993d36bb441c", null ], + [ "FIFO0", "structTPI__Type.html#aa4d7b5cf39dff9f53bf7f69bc287a814", null ], + [ "FIFO1", "structTPI__Type.html#a061372fcd72f1eea871e2d9c1be849bc", null ], + [ "FSCR", "structTPI__Type.html#ad6901bfd8a0089ca7e8a20475cf494a8", null ], + [ "ITATBCTR0", "structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0", null ], + [ "ITATBCTR2", "structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652", null ], + [ "ITCTRL", "structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d", null ], + [ "RESERVED0", "structTPI__Type.html#af143c5e8fc9a3b2be2878e9c1f331aa9", null ], + [ "RESERVED1", "structTPI__Type.html#ac3956fe93987b725d89d3be32738da12", null ], + [ "RESERVED2", "structTPI__Type.html#ac7bbb92e6231b9b38ac483f7d161a096", null ], + [ "RESERVED3", "structTPI__Type.html#a31700c8cdd26e4c094db72af33d9f24c", null ], + [ "RESERVED4", "structTPI__Type.html#a684071216fafee4e80be6aaa932cec46", null ], + [ "RESERVED5", "structTPI__Type.html#a3f80dd93f6bab6524603a7aa58de9a30", null ], + [ "RESERVED7", "structTPI__Type.html#a476ca23fbc9480f1697fbec871130550", null ], + [ "SPPR", "structTPI__Type.html#a12f79d4e3ddc69893ba8bff890d04cc5", null ], + [ "SSPSR", "structTPI__Type.html#a7b72598e20066133e505bb781690dc22", null ], + [ "TRIGGER", "structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/sync_off.png b/docs/Core/html/sync_off.png new file mode 100644 index 0000000..e8e314d Binary files /dev/null and b/docs/Core/html/sync_off.png differ diff --git a/docs/Core/html/sync_on.png b/docs/Core/html/sync_on.png new file mode 100644 index 0000000..f80906a Binary files /dev/null and b/docs/Core/html/sync_on.png differ diff --git a/docs/Core/html/system_c_pg.html b/docs/Core/html/system_c_pg.html new file mode 100644 index 0000000..337fc32 --- /dev/null +++ b/docs/Core/html/system_c_pg.html @@ -0,0 +1,265 @@ + + + + + +System Configuration Files system_<device>.c and system_<device>.h +CMSIS-Core (Cortex-M): System Configuration Files system_<device>.c and system_<device>.h + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    System Configuration Files system_<device>.c and system_<device>.h
    +
    +
    +

    The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.

    +

    For devices with external memory BUS the system_<device>.c also configures the BUS system.

    +

    The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.

    +

    +system_Device.c Template File

    +

    The system_Device.c Template File for the Cortex-M3 is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device <Device>
+ * @version  V5.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include "<Device>.h"
+
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization
+         following is an example for different system frequencies */
+#define XTAL            (12000000U)       /* Oscillator frequency             */
+
+#define SYSTEM_CLOCK    (5 * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit() */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Clock Frequency (Core Clock)*/
+
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings. */
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards. */
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+

    +system_Device.h Template File

    +

    The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V5.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_<Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */
+
    +
    + + + + diff --git a/docs/Core/html/tab_a.png b/docs/Core/html/tab_a.png new file mode 100644 index 0000000..fffadc1 Binary files /dev/null and b/docs/Core/html/tab_a.png differ diff --git a/docs/Core/html/tab_b.png b/docs/Core/html/tab_b.png new file mode 100644 index 0000000..b7ce1af Binary files /dev/null and b/docs/Core/html/tab_b.png differ diff --git a/docs/Core/html/tab_h.png b/docs/Core/html/tab_h.png new file mode 100644 index 0000000..5e9188f Binary files /dev/null and b/docs/Core/html/tab_h.png differ diff --git a/docs/Core/html/tab_s.png b/docs/Core/html/tab_s.png new file mode 100644 index 0000000..956e1c2 Binary files /dev/null and b/docs/Core/html/tab_s.png differ diff --git a/docs/Core/html/tab_topnav.png b/docs/Core/html/tab_topnav.png new file mode 100644 index 0000000..b257b77 Binary files /dev/null and b/docs/Core/html/tab_topnav.png differ diff --git a/docs/Core/html/tabs.css b/docs/Core/html/tabs.css new file mode 100644 index 0000000..ffbab50 --- /dev/null +++ b/docs/Core/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/docs/Core/html/templates_pg.html b/docs/Core/html/templates_pg.html new file mode 100644 index 0000000..41927d4 --- /dev/null +++ b/docs/Core/html/templates_pg.html @@ -0,0 +1,275 @@ + + + + + +CMSIS-Core Device Templates +CMSIS-Core (Cortex-M): CMSIS-Core Device Templates + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    CMSIS-Core Device Templates
    +
    +
    +

    Arm supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliance.

    +

    These CMSIS-Core device template files include the following:

    +
      +
    • Register names of the Core Peripherals and names of the Core Exception Vectors.
      • +
    • Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4 and Cortex-M7)
      • +
    • Generic startup code and system configuration code.
      • +
    +

    The detailed file structure of the CMSIS-Core device templates is shown in the following picture.

    +
    +CMSIS_CORE_Files.png +
    +CMSIS-Core File Structure
    +

    +CMSIS-Core Processor Files

    +

    The CMSIS-Core processor files provided by Arm are in the directory .\CMSIS\Core\Include. These header files define all processor specific attributes do not need any modifications. The core_<cpu>.h defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-M processor:

    + + + + + + + + + + + + + + + + + + + + + + + + + +
    Header File Processor
    core_cm0.h for the Cortex-M0 processor
    core_cm0plus.h for the Cortex-M0+ processor
    core_cm3.h for the Cortex-M3 processor
    core_cm4.h for the Cortex-M4 processor
    core_cm7.h for the Cortex-M7 processor
    core_cm23.h for the Cortex-M23 processor
    core_cm33.h for the Cortex-M33 processor
    core_sc000.h for the SecurCore SC000 processor
    core_sc300.h for the SecurCore SC300 processor
    core_armv8mbl.h for the Armv8-M Baseline processor
    core_armv8mml.h for the Armv8-M Mainline processor
    +

    +Device Examples

    +

    The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\Device\ARM and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file ARM.CMSIS.pdsc:

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Family Device Description
    ARM Cortex-M0 ARMCM0 Cortex-M0 based device
    ARM Cortex-M0 plus ARMCM0P Cortex-M0+ based device
    ARM Cortex-M3 ARMCM3 Cortex-M3 based device
    ARM Cortex-M4 ARMCM4 Cortex-M4 based device without floating-point hardware
    ARM Cortex-M4 ARMCM4_FP Cortex-M4 based device with floating-point hardware
    ARM Cortex-M7 ARMCM7 Cortex-M4 based device without floating-point hardware
    ARM Cortex-M7 ARMCM7_FP Cortex-M7 based device with single precision floating-point unit (FPU)
    ARM Cortex-M7 ARMCM7_DP Cortex-M7 based device with double precision floating-point unit
    ARM Cortex-M7 ARMCM7 Cortex-M7 based device without floating-point hardware
    ARM Cortex-M23 ARMCM23 Cortex-M23 based device without TrustZone
    ARM Cortex-M23 ARMCM23_TZ Cortex-M23 based device with TrustZone
    ARM Cortex-M33 ARMCM33 Cortex-M33 based device without TrustZone, SIMD, FPU
    ARM Cortex-M33 ARMCM33_TZ Cortex-M33 based device with TrustZone, no SIMD, no FPU
    ARM Cortex-M33 ARMCM33_DSP_FP Cortex-M23 based device with SIMD, FPU, no TrustZone
    ARM Cortex-M33 ARMCM33_DSP_FP_TZ Cortex-M23 based device with TrustZone, SIMD, FPU
    ARM SC000 ARM SC000 SC000 based device
    ARM SC300 ARM SC300 SC300 based device
    ARMv8-M Baseline ARMv8MBL Armv8-M Baseline based device with TrustZone
    ARMv8-M Mainline ARMv8MML Armv8-M Mainline based device with TrustZone
    ARMv8-M Mainline ARMv8MML_DP Armv8-M Mainline based device with TrustZone and double precision FPU
    ARMv8-M Mainline ARMv8MML_SP Armv8-M Mainline based device with TrustZone and single precision FPU
    ARMv8-M Mainline ARMv8MML_DSP Armv8-M Mainline based device with TrustZone and SIMD
    ARMv8-M Mainline ARMv8MML_DSP_DP Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU
    ARMv8-M Mainline ARMv8MML_DSP_SP Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU
    +

    +Template Files

    +

    To simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add to these template files the following information:

    +
      +
    • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
      • +
    • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
      • +
    • Interrupt vectors in the startup file that are device specific.
      • +
    + + + + + + + + + + + + + + + +
    Template File Description
    .\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s Startup file template for Arm C/C++ Compiler.
    .\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s Startup file template for GNU GCC Arm Embedded Compiler.
    .\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s Startup file template for IAR C/C++ Compiler.
    .\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).
    .\Device\_Template_Vendor\Vendor\Device\Include\Device.h Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.
    .\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h Generic system device configuration include file.
    +

    Adapt Template Files to a Device

    +

    The following steps describe how to adopt the template files to a specific device or device family. Copy the complete all files in the template directory and replace:

    +
      +
    • directory name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
      • +
    • directory name 'Device' with the specific device name e.g.: LPC17xx.
      • +
    • in the file names 'Device' with the specific device name e.g.: LPC17xx.
      • +
    +

    Each template file contains comments that start with ToDo: that describe a required modification. The template files contain place holders:

    + + + + + + + + + + + +
    Placeholder Replaced with
    <Device> the specific device name or device family name; i.e. LPC17xx.
    <DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1.
    <DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.
    Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.
    +

    The device configuration of the template files is described in detail on the following pages:

    + +
    +
    + + + + diff --git a/docs/Core/html/templates_pg.js b/docs/Core/html/templates_pg.js new file mode 100644 index 0000000..d47081f --- /dev/null +++ b/docs/Core/html/templates_pg.js @@ -0,0 +1,26 @@ +var templates_pg = +[ + [ "CMSIS-Core Processor Files", "templates_pg.html#CMSIS_Processor_files", null ], + [ "Device Examples", "templates_pg.html#device_examples", null ], + [ "Template Files", "templates_pg.html#template_files_sec", null ], + [ "Startup File startup_.s", "startup_s_pg.html", [ + [ "startup_Device.s Template File", "startup_s_pg.html#startup_s_sec", null ] + ] ], + [ "System Configuration Files system_.c and system_.h", "system_c_pg.html", [ + [ "system_Device.c Template File", "system_c_pg.html#system_Device_sec", null ], + [ "system_Device.h Template File", "system_c_pg.html#system_Device_h_sec", null ] + ] ], + [ "Device Header File ", "device_h_pg.html", [ + [ "Interrupt Number Definition", "device_h_pg.html#interrupt_number_sec", null ], + [ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#core_config_sect", null ], + [ "CMSIS Version and Processor Information", "device_h_pg.html#core_version_sect", null ], + [ "Device Peripheral Access Layer", "device_h_pg.html#device_access", null ], + [ "Device.h Template File", "device_h_pg.html#device_h_sec", null ] + ] ], + [ "System Partition Header File partition_.h", "partition_h_pg.html", [ + [ "SAU CTRL register settings", "partition_h_pg.html#sau_ctrlregister_sec", null ], + [ "Configuration of the SAU Address Regions", "partition_h_pg.html#sau_regions_sect", null ], + [ "Configuration of Sleep and Exception behaviour", "partition_h_pg.html#sau_sleepexception_sec", null ], + [ "Configuration of Interrupt Target settings", "partition_h_pg.html#sau_interrupttarget_sec", null ] + ] ] +]; \ No newline at end of file diff --git a/docs/Core/html/unionAPSR__Type.html b/docs/Core/html/unionAPSR__Type.html new file mode 100644 index 0000000..47c8164 --- /dev/null +++ b/docs/Core/html/unionAPSR__Type.html @@ -0,0 +1,266 @@ + + + + + +APSR_Type Union Reference +CMSIS-Core (Cortex-M): APSR_Type Union Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    APSR_Type Union Reference
    +
    +
    + +

    Union type to access the Application Program Status Register (APSR). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   _reserved0:27
     bit: 0..26 Reserved More...
     
       uint32_t   Q:1
     bit: 27 Saturation condition flag More...
     
       uint32_t   V:1
     bit: 28 Overflow condition code flag More...
     
       uint32_t   C:1
     bit: 29 Carry condition code flag More...
     
       uint32_t   Z:1
     bit: 30 Zero condition code flag More...
     
       uint32_t   N:1
     bit: 31 Negative condition code flag More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t APSR_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } APSR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::C
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::N
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::Q
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::V
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::Z
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/unionAPSR__Type.js b/docs/Core/html/unionAPSR__Type.js new file mode 100644 index 0000000..a962e31 --- /dev/null +++ b/docs/Core/html/unionAPSR__Type.js @@ -0,0 +1,11 @@ +var unionAPSR__Type = +[ + [ "_reserved0", "unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728", null ], + [ "b", "unionAPSR__Type.html#a7dbc79a057ded4b11ca5323fc2d5ab14", null ], + [ "C", "unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6", null ], + [ "N", "unionAPSR__Type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0", null ], + [ "Q", "unionAPSR__Type.html#a22d10913489d24ab08bd83457daa88de", null ], + [ "V", "unionAPSR__Type.html#a8004d224aacb78ca37774c35f9156e7e", null ], + [ "w", "unionAPSR__Type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94", null ], + [ "Z", "unionAPSR__Type.html#a3b04d58738b66a28ff13f23d8b0ba7e5", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/unionCONTROL__Type.html b/docs/Core/html/unionCONTROL__Type.html new file mode 100644 index 0000000..89314db --- /dev/null +++ b/docs/Core/html/unionCONTROL__Type.html @@ -0,0 +1,236 @@ + + + + + +CONTROL_Type Union Reference +CMSIS-Core (Cortex-M): CONTROL_Type Union Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CONTROL_Type Union Reference
    +
    +
    + +

    Union type to access the Control Registers (CONTROL). +

    + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   nPRIV:1
     bit: 0 Execution privilege in Thread mode More...
     
       uint32_t   SPSEL:1
     bit: 1 Stack to be used More...
     
       uint32_t   FPCA:1
     bit: 2 FP extension active flag More...
     
       uint32_t   _reserved0:29
     bit: 3..31 Reserved More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t CONTROL_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CONTROL_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::FPCA
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::nPRIV
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::SPSEL
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/unionCONTROL__Type.js b/docs/Core/html/unionCONTROL__Type.js new file mode 100644 index 0000000..059a405 --- /dev/null +++ b/docs/Core/html/unionCONTROL__Type.js @@ -0,0 +1,9 @@ +var unionCONTROL__Type = +[ + [ "_reserved0", "unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50", null ], + [ "b", "unionCONTROL__Type.html#adc6a38ab2980d0e9577b5a871da14eb9", null ], + [ "FPCA", "unionCONTROL__Type.html#ac62cfff08e6f055e0101785bad7094cd", null ], + [ "nPRIV", "unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605", null ], + [ "SPSEL", "unionCONTROL__Type.html#a8cc085fea1c50a8bd9adea63931ee8e2", null ], + [ "w", "unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/unionIPSR__Type.html b/docs/Core/html/unionIPSR__Type.html new file mode 100644 index 0000000..e36bca0 --- /dev/null +++ b/docs/Core/html/unionIPSR__Type.html @@ -0,0 +1,206 @@ + + + + + +IPSR_Type Union Reference +CMSIS-Core (Cortex-M): IPSR_Type Union Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    IPSR_Type Union Reference
    +
    +
    + +

    Union type to access the Interrupt Program Status Register (IPSR). +

    + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   ISR:9
     bit: 0.. 8 Exception number More...
     
       uint32_t   _reserved0:23
     bit: 9..31 Reserved More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t IPSR_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } IPSR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IPSR_Type::ISR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IPSR_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/unionIPSR__Type.js b/docs/Core/html/unionIPSR__Type.js new file mode 100644 index 0000000..e341e5f --- /dev/null +++ b/docs/Core/html/unionIPSR__Type.js @@ -0,0 +1,7 @@ +var unionIPSR__Type = +[ + [ "_reserved0", "unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa", null ], + [ "b", "unionIPSR__Type.html#add0d6497bd50c25569ea22b48a03ec50", null ], + [ "ISR", "unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5", null ], + [ "w", "unionIPSR__Type.html#a4adca999d3a0bc1ae682d73ea7cfa879", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/unionxPSR__Type.html b/docs/Core/html/unionxPSR__Type.html new file mode 100644 index 0000000..017f0a1 --- /dev/null +++ b/docs/Core/html/unionxPSR__Type.html @@ -0,0 +1,311 @@ + + + + + +xPSR_Type Union Reference +CMSIS-Core (Cortex-M): xPSR_Type Union Reference + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    xPSR_Type Union Reference
    +
    +
    + +

    Union type to access the Special-Purpose Program Status Registers (xPSR). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   ISR:9
     bit: 0.. 8 Exception number More...
     
       uint32_t   _reserved0:15
     bit: 9..23 Reserved More...
     
       uint32_t   T:1
     bit: 24 Thumb bit (read 0) More...
     
       uint32_t   IT:2
     bit: 25..26 saved IT state (read 0) More...
     
       uint32_t   Q:1
     bit: 27 Saturation condition flag More...
     
       uint32_t   V:1
     bit: 28 Overflow condition code flag More...
     
       uint32_t   C:1
     bit: 29 Carry condition code flag More...
     
       uint32_t   Z:1
     bit: 30 Zero condition code flag More...
     
       uint32_t   N:1
     bit: 31 Negative condition code flag More...
     
    } b
     Structure used for bit access. More...
     
    uint32_t w
     Type used for word access. More...
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t xPSR_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } xPSR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::C
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::ISR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::IT
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::N
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::Q
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::T
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::V
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t xPSR_Type::Z
    +
    + +
    +
    +
    +
    + + + + diff --git a/docs/Core/html/unionxPSR__Type.js b/docs/Core/html/unionxPSR__Type.js new file mode 100644 index 0000000..111692f --- /dev/null +++ b/docs/Core/html/unionxPSR__Type.js @@ -0,0 +1,14 @@ +var unionxPSR__Type = +[ + [ "_reserved0", "unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5", null ], + [ "b", "unionxPSR__Type.html#a3b1063bb5cdad67e037cba993b693b70", null ], + [ "C", "unionxPSR__Type.html#a40213a6b5620410cac83b0d89564609d", null ], + [ "ISR", "unionxPSR__Type.html#a3e9120dcf1a829fc8d2302b4d0673970", null ], + [ "IT", "unionxPSR__Type.html#a3200966922a194d84425e2807a7f1328", null ], + [ "N", "unionxPSR__Type.html#a2db9a52f6d42809627d1a7a607c5dbc5", null ], + [ "Q", "unionxPSR__Type.html#add7cbd2b0abd8954d62cd7831796ac7c", null ], + [ "T", "unionxPSR__Type.html#a7eed9fe24ae8d354cd76ae1c1110a658", null ], + [ "V", "unionxPSR__Type.html#af14df16ea0690070c45b95f2116b7a0a", null ], + [ "w", "unionxPSR__Type.html#a1a47176768f45f79076c4f5b1b534bc2", null ], + [ "Z", "unionxPSR__Type.html#a1e5d9801013d5146f2e02d9b7b3da562", null ] +]; \ No newline at end of file diff --git a/docs/Core/html/using_ARM_pg.html b/docs/Core/html/using_ARM_pg.html new file mode 100644 index 0000000..551b056 --- /dev/null +++ b/docs/Core/html/using_ARM_pg.html @@ -0,0 +1,169 @@ + + + + + +Using CMSIS with generic Arm Processors +CMSIS-Core (Cortex-M): Using CMSIS with generic Arm Processors + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Using CMSIS with generic Arm Processors
    +
    +
    +

    Arm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors. These files can be used when standard Arm processors should be used in a project. The table below lists the folder and device names of the Arm processors.

    + + + + + + + + + + + + + + + + + +
    Folder Processor Description
    ".\Device\ARM\ARMCM0" Cortex-M0 Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.
    ".\Device\ARM\ARMCM0plus" Cortex-M0+ Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.
    ".\Device\ARM\ARMCM3" Cortex-M3 Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.
    ".\Device\ARM\ARMCM4" Cortex-M4 Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.
    ".\Device\ARM\ARMCM7" Cortex-M7 Contains Include and Source template files configured for the Cortex-M7 processor. The device name is ARMCM7 and the name of the Device Header File <device.h> is <ARMCM7.h>.
    ".\Device\ARM\ARMSC000" SecurCore SC000 Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.
    ".\Device\ARM\ARMSC300" SecurCore SC300 Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.
    +

    +Create generic Libraries with CMSIS

    +

    The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP Libraries are an example for such a generic library.

    +

    To build a generic Library set the define __CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define __CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.

    +

    Example:

    +

    The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To select the processor, the source code uses the define CORTEX_M7, CORTEX_M4, CORTEX_M3, CORTEX_M0, or CORTEX_M0PLUS. One of these defines needs to be provided on the compiler command line. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7], and Debug Access.

    +
    #define __CMSIS_GENERIC /* disable NVIC and Systick functions */
    +
    +
    #if defined (CORTEX_M7)
    +
    #include "core_cm7.h"
    +
    #elif defined (CORTEX_M4)
    +
    #include "core_cm4.h"
    +
    #elif defined (CORTEX_M3)
    +
    #include "core_cm3.h"
    +
    #elif defined (CORTEX_M0)
    +
    #include "core_cm0.h"
    +
    #elif defined (CORTEX_M0PLUS)
    +
    #include "core_cm0plus.h"
    +
    #else
    +
    #error "Processor not specified or unsupported."
    +
    #endif
    +
    +
    + + + + diff --git a/docs/Core/html/using_CMSIS.html b/docs/Core/html/using_CMSIS.html new file mode 100644 index 0000000..dbd6688 --- /dev/null +++ b/docs/Core/html/using_CMSIS.html @@ -0,0 +1,177 @@ + + + + + +Basic CMSIS Example +CMSIS-Core (Cortex-M): Basic CMSIS Example + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Basic CMSIS Example
    +
    +
    +

    A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.

    +
    #include <stm32f10x.h> // File name depends on device used
    +
    +
    uint32_t volatile msTicks; // Counter for millisecond Interval
    +
    +
    void SysTick_Handler (void) { // SysTick Interrupt Handler
    +
    msTicks++; // Increment Counter
    +
    }
    +
    +
    void WaitForTick (void) {
    +
    uint32_t curTicks;
    +
    +
    curTicks = msTicks; // Save Current SysTick Value
    +
    while (msTicks == curTicks) { // Wait for next SysTick Interrupt
    +
    __WFE (); // Power-Down until next Event/Interrupt
    +
    }
    +
    }
    +
    +
    void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
    +
    ; // Add user code here
    +
    }
    +
    +
    void timer1_init(int frequency) { // Set up Timer (device specific)
    +
    NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
    +
    NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
    +
    }
    +
    +
    +
    void Device_Initialization (void) { // Configure & Initialize MCU
    +
    if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
    +
    : // Handle Error
    +
    }
    +
    timer1_init (); // setup device-specific timer
    +
    }
    +
    +
    +
    // The processor clock is initialized by CMSIS startup + system file
    +
    void main (void) { // user application starts here
    +
    Device_Initialization (); // Configure & Initialize MCU
    +
    while (1) { // Endless Loop (the Super-Loop)
    +
    __disable_irq (); // Disable all interrupts
    +
    Get_InputValues (); // Read Values
    +
    __enable_irq (); // Enable all interrupts
    +
    Calculation_Response (); // Calculate Results
    +
    Output_Response (); // Output Results
    +
    WaitForTick (); // Synchronize to SysTick Timer
    +
    }
    +
    }
    +
    +
    + + + + diff --git a/docs/Core/html/using_TrustZone_pg.html b/docs/Core/html/using_TrustZone_pg.html new file mode 100644 index 0000000..1604bbb --- /dev/null +++ b/docs/Core/html/using_TrustZone_pg.html @@ -0,0 +1,216 @@ + + + + + +Using TrustZone for Armv8-M +CMSIS-Core (Cortex-M): Using TrustZone for Armv8-M + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Using TrustZone for Armv8-M
    +
    +
    +

    The optional Armv8-M Security Extension is similar to Arm TrustZone technology used in Cortex-A processors, but is optimized for ultra-low power embedded applications. TrustZone for Armv8-M enables of multiple software security domains that restrict access to secure memory and I/O only for trusted software.

    +

    TrustZone for Armv8-M:

    +
      +
    • preserves low interrupt latencies for both Secure and Non-secure domains.
      • +
    • does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.
      • +
    • introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.
      • +
    +

    Notations

    +

    This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:

    +
      +
    • prefix TZ or __TZ indicates a function that is available only in Armv8-M TrustZone enabled devices.
      • +
    • postfix _NS indicates a hardware resource that belongs to the Non-secure state.
      • +
    • postfix _S indicates a hardware resource that belongs to the Secure state.
      • +
    +

    +Simplified Use Case with TrustZone

    +

    An Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted software that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection, or multi-party embedded software deployments.

    +

    The figure Simplified Use Case shows and embedded application that is split into a User Project (executed in Non-secure state) and a Firmware Project (executed in Secure state).

    +
      +
    • System Start: after power on or reset, an Armv8-M system starts code execution in the Secure state. The access rights for the Non-secure state is configured.
      • +
    • User Application: control can be transferred to Non-secure state to execute user code. This code can only call functions in the secure state that are marked for execution with the SG (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the Secure state triggers a security exception.
      • +
    • Firmware callbacks: code running in the Secure state can execute code in the Non-secure state using call-back function pointers. For example, a communication stack (protected firmware) could use an I/O driver that is configured in user space.
      • +
    +

    +
    +SimpleUseCase.png +
    +Simplified Use Case
    +

    Program execution in the Secure state is further protected by TrustZone hardware from software failures. For example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution in Non-secure state in case of timing violations. Also function pointer callbacks from Secure state to Non-secure state protected by a special CPU instruction and the address bit 0 which prevents anciently executing code in Non-secure state.

    +

    +Program Examples

    +

    This CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:

    + + + + + + + + + +
    Example Description
    TrustZone for Armv8-M No RTOS bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).
    TrustZone for Armv8-M RTOS secure/non-secure RTOS example with thread context management
    TrustZone for Armv8-M RTOS Security Tests secure/non-secure RTOS example with security test cases and system recovery
    +

    Other sample application that reflects this Simplified Use Case is the Armv8MBL Secure/Non-Secure example that is available in the Software Pack Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices (Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).

    +

    +Programmers Model with TrustZone

    +

    The figure Secure Memory Map shows the memory view for the Secure state. In the Secure state all memory and peripherals can be accessed. The System Control and Debug area provides access to secure peripherals and non-secure peripherals that are mirrored at a memory alias.

    +

    The secure peripherals are only accessible during program execution in Secure state. The Secure Attribute Unit (SAU) configures the non-secure memory, peripheral, and interrupt access. Also available are a secure MPU (memory protection unit), secure SCB (system control block), and secure SysTick timer.

    +

    The system supports two separate interrupt vector tables for secure and non-secure code execution. This interrupt assignment is controlled during Secure state code execution via the NVIC (nested vector interrupt controller).

    +

    +
    +MemoryMap_S.png +
    +Secure Memory Map
    +

    The figure Non-Secure Memory Map shows the memory view for the Non-secure state. This memory view is identical to the traditional Cortex-M memory map. Access to any secure memory or peripheral space triggers the secure exception that executes a handler in Secure state.

    +

    The System Partition Header File partition_<device>.h defines the initial setup of the Non-Secure Memory Map during system start in the Secure state (refer to functions SystemInit and TZ_SAU_Setup).

    +

    +
    +MemoryMap_NS.png +
    +Non-Secure Memory Map
    +

    The figure Registers shows the register view of the Armv8-M system with TrustZone. As the general purpose registers are can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter and return values.

    +

    The register R13 is the stack pointer alias, and the actual stack pointer (PSP_NS, MSP_NS, PSP_S, MSP_S) accessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or thread=normal code execution).

    +

    In Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S) that traps stack overflows with the UsageFault exception (register UFSR bit STKOF=1).

    +

    An Armv8-M system with TrustZone has an independent CONTROL register for each state (Secure or Non-secure). The interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure), however the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that secure interrupts have always higher priority.

    +

    The core registers of the current state (Secure or Non-secure) are accessed using the standard Core Register Access functions. In Secure state all non-secure registers are accessible using the Core Register Access Functions related to TrustZone for Armv8-M.

    +
    +Registers.png +
    +Registers
    +

    +CMSIS Files for TrustZone

    +

    The CMSIS-Core files are extended by the System Partition Header File partition_<device>.h which defines the initial system configuration and during SystemInit in Secure state.

    +
    +CMSIS_TZ_files.png +
    +CMSIS with extensions for TrustZone
    +
    Note
    Refer to Using CMSIS in Embedded Applications for a general description of the CMSIS-Core (Cortex-M) files.
    +

    +RTOS Thread Context Management

    +

    To provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file TZ_context.h with API definitions. An non-secure application which uses an RTOS and calls secure library modules requires the management of the secure stack space. Since secure state registers cannot be accessed by the RTOS that runs in non-secure state secure functions implement the thread context switch.

    +

    As the non-secure state and secure state parts of an application are separated, the API for managing the secure stack space should be standardized. Otherwise the secure library modules would force the non-secure state application to use a matching RTOS implementation.

    +
    +TZ_context.png +
    +RTOS Thread Context Management for Armv8-M TrustZone
    +

    To allocate the context memory for threads, an RTOS kernel that runs in non-secure state calls the interface functions defined by the header file TZ_context.h. The TZ_context functions itself are part of the secure state application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory management system with additional features such as access control to secure state memory regions using an MPU.

    +

    The API functions of TZ_context are described in the chapter Reference under TrustZone for Armv8-M - RTOS Context Management.

    +

    Refer to Program Examples for RTOS examples that provide a template implementation for TZ_context.c.

    +
    +
    + + + + diff --git a/docs/Core/html/using_VTOR_pg.html b/docs/Core/html/using_VTOR_pg.html new file mode 100644 index 0000000..38958cc --- /dev/null +++ b/docs/Core/html/using_VTOR_pg.html @@ -0,0 +1,181 @@ + + + + + +Using Interrupt Vector Remap +CMSIS-Core (Cortex-M): Using Interrupt Vector Remap + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Using Interrupt Vector Remap
    +
    +
    +

    Most Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows a typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.

    +
    #include "ARMCM3.h" // Device header
    +
    +
    /* externals from startup_ARMCM3.s */
    +
    extern uint32_t __Vectors[]; /* vector table ROM */
    +
    +
    #define VECTORTABLE_SIZE (256) /* size Cortex-M3 vector table */
    +
    #define VECTORTABLE_ALIGNMENT (0x100ul) /* 16 Cortex + 32 ARMCM3 = 48 words */
    +
    /* next power of 2 = 256 */
    +
    +
    /* new vector table in RAM */
    +
    uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));
    +
    +
    /*----------------------------------------------------------------------------
    +
    SysTick_Handler
    +
    *----------------------------------------------------------------------------*/
    +
    volatile uint32_t msTicks = 0; /* counts 1ms timeTicks */
    +
    void SysTick_Handler(void) {
    +
    msTicks++; /* increment counter */
    +
    }
    +
    +
    /*----------------------------------------------------------------------------
    +
    SysTick_Handler (RAM)
    +
    *----------------------------------------------------------------------------*/
    +
    volatile uint32_t msTicks_RAM = 0; /* counts 1ms timeTicks */
    +
    void SysTick_Handler_RAM(void) {
    +
    msTicks_RAM++; /* increment counter */
    +
    }
    +
    +
    /*----------------------------------------------------------------------------
    +
    MAIN function
    +
    *----------------------------------------------------------------------------*/
    +
    int main (void) {
    +
    uint32_t i;
    +
    +
    for (i = 0; i < VECTORTABLE_SIZE; i++) {
    +
    vectorTable_RAM[i] = __Vectors[i]; /* copy vector table to RAM */
    +
    }
    +
    /* replace SysTick Handler */
    +
    vectorTable_RAM[SysTick_IRQn + 16] = (uint32_t)SysTick_Handler_RAM;
    +
    +
    /* relocate vector table */
    +
    __disable_irq();
    +
    SCB->VTOR = (uint32_t)&vectorTable_RAM;
    +
    __DSB();
    +
    __enable_irq();
    +
    +
    SystemCoreClockUpdate(); /* Get Core Clock Frequency */
    +
    SysTick_Config(SystemCoreClock / 1000ul); /* Setup SysTick Timer for 1 msec */
    +
    +
    while(1);
    +
    }
    +
    +
    + + + + diff --git a/docs/Core/html/using_pg.html b/docs/Core/html/using_pg.html new file mode 100644 index 0000000..b82e1c9 --- /dev/null +++ b/docs/Core/html/using_pg.html @@ -0,0 +1,172 @@ + + + + + +Using CMSIS in Embedded Applications +CMSIS-Core (Cortex-M): Using CMSIS in Embedded Applications + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-Core (Cortex-M) +  Version 5.1.2 +
    +
    CMSIS-Core support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Using CMSIS in Embedded Applications
    +
    +
    +

    To use the CMSIS-Core (Cortex-M) the following files are added to the embedded application:

    + +
    Note
    The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
    +

    The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.

    +

    The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.

    +

    The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:

    + +
    +CMSIS_CORE_Files_user.png +
    +CMSIS-Core (Cortex-M) User Files
    +

    The CMSIS-Core (Cortex-M) are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.

    +

    For example, the following files are provided in MDK to support the STM32F10x Connectivity Line device variants:

    + + + + + + + + + + + +
    File Description
    ".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.
    ".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.
    ".\ARM\INC\ST\STM32F10x\stm32f10x.h" Device Header File <device.h> for the STM32F10x device families.
    ".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" system_Device.h Template File for the STM32F10x device families.
    +
    Note
    The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on CMSIS-Core Device Templates provide by Arm.
    +

    Thereafter, the functions described under Reference can be used in the application.

    +

    Examples

    + +
    +
    + + + + diff --git a/docs/Core/html/using_pg.js b/docs/Core/html/using_pg.js new file mode 100644 index 0000000..caa160b --- /dev/null +++ b/docs/Core/html/using_pg.js @@ -0,0 +1,8 @@ +var using_pg = +[ + [ "Basic CMSIS Example", "using_CMSIS.html", null ], + [ "Using Interrupt Vector Remap", "using_VTOR_pg.html", null ], + [ "Using CMSIS with generic Arm Processors", "using_ARM_pg.html", [ + [ "Create generic Libraries with CMSIS", "using_ARM_pg.html#using_ARM_Lib_sec", null ] + ] ] +]; \ No newline at end of file -- cgit