From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/structSCB__Type.html | 460 ++++++++++++++++++++++++++++++++++++ 1 file changed, 460 insertions(+) create mode 100644 docs/Core/html/structSCB__Type.html (limited to 'docs/Core/html/structSCB__Type.html') diff --git a/docs/Core/html/structSCB__Type.html b/docs/Core/html/structSCB__Type.html new file mode 100644 index 0000000..c3facb9 --- /dev/null +++ b/docs/Core/html/structSCB__Type.html @@ -0,0 +1,460 @@ + + + + + +SCB_Type Struct Reference +CMSIS-Core (Cortex-M): SCB_Type Struct Reference + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.1.2 +
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CMSIS-Core support for Cortex-M processor-based devices
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SCB_Type Struct Reference
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Structure type to access the System Control Block (SCB). +

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__IM uint32_t CPUID
 Offset: 0x000 (R/ ) CPUID Base Register. More...
 
__IOM uint32_t ICSR
 Offset: 0x004 (R/W) Interrupt Control and State Register. More...
 
__IOM uint32_t VTOR
 Offset: 0x008 (R/W) Vector Table Offset Register. More...
 
__IOM uint32_t AIRCR
 Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. More...
 
__IOM uint32_t SCR
 Offset: 0x010 (R/W) System Control Register. More...
 
__IOM uint32_t CCR
 Offset: 0x014 (R/W) Configuration Control Register. More...
 
__IOM uint8_t SHP [12]
 Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) More...
 
__IOM uint32_t SHCSR
 Offset: 0x024 (R/W) System Handler Control and State Register. More...
 
__IOM uint32_t CFSR
 Offset: 0x028 (R/W) Configurable Fault Status Register. More...
 
__IOM uint32_t HFSR
 Offset: 0x02C (R/W) HardFault Status Register. More...
 
__IOM uint32_t DFSR
 Offset: 0x030 (R/W) Debug Fault Status Register. More...
 
__IOM uint32_t MMFAR
 Offset: 0x034 (R/W) MemManage Fault Address Register. More...
 
__IOM uint32_t BFAR
 Offset: 0x038 (R/W) BusFault Address Register. More...
 
__IOM uint32_t AFSR
 Offset: 0x03C (R/W) Auxiliary Fault Status Register. More...
 
__IM uint32_t PFR [2]
 Offset: 0x040 (R/ ) Processor Feature Register. More...
 
__IM uint32_t DFR
 Offset: 0x048 (R/ ) Debug Feature Register. More...
 
__IM uint32_t ADR
 Offset: 0x04C (R/ ) Auxiliary Feature Register. More...
 
__IM uint32_t MMFR [4]
 Offset: 0x050 (R/ ) Memory Model Feature Register. More...
 
__IM uint32_t ISAR [5]
 Offset: 0x060 (R/ ) Instruction Set Attributes Register. More...
 
uint32_t RESERVED0 [5]
 Reserved. More...
 
__IOM uint32_t CPACR
 Offset: 0x088 (R/W) Coprocessor Access Control Register. More...
 
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Field Documentation

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__IM uint32_t SCB_Type::ADR
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__IOM uint32_t SCB_Type::AFSR
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__IOM uint32_t SCB_Type::AIRCR
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__IOM uint32_t SCB_Type::BFAR
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__IOM uint32_t SCB_Type::CCR
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__IOM uint32_t SCB_Type::CFSR
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__IOM uint32_t SCB_Type::CPACR
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__IM uint32_t SCB_Type::CPUID
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__IM uint32_t SCB_Type::DFR
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__IOM uint32_t SCB_Type::DFSR
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__IOM uint32_t SCB_Type::HFSR
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__IOM uint32_t SCB_Type::ICSR
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__IM uint32_t SCB_Type::ISAR[5]
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__IOM uint32_t SCB_Type::MMFAR
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__IM uint32_t SCB_Type::MMFR[4]
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__IM uint32_t SCB_Type::PFR[2]
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uint32_t SCB_Type::RESERVED0[5]
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__IOM uint32_t SCB_Type::SCR
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__IOM uint32_t SCB_Type::SHCSR
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__IOM uint8_t SCB_Type::SHP[12]
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__IOM uint32_t SCB_Type::VTOR
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