From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/structNVIC__Type.html | 340 +++++++++++++++++++++++++++++++++++ 1 file changed, 340 insertions(+) create mode 100644 docs/Core/html/structNVIC__Type.html (limited to 'docs/Core/html/structNVIC__Type.html') diff --git a/docs/Core/html/structNVIC__Type.html b/docs/Core/html/structNVIC__Type.html new file mode 100644 index 0000000..386ca6c --- /dev/null +++ b/docs/Core/html/structNVIC__Type.html @@ -0,0 +1,340 @@ + + + + + +NVIC_Type Struct Reference +CMSIS-Core (Cortex-M): NVIC_Type Struct Reference + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Data Fields
+
+
NVIC_Type Struct Reference
+
+
+ +

Structure type to access the Nested Vectored Interrupt Controller (NVIC). +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Data Fields

__IOM uint32_t ISER [8]
 Offset: 0x000 (R/W) Interrupt Set Enable Register. More...
 
uint32_t RESERVED0 [24]
 Reserved. More...
 
__IOM uint32_t ICER [8]
 Offset: 0x080 (R/W) Interrupt Clear Enable Register. More...
 
uint32_t RSERVED1 [24]
 Reserved. More...
 
__IOM uint32_t ISPR [8]
 Offset: 0x100 (R/W) Interrupt Set Pending Register. More...
 
uint32_t RESERVED2 [24]
 Reserved. More...
 
__IOM uint32_t ICPR [8]
 Offset: 0x180 (R/W) Interrupt Clear Pending Register. More...
 
uint32_t RESERVED3 [24]
 Reserved. More...
 
__IOM uint32_t IABR [8]
 Offset: 0x200 (R/W) Interrupt Active bit Register. More...
 
uint32_t RESERVED4 [56]
 Reserved. More...
 
__IOM uint8_t IP [240]
 Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) More...
 
uint32_t RESERVED5 [644]
 Reserved. More...
 
__OM uint32_t STIR
 Offset: 0xE00 ( /W) Software Trigger Interrupt Register. More...
 
+

Field Documentation

+ +
+
+ + + + +
__IOM uint32_t NVIC_Type::IABR[8]
+
+ +
+
+ +
+
+ + + + +
__IOM uint32_t NVIC_Type::ICER[8]
+
+ +
+
+ +
+
+ + + + +
__IOM uint32_t NVIC_Type::ICPR[8]
+
+ +
+
+ +
+
+ + + + +
__IOM uint8_t NVIC_Type::IP[240]
+
+ +
+
+ +
+
+ + + + +
__IOM uint32_t NVIC_Type::ISER[8]
+
+ +
+
+ +
+
+ + + + +
__IOM uint32_t NVIC_Type::ISPR[8]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED0[24]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED2[24]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED3[24]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED4[56]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RESERVED5[644]
+
+ +
+
+ +
+
+ + + + +
uint32_t NVIC_Type::RSERVED1[24]
+
+ +
+
+ +
+
+ + + + +
__OM uint32_t NVIC_Type::STIR
+
+ +
+
+
+
+ + + + -- cgit