From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/structMPU__Type.html | 395 ++++++++++++++++++++++++++++++++++++ 1 file changed, 395 insertions(+) create mode 100644 docs/Core/html/structMPU__Type.html (limited to 'docs/Core/html/structMPU__Type.html') diff --git a/docs/Core/html/structMPU__Type.html b/docs/Core/html/structMPU__Type.html new file mode 100644 index 0000000..2e66293 --- /dev/null +++ b/docs/Core/html/structMPU__Type.html @@ -0,0 +1,395 @@ + + + + + +MPU_Type Struct Reference +CMSIS-Core (Cortex-M): MPU_Type Struct Reference + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.1.2 +
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CMSIS-Core support for Cortex-M processor-based devices
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MPU_Type Struct Reference
MPU Functions for Armv7-M
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Structure type to access the Memory Protection Unit (MPU). +

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__IM uint32_t TYPE
 Offset: 0x000 (R/ ) MPU Type Register. More...
 
__IOM uint32_t CTRL
 Offset: 0x004 (R/W) MPU Control Register. More...
 
__IOM uint32_t RNR
 Offset: 0x008 (R/W) MPU Region RNRber Register. More...
 
__IOM uint32_t RBAR
 Offset: 0x00C (R/W) MPU Region Base Address Register. More...
 
__IOM uint32_t RASR
 Offset: 0x010 (R/W) MPU Region Attribute and Size Register. More...
 
__IOM uint32_t RBAR_A1
 Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. More...
 
__IOM uint32_t RASR_A1
 Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. More...
 
__IOM uint32_t RBAR_A2
 Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. More...
 
__IOM uint32_t RASR_A2
 Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. More...
 
__IOM uint32_t RBAR_A3
 Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. More...
 
__IOM uint32_t RASR_A3
 Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. More...
 
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Field Documentation

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MPU_Type::CTRL
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Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.

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Bits Name Function
[31:3] - Reserved.
[2] PRIVDEFENA 0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access.
[1] HFNMIENA 0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers.
[0] ENABLE 0 - The MPU is disabled. 1 - The MPU is enabled.
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MPU_Type::RASR
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Defines the size and access behavior of the region identified by MPU_RNR, and enables that region.

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Bits Name Function
[31:29] - Reserved.
[28] XN Execute Never.
[27] - Reserved.
[26:24] AP Access Permissions, see ARM_MPU_AP_xxx.
[23:22] - Reserved.
[21:19] TEX Type Extension.
[18] S Shareable.
[17] C Cacheable.
[16] B Bufferable.
[15:8] SRD Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1).
[7:6] - Reserved.
[5:1] SIZE Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes.
[0] ENABLE 0 - This region is disabled. 1 - This region is enabled.
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MPU_Type::RASR_A1
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Alias for MPU_Type::RASR.

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MPU_Type::RASR_A2
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Alias for MPU_Type::RASR.

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MPU_Type::RASR_A3
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Alias for MPU_Type::RASR.

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MPU_Type::RBAR
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Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.

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Bits Name Function
[31:5] ADDR Base address of the region.
[4] VALID 1 - Update MPU_Type::RNR to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region.
[3:0] REGION On writes, can specify the number of the region to update, see VALID field description.
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MPU_Type::RBAR_A1
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Alias for MPU_Type::RBAR.

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MPU_Type::RBAR_A2
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Alias for MPU_Type::RBAR.

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MPU_Type::RBAR_A3
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Alias for MPU_Type::RBAR.

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MPU_Type::RNR
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Selects the region currently accessed by MPU_Type::RBAR and MPU_Type::RASR.

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Bits Name Function
[31:8] - Reserved.
[7:0] REGION Indicates the memory region accessed.
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MPU_Type::TYPE
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The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.

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Bits Name Function
[31:24] - Reserved.
[23:16] IREGION Instruction region. RAZ. Armv7-M only supports a unified MPU.
[15:8] DREGION Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU.
[7:1] - Reserved.
[0] SEPARATE Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU.
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