From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001
From: Ali Labbene <ali.labbene@st.com>
Date: Wed, 11 Dec 2019 08:59:21 +0100
Subject: Official ARM version: v5.4.0

    Add CMSIS V5.4.0, please refer to index.html available under \docs folder.

    Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
         used in existing projects, and thus avoid projects mass update
    Note: the following components have been removed from ARM original delivery (as not used in ST packages)
        - CMSIS_EW2018.pdf
        - .gitattributes
        - .gitignore
        - \Device
        - \CMSIS
           - \CoreValidation
		   - \DAP
           - \Documentation
           - \DoxyGen
           - \Driver
           - \Pack
           - \RTOS\CMSIS_RTOS_Tutorial.pdf
           - \RTOS\RTX
           - \RTOS\Template
           - \RTOS2\RTX
           - \Utilities
           - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2

Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
---
 docs/Core/html/search/all_3.js | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 docs/Core/html/search/all_3.js

(limited to 'docs/Core/html/search/all_3.js')

diff --git a/docs/Core/html/search/all_3.js b/docs/Core/html/search/all_3.js
new file mode 100644
index 0000000..472f2ba
--- /dev/null
+++ b/docs/Core/html/search/all_3.js
@@ -0,0 +1,33 @@
+var searchData=
+[
+  ['c',['C',['../unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6',1,'APSR_Type::C()'],['../unionxPSR__Type.html#a40213a6b5620410cac83b0d89564609d',1,'xPSR_Type::C()']]],
+  ['cache_20functions_20_20_28only_20cortex_2dm7_29',['Cache Functions  (only Cortex-M7)',['../group__cache__functions__m7.html',1,'']]],
+  ['calib',['CALIB',['../structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de',1,'SysTick_Type']]],
+  ['ccr',['CCR',['../structSCB__Type.html#a2d6653b0b70faac936046a02809b577f',1,'SCB_Type']]],
+  ['cfsr',['CFSR',['../structSCB__Type.html#a0cda9e061b42373383418663092ad19a',1,'SCB_Type']]],
+  ['cid0',['CID0',['../structITM__Type.html#a30bb2b166b1723867da4a708935677ba',1,'ITM_Type']]],
+  ['cid1',['CID1',['../structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f',1,'ITM_Type']]],
+  ['cid2',['CID2',['../structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d',1,'ITM_Type']]],
+  ['cid3',['CID3',['../structITM__Type.html#a43451f43f514108d9eaed5b017f8d921',1,'ITM_Type']]],
+  ['claimclr',['CLAIMCLR',['../structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac',1,'TPI_Type']]],
+  ['claimset',['CLAIMSET',['../structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a',1,'TPI_Type']]],
+  ['cmsis_5fnvic_5fvirtual',['CMSIS_NVIC_VIRTUAL',['../group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c',1,'Ref_NVIC.txt']]],
+  ['cmsis_5fvectab_5fvirtual',['CMSIS_VECTAB_VIRTUAL',['../group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d',1,'Ref_NVIC.txt']]],
+  ['comp0',['COMP0',['../structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9',1,'DWT_Type']]],
+  ['comp1',['COMP1',['../structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931',1,'DWT_Type']]],
+  ['comp2',['COMP2',['../structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46',1,'DWT_Type']]],
+  ['comp3',['COMP3',['../structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847',1,'DWT_Type']]],
+  ['compiler_20control',['Compiler Control',['../group__compiler__conntrol__gr.html',1,'']]],
+  ['control_5ftype',['CONTROL_Type',['../unionCONTROL__Type.html',1,'']]],
+  ['core_5fcm7_2etxt',['core_cm7.txt',['../core__cm7_8txt.html',1,'']]],
+  ['core_20register_20access',['Core Register Access',['../group__Core__Register__gr.html',1,'']]],
+  ['coredebug_5ftype',['CoreDebug_Type',['../structCoreDebug__Type.html',1,'']]],
+  ['core_20register_20access_20functions',['Core Register Access Functions',['../group__coreregister__trustzone__functions.html',1,'']]],
+  ['cpacr',['CPACR',['../structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764',1,'SCB_Type']]],
+  ['cpicnt',['CPICNT',['../structDWT__Type.html#a2c08096c82abe245c0fa97badc458154',1,'DWT_Type']]],
+  ['cpuid',['CPUID',['../structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46',1,'SCB_Type']]],
+  ['cspsr',['CSPSR',['../structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f',1,'TPI_Type']]],
+  ['ctrl',['CTRL',['../structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e',1,'SysTick_Type::CTRL()'],['../structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f',1,'MPU_Type::CTRL()'],['../structDWT__Type.html#add790c53410023b3b581919bb681fe2a',1,'DWT_Type::CTRL()']]],
+  ['cyccnt',['CYCCNT',['../structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9',1,'DWT_Type']]],
+  ['cmsis_2dcore_20device_20templates',['CMSIS-Core Device Templates',['../templates_pg.html',1,'']]]
+];
-- 
cgit