From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001
From: Ali Labbene <ali.labbene@st.com>
Date: Wed, 11 Dec 2019 08:59:21 +0100
Subject: Official ARM version: v5.4.0

    Add CMSIS V5.4.0, please refer to index.html available under \docs folder.

    Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
         used in existing projects, and thus avoid projects mass update
    Note: the following components have been removed from ARM original delivery (as not used in ST packages)
        - CMSIS_EW2018.pdf
        - .gitattributes
        - .gitignore
        - \Device
        - \CMSIS
           - \CoreValidation
		   - \DAP
           - \Documentation
           - \DoxyGen
           - \Driver
           - \Pack
           - \RTOS\CMSIS_RTOS_Tutorial.pdf
           - \RTOS\RTX
           - \RTOS\Template
           - \RTOS2\RTX
           - \Utilities
           - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2

Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
---
 docs/Core/html/search/all_1.js | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 docs/Core/html/search/all_1.js

(limited to 'docs/Core/html/search/all_1.js')

diff --git a/docs/Core/html/search/all_1.js b/docs/Core/html/search/all_1.js
new file mode 100644
index 0000000..f90b141
--- /dev/null
+++ b/docs/Core/html/search/all_1.js
@@ -0,0 +1,23 @@
+var searchData=
+[
+  ['acpr',['ACPR',['../structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3',1,'TPI_Type']]],
+  ['actlr',['ACTLR',['../structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23',1,'SCnSCB_Type']]],
+  ['adr',['ADR',['../structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1',1,'SCB_Type']]],
+  ['afsr',['AFSR',['../structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e',1,'SCB_Type']]],
+  ['aircr',['AIRCR',['../structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380',1,'SCB_Type']]],
+  ['apsr_5ftype',['APSR_Type',['../unionAPSR__Type.html',1,'']]],
+  ['arm_5fmpu_5faccess_5fxxx',['ARM_MPU_ACCESS_xxx',['../group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fap_5fxxx',['ARM_MPU_AP_xxx',['../group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fcachep_5fxxx',['ARM_MPU_CACHEP_xxx',['../group__mpu__defines.html#gab23596306119e7831847bd9683de3934',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fclrregion',['ARM_MPU_ClrRegion',['../group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fdisable',['ARM_MPU_Disable',['../group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fenable',['ARM_MPU_Enable',['../group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fload',['ARM_MPU_Load',['../group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5frasr',['ARM_MPU_RASR',['../group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5frasr_5fex',['ARM_MPU_RASR_EX',['../group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5frbar',['ARM_MPU_RBAR',['../group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fregion_5fsize_5fxxx',['ARM_MPU_REGION_SIZE_xxx',['../group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fregion_5ft',['ARM_MPU_Region_t',['../structARM__MPU__Region__t.html',1,'']]],
+  ['arm_5fmpu_5fsetregion',['ARM_MPU_SetRegion',['../group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d',1,'Ref_MPU.txt']]],
+  ['arm_5fmpu_5fsetregionex',['ARM_MPU_SetRegionEx',['../group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809',1,'Ref_MPU.txt']]]
+];
-- 
cgit