From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/modules.html | 155 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 docs/Core/html/modules.html (limited to 'docs/Core/html/modules.html') diff --git a/docs/Core/html/modules.html b/docs/Core/html/modules.html new file mode 100644 index 0000000..d6f059c --- /dev/null +++ b/docs/Core/html/modules.html @@ -0,0 +1,155 @@ + + + + + +Reference +CMSIS-Core (Cortex-M): Reference + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.1.2 +
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CMSIS-Core support for Cortex-M processor-based devices
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Reference
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Here is a list of all modules:
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[detail level 12]
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oVersion ControlVersion #define symbols for CMSIS release specific C/C++ source code
|\Version Control per Core (Depricated)Version #define symbols for CMSIS release specific C/C++ source code
oCompiler ControlCompiler agnostic #define symbols for generic C/C++ source code
oPeripheral AccessNaming conventions and optional features for accessing peripherals
oSystem and Clock ConfigurationFunctions for system and clock setup available in system_device.c
oInterrupts and Exceptions (NVIC)Functions to access the Nested Vector Interrupt Controller (NVIC)
oCore Register AccessFunctions to access the Cortex-M core registers
oIntrinsic Functions for CPU InstructionsFunctions that generate specific Cortex-M CPU Instructions
oIntrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]Access to dedicated SIMD instructions
oFPU FunctionsFunctions that relate to the Floating-Point Arithmetic Unit
oMPU Functions for Armv7-MFunctions that relate to the Memory Protection Unit
|\Define valuesDefine values for MPU region setup
oSystick Timer (SYSTICK)Initialize and start the SysTick timer
oDebug AccessDebug Access to the Instrumented Trace Macrocell (ITM)
oTrustZone for Armv8-MFunctions that related to optional Armv8-M security extension
|oCore Register Access FunctionsCore register Access functions related to TrustZone for Armv8-M
|oNVIC FunctionsNested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M
|oSysTick FunctionsSysTick functions related to TrustZone for Armv8-M
|oSAU FunctionsSecure Attribution Unit (SAU) functions related to TrustZone for Armv8-M
|\RTOS Context ManagementRTOS Thread Context Management for Armv8-M TrustZone
\Cache Functions (only Cortex-M7)Functions for Instruction and Data Cache
 oI-Cache FunctionsFunctions for the instruction cache
 \D-Cache FunctionsFunctions for the data cache
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