From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- docs/Core/html/group__mpu__functions.html | 59 ++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 8 deletions(-) (limited to 'docs/Core/html/group__mpu__functions.html') diff --git a/docs/Core/html/group__mpu__functions.html b/docs/Core/html/group__mpu__functions.html index 0803dee..82bccc6 100644 --- a/docs/Core/html/group__mpu__functions.html +++ b/docs/Core/html/group__mpu__functions.html @@ -3,8 +3,8 @@ -MPU Functions for Armv7-M -CMSIS-Core (Cortex-M): MPU Functions for Armv7-M +MPU Functions for Armv6-M/v7-M +CMSIS-Core (Cortex-M): MPU Functions for Armv6-M/v7-M @@ -32,7 +32,7 @@ Logo
CMSIS-Core (Cortex-M) -  Version 5.1.2 +  Version 5.3.0
CMSIS-Core support for Cortex-M processor-based devices
@@ -113,7 +113,7 @@ $(document).ready(function(){initNavTree('group__mpu__functions.html','');}); Macros | Functions
-
MPU Functions for Armv7-M
+
MPU Functions for Armv6-M/v7-M
@@ -160,6 +160,8 @@ Functions   __STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr, uint32_t rbar, uint32_t rasr)   +__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len) +  __STATIC_INLINE void ARM_MPU_Load (MPU_Region_t const *table, uint32_t cnt)   @@ -403,7 +405,7 @@ Functions -

The function ARM_MPU_Enable writes to the register MPU->CTRL and sets bit ENABLE. The parameter MPU_CTRL provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an MPU Fault Handler the MemoryManagement_IRQn exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.

+

The function ARM_MPU_Enable writes to the register MPU->CTRL and sets bit ENABLE. The parameter MPU_CTRL provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an MPU Fault Handler the MemoryManagement_IRQn exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.

The following table contains possible values for the parameter MPU_CTRL that set specific bits in register MPU->CTRL.

@@ -453,11 +455,11 @@ Functions
-
Note
only up to 16 regions can be handled as the function ARM_MPU_Load uses the REGION field in MPU->RBAR.
+
Note
only up to 16 regions can be handled as the function ARM_MPU_Load uses the REGION field in MPU->RBAR.

Example:

const ARM_MPU_Region_t mpuTable[3][4] = {
{
-
{ .RBAR = ARM_MPU_RBAR(0UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
+
{ .RBAR = ARM_MPU_RBAR(0UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
{ .RBAR = ARM_MPU_RBAR(1UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
{ .RBAR = ARM_MPU_RBAR(2UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
{ .RBAR = ARM_MPU_RBAR(3UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
@@ -481,6 +483,47 @@ Functions
ARM_MPU_Load(mpuTable[idx], 4);
}
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t * dst,
const uint32_t *__RESTRICT src,
uint32_t len 
)
+
+

Memcopy with strictly ordered memory access, e.g. for register targets.

+
Parameters
+ + + + +
dstDestination data is copied to.
srcSource data is copied from.
lenAmount of data words to be copied.
+
+
+
@@ -564,7 +607,7 @@ Functions