From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/group__mpu__defines.html | 303 ++++++++++++++++++++++++++++++++ 1 file changed, 303 insertions(+) create mode 100644 docs/Core/html/group__mpu__defines.html (limited to 'docs/Core/html/group__mpu__defines.html') diff --git a/docs/Core/html/group__mpu__defines.html b/docs/Core/html/group__mpu__defines.html new file mode 100644 index 0000000..ba7ee01 --- /dev/null +++ b/docs/Core/html/group__mpu__defines.html @@ -0,0 +1,303 @@ + + + + + +Define values +CMSIS-Core (Cortex-M): Define values + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.1.2 +
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CMSIS-Core support for Cortex-M processor-based devices
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+Macros
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Define values
MPU Functions for Armv7-M
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Define values for MPU region setup. +More...

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#define ARM_MPU_REGION_SIZE_xxx
 Size values of a MPU region (in RASR field) More...
 
#define ARM_MPU_AP_xxx
 Values for MPU region access permissions (in RASR field) More...
 
#define ARM_MPU_ACCESS_xxx
 Values for MPU region access attributes (in RASR field) More...
 
#define ARM_MPU_CACHEP_xxx
 Cache policy values for MPU region access attributes (in RASR field) More...
 
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Description

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The following define values are used with ARM_MPU_RASR to setup the RASR value field in the MPU region.

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See Also
ARM_MPU_Region_t, ARM_MPU_SetRegion, ARM_MPU_SetRegionEx.
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Macro Definition Documentation

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#define ARM_MPU_ACCESS_xxx
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The following define values are used to compose the access attributes for an MPU region:

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#define TEX Shareable Cacheable Bufferable Description
ARM_MPU_ACCESS_ORDERED 000b 1 0 0 Strongly ordered memory
ARM_MPU_ACCESS_DEVICE(S) 0s0b S 0 S Memory mapped peripheral device, shared (S=1) or non-shared (S=0)
ARM_MPU_ACCESS_NORMAL(O,I,S) 1BBb S A A Normal memory, with outer/inner cache policy (O/I=ARM_MPU_CACHEP_xxx, shared (S=1) or non-share (S=0)
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#define ARM_MPU_AP_xxx
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The following define values are used to compose the access permission for an MPU region:

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#define Value Access permissions
ARM_MPU_AP_NONE 0x0U None: any access generates a permission fault.
ARM_MPU_AP_PRIV 0x1U Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault.
ARM_MPU_AP_URO 0x2U Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault.
ARM_MPU_AP_FULL 0x3U Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated.
ARM_MPU_AP_PRO 0x5U Privileged Read-only: any unprivileged access or privileged write generates a permission fault.
ARM_MPU_AP_RO 0x6U Privileged and Unprivileged Read-only: any write generates a permission fault.
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#define ARM_MPU_CACHEP_xxx
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The following define values are used to compose the cacheability flags within the access attributes for an MPU region:

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#define Value Cacheability policy
ARM_MPU_CACHEP_NOCACHE 00b Non-cacheable
ARM_MPU_CACHEP_WB_WRA 01b Write-back, write and read allocate
ARM_MPU_CACHEP_WT_NWA 10b Write-through, no write allocate
ARM_MPU_CACHEP_WB_NWA 11b Write-back, no write allocate
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#define ARM_MPU_REGION_SIZE_xxx
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The following define values are used to compose the size information for an MPU region:

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#define Value Description
ARM_MPU_REGION_SIZE_32B 0x04U Region size 32 Bytes
ARM_MPU_REGION_SIZE_64B 0x05U Region size 64 Bytes
ARM_MPU_REGION_SIZE_128B 0x06U Region size 128 Bytes
ARM_MPU_REGION_SIZE_256B 0x07U Region size 256 Bytes
ARM_MPU_REGION_SIZE_512B 0x08U Region size 512 Bytes
ARM_MPU_REGION_SIZE_1KB 0x09U Region size 1 KByte
ARM_MPU_REGION_SIZE_2KB 0x0AU Region size 2 KBytes
ARM_MPU_REGION_SIZE_4KB 0x0BU Region size 4 KBytes
ARM_MPU_REGION_SIZE_8KB 0x0CU Region size 8 KBytes
ARM_MPU_REGION_SIZE_16KB 0x0DU Region size 16 KBytes
ARM_MPU_REGION_SIZE_32KB 0x0EU Region size 32 KBytes
ARM_MPU_REGION_SIZE_64KB 0x0FU Region size 64 KBytes
ARM_MPU_REGION_SIZE_128KB 0x10U Region size 128 KBytes
ARM_MPU_REGION_SIZE_256KB 0x11U Region size 256 KBytes
ARM_MPU_REGION_SIZE_512KB 0x12U Region size 512 KBytes
ARM_MPU_REGION_SIZE_1MB 0x13U Region size 1 MByte
ARM_MPU_REGION_SIZE_2MB 0x14U Region size 2 MBytes
ARM_MPU_REGION_SIZE_4MB 0x15U Region size 4 MBytes
ARM_MPU_REGION_SIZE_8MB 0x16U Region size 8 MBytes
ARM_MPU_REGION_SIZE_16MB 0x17U Region size 16 MBytes
ARM_MPU_REGION_SIZE_32MB 0x18U Region size 32 MBytes
ARM_MPU_REGION_SIZE_64MB 0x19U Region size 64 MBytes
ARM_MPU_REGION_SIZE_128MB 0x1AU Region size 128 MBytes
ARM_MPU_REGION_SIZE_256MB 0x1BU Region size 256 MBytes
ARM_MPU_REGION_SIZE_512MB 0x1CU Region size 512 MBytes
ARM_MPU_REGION_SIZE_1GB 0x1DU Region size 1 GByte
ARM_MPU_REGION_SIZE_2GB 0x1EU Region size 2 GBytes
ARM_MPU_REGION_SIZE_4GB 0x1FU Region size 4 GBytes
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