From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- docs/Core/html/group__mpu8__functions.html | 1142 ++++++++++++++++++++++++++++ 1 file changed, 1142 insertions(+) create mode 100644 docs/Core/html/group__mpu8__functions.html (limited to 'docs/Core/html/group__mpu8__functions.html') diff --git a/docs/Core/html/group__mpu8__functions.html b/docs/Core/html/group__mpu8__functions.html new file mode 100644 index 0000000..80175a8 --- /dev/null +++ b/docs/Core/html/group__mpu8__functions.html @@ -0,0 +1,1142 @@ + + + + + +MPU Functions for Armv8-M +CMSIS-Core (Cortex-M): MPU Functions for Armv8-M + + + + + + + + + + + + + + +
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CMSIS-Core (Cortex-M) +  Version 5.3.0 +
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CMSIS-Core support for Cortex-M processor-based devices
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+Data Structures | +Macros | +Functions
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MPU Functions for Armv8-M
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Functions that relate to the Memory Protection Unit. +More...

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+Data Structures

struct  ARM_MPU_Region_t
 Setup information of a single MPU Region. More...
 
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+Macros

#define ARM_MPU_ATTR_DEVICE   ( 0U )
 Attribute for device memory (outer only) More...
 
#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )
 Attribute for non-cacheable, normal memory. More...
 
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)
 Attribute for normal memory (outer and inner) More...
 
#define ARM_MPU_ATTR_DEVICE_nGnRnE
 Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR_DEVICE_nGnRE
 Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR_DEVICE_nGRE
 Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR_DEVICE_GRE
 Device memory type Gathering, Re-ordering, Early Write Acknowledgement. More...
 
#define ARM_MPU_ATTR(O, I)
 Memory Attribute. More...
 
#define ARM_MPU_SH_NON
 Normal memory non-shareable. More...
 
#define ARM_MPU_SH_OUTER
 Normal memory outer shareable. More...
 
#define ARM_MPU_SH_INNER
 Normal memory inner shareable. More...
 
#define ARM_MPU_AP_(RO, NP)
 Memory access permissions. More...
 
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN)
 Region Base Address Register value. More...
 
#define ARM_MPU_RLAR(LIMIT, IDX)
 Region Limit Address Register value. More...
 
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+Functions

__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_Control)
 
__STATIC_INLINE void ARM_MPU_Disable (void)
 
__STATIC_INLINE ARM_MPU_Enable_NS (uint32_t MPU_Control)
 
__STATIC_INLINE void ARM_MPU_Disable_NS (void)
 
__STATIC_INLINE void ARM_MPU_SetMemAttrEx (MPU_Type *mpu, uint8_t idx, uint8_t attr)
 
__STATIC_INLINE void ARM_MPU_SetMemAttr (uint8_t idx, uint8_t attr)
 
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS (uint8_t idx, uint8_t attr)
 
__STATIC_INLINE void ARM_MPU_ClrRegionEx (MPU_Type *mpu, uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_ClrRegion_NS (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_SetRegionEx (MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
 
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rnr, uint32_t rbar, uint32_t rlar)
 
__STATIC_INLINE void ARM_MPU_SetRegion_NS (uint32_t rnr, uint32_t rbar, uint32_t rlar)
 
__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
 
__STATIC_INLINE void ARM_MPU_LoadEx (MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
 
__STATIC_INLINE void ARM_MPU_Load (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
 
__STATIC_INLINE void ARM_MPU_Load_NS (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
 
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Description

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The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.

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The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.

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Example:

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void main()
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{
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// Set Region 0 using Attr 0
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ARM_MPU_SetMemAttr(0UL, ARM_MPU_ATTR( /* Normal memory */
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ARM_MPU_ATTR_MEMORY_(0UL, 1UL, 1UL, 1UL), /* Outer Write-Back transient with read and write allocate */
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ARM_MPU_ATTR_MEMORY_(0UL, 0UL, 1UL, 1UL) /* Inner Write-Through transient with read and write allocate */
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));
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ARM_MPU_SetRegion(0UL,
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ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), /* Non-shareable, read/write, non-privileged, execute-never */
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ARM_MPU_RLAR(0x080FFFFFUL, 0UL) /* 1MB memory block using Attr 0 */
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);
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ARM_MPU_Enable(0);
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// Execute application code that is access protected by the MPU
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ARM_MPU_Disable();
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}
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Macro Definition Documentation

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#define ARM_MPU_AP_( RO,
 NP 
)
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Parameters
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RORead-Only: Set to 1 for read-only memory.
NPNon-Privileged: Set to 1 for non-privileged memory.
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#define ARM_MPU_ATTR( O,
 I 
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Parameters
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OOuter memory attributes
IO == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
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#define ARM_MPU_ATTR_DEVICE   ( 0U )
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#define ARM_MPU_ATTR_DEVICE_GRE
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#define ARM_MPU_ATTR_DEVICE_nGnRE
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#define ARM_MPU_ATTR_DEVICE_nGnRnE
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#define ARM_MPU_ATTR_DEVICE_nGRE
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#define ARM_MPU_ATTR_MEMORY_( NT,
 WB,
 RA,
 WA 
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Parameters
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NTNon-Transient: Set to 1 for non-transient data.
WBWrite-Back: Set to 1 to use write-back update policy.
RARead Allocation: Set to 1 to use cache allocation on read miss.
WAWrite Allocation: Set to 1 to use cache allocation on write miss.
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#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )
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#define ARM_MPU_RBAR( BASE,
 SH,
 RO,
 NP,
 XN 
)
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BASEThe base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
SHDefines the Shareability domain for this memory region.
RORead-Only: Set to 1 for a read-only memory region.
NPNon-Privileged: Set to 1 for a non-privileged memory region.
XNeXecute Never: Set to 1 for a non-executable memory region.
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#define ARM_MPU_RLAR( LIMIT,
 IDX 
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LIMITThe limit address bits [31:5] for this memory region. The value is one extended.
IDXThe attribute index to be associated with this memory region.
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#define ARM_MPU_SH_INNER
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#define ARM_MPU_SH_NON
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#define ARM_MPU_SH_OUTER
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Function Documentation

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__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
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Clear and disable the given MPU region.

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rnrRegion number to be cleared.
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__STATIC_INLINE void ARM_MPU_ClrRegion_NS (uint32_t rnr)
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Clear and disable the given Non-secure MPU region.

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rnrRegion number to be cleared.
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__STATIC_INLINE void ARM_MPU_ClrRegionEx (MPU_Type * mpu,
uint32_t rnr 
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Clear and disable the given MPU region of the given MPU.

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mpuPointer to MPU to be used.
rnrRegion number to be cleared.
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__STATIC_INLINE void ARM_MPU_Disable (void )
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Disable the MPU.

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__STATIC_INLINE void ARM_MPU_Disable_NS (void )
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Disable the Non-secure MPU.

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__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_Control)
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Enable the MPU.

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MPU_ControlDefault access permissions for unconfigured regions.
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__STATIC_INLINE ARM_MPU_Enable_NS (uint32_t MPU_Control)
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Enable the Non-secure MPU.

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MPU_ControlDefault access permissions for unconfigured regions.
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__STATIC_INLINE void ARM_MPU_Load (uint32_t rnr,
ARM_MPU_Region_t const * table,
uint32_t cnt 
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Load the given number of MPU regions from a table.

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rnrFirst region number to be configured.
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.
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Example:

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const ARM_MPU_Region_t mpuTable[1][4] = {
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{
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// BASE SH RO NP XN LIMIT ATTR
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{ .RBAR = ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, 0UL, 1UL, 0UL), .RLAR = ARM_MPU_RLAR(0x080FFFFFUL, 0UL) },
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{ .RBAR = ARM_MPU_RBAR(0x20000000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), .RLAR = ARM_MPU_RLAR(0x20007FFFUL, 0UL) },
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{ .RBAR = ARM_MPU_RBAR(0x40020000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), .RLAR = ARM_MPU_RLAR(0x40021FFFUL, 1UL) },
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{ .RBAR = ARM_MPU_RBAR(0x40022000UL, ARM_MPU_SH_NON, 0UL, 1UL, 1UL), .RLAR = ARM_MPU_RLAR(0x40022FFFUL, 1UL) }
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}
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};
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void UpdateMpu(uint32_t idx)
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{
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ARM_MPU_Load(0, mpuTable[idx], 4);
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}
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__STATIC_INLINE void ARM_MPU_Load_NS (uint32_t rnr,
ARM_MPU_Region_t const * table,
uint32_t cnt 
)
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Load the given number of MPU regions from a table to the Non-secure MPU.

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rnrFirst region number to be configured.
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.
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__STATIC_INLINE void ARM_MPU_LoadEx (MPU_Type * mpu,
uint32_t rnr,
ARM_MPU_Region_t const * table,
uint32_t cnt 
)
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Load the given number of MPU regions from a table to the given MPU.

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mpuPointer to the MPU registers to be used.
rnrFirst region number to be configured.
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.
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__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t * dst,
const uint32_t *__RESTRICT src,
uint32_t len 
)
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Memcopy with strictly ordered memory access, e.g. for register targets.

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dstDestination data is copied to.
srcSource data is copied from.
lenAmount of data words to be copied.
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__STATIC_INLINE void ARM_MPU_SetMemAttr (uint8_t idx,
uint8_t attr 
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Set the memory attribute encoding.

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idxThe attribute index to be set [0-7]
attrThe attribute value to be set.
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__STATIC_INLINE void ARM_MPU_SetMemAttr_NS (uint8_t idx,
uint8_t attr 
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Set the memory attribute encoding to the Non-secure MPU.

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idxThe attribute index to be set [0-7]
attrThe attribute value to be set.
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__STATIC_INLINE void ARM_MPU_SetMemAttrEx (MPU_Type * mpu,
uint8_t idx,
uint8_t attr 
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Set the memory attribute encoding to the given MPU.

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mpuPointer to the MPU to be configured.
idxThe attribute index to be set [0-7]
attrThe attribute value to be set.
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__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rnr,
uint32_t rbar,
uint32_t rlar 
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Configure the given MPU region.

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rnrRegion number to be configured.
rbarValue for RBAR register.
rlarValue for RLAR register.
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__STATIC_INLINE void ARM_MPU_SetRegion_NS (uint32_t rnr,
uint32_t rbar,
uint32_t rlar 
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Configure the given Non-secure MPU region.

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rnrRegion number to be configured.
rbarValue for RBAR register.
rlarValue for RLAR register.
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__STATIC_INLINE void ARM_MPU_SetRegionEx (MPU_Type * mpu,
uint32_t rnr,
uint32_t rbar,
uint32_t rlar 
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Configure the given MPU region of the given MPU.

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mpuPointer to MPU to be used.
rnrRegion number to be configured.
rbarValue for RBAR register.
rlarValue for RLAR register.
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