From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/group__NVIC__gr.html | 1425 +++++++++++++++++++++++++++++++++++ 1 file changed, 1425 insertions(+) create mode 100644 docs/Core/html/group__NVIC__gr.html (limited to 'docs/Core/html/group__NVIC__gr.html') diff --git a/docs/Core/html/group__NVIC__gr.html b/docs/Core/html/group__NVIC__gr.html new file mode 100644 index 0000000..37b03e6 --- /dev/null +++ b/docs/Core/html/group__NVIC__gr.html @@ -0,0 +1,1425 @@ + + + + + +Interrupts and Exceptions (NVIC) +CMSIS-Core (Cortex-M): Interrupts and Exceptions (NVIC) + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros | +Enumerations | +Functions
+
+
Interrupts and Exceptions (NVIC)
+
+
+ +

Functions to access the Nested Vector Interrupt Controller (NVIC). +More...

+ + + + + + + + +

+Macros

#define CMSIS_NVIC_VIRTUAL
 Virtualization of the NVIC API. More...
 
#define CMSIS_VECTAB_VIRTUAL
 Virtualization of interrupt vector table access functions. More...
 
+ + + + +

+Enumerations

enum  IRQn_Type {
+  NonMaskableInt_IRQn = -14, +
+  HardFault_IRQn = -13, +
+  MemoryManagement_IRQn = -12, +
+  BusFault_IRQn = -11, +
+  UsageFault_IRQn = -10, +
+  SecureFault_IRQn = -9, +
+  SVCall_IRQn = -5, +
+  DebugMonitor_IRQn = -4, +
+  PendSV_IRQn = -2, +
+  SysTick_IRQn = -1, +
+  WWDG_STM_IRQn = 0, +
+  PVD_STM_IRQn = 1 +
+ }
 Definition of IRQn numbers. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t NVIC_GetPriorityGrouping (void)
 Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable a device specific interrupt. More...
 
uint32_t NVIC_GetEnableIRQ (IRQn_Type IRQn)
 Get a device specific interrupt enable status. More...
 
void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable a device specific interrupt. More...
 
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get the pending device specific interrupt. More...
 
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set a device specific interrupt to pending. More...
 
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear a device specific interrupt from pending. More...
 
uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for an interrupt. More...
 
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get the priority of an interrupt. More...
 
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]. More...
 
uint32_t NVIC_GetVector (IRQn_Type IRQn)
 Read Interrupt Vector [not for Cortex-M0, SC000]. More...
 
void NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
 Modify Interrupt Vector [not for Cortex-M0, SC000]. More...
 
void NVIC_SystemReset (void)
 Reset the system. More...
 
uint32_t NVIC_GetTargetState (IRQn_Type IRQn)
 Get Interrupt Target State. More...
 
uint32_t NVIC_SetTargetState (IRQn_Type IRQn)
 Set Interrupt Target State. More...
 
uint32_t NVIC_ClearTargetState (IRQn_Type IRQn)
 Clear Interrupt Target State. More...
 
+

Description

+

This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).

+

Arm provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.

+

The table below lists the core exception vectors of the various Cortex-M processors.

+ + + + + + + + + + + + + + + + + + + + + + + +
Exception Vector IRQn
+Value 		M0 M0+ M3 M4 M7 SC000 SC300 Armv8-M
+Baseline 		Armv8-M
+Mainline 		Description
NonMaskableInt_IRQn -14
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Non Maskable Interrupt
HardFault_IRQn -13
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Hard Fault Interrupt
MemoryManagement_IRQn -12    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Memory Management Interrupt
BusFault_IRQn -11    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Bus Fault Interrupt
UsageFault_IRQn -10    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Usage Fault Interrupt
SecureFault_IRQn -9              
+available +
+
+available +
+ 		Secure Fault Interrupt
SVCall_IRQn -5
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		SV Call Interrupt
DebugMonitor_IRQn -4    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		 
+available +
+ 		Debug Monitor Interrupt
PendSV_IRQn -2
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Pend SV Interrupt
SysTick_IRQn -1
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		System Tick Interrupt
+

Vector Table

+

The Vector Table defines the entry addresses of the processor exceptions and the device specific interrupts. It is typically located at the beginning of the program memory, however Using Interrupt Vector Remap it can be relocated to RAM. The symbol __Vectors is the address of the vector table in the startup code and the register SCB->VTOR holds the start address of the vector table.

+

An Armv8-M implementation with TrustZone provides two vector tables:

+
    +
  • vector table for Secure handlers
    • +
  • vector table for Non-Secure handlers
    • +
+

Refer to Programmers Model with TrustZone for more information.

+

Processor Exceptions

+

At the beginning of the vector table, the initial stack value and the exception vectors of the processor are defined. The vector table below shows the exception vectors of a Armv8-M Mainline processor. Other processor variants may have fewer vectors.

+
__Vectors DCD __initial_sp ; Top of Stack initialization
+
DCD Reset_Handler ; Reset Handler
+
DCD NMI_Handler ; NMI Handler
+
DCD HardFault_Handler ; Hard Fault Handler
+
DCD MemManage_Handler ; MPU Fault Handler
+
DCD BusFault_Handler ; Bus Fault Handler
+
DCD UsageFault_Handler ; Usage Fault Handler
+
DCD SecureFault_Handler ; Secure Fault Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD SVC_Handler ; SVCall Handler
+
DCD DebugMon_Handler ; Debug Monitor Handler
+
DCD 0 ; Reserved
+
DCD PendSV_Handler ; PendSV Handler
+
DCD SysTick_Handler ; SysTick Handler
+

Device Specific Vectors

+

Following the processor exception vectors, the vector table contains also the device specific interrupt vectors.

+
; device specific interrupts
+
DCD WWDG_IRQHandler ; Window Watchdog
+
DCD PVD_IRQHandler ; PVD through EXTI Line detect
+
DCD TAMPER_IRQHandler ; Tamper
+

All device specific interrupts should have a default interrupt handler function that can be overwritten in user code. Below is an example for this default handler function.

+
Default_Handler PROC
+
EXPORT WWDG_IRQHandler [WEAK]
+
EXPORT PVD_IRQHandler [WEAK]
+
EXPORT TAMPER_IRQHandler [WEAK]
+
:
+
:
+
WWDG_IRQHandler
+
PVD_IRQHandler
+
TAMPER_IRQHandler
+
:
+
:
+
B .
+
ENDP
+

The user application may simply define an interrupt handler function by using the handler name as shown below.

+
void WWDG_IRQHandler(void)
+
{
+
...
+
}
+

NVIC Function Usage

+

The code below shows the usage of various CMSIS NVIC functions with an LPC1700 device.

+

Code Example 1

+
#include "LPC17xx.h"
+
+
uint32_t priorityGroup; /* Variables to store priority group and priority */
+
uint32_t priority;
+
uint32_t preemptPriority;
+
uint32_t subPriority;
+
+
int main (void) {
+
NVIC_SetPriorityGrouping(5); /* Set priority group to 5:
+
Bit[7..6] preempt priority Bits,
+
Bit[5..3] subpriority Bits
+
(valid for five priority bits) */
+
+
priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping */
+
+
priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority
+
Note: priority depends on the used priority grouping */
+
NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority */
+
+
priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again */
+
NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
+
+
while(1);
+
}
+

Code Example 2

+
#include "LPC17xx.h"
+
+
uint32_t active; /* Variable to store interrupt active state */
+
+
void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */
+
+
if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occured */
+
LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occured */
+
}
+
active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0 */
+
}
+
+
int main (void) {
+
/* Set match channel register MR0 to 1 millisecond */
+
LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms? */
+
+
LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0 */
+
NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0 */
+
LPC_TIM0->TCR = (1 << 0); /* Enable timer 0 */
+
+
while(1);
+
}
+

NVIC API Virtualization

+

The CMSIS-Core has provisions for overriding NVIC APIs as required for implementing secure systems that control access to peripherals and related interrupts. These overrides allow an operating system to control the access privileges of application code to critical interrupts.

+

The NVIC function virtualization is enabled with the following #define symbols:

+
    +
  • CMSIS_NVIC_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) NVIC functions.
    • +
  • CMSIS_VECTAB_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions.
    • +
+

Macro Definition Documentation

+ +
+
+ + + + +
#define CMSIS_NVIC_VIRTUAL
+
+

When CMSIS_NVIC_VIRTUAL is defined, the NVIC access functions in the table below must be implemented for virtualizing NVIC access. These functions should be implemented in a separate source module. The original CMSIS-Core __NVIC functions are always available independent of CMSIS_NVIC_VIRTUAL.

+ + + + + + + + + + + + + + + + + + + + + + + + + +
NVIC Access Functions CMSIS-Core Functions
NVIC_EnableIRQ __NVIC_EnableIRQ
NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NVIC_DisableIRQ __NVIC_DisableIRQ
NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NVIC_GetActive __NVIC_GetActive
NVIC_SetPriority __NVIC_SetPriority
NVIC_GetPriority __NVIC_GetPriority
NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ +
+
+ +
+
+ + + + +
#define CMSIS_VECTAB_VIRTUAL
+
+

When CMSIS_NVIC_VIRTUAL is defined, the functions in the table below must be replaced to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.

+

The original CMSIS-Core functions are always available, but prefixed with __NVIC.

+ + + + + + + +
Interrupt Vector Table Access CMSIS-Core Functions
NVIC_GetVector __NVIC_GetVector
NVIC_SetVector __NVIC_SetVector
+ +
+
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn_Type
+
+

The core exception enumeration names for IRQn values are defined in the file device.h.

+
    +
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • +
  • Positive IRQn values represent device-specific exceptions (external interrupts).
    • +
  • The first device-specific interrupt has the IRQn value 0.
    • +
+

The table below describes the core exception names and their availability in various Cortex-M cores.

+ + + + + + + + + + + + + +
Enumerator
NonMaskableInt_IRQn  +

Exception 2: Non Maskable Interrupt.

+
HardFault_IRQn  +

Exception 3: Hard Fault Interrupt.

+
MemoryManagement_IRQn  +

Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].

+
BusFault_IRQn  +

Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].

+
UsageFault_IRQn  +

Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].

+
SecureFault_IRQn  +

Exception 7: Secure Fault Interrupt [only on Armv8-M].

+
SVCall_IRQn  +

Exception 11: SV Call Interrupt.

+
DebugMonitor_IRQn  +

Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].

+
PendSV_IRQn  +

Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].

+
SysTick_IRQn  +

Exception 15: System Tick Interrupt.

+
WWDG_STM_IRQn  +

Device Interrupt 0: Window WatchDog Interrupt.

+
PVD_STM_IRQn  +

Device Interrupt 1: PVD through EXTI Line detection Interrupt.

+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
+
+

This function removes the pending state of the specified device specific interrupt IRQn. IRQn cannot be a negative number.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
  • An interrupt can have the status pending though it is not active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_ClearTargetState (IRQn_Type IRQn)
+
+

Clears the interrupt target field in the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
Returns
    +
  • 0 if interrupt is assigned to Secure
    • +
  • 1 if interrupt is assigned to Non Secure
    • +
+
+
Remarks
    +
  • Only available for Armv8-M in secure state.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void NVIC_DecodePriority (uint32_t Priority,
uint32_t PriorityGroup,
uint32_t * pPreemptPriority,
uint32_t * pSubPriority 
)
+
+

This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + + +
[in]PriorityPriority
[in]PriorityGroupPriority group
[out]*pPreemptPriorityPreemptive priority value (starting from 0)
[out]*pSubPrioritySubpriority value (starting from 0)
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_DisableIRQ (IRQn_Type IRQn)
+
+

This function disables the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnNumber of the external interrupt to disable
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_EnableIRQ (IRQn_Type IRQn)
+
+

This function enables the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
  • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
    + ICTR[4:0]
      +
    • 0 - 32 interrupts supported
      • +
    • 1 - 64 interrupts supported
      • +
    • ...
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
uint32_t PreemptPriority,
uint32_t SubPriority 
)
+
+

This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + +
[in]PriorityGroupPriority group
[in]PreemptPriorityPreemptive priority value (starting from 0)
[in]SubPrioritySubpriority value (starting from 0)
+
+
+
Returns
Encoded priority for the interrupt
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetActive (IRQn_Type IRQn)
+
+

This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • 0 Interrupt is not active
    • +
  • 1 Interrupt is active, or active and pending
    • +
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • IRQn must not be negative.
    • +
  • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
    • +
  • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetEnableIRQ (IRQn_Type IRQn)
+
+

This function returns the interrupt enable status for the specified device specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • 0 Interrupt is not enabled
    • +
  • 1 Interrupt is pending
    • +
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
+
+

This function returns the pending status of the specified device specific interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • 0 Interrupt is not pending
    • +
  • 1 Interrupt is pending
    • +
+
+
Remarks
    +
  • IRQn must not be negative.
    • +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
+
+

This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device specific interrupt, or processor exception.

+

The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
Interrupt priority
+
Remarks
    +
  • Each external interrupt has an associated priority-level register.
    • +
  • Unimplemented bits are read as zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriorityGrouping (void )
+
+

This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).

+
Returns
Priority grouping field
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetTargetState (IRQn_Type IRQn)
+
+

Reads the interrupt target field from the non-secure NVIC when in secure state.

+
Parameters
+ + +
[in]IRQnExternal interrupt number. Value cannot be negative.
+
+
+
Returns
    +
  • 0 if interrupt is assigned to Secure
    • +
  • 1 if interrupt is assigned to Non Secure
    • +
+
+
Remarks
    +
  • Only available for Armv8-M in secure state.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetVector (IRQn_Type IRQn)
+
+

This function allows to read the address of an interrupt handler function.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
Address of interrupt handler function
+
Remarks
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  • For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.
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See Also
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void NVIC_SetPendingIRQ (IRQn_Type IRQn)
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This function sets the pending bit for the specified device specific interrupt IRQn. IRQn cannot be a negative value.

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Parameters
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[in]IRQnInterrupt number
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Remarks
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  • IRQn must not be negative.
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  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
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See Also
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void NVIC_SetPriority (IRQn_Type IRQn,
uint32_t priority 
)
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Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device specific interrupt, or processor exception. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.

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The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.

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Parameters
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[in]IRQnInterrupt Number
[in]priorityPriority to set
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Remarks
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  • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
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  • Writes to unimplemented bits are ignored.
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  • For Cortex-M0:
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    • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
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    • Supports 0 to 192 priority levels.
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    • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
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  • For Cortex-M3, Cortex-M4, and Cortex-M7:
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    • Dynamic switching of interrupt priority levels is supported.
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    • Supports 0 to 255 priority levels.
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    • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
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void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
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The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

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Parameters
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[in]PriorityGroupPriority group
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Remarks
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  • not for Cortex-M0, Cortex-M0+, or SC000.
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  • By default, priority group setting is zero.
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See Also
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uint32_t NVIC_SetTargetState (IRQn_Type IRQn)
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Sets the interrupt target field in the non-secure NVIC when in secure state.

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Parameters
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[in]IRQnExternal interrupt number. Value cannot be negative.
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Returns
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  • 0 if interrupt is assigned to Secure
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  • 1 if interrupt is assigned to Non Secure
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Remarks
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  • Only available for Armv8-M in secure state.
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See Also
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void NVIC_SetVector (IRQn_Type IRQn,
uint32_t vector 
)
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This function allows to change the address of an interrupt handler function.

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Parameters
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[in]IRQnInterrupt number
[in]vectorAddress of new interrupt handler function
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Remarks
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  • Usage of this function requires vector relocation to RAM. Refer to Using Interrupt Vector Remap for more information.
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    • For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.
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See Also
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void NVIC_SystemReset (void )
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This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.

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Remarks
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  • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
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See Also
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+ + + + -- cgit