From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- docs/Core/html/device_h_pg.html | 655 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 655 insertions(+) create mode 100644 docs/Core/html/device_h_pg.html (limited to 'docs/Core/html/device_h_pg.html') diff --git a/docs/Core/html/device_h_pg.html b/docs/Core/html/device_h_pg.html new file mode 100644 index 0000000..d72aff3 --- /dev/null +++ b/docs/Core/html/device_h_pg.html @@ -0,0 +1,655 @@ + + + + + +Device Header File <device.h> +CMSIS-Core (Cortex-M): Device Header File <device.h> + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-Core (Cortex-M) +  Version 5.1.2 +
+
CMSIS-Core support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Device Header File <device.h>
+
+
+

The Device Header File <device.h> contains the following sections that are device specific:

+
    +
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • +
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • +
  • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • +
+

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

+

+Interrupt Number Definition

+

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

+
    +
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • +
  • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
    • +
+

Example:

+

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
typedef enum IRQn
+
{
+
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+
NonMaskableInt_IRQn = -14,
+
HardFault_IRQn = -13,
+
SVCall_IRQn = -5,
+
PendSV_IRQn = -2,
+
SysTick_IRQn = -1,
+
/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
+
WAKEUP0_IRQn = 0,
+
WAKEUP1_IRQn = 1,
+
WAKEUP2_IRQn = 2,
+
: :
+
: :
+
EINT1_IRQn = 30,
+
EINT0_IRQn = 31,
+
} IRQn_Type;
+

+Configuration of the Processor and Core Peripherals

+

The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

+

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

+

core_cm0.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm0plus.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm3.h

+ + + + + + + + + + + +
#define Value Range Default Description
__CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm4.h

+ + + + + + + + + + + + + +
#define Value Range Default Description
__CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm7.h

+ + + + + + + + + + + + + + + + + + + + + +
#define Value Range Default Description
__CM7_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not. See __FPU_DP description below.
__FPU_DP 0 .. 1 0 The combination of the defines __FPU_PRESENT and __FPU_DP determine the whether the FPU is with single or double precision as shown in the table below.
+
+ + + + + + + + + +
__FPU_PRESENT __FPU_DP Description
0 ignored Processor has no FPU. The value set for __FPU_DP has no influence.
1 0 Processor with FPU with single precision. The file ARMCM7_SP.h has preconfigured settings for this combination.
1 1 Processor with FPU with double precision. The file ARMCM7_DP.h has preconfigured settings for this combination.
+
__ICACHE_PRESENT 0 .. 1 1 Instruction Chache present or not
__DCACHE_PRESENT 0 .. 1 1 Data Chache present or not
__DTCM_PRESENT 0 .. 1 1 Data Tightly Coupled Memory is present or not
+

core_sc000.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_sc300.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_CM23.h or core_ARMv8MBL.h

+ + + + + + + + + + + + + + + +
#define Value Range Default Description
__ARMv8MBL_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__SAUREGION_PRESENT 0 .. 1 0 Defines if SAU regions are present or not
__VTOR_PRESENT 0 .. 1 0 Defines if a VTOR register is present or not
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_CM33.h or core_ARMv8MML.h

+ + + + + + + + + + + + + + + +
#define Value Range Default Description
__ARMv8MML_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__SAUREGION_PRESENT 0 .. 1 0 Defines if SAU regions are present or not
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
__NVIC_PRIO_BITS 2 .. 8 3 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

Example

+

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

+
#define __CM4_REV 0x0001 /* Core revision r0p1 */
+
#define __MPU_PRESENT 1 /* MPU present or not */
+
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
#define __FPU_PRESENT 1 /* FPU present or not */
+
.
+
.
+
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
+

+CMSIS Version and Processor Information

+

Defines in the core_cpu.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

+

core_cm0.h

+
#define __CM0_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM0_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+
__CM0_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (0U) /* Cortex-M Core */
+

core_cm0plus.h

+
#define __CM0PLUS_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM0PLUS_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16U) | \
+
__CM0P_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (0U) /* Cortex-M Core */
+

core_cm3.h

+
#define __CM3_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM3_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+
__CM3_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (3U) /* Cortex-M Core */
+

core_cm4.h

+
#define __CM4_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM4_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+
__CM4_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (4U) /* Cortex-M Core */
+

core_cm7.h

+
#define __CM7_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __CM7_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+
__CM7_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (7U) /* Cortex-M Core */
+

core_sc000.h

+
#define __SC000_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __SC000_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+
__SC000_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_SC (0U) /* Cortex secure core */
+

core_sc300.h

+
#define __SC300_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __SC300_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+
__SC300_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_SC (300U) /* Cortex secure core */
+

core_ARMv8MBL.h

+
#define __ARMv8MBL_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __ARMv8MBL_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+
__ARMv8MBL_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (tbd) /* Cortex secure core */
+

core_ARMv8MML.h

+
#define __ARMv8MML_CMSIS_VERSION_MAIN (5U) /* [31:16] CMSIS HAL main version */
+
#define __ARMv8MML_CMSIS_VERSION_SUB (0U) /* [15:0] CMSIS HAL sub version */
+
#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+
__ARMv8MML_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
+
#define __CORTEX_M (tbd) /* Cortex secure core */
+

+Device Peripheral Access Layer

+

The Device Header File <device.h> contains for each peripheral:

+
    +
  • Register Layout Typedef
    • +
  • Base Address
    • +
  • Access Definitions
    • +
+

The section Peripheral Access shows examples for peripheral definitions.

+

+Device.h Template File

+

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

+
/**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V5.00
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment   */
+/** @addtogroup <Vendor>
+  * @{
+  */
+
+
+/* ToDo: replace '<Device>' with device name; add your doxyGen comment   */
+/** @addtogroup <Device>
+  * @{
+  */
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+
+/* =========================================================================================================================== */
+/* ================                                Interrupt Number Definition                                ================ */
+/* =========================================================================================================================== */
+
+typedef enum IRQn
+{
+/* =======================================  ARM Cortex-M# Specific Interrupt Numbers  ======================================== */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M0 / Cortex-M0+ device */
+  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M3 / Cortex-M4 / Cortex-M7 device */
+  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
+  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
+  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
+  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
+                                                          and No Match                                                         */
+  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                          related Fault                                                        */
+  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
+  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
+  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
+  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
+  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
+
+/* ===========================================  <Device> Specific Interrupt Numbers  ========================================= */
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn */
+  <DeviceInterrupt>_IRQn    = 0,                /*!< Device Interrupt                                                          */
+} IRQn_Type;
+
+
+
+/* =========================================================================================================================== */
+/* ================                           Processor and Core Peripheral Section                           ================ */
+/* =========================================================================================================================== */
+
+/* ===========================  Configuration of the Arm Cortex-M4 Processor and Core Peripherals  =========================== */
+/* ToDo: set the defines according your Device */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a Cortex-M0 device
+         __CM3_REV if your device is a Cortex-M3 device
+         __CM4_REV if your device is a Cortex-M4 device
+         __CM7_REV if your device is a Cortex-M7 device */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1 */
+/* ToDo: define the correct core features for the <Device> */
+#define __MPU_PRESENT             1         /*!< Set to 1 if MPU is present */
+#define __VTOR_PRESENT            1         /*!< Set to 1 if VTOR is present */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             0         /*!< Set to 1 if FPU is present */
+#define __FPU_DP                  0         /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
+#define __ICACHE_PRESENT          0         /*!< Set to 1 if I-Cache is present */
+#define __DCACHE_PRESENT          0         /*!< Set to 1 if D-Cache is present */
+#define __DTCM_PRESENT            0         /*!< Set to 1 if DTCM is present */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device
+         core_cm7.h if your device is a CORTEX-M4 device */
+#include <core_cm#.h>                           /*!< Arm Cortex-M# processor and core peripherals */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name */
+#include "system_<Device>.h"                    /*!< <Device> System */
+
+
+/* ========================================  Start of section using anonymous unions  ======================================== */
+#if   defined (__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined (__ICCARM__)
+  #pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wc11-extensions"
+  #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning 586
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                            Device Specific Peripheral Section                             ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+  * @{
+  */
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer */
+
+/* =========================================================================================================================== */
+/* ================                                            TMR                                            ================ */
+/* =========================================================================================================================== */
+
+
+/**
+  * @brief Timer (TMR)
+  */
+
+typedef struct
+{                                               /*!< (@ 0x40000000) TIM Structure                                              */
+  __IOM uint32_t   TimerLoad;                   /*!< (@ 0x00000004) Timer Load                                                 */
+  __IM  uint32_t   TimerValue;                  /*!< (@ 0x00000008) Timer Counter Current Value                                */
+  __IOM uint32_t   TimerControl;                /*!< (@ 0x0000000C) Timer Control                                              */
+  __OM  uint32_t   TimerIntClr;                 /*!< (@ 0x00000010) Timer Interrupt Clear                                      */
+  __IM  uint32_t   TimerRIS;                    /*!< (@ 0x00000014) Timer Raw Interrupt Status                                 */
+  __IM  uint32_t   TimerMIS;                    /*!< (@ 0x00000018) Timer Masked Interrupt Status                              */
+  __IM  uint32_t   RESERVED[1];
+  __IOM uint32_t   TimerBGLoad;                 /*!< (@ 0x00000020) Background Load Register                                   */
+} <DeviceAbbreviation>_TMR_TypeDef;
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/* =========================================  End of section using anonymous unions  ========================================= */
+#if   defined (__CC_ARM)
+  #pragma pop
+#elif defined (__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+  #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+  #pragma warning restore
+#elif defined (__CSMC__)
+  /* anonymous unions are enabled by default */
+#else
+  #warning Not supported compiler type
+#endif
+
+
+/* =========================================================================================================================== */
+/* ================                          Device Specific Peripheral Address Map                           ================ */
+/* =========================================================================================================================== */
+
+
+/* ToDo: add here your device peripherals base addresses
+         following is an example for timer */
+/** @addtogroup Device_Peripheral_peripheralAddr
+  * @{
+  */
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================                                  Peripheral declaration                                   ================ */
+/* =========================================================================================================================== */
+
+
+/* ToDo: add here your device peripherals pointer definitions
+         following is an example for timer */
+/** @addtogroup Device_Peripheral_declaration
+  * @{
+  */
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+
+
+/** @} */ /* End of group <Device> */
+
+/** @} */ /* End of group <Vendor> */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
+
+ + + + -- cgit