From 76177aa280494bb36d7a0bcbda1078d4db717020 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Mon, 9 Dec 2019 11:25:19 +0100 Subject: Official ARM version: v4.5 --- Documentation/DSP/html/group___conv.html | 766 +++++++++++++++++++++++++++++++ 1 file changed, 766 insertions(+) create mode 100644 Documentation/DSP/html/group___conv.html (limited to 'Documentation/DSP/html/group___conv.html') diff --git a/Documentation/DSP/html/group___conv.html b/Documentation/DSP/html/group___conv.html new file mode 100644 index 0000000..c623463 --- /dev/null +++ b/Documentation/DSP/html/group___conv.html @@ -0,0 +1,766 @@ + + + + + +Convolution +CMSIS-DSP: Convolution + + + + + + + + + + + + + + + +
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CMSIS-DSP +  Version 1.4.7 +
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CMSIS DSP Software Library
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+Functions
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Convolution
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Filtering Functions
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+Functions

void arm_conv_f32 (float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst)
 Convolution of floating-point sequences.
 
void arm_conv_fast_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
 
void arm_conv_fast_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
 
void arm_conv_fast_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
 
void arm_conv_opt_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q15 sequences.
 
void arm_conv_opt_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, q15_t *pScratch1, q15_t *pScratch2)
 Convolution of Q7 sequences.
 
void arm_conv_q15 (q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst)
 Convolution of Q15 sequences.
 
void arm_conv_q31 (q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst)
 Convolution of Q31 sequences.
 
void arm_conv_q7 (q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst)
 Convolution of Q7 sequences.
 
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Description

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Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. Convolution is similar to correlation and is frequently used in filtering and data analysis. The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.

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Algorithm
Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. Then the convolution
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+                  c[n] = a[n] * b[n]    
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is defined as
+ConvolutionEquation.gif +
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Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.
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Conceptually, when two signals a[n] and b[n] are convolved, the signal b[n] slides over a[n]. For each offset n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
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Note that convolution is a commutative operation:
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+                  a[n] * b[n] = b[n] * a[n].    
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This means that switching the A and B arguments to the convolution functions has no effect.
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Fixed-Point Behavior

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Convolution requires summing up a large number of intermediate products. As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. Refer to the function specific documentation below for further details of the particular algorithm used.
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Fast Versions

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Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires the input signals should be scaled down to avoid intermediate overflows.
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Opt Versions

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Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
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Function Documentation

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void arm_conv_f32 (float32_t * pSrcA,
uint32_t srcALen,
float32_t * pSrcB,
uint32_t srcBLen,
float32_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
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Returns
none.
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References srcALen, and srcBLen.

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void arm_conv_fast_opt_q15 (q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen).
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Returns
none.
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Restrictions
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
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Scaling and Overflow Behavior:

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This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
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See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
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References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.

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void arm_conv_fast_q15 (q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
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Returns
none.
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Scaling and Overflow Behavior:

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This fast version uses a 32-bit accumulator with 2.30 format. The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
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See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
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References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.

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void arm_conv_fast_q31 (q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
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Returns
none.
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Scaling and Overflow Behavior:

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This function is optimized for speed at the expense of fixed-point precision and overflow protection. The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 format. Finally, the accumulator is saturated and converted to a 1.31 result.
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The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. In order to avoid overflows completely the input signals must be scaled down. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally.
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See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
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References srcALen, and srcBLen.

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void arm_conv_opt_q15 (q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
[in]*pScratch1points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
[in]*pScratch2points to scratch buffer of size min(srcALen, srcBLen).
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Returns
none.
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Restrictions
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
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Scaling and Overflow Behavior:

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The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
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Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
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References __SIMD32, _SIMD32_OFFSET, arm_copy_q15(), arm_fill_q15(), srcALen, and srcBLen.

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void arm_conv_opt_q7 (q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst,
q15_t * pScratch1,
q15_t * pScratch2 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
[in]*pScratch1points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
[in]*pScratch2points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
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Returns
none.
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Restrictions
If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
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Scaling and Overflow Behavior:

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The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
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References __PACKq7, __SIMD32, _SIMD32_OFFSET, arm_fill_q15(), srcALen, and srcBLen.

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void arm_conv_q15 (q15_t * pSrcA,
uint32_t srcALen,
q15_t * pSrcB,
uint32_t srcBLen,
q15_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
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Returns
none.
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Scaling and Overflow Behavior:

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The function is implemented using a 64-bit internal accumulator. Both inputs are in 1.15 format and multiplications yield a 2.30 result. The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
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Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
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Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
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References __SIMD32, _SIMD32_OFFSET, srcALen, and srcBLen.

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void arm_conv_q31 (q31_t * pSrcA,
uint32_t srcALen,
q31_t * pSrcB,
uint32_t srcBLen,
q31_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
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Returns
none.
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Scaling and Overflow Behavior:

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The function is implemented using an internal 64-bit accumulator. The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. There is no saturation on intermediate additions. Thus, if the accumulator overflows it wraps around and distorts the result. The input signals should be scaled down to avoid intermediate overflows. Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, as maximum of min(srcALen, srcBLen) number of additions are carried internally. The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
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See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
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References srcALen, and srcBLen.

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void arm_conv_q7 (q7_t * pSrcA,
uint32_t srcALen,
q7_t * pSrcB,
uint32_t srcBLen,
q7_t * pDst 
)
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Parameters
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[in]*pSrcApoints to the first input sequence.
[in]srcALenlength of the first input sequence.
[in]*pSrcBpoints to the second input sequence.
[in]srcBLenlength of the second input sequence.
[out]*pDstpoints to the location where the output result is written. Length srcALen+srcBLen-1.
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Returns
none.
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Scaling and Overflow Behavior:

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The function is implemented using a 32-bit internal accumulator. Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
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Refer the function arm_conv_opt_q7() for a faster implementation of this function.
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References srcALen, and srcBLen.

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