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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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MISRA-C:2004 Compliance Exceptions
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CMSIS-CORE uses the common coding rules for CMSIS components that are documented under Introduction.

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CMSIS-CORE violates the following MISRA-C:2004 rules:

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  • Required Rule 8.5, object/function definition in header file.
    + Violated since function definitions in header files are used for function inlining'.
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  • Advisory Rule 12.4, Side effects on right hand side of logical operator.
    + Violated because volatile is used for core register definitions.
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  • Advisory Rule 14.7, Return statement before end of function.
    + Violated to simplify code logic.
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  • Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Violated since unions are used for effective representation of core registers.
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  • Advisory Rule 19.4, Disallowed definition for macro.
    + Violated since macros are used for assembler keywords.
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  • Advisory Rule 19.7, Function-like macro defined.
    + Violated since function-like macros are used to generate more efficient code.
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  • Advisory Rule 19.16, all preprocessing directives must be valid.
    + Violated to set default settings for macros.
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<device>.h files generated by SVDConv.exe violate the following MISRA-C:2004 rules:

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  • Advisory Rule 20.2, Re-use of C90 identifier pattern.
    + Violated since CMSIS macros begin with '__'. Since CMSIS is developed and verified with various compilers this approach is acceptable and avoids conflicts with user symbols.
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  • Advisory Rule 19.1, Declaration before #include.
    + Violated since Interrupt Number Definition Type (IRQn_Type) must be defined before including the core header file.
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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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Register Mapping
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The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.

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CMSIS Register Name Cortex-M3, Cortex-M4, and Cortex-M7 Cortex-M0 and Cortex-M0+ Register Name
Nested Vectored Interrupt Controller (NVIC) Register Access
NVIC->ISER[] NVIC_ISER0..7 ISER Interrupt Set-Enable Registers
NVIC->ICER[] NVIC_ICER0..7 ICER Interrupt Clear-Enable Registers
NVIC->ISPR[] NVIC_ISPR0..7 ISPR Interrupt Set-Pending Registers
NVIC->ICPR[] NVIC_ICPR0..7 ICPR Interrupt Clear-Pending Registers
NVIC->IABR[] NVIC_IABR0..7 - Interrupt Active Bit Register
NVIC->IP[] NVIC_IPR0..59 IPR0..7 Interrupt Priority Register
NVIC->STIR STIR - Software Triggered Interrupt Register
System Control Block (SCB) Register Access
SCB->CPUID CPUID CPUID CPUID Base Register
SCB->ICSR ICSR ICSR Interrupt Control and State Register
SCB->VTOR VTOR - Vector Table Offset Register
SCB->AIRCR AIRCR AIRCR Application Interrupt and Reset Control Register
SCB->SCR SCR SCR System Control Register
SCB->CCR CCR CCR Configuration and Control Register
SCB->SHP[] SHPR1..3 SHPR2..3 System Handler Priority Registers
SCB->SHCSR SHCSR SHCSR System Handler Control and State Register
SCB->CFSR CFSR - Configurable Fault Status Registers
SCB->HFSR HFSR - HardFault Status Register
SCB->DFSR DFSR - Debug Fault Status Register
SCB->MMFAR MMFAR - MemManage Fault Address Register
SCB->BFAR BFAR - BusFault Address Register
SCB->AFSR AFSR - Auxiliary Fault Status Register
SCB->PFR[] ID_PFR0..1 - Processor Feature Registers
SCB->DFR ID_DFR0 - Debug Feature Register
SCB->ADR ID_AFR0 - Auxiliary Feature Register
SCB->MMFR[] ID_MMFR0..3 - Memory Model Feature Registers
SCB->ISAR[] ID_ISAR0..4 - Instruction Set Attributes Registers
SCB->CPACR CPACR - Coprocessor Access Control Register
System Control and ID Registers not in the SCB (SCnSCB) Register Access
SCnSCB->ICTR ICTR - Interrupt Controller Type Register
SCnSCB->ACTLR ACTLR - Auxiliary Control Register
System Timer (SysTick) Control and Status Register Access
SysTick->CTRL STCSR SYST_CSR SysTick Control and Status Register
SysTick->LOAD STRVR SYST_RVR SysTick Reload Value Register
SysTick->VAL STCVR SYST_CVR SysTick Current Value Register
SysTick->CALIB STCR SYST_CALIB SysTick Calibaration Value Register
Data Watchpoint and Trace (DWT) Register Access
DWT->CTRL DWT_CTRL - Control Register
DWT->CYCCNT DWT_CYCCNT - Cycle Count Register
DWT->CPICNT DWT_CPICNT - CPI Count Register
DWT->EXCCNT DWT_EXCCNT - Exception Overhead Count Register
DWT->SLEEPCNT DWT_SLEEPCNT - Sleep Count Register
DWT->LSUCNT DWT_LSUCNT - LSU Count Register
DWT->FOLDCNT DWT_FOLDCNT - Folded-instruction Count Register
DWT->PCSR DWT_PCSR - Program Counter Sample Register
DWT->COMP0..3 DWT_COMP0..3 - Comparator Register 0..3
DWT->MASK0..3 DWT_MASK0..3 - Mask Register 0..3
DWT->FUNCTION0..3 DWT_FUNCTION0..3 - Function Register 0..3
Instrumentation Trace Macrocell (ITM) Register Access
ITM->PORT[] ITM_STIM0..31 - Stimulus Port Registers
ITM->TER ITM_TER - Trace Enable Register
ITM->TPR ITM_TPR - ITM Trace Privilege Register
ITM->TCR ITM_TCR - Trace Control Register
Trace Port Interface (TPIU) Register Access
TPI->SSPSR TPIU_SSPR - Supported Parallel Port Size Register
TPI->CSPSR TPIU_CSPSR - Current Parallel Port Size Register
TPI->ACPR TPIU_ACPR - Asynchronous Clock Prescaler Register
TPI->SPPR TPIU_SPPR - Selected Pin Protocol Register
TPI->FFSR TPIU_FFSR - Formatter and Flush Status Register
TPI->FFCR TPIU_FFCR - Formatter and Flush Control Register
TPI->FSCR TPIU_FSCR - Formatter Synchronization Counter Register
TPI->TRIGGER TRIGGER - TRIGGER
TPI->FIFO0 FIFO data 0 - Integration ETM Data
TPI->ITATBCTR2 ITATBCTR2 - ITATBCTR2
TPI->ITATBCTR0 ITATBCTR0 - ITATBCTR0
TPI->FIFO1 FIFO data 1 - Integration ITM Data
TPI->ITCTRL TPIU_ITCTRL - Integration Mode Control
TPI->CLAIMSET CLAIMSET - Claim tag set
TPI->CLAIMCLR CLAIMCLR - Claim tag clear
TPI->DEVID TPIU_DEVID - TPIU_DEVID
TPI->DEVTYPE TPIU_DEVTYPE - TPIU_DEVTYPE
Memory Protection Unit (MPU) Register Access
MPU->TYPE MPU_TYPE - MPU Type Register
MPU->CTRL MPU_CTRL - MPU Control Register
MPU->RNR MPU_RNR - MPU Region Number Register
MPU->RBAR MPU_RBAR - MPU Region Base Address Register
MPU->RASR MPU_RASR - MPU Region Attribute and Size Register
MPU->RBAR_A1..3 MPU_RBAR_A1..3 - MPU alias Register
MPU->RSAR_A1..3 MPU_RSAR_A1..3 - MPU alias Register
Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]
FPU->FPCCR FPCCR - FP Context Control Register
FPU->FPCAR FPCAR - FP Context Address Register
FPU->FPDSCR FPDSCR - FP Default Status Control Register
FPU->MVFR0..1 MVFR0..1 - Media and VFP Feature Registers
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Template Files
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ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of Tested and Verified Toolchains for compliance. These template files include the following:

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  • Register names of the Core Peripherals and names of the Core Exception Vectors.
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  • Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4 and Cortex-M7)
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  • Generic startup code and system configuration code.
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The detailed file structure of the CMSIS-CORE is shown in the following picture.

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+CMSIS_CORE_Files.png +
+CMSIS-CORE File Structure
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+Template Files

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The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:

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  • Device Peripheral Access Layer that provides definitions for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) that provides additional helper functions to access device-specific peripherals.
    • +
  • Interrupt vectors in the startup file that are device specific.
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Template File Description
.\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s Startup file template for ARM C/C++ Compiler.
.\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s Startup file template for GNU GCC ARM Embedded Compiler.
.\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s Startup file template for IAR C/C++ Compiler.
.\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).
.\Device\_Template_Vendor\Vendor\Device\Include\Device.h Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file.
.\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h Generic system device configuration include file.
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In addition ARM provides the following core header files that do not need any modifications.

+ + + + + + + + + + + +
Core Header Files Description
core_<cpu>.h Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:
    +
  • core_cm0.h: for the Cortex-M0 processor
    • +
  • core_cm0plus.h: for the Cortex-M0+ processor
    • +
  • core_cm3.h: for the Cortex-M3 processor
    • +
  • core_cm4.h: for the Cortex-M4 processor
    • +
  • core_cm7.h: for the Cortex-M7 processor
    • +
  • core_sc000.h: for the SecurCore SC000 processor
    • +
  • core_sc300.h: for the SecurCore SC300 processor
    • +
+
core_cmInstr.h Defines intrinsic functions to access special Cortex-M instructions.
core_cmFunc.h Defines functions to access the Cortex-M core peripherals.
core_cm4_simd.h Defines intrinsic functions to access the SIMD instructions for Cortex-M4 and Cortex-M7.
+

+Adaption of Template Files to Devices

+

Copy the complete folder including files and replace:

+
    +
  • folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
    • +
  • folder name 'Device' with the specific device name e.g.: LPC17xx.
    • +
  • in the filenames 'Device' with the specific device name e.g.: LPC17xx.
    • +
+

Each template file contains comments that start with ToDo: that describe a required modification. The template files contain placeholders:

+ + + + + + + + + + + +
Placeholder Replaced with
<Device> the specific device name or device family name; i.e. LPC17xx.
<DeviceInterrupt> a specific interrupt name of the device; i.e. TIM1 for Timer 1.
<DeviceAbbreviation> short name or abbreviation of the device family; i.e. LPC.
Cortex-M# the specific Cortex-M processor name; i.e. Cortex-M3.
+

The adaption of the template files is described in detail on the following pages:

+ +
+
+ + + + diff --git a/Documentation/Core/html/_templates_pg.js b/Documentation/Core/html/_templates_pg.js new file mode 100644 index 0000000..972e1a1 --- /dev/null +++ b/Documentation/Core/html/_templates_pg.js @@ -0,0 +1,19 @@ +var _templates_pg = +[ + [ "Template Files", "_templates_pg.html#template_files_sec", null ], + [ "Adaption of Template Files to Devices", "_templates_pg.html#adapt_template_files_sec", null ], + [ "Startup File startup_.s", "startup_s_pg.html", [ + [ "startup_Device.s Template File", "startup_s_pg.html#startup_s_sec", null ] + ] ], + [ "System Configuration Files system_.c and system_.h", "system_c_pg.html", [ + [ "system_Device.c Template File", "system_c_pg.html#system_Device_sec", null ], + [ "system_Device.h Template File", "system_c_pg.html#system_Device_h_sec", null ] + ] ], + [ "Device Header File ", "device_h_pg.html", [ + [ "Interrupt Number Definition", "device_h_pg.html#interrupt_number_sec", null ], + [ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#core_config_sect", null ], + [ "CMSIS Version and Processor Information", "device_h_pg.html#core_version_sect", null ], + [ "Device Peripheral Access Layer", "device_h_pg.html#device_access", null ], + [ "Device.h Template File", "device_h_pg.html#device_h_sec", null ] + ] ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/_using__a_r_m_pg.html b/Documentation/Core/html/_using__a_r_m_pg.html new file mode 100644 index 0000000..b8b2a16 --- /dev/null +++ b/Documentation/Core/html/_using__a_r_m_pg.html @@ -0,0 +1,169 @@ + + + + + +Using CMSIS with generic ARM Processors +CMSIS-CORE: Using CMSIS with generic ARM Processors + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using CMSIS with generic ARM Processors
+
+
+

ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.

+ + + + + + + + + + + + + + + + + +
Folder Processor Description
".\Device\ARM\ARMCM0" Cortex-M0 Contains Include and Source template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the Device Header File <device.h> is <ARMCM0.h>.
".\Device\ARM\ARMCM0plus" Cortex-M0+ Contains Include and Source template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the Device Header File <device.h> is <ARMCM0plus.h>.
".\Device\ARM\ARMCM3" Cortex-M3 Contains Include and Source template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the Device Header File <device.h> is <ARMCM3.h>.
".\Device\ARM\ARMCM4" Cortex-M4 Contains Include and Source template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the Device Header File <device.h> is <ARMCM4.h>.
".\Device\ARM\ARMCM7" Cortex-M7 Contains Include and Source template files configured for the Cortex-M7 processor. The device name is ARMCM7 and the name of the Device Header File <device.h> is <ARMCM7.h>.
".\Device\ARM\ARMSC000" SecurCore SC000 Contains Include and Source template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the Device Header File <device.h> is <ARMSC000.h>.
".\Device\ARM\ARMSC300" SecurCore SC300 Contains Include and Source template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the Device Header File <device.h> is <ARMSC300.h>.
+

+Create generic Libraries with CMSIS

+

The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The CMSIS-DSP Libraries are an example for such a generic library.

+

To build a generic Library set the define CMSIS_GENERIC and include the relevant core_<cpu>.h CMSIS CPU & Core Access header file for the processor. The define CMSIS_GENERIC disables device-dependent features such as the SysTick timer and the Interrupt System. Refer to Configuration of the Processor and Core Peripherals for a list of the available core_<cpu>.h header files.

+

Example:

+

The following code section shows the usage of the core_<cpu>.h header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To select the processor, the source code uses the define CORTEX_M7, CORTEX_M4, CORTEX_M3, CORTEX_M0, or CORTEX_M0PLUS. By using this header file, the source code can access the functions for Core Register Access, Intrinsic Functions for CPU Instructions, Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7], and Debug Access.

+
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+
#if defined (CORTEX_M7)
+
#include "core_cm7.h"
+
#if defined (CORTEX_M4)
+
#include "core_cm4.h"
+
#elif defined (CORTEX_M3)
+
#include "core_cm3.h"
+
#elif defined (CORTEX_M0)
+
#include "core_cm0.h"
+
#elif defined (CORTEX_M0PLUS)
+
#include "core_cm0plus.h"
+
#else
+
#error "Processor not specified or unsupported."
+
#endif
+
+
+ + + + diff --git a/Documentation/Core/html/_using__c_m_s_i_s.html b/Documentation/Core/html/_using__c_m_s_i_s.html new file mode 100644 index 0000000..6c17a2e --- /dev/null +++ b/Documentation/Core/html/_using__c_m_s_i_s.html @@ -0,0 +1,177 @@ + + + + + +Basic CMSIS Example +CMSIS-CORE: Basic CMSIS Example + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Basic CMSIS Example
+
+
+

A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.

+
#include <stm32f10x.h> // File name depends on device used
+
+
uint32_t volatile msTicks; // Counter for millisecond Interval
+
+
void SysTick_Handler (void) { // SysTick Interrupt Handler
+
msTicks++; // Increment Counter
+
}
+
+
void WaitForTick (void) {
+
uint32_t curTicks;
+
+
curTicks = msTicks; // Save Current SysTick Value
+
while (msTicks == curTicks) { // Wait for next SysTick Interrupt
+
__WFE (); // Power-Down until next Event/Interrupt
+
}
+
}
+
+
void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
+
; // Add user code here
+
}
+
+
void timer1_init(int frequency) { // Set up Timer (device specific)
+
NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
+
NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
+
}
+
+
+
void Device_Initialization (void) { // Configure & Initialize MCU
+
if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
+
: // Handle Error
+
}
+
timer1_init (); // setup device-specific timer
+
}
+
+
+
// The processor clock is initialized by CMSIS startup + system file
+
void main (void) { // user application starts here
+
Device_Initialization (); // Configure & Initialize MCU
+
while (1) { // Endless Loop (the Super-Loop)
+
__disable_irq (); // Disable all interrupts
+
Get_InputValues (); // Read Values
+
__enable_irq (); // Enable all interrupts
+
Calculation_Response (); // Calculate Results
+
Output_Response (); // Output Results
+
WaitForTick (); // Synchronize to SysTick Timer
+
}
+
}
+
+
+ + + + diff --git a/Documentation/Core/html/_using__v_t_o_r_pg.html b/Documentation/Core/html/_using__v_t_o_r_pg.html new file mode 100644 index 0000000..ec02a35 --- /dev/null +++ b/Documentation/Core/html/_using__v_t_o_r_pg.html @@ -0,0 +1,181 @@ + + + + + +Using Interrupt Vector Remap +CMSIS-CORE: Using Interrupt Vector Remap + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using Interrupt Vector Remap
+
+
+

Most Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows a typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.

+
#include "ARMCM3.h" // Device header
+
+
/* externals from startup_ARMCM3.s */
+
extern uint32_t __Vectors[]; /* vector table ROM */
+
+
#define VECTORTABLE_SIZE (256) /* size Cortex-M3 vector table */
+
#define VECTORTABLE_ALIGNMENT (0x100ul) /* 16 Cortex + 32 ARMCM3 = 48 words */
+
/* next power of 2 = 256 */
+
+
/* new vector table in RAM */
+
uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));
+
+
/*----------------------------------------------------------------------------
+
SysTick_Handler
+
*----------------------------------------------------------------------------*/
+
volatile uint32_t msTicks = 0; /* counts 1ms timeTicks */
+
void SysTick_Handler(void) {
+
msTicks++; /* increment counter */
+
}
+
+
/*----------------------------------------------------------------------------
+
SysTick_Handler (RAM)
+
*----------------------------------------------------------------------------*/
+
volatile uint32_t msTicks_RAM = 0; /* counts 1ms timeTicks */
+
void SysTick_Handler_RAM(void) {
+
msTicks_RAM++; /* increment counter */
+
}
+
+
/*----------------------------------------------------------------------------
+
MAIN function
+
*----------------------------------------------------------------------------*/
+
int main (void) {
+
uint32_t i;
+
+
for (i = 0; i < VECTORTABLE_SIZE; i++) {
+
vectorTable_RAM[i] = __Vectors[i]; /* copy vector table to RAM */
+
}
+
/* replace SysTick Handler */
+
vectorTable_RAM[SysTick_IRQn + 16] = (uint32_t)SysTick_Handler_RAM;
+
+
/* relocate vector table */
+
__disable_irq();
+
SCB->VTOR = (uint32_t)&vectorTable_RAM;
+
__DSB();
+
__enable_irq();
+
+
SystemCoreClockUpdate(); /* Get Core Clock Frequency */
+
SysTick_Config(SystemCoreClock / 1000ul); /* Setup SysTick Timer for 1 msec */
+
+
while(1);
+
}
+
+
+ + + + diff --git a/Documentation/Core/html/_using_pg.html b/Documentation/Core/html/_using_pg.html new file mode 100644 index 0000000..591e7bc --- /dev/null +++ b/Documentation/Core/html/_using_pg.html @@ -0,0 +1,172 @@ + + + + + +Using CMSIS in Embedded Applications +CMSIS-CORE: Using CMSIS in Embedded Applications + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Using CMSIS in Embedded Applications
+
+
+

To use the CMSIS-CORE the following files are added to the embedded application:

+ +
Note
The files Startup File startup_<device>.s and System Configuration Files system_<device>.c and system_<device>.h may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The Device Header File <device.h> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.
+

The Startup File startup_<device>.s is executed after reset and calls SystemInit. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the main function in the user code. In addition the Startup File startup_<device>.s contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.

+

The System Configuration Files system_<device>.c and system_<device>.h performs the setup for the processor clock. The variable SystemCoreClock indicates the CPU clock speed. System and Clock Configuration describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.

+

The Device Header File <device.h> is the central include file that the application programmer is using in the C source code. It provides the following features:

+ +
+CMSIS_CORE_Files_user.png +
+CMSIS-CORE User Files
+

The CMSIS-CORE are device specific. In addition, the Startup File startup_<device>.s is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.

+

For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:

+ + + + + + + + + + + +
File Description
".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" Startup File startup_<device>.s for the STM32F10x Connectivity Line device variants.
".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" System Configuration Files system_<device>.c and system_<device>.h for the STM32F10x device families.
".\ARM\INC\ST\STM32F10x\stm32f10x.h" Device Header File <device.h> for the STM32F10x device families.
".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" system_Device.h Template File for the STM32F10x device families.
+
Note
The silicon vendors create these device-specific CMSIS-CORE files based on Template Files provide by ARM.
+

Thereafter, the functions described under Reference can be used in the application.

+

Examples

+ +
+
+ + + + diff --git a/Documentation/Core/html/_using_pg.js b/Documentation/Core/html/_using_pg.js new file mode 100644 index 0000000..69ebae1 --- /dev/null +++ b/Documentation/Core/html/_using_pg.js @@ -0,0 +1,8 @@ +var _using_pg = +[ + [ "Basic CMSIS Example", "_using__c_m_s_i_s.html", null ], + [ "Using Interrupt Vector Remap", "_using__v_t_o_r_pg.html", null ], + [ "Using CMSIS with generic ARM Processors", "_using__a_r_m_pg.html", [ + [ "Create generic Libraries with CMSIS", "_using__a_r_m_pg.html#Using_ARM_Lib_sec", null ] + ] ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/annotated.html b/Documentation/Core/html/annotated.html new file mode 100644 index 0000000..9459e29 --- /dev/null +++ b/Documentation/Core/html/annotated.html @@ -0,0 +1,152 @@ + + + + + +Data Structures +CMSIS-CORE: Data Structures + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structures
+
+
+
Here are the data structures with brief descriptions:
+ + + + + + + + + + + + + + + +
oCAPSR_TypeUnion type to access the Application Program Status Register (APSR)
oCCONTROL_TypeUnion type to access the Control Registers (CONTROL)
oCCoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug)
oCDWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT)
oCFPU_TypeStructure type to access the Floating Point Unit (FPU)
oCIPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR)
oCITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM)
oCMPU_TypeStructure type to access the Memory Protection Unit (MPU)
oCNVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC)
oCSCB_TypeStructure type to access the System Control Block (SCB)
oCSCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB
oCSysTick_TypeStructure type to access the System Timer (SysTick)
oCTPI_TypeStructure type to access the Trace Port Interface Register (TPI)
\CxPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR)
+
+
+
+ + + + diff --git a/Documentation/Core/html/annotated.js b/Documentation/Core/html/annotated.js new file mode 100644 index 0000000..fa4ad87 --- /dev/null +++ b/Documentation/Core/html/annotated.js @@ -0,0 +1,17 @@ +var annotated = +[ + [ "APSR_Type", "union_a_p_s_r___type.html", "union_a_p_s_r___type" ], + [ "CONTROL_Type", "union_c_o_n_t_r_o_l___type.html", "union_c_o_n_t_r_o_l___type" ], + [ "CoreDebug_Type", "struct_core_debug___type.html", "struct_core_debug___type" ], + [ "DWT_Type", "struct_d_w_t___type.html", "struct_d_w_t___type" ], + [ "FPU_Type", "struct_f_p_u___type.html", "struct_f_p_u___type" ], + [ "IPSR_Type", "union_i_p_s_r___type.html", "union_i_p_s_r___type" ], + [ "ITM_Type", "struct_i_t_m___type.html", "struct_i_t_m___type" ], + [ "MPU_Type", "struct_m_p_u___type.html", "struct_m_p_u___type" ], + [ "NVIC_Type", "struct_n_v_i_c___type.html", "struct_n_v_i_c___type" ], + [ "SCB_Type", "struct_s_c_b___type.html", "struct_s_c_b___type" ], + [ "SCnSCB_Type", "struct_s_cn_s_c_b___type.html", "struct_s_cn_s_c_b___type" ], + [ "SysTick_Type", "struct_sys_tick___type.html", "struct_sys_tick___type" ], + [ "TPI_Type", "struct_t_p_i___type.html", "struct_t_p_i___type" ], + [ "xPSR_Type", "unionx_p_s_r___type.html", "unionx_p_s_r___type" ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/bc_s.png b/Documentation/Core/html/bc_s.png new file mode 100644 index 0000000..66f8e9a Binary files /dev/null and b/Documentation/Core/html/bc_s.png differ diff --git a/Documentation/Core/html/bdwn.png b/Documentation/Core/html/bdwn.png new file mode 100644 index 0000000..d400769 Binary files /dev/null and b/Documentation/Core/html/bdwn.png differ diff --git a/Documentation/Core/html/check.png b/Documentation/Core/html/check.png new file mode 100644 index 0000000..094e59c Binary files /dev/null and b/Documentation/Core/html/check.png differ diff --git a/Documentation/Core/html/classes.html b/Documentation/Core/html/classes.html new file mode 100644 index 0000000..2773f85 --- /dev/null +++ b/Documentation/Core/html/classes.html @@ -0,0 +1,158 @@ + + + + + +Data Structure Index +CMSIS-CORE: Data Structure Index + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Data Structure Index
+
+
+
A | C | D | F | I | M | N | S | T | X
+ + + + + + + + + + + +
  A  
+
  D  
+		ITM_Type   
  S  
+
  X  
+
  M  
+
APSR_Type   DWT_Type   SCB_Type   xPSR_Type   
  C  
+
  F  
+		MPU_Type   SCnSCB_Type   
  N  
+		SysTick_Type   
CONTROL_Type   FPU_Type   
  T  
+
CoreDebug_Type   
  I  
+		NVIC_Type   
TPI_Type   
IPSR_Type   
+
A | C | D | F | I | M | N | S | T | X
+
+
+ + + + diff --git a/Documentation/Core/html/closed.png b/Documentation/Core/html/closed.png new file mode 100644 index 0000000..ccbcf62 Binary files /dev/null and b/Documentation/Core/html/closed.png differ diff --git a/Documentation/Core/html/cmsis.css b/Documentation/Core/html/cmsis.css new file mode 100644 index 0000000..293d0d0 --- /dev/null +++ b/Documentation/Core/html/cmsis.css @@ -0,0 +1,1269 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif; + font-size: 13px; + line-height: 1.3; +} + +/* CMSIS styles */ + +.style1 { + text-align: center; +} +.style2 { + color: #0000FF; + font-weight: normal; +} +.style3 { + text-align: left; +} +.style4 { + color: #008000; +} +.style5 { + color: #0000FF; +} +.style6 { + color: #000000; + font-style:italic; +} +.mand { + color: #0000FF; +} +.opt { + color: #008000; +} +.cond { + color: #990000; +} + +.choice +{ + background-color:#F7F9D0; +} +.seq +{ + background-color:#C9DECB; +} +.group1 +{ + background-color:#F8F1F1; +} +.group2 +{ + background-color:#DCEDEA; +} + + +ul ul { + list-style-type: disc; +} + +ul ul ul { + list-style-type: disc; +} + +ul.hierarchy { + color: green; +} + +em { + color: #000000; + font-style:italic; +} + + + +/* CMSIS Tables */ +table.cmtab1 { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A3B4D7; + text-align: justify; + width:70%; +} + +th.cmtab1 { + background: #EBEFF6; + font-weight: bold; + height: 28px; +} + +td.cmtab1 { + padding:1px; + text-align: left; +} + +table.cmtable { + border-collapse:collapse; + text-align: justify; +} + +table.cmtable td, table.cmtable th { + border: 1px solid #2D4068; + padding: 3px 7px 2px; +} + +table.cmtable th { + background-color: #EBEFF6; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; +} + +td.MonoTxt { + font-family:"Arial monospaced for SAP"; +} + +td.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +span.XML-Token +{ + azimuth: 180; + font-style:italic; + color:Maroon; + z-index:20; + +} + +span.h2 +{ + font-size: 120%; + font-weight: bold; +} + + + +/* @group Heading Levels */ + +h1 { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2 { + font-size: 120%; +} + +h3 { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; +} + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #EBEFF6; + color: #000000; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + margin-left: 5px; + font-size: 8pt; + padding-left: 5px; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 7px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/Documentation/Core/html/core_revision_history.html b/Documentation/Core/html/core_revision_history.html new file mode 100644 index 0000000..cf554d5 --- /dev/null +++ b/Documentation/Core/html/core_revision_history.html @@ -0,0 +1,206 @@ + + + + + +Revision History of CMSIS-CORE +CMSIS-CORE: Revision History of CMSIS-CORE + + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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Revision History of CMSIS-CORE
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+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Version Description
V4.30 Corrected: DoxyGen function parameter comments.
+ Corrected: IAR toolchain: removed for NVIC_SystemReset the attribute(noreturn).
+ Corrected: GCC toolchain: supressed irrelevant compiler warnings.
+ Added: Support files for ARM Compiler v6 (cmsis_armcc_v6.h).
V4.20 Corrected: MISRA-C:2004 violations.
+ Corrected: predefined macro for TI CCS Compiler.
+ Corrected: function __SHADD16 in arm_math.h.
+ Updated: cache functions for Cortex-M7.
+ Added: macros _VAL2FLD, _FLD2VAL to core_*.h.
+ Updated: functions __QASX, __QSAX, __SHASX, __SHSAX.
+ Corrected: potential bug in function __SHADD16.
V4.10 Corrected: MISRA-C:2004 violations.
+ Corrected: intrinsic functions __DSB, __DMB, __ISB.
+ Corrected: register definitions for ITCMCR register.
+ Corrected: register definitions for CONTROL_Type register.
+ Added: functions SCB_GetFPUType, SCB_InvalidateDCache_by_Addr to core_cm7.h.
+ Added: register definitions for APSR_Type, IPSR_Type, xPSR_Type register.
+ Added: __set_BASEPRI_MAX function to core_cmFunc.h.
+ Added: intrinsic functions __RBIT, __CLZ for Cortex-M0/CortexM0+.
+
V4.00 Added: Cortex-M7 support.
+ Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
+
V3.40 Corrected: C++ include guard settings.
+
V3.30 Added: COSMIC tool chain support.
+ Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
+ Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
+ Corrected: GCC/CLang warnings.
+
V3.20 Added: __BKPT instruction intrinsic.
+ Added: __SMMLA instruction intrinsic for Cortex-M4.
+ Corrected: ITM_SendChar.
+ Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
+ Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
+
V3.01 Added support for Cortex-M0+ processor.
+
V3.00 Added support for GNU GCC ARM Embedded Compiler.
+ Added function __ROR.
+ Added Register Mapping for TPIU, DWT.
+ Added support for SC000 and SC300 processors.
+ Corrected ITM_SendChar function.
+ Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
+ Documentation restructured.
V2.10 Updated documentation.
+ Updated CMSIS core include files.
+ Changed CMSIS/Device folder structure.
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
+ Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
+ Added additional Debug Functionality.
+ Changed folder structure.
+ Added doxygen comments.
+ Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
+
+
+ + + + diff --git a/Documentation/Core/html/device_h_pg.html b/Documentation/Core/html/device_h_pg.html new file mode 100644 index 0000000..0d6f05d --- /dev/null +++ b/Documentation/Core/html/device_h_pg.html @@ -0,0 +1,570 @@ + + + + + +Device Header File <device.h> +CMSIS-CORE: Device Header File <device.h> + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Device Header File <device.h>
+
+
+

The Device Header File <device.h> contains the following sections that are device specific:

+
    +
  • Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
    • +
  • Configuration of the Processor and Core Peripherals reflect the features of the device.
    • +
  • Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
    • +
  • Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
    • +
+

Reference describes the standard features and functions of the Device Header File <device.h> in detail.

+

+Interrupt Number Definition

+

Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.

+
    +
  • Negative IRQn values represent processor core exceptions (internal interrupts).
    • +
  • Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<device>.s.
    • +
+

Example:

+

The following example shows the extension of the interrupt vector table for the LPC1100 device family.

+
typedef enum IRQn
+
{
+
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+
NonMaskableInt_IRQn = -14,
+
HardFault_IRQn = -13,
+
SVCall_IRQn = -5,
+
PendSV_IRQn = -2,
+
SysTick_IRQn = -1,
+
/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/
+
WAKEUP0_IRQn = 0,
+
WAKEUP1_IRQn = 1,
+
WAKEUP2_IRQn = 2,
+
: :
+
: :
+
EINT1_IRQn = 30,
+
EINT0_IRQn = 31,
+
} IRQn_Type;
+

+Configuration of the Processor and Core Peripherals

+

The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.

+

The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.

+

core_cm0.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm0plus.h

+ + + + + + + + + +
#define Value Range Default Description
__CM0PLUS_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm3.h

+ + + + + + + + + + + +
#define Value Range Default Description
__CM3_REV 0x0101 | 0x0200 0x0200 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm4.h

+ + + + + + + + + + + + + +
#define Value Range Default Description
__CM4_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_cm7.h

+ + + + + + + + + + + + + + + + + + + + + +
#define Value Range Default Description
__CM7_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
__FPU_PRESENT 0 .. 1 0 Defines if a FPU is present or not. See __FPU_DP description below.
__FPU_DP 0 .. 1 0 The combination of the defines __FPU_PRESENT and __FPU_DP determine the whether the FPU is with single or double precision as shown in the table below.
+
+ + + + + + + + + +
__FPU_PRESENT __FPU_DP Description
0 ignored Processor has no FPU. The value set for __FPU_DP has no influence.
1 0 Processor with FPU with single precision. The file ARMCM7_SP.h has preconfigured settings for this combination.
1 1 Processor with FPU with double precision. The file ARMCM7_DP.h has preconfigured settings for this combination.
+
__ICACHE_PRESENT 0 .. 1 1 Instruction Chache present or not
__DCACHE_PRESENT 0 .. 1 1 Data Chache present or not
__DTCM_PRESENT 0 .. 1 1

Data Tightly Coupled Memory is present or not

+

+
+

core_sc000.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC000_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 2 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

core_sc300.h

+ + + + + + + + + + + +
#define Value Range Default Description
__SC300_REV 0x0000 0x0000 Core revision number ([15:8] revision number, [7:0] patch number)
__NVIC_PRIO_BITS 2 .. 8 4 Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENT 0 .. 1 0 Defines if a MPU is present or not
__Vendor_SysTickConfig 0 .. 1 0 If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+

Example

+

The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.

+
#define __CM4_REV 0x0001 /* Core revision r0p1 */
+
#define __MPU_PRESENT 1 /* MPU present or not */
+
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
+
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
+
#define __FPU_PRESENT 1 /* FPU present or not */
+
.
+
.
+
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
+

+CMSIS Version and Processor Information

+

Defines in the core_cpu.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.

+

core_cm0.h

+
#define __CM0_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+
__CM0_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x00) /* Cortex-M Core */
+

core_cm0plus.h

+
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16) | \
+
__CM0P_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x00) /* Cortex-M Core */
+

core_cm3.h

+
#define __CM3_CMSIS_VERSION_MAIN (0x03) /* [31:16] CMSIS HAL main version */
+
#define __CM3_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+
__CM3_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x03) /* Cortex-M Core */
+

core_cm4.h

+
#define __CM4_CMSIS_VERSION_MAIN (0x04) /* [31:16] CMSIS HAL main version */
+
#define __CM4_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+
__CM4_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_M (0x04) /* Cortex-M Core */
+

core_cm7.h

+
#define __CM7_CMSIS_VERSION_MAIN (0x04)
+
#define __CM7_CMSIS_VERSION_SUB (0x00)
+
#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+
__CM7_CMSIS_VERSION_SUB )
+
#define __CORTEX_M (0x07)
+

core_sc000.h

+
#define __SC000_CMSIS_VERSION_MAIN (0x04) /* [31:16] CMSIS HAL main version */
+
#define __SC000_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+
__SC000_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_SC (000) /* Cortex secure core */
+

core_sc300.h

+
#define __SC300_CMSIS_VERSION_MAIN (0x04) /* [31:16] CMSIS HAL main version */
+
#define __SC300_CMSIS_VERSION_SUB (0x00) /* [15:0] CMSIS HAL sub version */
+
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+
__SC300_CMSIS_VERSION_SUB ) /* CMSIS HAL version number */
+
...
+
#define __CORTEX_SC (300) /* Cortex secure core */
+

+Device Peripheral Access Layer

+

The Device Header File <device.h> contains for each peripheral:

+
    +
  • Register Layout Typedef
    • +
  • Base Address
    • +
  • Access Definitions
    • +
+

The section Peripheral Access shows examples for peripheral definitions.

+

+Device.h Template File

+

The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.

+
/**************************************************************************//**
+ * @file     <Device>.h
+ * @brief    CMSIS Cortex-M# Core Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */
+#define <Device>_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* ToDo: replace '<Device>' with your device name; add your doxyGen comment   */
+/** @addtogroup <Device>_Definitions <Device> Definitions
+  This file defines all structures and symbols for <Device>:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - Peripheral definitions
+  @{
+*/
+
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
+  Configuration of the Cortex-M# Processor and Core Peripherals
+  @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M# Processor Exceptions Numbers ***************************************************/
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device                   */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  HardFault_IRQn                = -13,      /*!<  3 Hard Fault Interrupt                          */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
+  NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
+  MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
+  BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
+  UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
+  SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
+  DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
+  PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
+  SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */
+
+/******  Device Specific Interrupt Numbers ********************************************************/
+/* ToDo: add here your device specific external interrupt numbers
+         according the interrupt handlers defined in startup_Device.s
+         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
+  <DeviceInterrupt>_IRQn        = 0,        /*!< Device Interrupt                                 */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+/* ToDo: set the defines according your Device                                                    */
+/* ToDo: define the correct core revision
+         __CM0_REV if your device is a CORTEX-M0 device
+         __CM3_REV if your device is a CORTEX-M3 device
+         __CM4_REV if your device is a CORTEX-M4 device                                           */
+#define __CM#_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             0         /*!< MPU present or not                               */
+/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
+#define __FPU_PRESENT             0        /*!< FPU present or not                                */
+
+/*@}*/ /* end of group <Device>_CMSIS */
+
+
+/* ToDo: include the correct core_cm#.h file
+         core_cm0.h if your device is a CORTEX-M0 device
+         core_cm3.h if your device is a CORTEX-M3 device
+         core_cm4.h if your device is a CORTEX-M4 device                                          */
+#include <core_cm#.h>                       /* Cortex-M# processor and core peripherals           */
+/* ToDo: include your system_<Device>.h file
+         replace '<Device>' with your device name                                                 */
+#include "system_<Device>.h"                /* <Device> System  include file                      */
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+/** @addtogroup <Device>_Peripherals <Device> Peripherals
+  <Device> Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/* ToDo: add here your device specific peripheral access structure typedefs
+         following is an example for a timer                                  */
+
+/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
+/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
+  @{
+*/
+typedef struct
+{
+  __IO uint32_t EN;                         /*!< Offset: 0x0000   Timer Enable Register           */
+  __IO uint32_t RUN;                        /*!< Offset: 0x0004   Timer RUN Register              */
+  __IO uint32_t CR;                         /*!< Offset: 0x0008   Timer Control Register          */
+  __IO uint32_t MOD;                        /*!< Offset: 0x000C   Timer Mode Register             */
+       uint32_t RESERVED0[1];
+  __IO uint32_t ST;                         /*!< Offset: 0x0014   Timer Status Register           */
+  __IO uint32_t IM;                         /*!< Offset: 0x0018   Interrupt Mask Register         */
+  __IO uint32_t UC;                         /*!< Offset: 0x001C   Timer Up Counter Register       */
+  __IO uint32_t RG0                         /*!< Offset: 0x0020   Timer Register                  */
+       uint32_t RESERVED1[2];
+  __IO uint32_t CP;                         /*!< Offset: 0x002C   Capture register                */
+} <DeviceAbbreviation>_TMR_TypeDef;
+/*@}*/ /* end of group <Device>_TMR */
+
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group <Device>_Peripherals */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/* ToDo: add here your device peripherals base addresses
+         following is an example for timer                                    */
+/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
+  @{
+*/
+
+/* Peripheral and SRAM base address */
+#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */
+#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */
+
+/* Peripheral memory map */
+#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */
+#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */
+#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */
+/*@}*/ /* end of group <Device>_MemoryMap */
+
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+/* ToDo: add here your device peripherals pointer definitions
+         following is an example for timer                                    */
+
+/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
+  @{
+*/
+
+#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
+/*@}*/ /* end of group <Device>_PeripheralDecl */
+
+/*@}*/ /* end of group <Device>_Definitions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* <Device>_H */
+
+
+ + + + diff --git a/Documentation/Core/html/doxygen.css b/Documentation/Core/html/doxygen.css new file mode 100644 index 0000000..0fa08d5 --- /dev/null +++ b/Documentation/Core/html/doxygen.css @@ -0,0 +1,1172 @@ +/* The standard CSS for doxygen */ + +body, table, div, p, dl { + font: 400 14px/19px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #859DCD; + color: #334C7D; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + -moz-transition: text-shadow 0.5s linear; + -ms-transition: text-shadow 0.5s linear; + -o-transition: text-shadow 0.5s linear; + transition: text-shadow 0.5s linear; + margin-right: 15px; +} + +h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow { + text-shadow: 0 0 15px cyan; +} + +dt { + font-weight: bold; +} + +div.multicol { + -moz-column-gap: 1em; + -webkit-column-gap: 1em; + -moz-column-count: 3; + -webkit-column-count: 3; +} + +p.startli, p.startdd, p.starttd { + margin-top: 2px; +} + +p.endli { + margin-bottom: 0px; +} + +p.enddd { + margin-bottom: 4px; +} + +p.endtd { + margin-bottom: 2px; +} + +/* @end */ + +caption { + font-weight: bold; +} + +span.legend { + font-size: 70%; + text-align: center; +} + +h3.version { + font-size: 90%; + text-align: center; +} + +div.qindex, div.navtab{ + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; +} + +div.qindex, div.navpath { + width: 100%; + line-height: 140%; +} + +div.navtab { + margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px; + margin: 4px; + background-color: #FBFCFD; + border: 1px solid #C3CFE6; +} + +div.line { + font-family: monospace, fixed; + font-size: 13px; + min-height: 13px; + line-height: 1.0; + text-wrap: unrestricted; + white-space: -moz-pre-wrap; /* Moz */ + white-space: -pre-wrap; /* Opera 4-6 */ + white-space: -o-pre-wrap; /* Opera 7 */ + white-space: pre-wrap; /* CSS3 */ + word-wrap: break-word; /* IE 5.5+ */ + text-indent: -53px; + padding-left: 53px; + padding-bottom: 0px; + margin: 0px; + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +div.line.glow { + background-color: cyan; + box-shadow: 0 0 10px cyan; +} + + +span.lineno { + padding-right: 4px; + text-align: right; + border-right: 2px solid #0F0; + background-color: #E8E8E8; + white-space: pre; +} +span.lineno a { + background-color: #D8D8D8; +} + +span.lineno a:hover { + background-color: #C8C8C8; +} + +div.ah { + background-color: black; + font-weight: bold; + color: #ffffff; + margin-bottom: 3px; + margin-top: 3px; + padding: 0.2em; + border: solid thin #333; + border-radius: 0.5em; + -webkit-border-radius: .5em; + -moz-border-radius: .5em; + box-shadow: 2px 2px 3px #999; + -webkit-box-shadow: 2px 2px 3px #999; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444)); + background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000); +} + +div.groupHeader { + margin-left: 16px; + margin-top: 12px; + font-weight: bold; +} + +div.groupText { + margin-left: 16px; + font-style: italic; +} + +body { + background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + +span.keywordflow { + color: #e08000 +} + +span.comment { + color: #800000 +} + +span.preprocessor { + color: #806020 +} + +span.stringliteral { + color: #002080 +} + +span.charliteral { + color: #008080 +} + +span.vhdldigit { + color: #ff00ff +} + +span.vhdlchar { + color: #000000 +} + +span.vhdlkeyword { + color: #700070 +} + +span.vhdllogic { + color: #ff0000 +} + +blockquote { + background-color: #F7F8FB; + border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + width: 100%; + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, .fieldtable th { + padding: 3px 7px 2px; +} + +.fieldtable td.fieldtype, .fieldtable td.fieldname { + white-space: nowrap; + border-right: 1px solid #A7B8DA; + border-bottom: 1px solid #A7B8DA; + vertical-align: top; +} + +.fieldtable td.fielddoc { + border-bottom: 1px solid #A7B8DA; + width: 100%; +} + +.fieldtable tr:last-child td { + border-bottom: none; +} + +.fieldtable th { + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + font-size: 90%; + color: #233456; + padding-bottom: 4px; + padding-top: 5px; + text-align:left; + -moz-border-radius-topleft: 4px; + -moz-border-radius-topright: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + border-top-left-radius: 4px; + border-top-right-radius: 4px; + border-bottom: 1px solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #27395E; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ + list-style-type:none; + float:right; + padding-left:10px; + padding-right:15px; + background-image:none; + background-repeat:no-repeat; + background-position:right; + color:#344D7E; + font-size: 8pt; +} + + +div.summary +{ + float: right; + font-size: 8pt; + padding-right: 5px; + width: 50%; + text-align: right; +} + +div.summary a +{ + white-space: nowrap; +} + +div.ingroups +{ + font-size: 8pt; + width: 50%; + text-align: left; +} + +div.ingroups a +{ + white-space: nowrap; +} + +div.header +{ + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + margin: 0px; + border-bottom: 1px solid #C3CFE6; +} + +div.headertitle +{ + padding: 5px 5px 5px 10px; +} + +dl +{ + padding: 0 0 0 10px; +} + +/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */ +dl.section +{ + margin-left: 0px; + padding-left: 0px; +} + +dl.note +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #D0C000; +} + +dl.warning, dl.attention +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #FF0000; +} + +dl.pre, dl.post, dl.invariant +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00D000; +} + +dl.deprecated +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #505050; +} + +dl.todo +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #00C0E0; +} + +dl.test +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #3030E0; +} + +dl.bug +{ + margin-left:-7px; + padding-left: 3px; + border-left:4px solid; + border-color: #C08050; +} + +dl.section dd { + margin-bottom: 6px; +} + + +#projectlogo +{ + text-align: center; + vertical-align: bottom; + border-collapse: separate; +} + +#projectlogo img +{ + border: 0px none; +} + +#projectname +{ + font: 300% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 2px 0px; +} + +#projectbrief +{ + font: 120% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#projectnumber +{ + font: 50% Tahoma, Arial,sans-serif; + margin: 0px; + padding: 0px; +} + +#titlearea +{ + padding: 0px; + margin: 0px; + width: 100%; + border-bottom: 1px solid #5072B7; +} + +.image +{ + text-align: center; +} + +.dotgraph +{ + text-align: center; +} + +.mscgraph +{ + text-align: center; +} + +.caption +{ + font-weight: bold; +} + +div.zoom +{ + border: 1px solid #8EA4D0; +} + +dl.citelist { + margin-bottom:50px; +} + +dl.citelist dt { + color:#314877; + float:left; + font-weight:bold; + margin-right:10px; + padding:5px; +} + +dl.citelist dd { + margin:2px 0; + padding:5px 0; +} + +div.toc { + padding: 14px 25px; + background-color: #F4F6FA; + border: 1px solid #D7DFEE; + border-radius: 7px 7px 7px 7px; + float: right; + height: auto; + margin: 0 20px 10px 10px; + width: 200px; +} + +div.toc li { + background: url("bdwn.png") no-repeat scroll 0 5px transparent; + font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif; + margin-top: 5px; + padding-left: 10px; + padding-top: 2px; +} + +div.toc h3 { + font: bold 12px/1.2 Arial,FreeSans,sans-serif; + color: #4464A5; + border-bottom: 0 none; + margin: 0; +} + +div.toc ul { + list-style: none outside none; + border: medium none; + padding: 0px; +} + +div.toc li.level1 { + margin-left: 0px; +} + +div.toc li.level2 { + margin-left: 15px; +} + +div.toc li.level3 { + margin-left: 30px; +} + +div.toc li.level4 { + margin-left: 45px; +} + +.inherit_header { + font-weight: bold; + color: gray; + cursor: pointer; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +.inherit_header td { + padding: 6px 0px 2px 5px; +} + +.inherit { + display: none; +} + +tr.heading h2 { + margin-top: 12px; + margin-bottom: 4px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/Documentation/Core/html/doxygen.png b/Documentation/Core/html/doxygen.png new file mode 100644 index 0000000..7765a33 Binary files /dev/null and b/Documentation/Core/html/doxygen.png differ diff --git a/Documentation/Core/html/dynsections.js b/Documentation/Core/html/dynsections.js new file mode 100644 index 0000000..116542f --- /dev/null +++ b/Documentation/Core/html/dynsections.js @@ -0,0 +1,78 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l + + + + +Data Fields +CMSIS-CORE: Data Fields + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + + + + +
+
+ +
+
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+ +
+ + + + +
+ +
+ +
+
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+Functions
+
+
Core Register Access
+
+
+ +

Functions to access the Cortex-M core registers. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __get_CONTROL (void)
 Read the CONTROL register.
 
void __set_CONTROL (uint32_t control)
 Set the CONTROL Register.
 
uint32_t __get_IPSR (void)
 Read the IPSR register.
 
uint32_t __get_APSR (void)
 Read the APSR register.
 
uint32_t __get_xPSR (void)
 Read the xPSR register.
 
uint32_t __get_PSP (void)
 Read the PSP register.
 
void __set_PSP (uint32_t topOfProcStack)
 Set the PSP register.
 
uint32_t __get_MSP (void)
 Read the MSP register.
 
void __set_MSP (uint32_t topOfMainStack)
 Set the MSP register.
 
uint32_t __get_PRIMASK (void)
 Read the PRIMASK register bit.
 
void __set_PRIMASK (uint32_t priMask)
 Set the Priority Mask bit.
 
uint32_t __get_BASEPRI (void)
 Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].
 
void __set_BASEPRI (uint32_t basePri)
 Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].
 
void __set_BASEPRI_MAX (uint32_t basePri)
 Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __get_FAULTMASK (void)
 Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].
 
void __set_FAULTMASK (uint32_t faultMask)
 Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __get_FPSCR (void)
 Read the FPSCR register [only Cortex-M4 and Cortex-M7].
 
void __set_FPSCR (uint32_t fpscr)
 Set the FPSC register [only for Cortex-M4 and Cortex-M7].
 
void __enable_irq (void)
 Globally enables interrupts and configurable fault handlers.
 
void __disable_irq (void)
 Globally disables interrupts and configurable fault handlers.
 
void __enable_fault_irq (void)
 Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].
 
void __disable_fault_irq (void)
 Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000].
 
+

Description

+

The following functions provide access to Cortex-M core registers.

+

Function Documentation

+ +
+
+ + + + + + + + +
void __disable_fault_irq (void )
+
+

The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction CPSID f.

+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Can be executed in privileged mode only.
    • +
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __disable_irq (void )
+
+

The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction CPSID i.

+
Remarks
    +
  • Can be executed in privileged mode only.
    • +
  • An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __enable_fault_irq (void )
+
+

The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction CPSIE f.

+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Can be executed in privileged mode only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __enable_irq (void )
+
+

The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction CPSIE i.

+
Remarks
    +
  • Can be executed in privileged mode only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_APSR (void )
+
+

The function reads the Application Program Status Register (APSR) using the instruction MRS.
+
+ The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:

+
    +
  • N (APSR[31]) (Negative flag)
      +
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • +
    • =0 The instruction result has a positive value or equal zero.
      +
      +
      • +
    +
    • +
  • Z (APSR[30]) (Zero flag)
      +
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
      +
      +
      • +
    +
    • +
  • C (APSR[29]) (Carry or borrow flag)
      +
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • +
    • =inverse of borrow output status For unsigned subtract operations.
      +
      +
      • +
    +
    • +
  • V (APSR[28]) (Overflow flag)
      +
    • =1 A signed overflow occurred (for signed additions or subtractions).
      +
      +
      • +
    +
    • +
  • Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
      +
    • This flag is a sticky flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.
      • +
    • =1 When saturation or an overflow occurred.
      +
      +
      • +
    +
    • +
  • GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
      +
    • Can be set by the parallel add and subtract instructions.
      • +
    • Are used by the SEL instruction to perform byte-based selection from two registers.
      • +
    +
    • +
+
Returns
APSR register value
+
Remarks
    +
  • Some instructions update all flags; some instructions update a subset of the flags.
    • +
  • If a flag is not updated, the original value is preserved.
    • +
  • Conditional instructions that are not executed have no effect on the flags.
    • +
  • The CMSIS does not provide a function to update this register.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_BASEPRI (void )
+
+

The function returns the Base Priority Mask register (BASEPRI) using the instruction MRS.
+
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Returns
BASEPRI register value
+
Remarks
    +
  • Not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_CONTROL (void )
+
+

The function reads the CONTROL register value using the instruction MRS.
+
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+

+
    +
  • CONTROL[2] [only Cortex-M4 and Cortex-M7]
      +
    • =0 FPU not active
      • +
    • =1 FPU active
      +
      +
      • +
    +
    • +
  • CONTROL[1]
      +
    • =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
      • +
    • =0 In thread mode - Default stack pointer MSP is used.
      • +
    • =1 In thread mode - Alternate stack pointer PSP is used.
      +
      +
      • +
    +
    • +
  • CONTROL[0] [not Cortex-M0]
      +
    • =0 In thread mode and privileged state.
      • +
    • =1 In thread mode and user state.
      • +
    +
    • +
+
Returns
CONTROL register value
+
Remarks
    +
  • The processor can be in user state or privileged state when running in thread mode.
    • +
  • Exception handlers always run in privileged state.
    • +
  • On reset, the processor is in thread mode with privileged access rights.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_FAULTMASK (void )
+
+

The function reads the Fault Mask register (FAULTMASK) value using the instruction MRS.
+
+ FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).

+
Returns
FAULTMASK register value
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_FPSCR (void )
+
+

The function reads the Floating-Point Status Control Register (FPSCR) value.
+
+ FPSCR provides all necessary User level controls of the floating-point system.

+
Returns
    +
  • FPSCR register value, when __FPU_PRESENT=1
    • +
  • =0, when __FPU_PRESENT=0
    • +
+
+
Remarks
    +
  • Only for Cortex-M4 and Cortex-M7.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_IPSR (void )
+
+

The function reads the Interrupt Program Status Register (IPSR) using the instruction MRS.
+
+ The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:

+
    +
  • ISR_NUMBER (IPSR[8:0])
      +
    • =0 Thread mode
      • +
    • =1 Reserved
      • +
    • =2 NMI
      • +
    • =3 HardFault
      • +
    • =4 MemManage
      • +
    • =5 BusFault
      • +
    • =6 UsageFault
      • +
    • =7-10 Reserved
      • +
    • =11 SVCall
      • +
    • =12 Reserved for Debug
      • +
    • =13 Reserved
      • +
    • =14 PendSV
      • +
    • =15 SysTick
      • +
    • =16 IRQ0
      • +
    • ...
      • +
    • =n+15 IRQ(n-1)
      • +
    +
    • +
+
Returns
ISPR register value
+
Remarks
    +
  • This register is read-only.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_MSP (void )
+
+

The function reads the Main Status Pointer (MSP) value using the instruction MRS.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Returns
MSP Register value
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PRIMASK (void )
+
+

The function reads the Priority Mask register (PRIMASK) value using the instruction MRS.
+
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Returns
PRIMASK register value
    +
  • =0 no effect
    • +
  • =1 prevents the activation of all exceptions with configurable priority
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_PSP (void )
+
+

The function reads the Program Status Pointer (PSP) value using the instruction MRS.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Returns
PSP register value
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __get_xPSR (void )
+
+

The function reads the combined Program Status Register (xPSR) using the instruction MRS.
+
+ xPSR provides information about program execution and the APSR flags. It consists of the following PSRs:

+
    +
  • Application Program Status Register (APSR)
    • +
  • Interrupt Program Status Register (IPSR)
    • +
  • Execution Program Status Register (EPSR)
    • +
+

In addition to the flags described in __get_APSR and __get_IPSR, the register provides the following flags:

+
    +
  • IT (xPSR[26:25]) (If-Then condition instruction)
      +
    • Contains up to four instructions following an IT instruction.
      • +
    • Each instruction in the block is conditional.
      • +
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      +
      +
      • +
    +
    • +
  • T (xPSR[24]) (Thumb bit)
      +
    • =1 Indicates that that the processor is in Thumb state.
      • +
    • =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
      • +
    • The conditions for the instructions are either all the same, or some can be the inverse of others.
      • +
    +
    • +
+
Returns
xPSR register value
+
Remarks
    +
  • The CMSIS does not provide functions that access EPSR.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_BASEPRI (uint32_t basePri)
+
+

The function sets the Base Priority Mask register (BASEPRI) value using the instruction MSR.
+
+ BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.

+
Parameters
+ + +
[in]basePriBASEPRI value to set
+
+
+
Remarks
    +
  • Not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Cannot be set in user state.
    • +
  • Useful for changing the masking level or disabling the masking.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_BASEPRI_MAX (uint32_t basePri)
+
+

The function only increases the Base Priority Mask register (BASEPRI) value using the instruction MSR. The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.
+
+ BASEPRI defines the minimum priority for exception processing.

+
Parameters
+ + +
[in]basePriBASEPRI value to set
+
+
+
Remarks
    +
  • Not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Cannot be set in user state.
    • +
  • Useful for increasing the masking level.
    • +
  • Has no effect when basePri is lower than the current value of BASEPRI.
    • +
  • Use __set_BASEPRI to lower the Base Priority Mask register.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_CONTROL (uint32_t control)
+
+

The function sets the CONTROL register value using the instruction MSR.
+
+ The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits:
+

+
    +
  • CONTROL[2] [only Cortex-M4 and Cortex-M7]
      +
    • =0 FPU not active
      • +
    • =1 FPU active
      +
      +
      • +
    +
    • +
  • CONTROL[1]
      +
    • Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
      • +
    • =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
      • +
    • =0 In thread mode - Default stack pointer MSP is used.
      • +
    • =1 In thread mode - Alternate stack pointer PSP is used.
      +
      +
      • +
    +
    • +
  • CONTROL[0] [not writeable for Cortex-M0]
      +
    • Writeable only when the processor is in privileged state.
      • +
    • Can be used to switch the processor to user state (thread mode).
      • +
    • Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).
      • +
    • =0 In thread mode and privileged state.
      • +
    • =1 In thread mode and user state.
      • +
    +
    • +
+
Parameters
+ + +
[in]controlCONTROL register value to set
+
+
+
Remarks
    +
  • The processor can be in user state or privileged state when running in thread mode.
    • +
  • Exception handlers always run in privileged state.
    • +
  • On reset, the processor is in thread mode with privileged access rights.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_FAULTMASK (uint32_t faultMask)
+
+

The function sets the Fault Mask register (FAULTMASK) value using the instruction MSR.
+
+ FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:

+
    +
  1. Mask BusFault by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.
    2. +
  2. Bypass the MPU, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.
    3. +
+
Parameters
+ + +
[in]faultMaskFAULTMASK register value to set
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.
    • +
  • When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.
    • +
  • Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).
    • +
  • When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_FPSCR (uint32_t fpscr)
+
+

The function sets the Floating-Point Status Control Register (FPSCR) value.
+
+ FPSCR provides all necessary User level control of the floating-point system.
+

+
    +
  • N (FPSC[31]) (Negative flag)
      +
    • =1 The instruction result has a negative value (when interpreted as signed integer).
      • +
    • =0 The instruction result has a positive value or equal zero.
      +
      +
      • +
    +
    • +
  • Z (FPSC[30]) (Zero flag)
      +
    • =1 The instruction result is zero. Or, after a compare instruction, when the two values are the same.
      +
      +
      • +
    +
    • +
  • C (FPSC[29]) (Carry or borrow flag)
      +
    • =1 For unsigned additions, if an unsigned overflow occurred.
      • +
    • =inverse of borrow output status For unsigned subtract operations.
      +
      +
      • +
    +
    • +
  • V (FPSC[28]) (Overflow flag)
      +
    • =1 A signed overflow occurred (for signed additions or subtractions).
      +
      +
      • +
    +
    • +
  • AHP (FPSC[26]) (Alternative half-precision flag)
      +
    • =1 Alternative half-precision format selected.
      • +
    • =0 IEEE half-precision format selected.
      +
      +
      • +
    +
    • +
  • DN (FPSC[25]) (Default NaN mode control flag)
      +
    • =1 Any operation involving one or more NaNs returns the Default NaN.
      • +
    • =0 NaN operands propagate through to the output of a floating-point operation.
      +
      +
      • +
    +
    • +
  • FZ (FPSC[24]) (Flush-to-zero mode control flag)
      +
    • =1 Flush-to-zero mode enabled.
      • +
    • =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
      +
      +
      • +
    +
    • +
  • RMode (FPSC[23:22]) (Rounding Mode control flags)
      +
    • =0b00 Round to Nearest (RN) mode.
      • +
    • =0b01 Round towards Plus Infinity (RP) mode.
      • +
    • =0b10 Round towards Minus Infinity (RM) mode.
      • +
    • =0b11 Round towards Zero (RZ) mode.
      • +
    • The specified rounding mode is used by almost all floating-point instructions.
      +
      +
      • +
    +
    • +
  • IDC (FPSC[7]) (Input Denormal cumulative exception flags)
      +
    • See Cumulative exception bits (FPSC[4:0]).
      +
      +
      • +
    +
    • +
  • IXC (FPSC[4]) (Inexact cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • UFC (FPSC[3]) (Underflow cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • OFC (FPSC[2]) (Overflow cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • DZC (FPSC[1]) (Division by Zero cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      +
      +
      • +
    +
    • +
  • IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
      +
    • =1 Exception occurred.
      • +
    • =0 Value has to be set explicitly.
      • +
    • Flag is not cleared automatically.
      • +
    +
    • +
+
Parameters
+ + +
[in]fpscrFPSCR value to set
+
+
+
Remarks
    +
  • Only for Cortex-M4 and Cortex-M7.
    • +
  • The variable __FPU_PRESENT has to be set to 1.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_MSP (uint32_t topOfMainStack)
+
+

The function sets the Main Status Pointer (MSP) value using the instruction MSR.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Parameters
+ + +
[in]topOfMainStackMSP value to set
+
+
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_PRIMASK (uint32_t priMask)
+
+

The function sets the Priority Mask register (PRIMASK) value using the instruction MSR.
+
+ PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.

+
Parameters
+ + +
[in]priMaskPriority Mask
    +
  • =0 no effect
    • +
  • =1 prevents the activation of all exceptions with configurable priority
    • +
+
+
+
+
Remarks
    +
  • When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.
    • +
  • When set and a fault occurs, the hard fault handler will be executed.
    • +
  • Useful for temprorarily disabling all interrupts for timing critical tasks.
    • +
  • Does not have the ability to mask BusFault or bypass MPU.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void __set_PSP (uint32_t topOfProcStack)
+
+

The function sets the Program Status Pointer (PSP) value using the instruction MSR.
+
+ Physically two different stack pointers (SP) exist:

+
    +
  • The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).
    • +
  • The Process Stack Pointer (PSP), which can be used only in thread mode.
    • +
+

Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:

+
    +
  • =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.
    • +
  • =1 PSP is the current stack pointer. The initial value is undefined.
    • +
+
Parameters
+ + +
[in]topOfProcStackPSP value to set
+
+
+
Remarks
    +
  • Only one of the two SPs is visible at a time.
    • +
  • For many applications, the system can completely rely on the MSP.
    • +
  • The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.
    • +
+
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group___core___register__gr.js b/Documentation/Core/html/group___core___register__gr.js new file mode 100644 index 0000000..9bdcfdb --- /dev/null +++ b/Documentation/Core/html/group___core___register__gr.js @@ -0,0 +1,25 @@ +var group___core___register__gr = +[ + [ "__disable_fault_irq", "group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939", null ], + [ "__disable_irq", "group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013", null ], + [ "__enable_fault_irq", "group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf", null ], + [ "__enable_irq", "group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27", null ], + [ "__get_APSR", "group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7", null ], + [ "__get_BASEPRI", "group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667", null ], + [ "__get_CONTROL", "group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7", null ], + [ "__get_FAULTMASK", "group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8", null ], + [ "__get_FPSCR", "group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905", null ], + [ "__get_IPSR", "group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8", null ], + [ "__get_MSP", "group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2", null ], + [ "__get_PRIMASK", "group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02", null ], + [ "__get_PSP", "group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9", null ], + [ "__get_xPSR", "group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd", null ], + [ "__set_BASEPRI", "group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882", null ], + [ "__set_BASEPRI_MAX", "group___core___register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9", null ], + [ "__set_CONTROL", "group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c", null ], + [ "__set_FAULTMASK", "group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a", null ], + [ "__set_FPSCR", "group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b", null ], + [ "__set_MSP", "group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4", null ], + [ "__set_PRIMASK", "group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f", null ], + [ "__set_PSP", "group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group___dcache__functions__m7.html b/Documentation/Core/html/group___dcache__functions__m7.html new file mode 100644 index 0000000..8d2c5bb --- /dev/null +++ b/Documentation/Core/html/group___dcache__functions__m7.html @@ -0,0 +1,356 @@ + + + + + +D-Cache Functions +CMSIS-CORE: D-Cache Functions + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
D-Cache Functions
+
Cache Functions (only Cortex-M7)
+
+ +

Functions for the data cache. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

__STATIC_INLINE void SCB_EnableDCache (void)
 Enable D-Cache.
 
__STATIC_INLINE void SCB_DisableDCache (void)
 Disable D-Cache.
 
__STATIC_INLINE void SCB_InvalidateDCache (void)
 Invalidate D-Cache.
 
__STATIC_INLINE void SCB_CleanDCache (void)
 Clean D-Cache.
 
__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
 Clean & Invalidate D-Cache.
 
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
 D-Cache Invalidate by address.
 
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
 D-Cache Clean by address.
 
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
 D-Cache Clean and Invalidate by address.
 
+

Description

+

// close ICache functions

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_CleanDCache (void )
+
+

The function cleans the entire data cache.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t * addr,
int32_t dsize 
)
+
+
Parameters
+ + + +
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)
+
+
+

The function cleans a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundry.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_CleanInvalidateDCache (void )
+
+

The function cleans and invalidates the entire data cache.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t * addr,
int32_t dsize 
)
+
+
Parameters
+ + + +
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)
+
+
+

The function invalidates and cleans a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundry.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_DisableDCache (void )
+
+

The function turns off the entire data cache.

+
Note
When disabling the data cache, you must clean (SCB_CleanDCache) the entire cache to ensure that any dirty data is flushed to external memory.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_EnableDCache (void )
+
+

The function turns on the entire data cache.

+
Note
Before enabling the data cache, you must invalidate the entire data cache (SCB_InvalidateDCache), because external memory might have changed from when the cache was disabled.
+
+After reset, you must invalidate (SCB_InvalidateDCache) each cache before enabling it.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_InvalidateDCache (void )
+
+

The function invalidates the entire data cache.

+
Note
After reset, you must invalidate each cache before enabling (SCB_EnableDCache) it.
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t * addr,
int32_t dsize 
)
+
+
Parameters
+ + + +
[in]addraddress (aligned to 32-byte boundary)
[in]dsizesize of memory block (in number of bytes)
+
+
+

The function invalidates a memory block of size dsize [bytes] starting at address address. The address is aligned to 32-byte boundry.

+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group___dcache__functions__m7.js b/Documentation/Core/html/group___dcache__functions__m7.js new file mode 100644 index 0000000..c789ca5 --- /dev/null +++ b/Documentation/Core/html/group___dcache__functions__m7.js @@ -0,0 +1,11 @@ +var group___dcache__functions__m7 = +[ + [ "SCB_CleanDCache", "group___dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c", null ], + [ "SCB_CleanDCache_by_Addr", "group___dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d", null ], + [ "SCB_CleanInvalidateDCache", "group___dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c", null ], + [ "SCB_CleanInvalidateDCache_by_Addr", "group___dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e", null ], + [ "SCB_DisableDCache", "group___dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe", null ], + [ "SCB_EnableDCache", "group___dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6", null ], + [ "SCB_InvalidateDCache", "group___dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6", null ], + [ "SCB_InvalidateDCache_by_Addr", "group___dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group___i_t_m___debug__gr.html b/Documentation/Core/html/group___i_t_m___debug__gr.html new file mode 100644 index 0000000..5c40fd2 --- /dev/null +++ b/Documentation/Core/html/group___i_t_m___debug__gr.html @@ -0,0 +1,280 @@ + + + + + +Debug Access +CMSIS-CORE: Debug Access + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
Debug Access
+
+
+ +

Debug Access to the Instrumented Trace Macrocell (ITM) +More...

+ + + + + + + + + + + +

+Functions

uint32_t ITM_SendChar (uint32_t ch)
 Transmits a character via channel 0.
 
int32_t ITM_ReceiveChar (void)
 ITM Receive Character.
 
int32_t ITM_CheckChar (void)
 ITM Check Character.
 
+ + + + +

+Variables

volatile int32_t ITM_RxBuffer
 external variable to receive characters
 
+

Description

+

CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.

+

The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the Instrumented Trace Macrocell (ITM) that provides together with the Serial Viewer Output (SVO) trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_SendChar function which can be used for printf-style output via the debug interface.
    • +
+
    +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
    • +
+
Remarks
    +
  • ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.
    • +
  • The ITM channel 0 can be enabled for the user task.
    • +
  • ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.
    • +
+
+
+

+ITM Debugger Support

+

A debugger may support a Debug (printf) Viewer window to display data.

+

Direction: Microcontroller –> Debugger:

+
    +
  • Characters received via ITM communication channel 0 are written in a printf-style to the Debug (printf) Viewer window.
    • +
+

Direction: Debugger –> Microcontroller:

+
    +
  • Check if ITM_RxBuffer variable is available (only performed once).
    • +
  • Read the character from the Debug (printf) Viewer window.
    • +
  • If ITM_RxBuffer is empty, write character to ITM_RxBuffer.
    • +
+
Note
The current solution does not use a buffer mechanism for transmitting the characters.
+
+

+Example:

+

Example for the usage of the ITM Channel 31 for RTOS Kernels:

+
// check if debugger connected and ITM channel enabled for tracing
+
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+
(ITM->TCR & ITM_TCR_ITMENA) &&
+
(ITM->TER & (1UL >> 31))) {
+
+
// transmit trace data
+
while (ITM->PORT31_U32 == 0);
+
ITM->PORT[31].u8 = task_id; // id of next task
+
while (ITM->PORT[31].u32 == 0);
+
ITM->PORT[31].u32 = task_status; // status information
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
int32_t ITM_CheckChar (void )
+
+

This function reads the external variable ITM_RxBuffer and checks whether a character is available or not.

+
Returns
    +
  • =0 - No character available
    • +
  • =1 - Character available
    • +
+
+ +
+
+ +
+
+ + + + + + + + +
int32_t ITM_ReceiveChar (void )
+
+

This function inputs a character via the external variable ITM_RxBuffer. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Returns
    +
  • Received character
    • +
  • =1 - No character received
    • +
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t ITM_SendChar (uint32_t ch)
+
+

This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.

+
Parameters
+ + +
[in]chCharacter to transmit
+
+
+
Returns
Character to transmit
+ +
+
+

Variable Documentation

+ +
+
+ + + + +
volatile int32_t ITM_RxBuffer
+
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group___i_t_m___debug__gr.js b/Documentation/Core/html/group___i_t_m___debug__gr.js new file mode 100644 index 0000000..eb22977 --- /dev/null +++ b/Documentation/Core/html/group___i_t_m___debug__gr.js @@ -0,0 +1,7 @@ +var group___i_t_m___debug__gr = +[ + [ "ITM_CheckChar", "group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535", null ], + [ "ITM_ReceiveChar", "group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c", null ], + [ "ITM_SendChar", "group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1", null ], + [ "ITM_RxBuffer", "group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group___icache__functions__m7.html b/Documentation/Core/html/group___icache__functions__m7.html new file mode 100644 index 0000000..1a1377c --- /dev/null +++ b/Documentation/Core/html/group___icache__functions__m7.html @@ -0,0 +1,203 @@ + + + + + +I-Cache Functions +CMSIS-CORE: I-Cache Functions + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
I-Cache Functions
+
Cache Functions (only Cortex-M7)
+
+ +

Functions for the instruction cache. +More...

+ + + + + + + + + + + +

+Functions

__STATIC_INLINE void SCB_EnableICache (void)
 Enable I-Cache.
 
__STATIC_INLINE void SCB_DisableICache (void)
 Disable I-Cache.
 
__STATIC_INLINE void SCB_InvalidateICache (void)
 Invalidate I-Cache.
 
+

Description

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_DisableICache (void )
+
+

The function turns off the instruction cache.

+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_EnableICache (void )
+
+

The function turns on the instruction cache.

+
Note
Before enabling the instruction cache, you must invalidate (SCB_InvalidateICache) the entire instruction cache if external memory might have changed since the cache was disabled.
+
+After reset, you must invalidate (SCB_InvalidateICache) each cache before enabling it.
+ +
+
+ +
+
+ + + + + + + + +
__STATIC_INLINE void SCB_InvalidateICache (void )
+
+

The function invalidates the instruction cache. The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction.

+
Note
After reset, you must invalidate each cache before enabling (SCB_EnableICache) it.
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group___icache__functions__m7.js b/Documentation/Core/html/group___icache__functions__m7.js new file mode 100644 index 0000000..e9c58ef --- /dev/null +++ b/Documentation/Core/html/group___icache__functions__m7.js @@ -0,0 +1,6 @@ +var group___icache__functions__m7 = +[ + [ "SCB_DisableICache", "group___icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8", null ], + [ "SCB_EnableICache", "group___icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68", null ], + [ "SCB_InvalidateICache", "group___icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group___n_v_i_c__gr.html b/Documentation/Core/html/group___n_v_i_c__gr.html new file mode 100644 index 0000000..2a8031c --- /dev/null +++ b/Documentation/Core/html/group___n_v_i_c__gr.html @@ -0,0 +1,1061 @@ + + + + + +Interrupts and Exceptions (NVIC) +CMSIS-CORE: Interrupts and Exceptions (NVIC) + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Enumerations | +Functions
+
+
Interrupts and Exceptions (NVIC)
+
+
+ +

Explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC). +More...

+ + + + + +

+Enumerations

enum  IRQn_Type {
+  NonMaskableInt_IRQn = -14, +
+  HardFault_IRQn = -13, +
+  MemoryManagement_IRQn = -12, +
+  BusFault_IRQn = -11, +
+  UsageFault_IRQn = -10, +
+  SVCall_IRQn = -5, +
+  DebugMonitor_IRQn = -4, +
+  PendSV_IRQn = -2, +
+  SysTick_IRQn = -1, +
+  WWDG_STM_IRQn = 0, +
+  PVD_STM_IRQn = 1 +
+ }
 Definition of IRQn numbers. More...
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t NVIC_GetPriorityGrouping (void)
 Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000].
 
void NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable an external interrupt.
 
void NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable an external interrupt.
 
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get the pending interrupt.
 
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set an interrupt to pending.
 
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear an interrupt from pending.
 
uint32_t NVIC_GetActive (IRQn_Type IRQn)
 Get the interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000].
 
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for an interrupt.
 
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
 Get the priority of an interrupt.
 
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000].
 
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
 Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000].
 
void NVIC_SystemReset (void)
 Reset the system.
 
+

Description

+

ARM provides a template file startup_device for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a weak function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.

+

The table below describes the core exception names and their availability in various Cortex-M cores.

+ + + + + + + + + + + + + + + + + + + + + +
Core Exception Name IRQn Value M0 M0+ M3 M4 M7 SC000 SC300 Description
NonMaskableInt_IRQn -14
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Non Maskable Interrupt
HardFault_IRQn -13
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Hard Fault Interrupt
MemoryManagement_IRQn -12    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		Memory Management Interrupt
BusFault_IRQn -11    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		Bus Fault Interrupt
UsageFault_IRQn -10    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		Usage Fault Interrupt
SVCall_IRQn -5
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		SV Call Interrupt
DebugMonitor_IRQn -4    
+available +
+
+available +
+
+available +
+ 		 
+available +
+ 		Debug Monitor Interrupt
PendSV_IRQn -2
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		Pend SV Interrupt
SysTick_IRQn -1
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+
+available +
+ 		System Tick Interrupt
+

+For Cortex-M0, Cortex-M0+, or SC000

+

The following exception names are fixed and define the start of the vector table for Cortex-M0, Cortex-M0+, or SC000:

+
__Vectors DCD __initial_sp ; Top of Stack
+
DCD Reset_Handler ; Reset Handler
+
DCD NMI_Handler ; NMI Handler
+
DCD HardFault_Handler ; Hard Fault Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD SVC_Handler ; SVCall Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD PendSV_Handler ; PendSV Handler
+
DCD SysTick_Handler ; SysTick Handler
+

+For Cortex-M3

+

The following exception names are fixed and define the start of the vector table for a Cortex-M3:

+
__Vectors DCD __initial_sp ; Top of Stack
+
DCD Reset_Handler ; Reset Handler
+
DCD NMI_Handler ; NMI Handler
+
DCD HardFault_Handler ; Hard Fault Handler
+
DCD MemManage_Handler ; MPU Fault Handler
+
DCD BusFault_Handler ; Bus Fault Handler
+
DCD UsageFault_Handler ; Usage Fault Handler
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD 0 ; Reserved
+
DCD SVC_Handler ; SVCall Handler
+
DCD DebugMon_Handler ; Debug Monitor Handler
+
DCD 0 ; Reserved
+
DCD PendSV_Handler ; PendSV Handler
+
DCD SysTick_Handler ; SysTick Handler
+

+Example

+

The following is an examples for device-specific interrupts:

+
; External Interrupts
+
DCD WWDG_IRQHandler ; Window Watchdog
+
DCD PVD_IRQHandler ; PVD through EXTI Line detect
+
DCD TAMPER_IRQHandler ; Tamper
+

Device-specific interrupts must have a dummy function that can be overwritten in user code. Below is an example for this dummy function.

+
Default_Handler PROC
+
EXPORT WWDG_IRQHandler [WEAK]
+
EXPORT PVD_IRQHandler [WEAK]
+
EXPORT TAMPER_IRQHandler [WEAK]
+
:
+
:
+
WWDG_IRQHandler
+
PVD_IRQHandler
+
TAMPER_IRQHandler
+
:
+
:
+
B .
+
ENDP
+

The user application may simply define an interrupt handler function by using the handler name as shown below.

+
void WWDG_IRQHandler(void)
+
{
+
...
+
}
+

+Code Example 1

+

The code below shows the usage of the CMSIS NVIC functions NVIC_SetPriorityGrouping(), NVIC_GetPriorityGrouping(), NVIC_SetPriority(), NVIC_GetPriority(), NVIC_EncodePriority(), and NVIC_DecodePriority() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t priorityGroup; /* Variables to store priority group and priority */
+
uint32_t priority;
+
uint32_t preemptPriority;
+
uint32_t subPriority;
+
+
+
int main (void) {
+
+
NVIC_SetPriorityGrouping(5); /* Set priority group to 5:
+
Bit[7..6] preempt priority Bits,
+
Bit[5..3] subpriority Bits
+
(valid for five priority bits) */
+
+
priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping */
+
+
priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority
+
Note: priority depends on the used priority grouping */
+
+
NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority */
+
+
priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again */
+
+
NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
+
+
while(1);
+
}
+

+Code Example 2

+

The code below shows the usage of the CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t active; /* Variable to store interrupt active state */
+
+
+
void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */
+
+
if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occured */
+
LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occured */
+
}
+
active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0 */
+
}
+
+
+
int main (void) {
+
/* Set match channel register MR0 to 1 millisecond */
+
LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms? */
+
+
LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0 */
+
+
NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0 */
+
+
LPC_TIM0->TCR = (1 << 0); /* Enable timer 0 */
+
+
while(1);
+
}
+

Enumeration Type Documentation

+ +
+
+ + + + +
enum IRQn_Type
+
+

The core exception enumeration names for IRQn values are defined in the file device.h.

+
Negative IRQn values represent processor core exceptions (internal interrupts).
+Positive IRQn values represent device-specific exceptions (external interrupts). 
+The first device-specific interrupt has the IRQn value 0.
+

The table below describes the core exception names and their availability in various Cortex-M cores.

+
Enumerator:
+ + + + + + + + + + + +
NonMaskableInt_IRQn  +

Exception 2: Non Maskable Interrupt.

+
HardFault_IRQn  +

Exception 3: Hard Fault Interrupt.

+
MemoryManagement_IRQn  +

Exception 4: Memory Management Interrupt [not on Cortex-M0 variants].

+
BusFault_IRQn  +

Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants].

+
UsageFault_IRQn  +

Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants].

+
SVCall_IRQn  +

Exception 11: SV Call Interrupt.

+
DebugMonitor_IRQn  +

Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants].

+
PendSV_IRQn  +

Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].

+
SysTick_IRQn  +

Exception 15: System Tick Interrupt.

+
WWDG_STM_IRQn  +

Device Interrupt 0: Window WatchDog Interrupt.

+
PVD_STM_IRQn  +

Device Interrupt 1: PVD through EXTI Line detection Interrupt.

+
+
+
+ +
+
+

Function Documentation

+ +
+
+ + + + + + + + +
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)
+
+

This function removes the pending state of the specified interrupt IRQn. IRQn cannot be a negative number.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
  • An interrupt can have the status pending though it is not active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
void NVIC_DecodePriority (uint32_t Priority,
uint32_t PriorityGroup,
uint32_t * pPreemptPriority,
uint32_t * pSubPriority 
)
+
+

This function decodes an interrupt priority value with the priority group PriorityGroup to preemptive priority value pPreemptPriority and subpriority value pSubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + + +
[in]PriorityPriority
[in]PriorityGroupPriority group
[out]*pPreemptPriorityPreemptive priority value (starting from 0)
[out]*pSubPrioritySubpriority value (starting from 0)
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_DisableIRQ (IRQn_Type IRQn)
+
+

This function disables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnNumber of the external interrupt to disable
+
+
+
Remarks
    +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_EnableIRQ (IRQn_Type IRQn)
+
+

This function enables the specified device-specific interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
    • +
  • The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
    + ICTR[4:0]
      +
    • =0 - 32 interrupts supported
      • +
    • =1 - 64 interrupts supported
      • +
    • ...
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
uint32_t PreemptPriority,
uint32_t SubPriority 
)
+
+

This function encodes the priority for an interrupt with the priority group PriorityGroup, preemptive priority value PreemptPriority, and subpriority value SubPriority. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

+
Parameters
+ + + + +
[in]PriorityGroupPriority group
[in]PreemptPriorityPreemptive priority value (starting from 0)
[in]SubPrioritySubpriority value (starting from 0)
+
+
+
Returns
Encoded priority for the interrupt
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetActive (IRQn_Type IRQn)
+
+

This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • =0 Interrupt is not active
    • +
  • =1 Interrupt is active, or active and pending
    • +
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.
    • +
  • When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)
+
+

This function returns the pending status of the specified interrupt IRQn.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
    +
  • =0 Interrupt is not pending
    • +
  • =1 Interrupt is pending
    • +
+
+
Remarks
    +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriority (IRQn_Type IRQn)
+
+

This function reads the priority for the specified interrupt IRQn. IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt.

+

The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Returns
Interrupt priority
+
Remarks
    +
  • Each external interrupt has an associated priority-level register.
    • +
  • Unimplemented bits are read as zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t NVIC_GetPriorityGrouping (void )
+
+

This functuion returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).

+
Returns
Priority grouping field
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SetPendingIRQ (IRQn_Type IRQn)
+
+

This function sets the pending bit for the specified interrupt IRQn. IRQn cannot be a negative value.

+
Parameters
+ + +
[in]IRQnInterrupt number
+
+
+
Remarks
    +
  • The registers that control the status of interrupts are called SETPEND and CLRPEND.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void NVIC_SetPriority (IRQn_Type IRQn,
uint32_t priority 
)
+
+

Sets the priority for the interrupt specified by IRQn.IRQn can can specify any device-specific (external) interrupt, or core (internal) interrupt. The priority specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.

+

The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.

+
Parameters
+ + + +
[in]IRQnInterrupt Number
[in]priorityPriority to set
+
+
+
Remarks
    +
  • The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write 0xFF to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is 0xE0.
    • +
  • Writes to unimplemented bits are ignored.
    • +
  • For Cortex-M0:
      +
    • Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.
      • +
    • Supports 0 to 192 priority levels.
      • +
    • Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.
      • +
    +
    • +
  • For Cortex-M3, Cortex-M4, and Cortex-M7:
      +
    • Dynamic switching of interrupt priority levels is supported.
      • +
    • Supports 0 to 255 priority levels.
      • +
    • Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.
      • +
    +
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
+
+

The function sets the priority grouping PriorityGroup using the required unlock sequence. PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

+
Parameters
+ + +
[in]PriorityGroupPriority group
+
+
+
Remarks
    +
  • not for Cortex-M0, Cortex-M0+, or SC000.
    • +
  • By default, priority group setting is zero.
    • +
+
+
See Also
+
+ +
+
+ +
+
+ + + + + + + + +
void NVIC_SystemReset (void )
+
+

This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.

+
Remarks
    +
  • In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.
    • +
+
+
See Also
+
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group___n_v_i_c__gr.js b/Documentation/Core/html/group___n_v_i_c__gr.js new file mode 100644 index 0000000..e7db41e --- /dev/null +++ b/Documentation/Core/html/group___n_v_i_c__gr.js @@ -0,0 +1,29 @@ +var group___n_v_i_c__gr = +[ + [ "IRQn_Type", "group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8", [ + [ "NonMaskableInt_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30", null ], + [ "HardFault_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85", null ], + [ "MemoryManagement_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa", null ], + [ "BusFault_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af", null ], + [ "UsageFault_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf", null ], + [ "SVCall_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237", null ], + [ "DebugMonitor_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c", null ], + [ "PendSV_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2", null ], + [ "SysTick_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7", null ], + [ "WWDG_STM_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2", null ], + [ "PVD_STM_IRQn", "group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86", null ] + ] ], + [ "NVIC_ClearPendingIRQ", "group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a", null ], + [ "NVIC_DecodePriority", "group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377", null ], + [ "NVIC_DisableIRQ", "group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c", null ], + [ "NVIC_EnableIRQ", "group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f", null ], + [ "NVIC_EncodePriority", "group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5", null ], + [ "NVIC_GetActive", "group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892", null ], + [ "NVIC_GetPendingIRQ", "group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662", null ], + [ "NVIC_GetPriority", "group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395", null ], + [ "NVIC_GetPriorityGrouping", "group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78", null ], + [ "NVIC_SetPendingIRQ", "group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2", null ], + [ "NVIC_SetPriority", "group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798", null ], + [ "NVIC_SetPriorityGrouping", "group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354", null ], + [ "NVIC_SystemReset", "group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group___sys_tick__gr.html b/Documentation/Core/html/group___sys_tick__gr.html new file mode 100644 index 0000000..6966d61 --- /dev/null +++ b/Documentation/Core/html/group___sys_tick__gr.html @@ -0,0 +1,197 @@ + + + + + +Systick Timer (SYSTICK) +CMSIS-CORE: Systick Timer (SYSTICK) + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Systick Timer (SYSTICK)
+
+
+ +

Initialize and start the SysTick timer. +More...

+ + + + + +

+Functions

uint32_t SysTick_Config (uint32_t ticks)
 System Tick Timer Configuration.
 
+

Description

+
The System Tick Time (SysTick) generates interrupt requests on a regular basis.
+This allows an OS to carry out context switching to support multiple tasking. For applications
+that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an 
+interrupt source for tasks that need to be executed regularly.
+

+Code Example

+

The code below shows the usage of the function SysTick_Config() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t msTicks = 0; /* Variable to store millisecond ticks */
+
+
+
void SysTick_Handler(void) { /* SysTick interrupt Handler.
+
msTicks++; See startup file startup_LPC17xx.s for SysTick vector */
+
}
+
+
+
int main (void) {
+
uint32_t returnCode;
+
+
returnCode = SysTick_Config(SystemCoreClock / 1000); /* Configure SysTick to generate an interrupt every millisecond */
+
+
if (returnCode != 0) { /* Check return code for errors */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
uint32_t SysTick_Config (uint32_t ticks)
+
+

Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.

+
Parameters
+ + +
[in]ticksNumber of ticks between two interrupts
+
+
+
Returns
0 - success
+
+1 - failure
+
Note
When #define __Vendor_SysTickConfig is set to 1, the standard function SysTick_Config is excluded. In this case, the file device.h must contain a vendor specific implementation of this function.
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group___sys_tick__gr.js b/Documentation/Core/html/group___sys_tick__gr.js new file mode 100644 index 0000000..99c5304 --- /dev/null +++ b/Documentation/Core/html/group___sys_tick__gr.js @@ -0,0 +1,4 @@ +var group___sys_tick__gr = +[ + [ "SysTick_Config", "group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group__cache__functions__m7.html b/Documentation/Core/html/group__cache__functions__m7.html new file mode 100644 index 0000000..7ba5f9a --- /dev/null +++ b/Documentation/Core/html/group__cache__functions__m7.html @@ -0,0 +1,152 @@ + + + + + +Cache Functions (only Cortex-M7) +CMSIS-CORE: Cache Functions (only Cortex-M7) + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Content
+
+
Cache Functions (only Cortex-M7)
+
+
+ +

Functions for Instruction and Data Cache. +More...

+ + + + + + + + +

+Content

 I-Cache Functions
 Functions for the instruction cache.
 
 D-Cache Functions
 Functions for the data cache.
 
+

Description

+

Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of [0;4;8;16;32;64]KB. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.

+

All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.

+
Note
After reset, you must invalidate each cache before enabling it.
+

The functions are grouped for:

+ +
+
+ + + + diff --git a/Documentation/Core/html/group__cache__functions__m7.js b/Documentation/Core/html/group__cache__functions__m7.js new file mode 100644 index 0000000..4db2220 --- /dev/null +++ b/Documentation/Core/html/group__cache__functions__m7.js @@ -0,0 +1,5 @@ +var group__cache__functions__m7 = +[ + [ "I-Cache Functions", "group___icache__functions__m7.html", "group___icache__functions__m7" ], + [ "D-Cache Functions", "group___dcache__functions__m7.html", "group___dcache__functions__m7" ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group__fpu__functions__m7.html b/Documentation/Core/html/group__fpu__functions__m7.html new file mode 100644 index 0000000..a30c139 --- /dev/null +++ b/Documentation/Core/html/group__fpu__functions__m7.html @@ -0,0 +1,166 @@ + + + + + +FPU Functions (only Cortex-M7) +CMSIS-CORE: FPU Functions (only Cortex-M7) + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
FPU Functions (only Cortex-M7)
+
+
+ +

Functions that relate to the Floating-Point Arithmetic Unit. +More...

+ + + + + +

+Functions

__STATIC_INLINE uint32_t SCB_GetFPUType (void)
 Get the FPU type.
 
+

Description

+

The Cortex-M7 processor includes optional floating-point arithmetic functionality, with support for single and double-precision arithmetic. The Cortex-M7 processor with FPU is an implementation of the single-precision and double-precision variant of the ARMv7-M Architecture with Floating-Point Extension (FPv5).

+

Function Documentation

+ +
+
+ + + + + + + + +
__STATIC_INLINE uint32_t SCB_GetFPUType (void )
+
+
Returns
    +
  • 0: No FPU
    • +
  • 1: Single precision FPU
    • +
  • 2: Double + Single precision FPU
    • +
+
+

The function returns the implemented FPU type.

+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group__fpu__functions__m7.js b/Documentation/Core/html/group__fpu__functions__m7.js new file mode 100644 index 0000000..d77dd8b --- /dev/null +++ b/Documentation/Core/html/group__fpu__functions__m7.js @@ -0,0 +1,4 @@ +var group__fpu__functions__m7 = +[ + [ "SCB_GetFPUType", "group__fpu__functions__m7.html#ga6bcad99ce80a0e7e4ddc6f2379081756", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group__intrinsic___c_p_u__gr.html b/Documentation/Core/html/group__intrinsic___c_p_u__gr.html new file mode 100644 index 0000000..85ecf96 --- /dev/null +++ b/Documentation/Core/html/group__intrinsic___c_p_u__gr.html @@ -0,0 +1,1013 @@ + + + + + +Intrinsic Functions for CPU Instructions +CMSIS-CORE: Intrinsic Functions for CPU Instructions + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Intrinsic Functions for CPU Instructions
+
+
+ +

Functions that generate specific Cortex-M CPU Instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

void __NOP (void)
 No Operation.
 
void __WFI (void)
 Wait For Interrupt.
 
void __WFE (void)
 Wait For Event.
 
void __SEV (void)
 Send Event.
 
void __BKPT (uint8_t value)
 Set Breakpoint.
 
void __ISB (void)
 Instruction Synchronization Barrier.
 
void __DSB (void)
 Data Synchronization Barrier.
 
void __DMB (void)
 Data Memory Barrier.
 
uint32_t __REV (uint32_t value)
 Reverse byte order (32 bit)
 
uint32_t __REV16 (uint32_t value)
 Reverse byte order (16 bit)
 
int32_t __REVSH (int32_t value)
 Reverse byte order in signed short value.
 
uint32_t __RBIT (uint32_t value)
 Reverse bit order of value [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __ROR (uint32_t value, uint32_t shift)
 Rotate a value right by a number of bits.
 
uint8_t __LDREXB (volatile uint8_t *addr)
 LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint16_t __LDREXH (volatile uint16_t *addr)
 LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __LDREXW (volatile uint32_t *addr)
 LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __STREXB (uint8_t value, volatile uint8_t *addr)
 STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __STREXH (uint16_t value, volatile uint16_t *addr)
 STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __STREXW (uint32_t value, volatile uint32_t *addr)
 STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000].
 
void __CLREX (void)
 Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __SSAT (unint32_t value, uint32_t sat)
 Signed Saturate [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __USAT (uint32_t value, uint32_t sat)
 Unsigned Saturate [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint8_t __CLZ (uint32_t value)
 Count leading zeros [not for Cortex-M0, Cortex-M0+, or SC000].
 
uint32_t __RRX (uint32_t value)
 Rotate Right with Extend (32 bit)
 
uint8_t __LDRBT (uint8_t ptr)
 LDRT Unprivileged (8 bit)
 
uint16_t __LDRHT (uint16_t ptr)
 LDRT Unprivileged (16 bit)
 
uint32_t __LDRT (uint32_t ptr)
 LDRT Unprivileged (32 bit)
 
void __STRBT (uint8_t value, uint8_t ptr)
 STRT Unprivileged (8 bit)
 
void __STRHT (uint16_t value, uint16_t ptr)
 STRT Unprivileged (16 bit)
 
void __STRT (uint32_t value, uint32_t ptr)
 STRT Unprivileged (32 bit)
 
+

Description

+

The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. Refer to the Cortex-M Reference Manuals for detailed information about these Cortex-M instructions.

+
Note
When using the ARM Compiler Toolchain the following Intrinsic Functions for CPU Instructions are implemented using the Embedded Assembler: __RRX, <Bruno: add more...>. The usage of the Embedded Assembler can be disabled by with define __NO_EMBEDDED_ASM. This avoids potential side effects of the Embedded Assembler. Refer to Compiler User Guide - Using the Inline and Embedded Assemblers of the ARM Compiler for more information.
+

Function Documentation

+ +
+
+ + + + + + + + +
void __BKPT (uint8_t value)
+
+

This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

+
Parameters
+ + +
[in]valueis ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.
+
+
+ +
+
+ +
+
+ + + + + + + + +
void __CLREX (void )
+
+

This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000].

+ +
+
+ +
+
+ + + + + + + + +
uint8_t __CLZ (uint32_t value)
+
+

This function counts the number of leading zeros of a data value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]valueValue to count the leading zeros
+
+
+
Returns
number of leading zeros in value
+ +
+
+ +
+
+ + + + + + + + +
void __DMB (void )
+
+

This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

+ +
+
+ +
+
+ + + + + + + + +
void __DSB (void )
+
+

This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

+ +
+
+ +
+
+ + + + + + + + +
void __ISB (void )
+
+

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

+ +
+
+ +
+
+ + + + + + + + +
uint8_t __LDRBT (uint8_t ptr)
+
+

This function executed an Unprivileged LDRT command for 8 bit value.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint8_t at (*ptr)
+ +
+
+ +
+
+ + + + + + + + +
uint8_t __LDREXB (volatile uint8_t * addr)
+
+

This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]*addrPointer to data
+
+
+
Returns
value of type uint8_t at (*addr)
+ +
+
+ +
+
+ + + + + + + + +
uint16_t __LDREXH (volatile uint16_t * addr)
+
+

This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]*addrPointer to data
+
+
+
Returns
value of type uint16_t at (*addr)
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __LDREXW (volatile uint32_t * addr)
+
+

This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]*addrPointer to data
+
+
+
Returns
value of type uint32_t at (*addr)
+ +
+
+ +
+
+ + + + + + + + +
uint16_t __LDRHT (uint16_t ptr)
+
+

This function executed an Unprivileged LDRT command for 16 bit values.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint16_t at (*ptr)
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __LDRT (uint32_t ptr)
+
+

This function executed an Unprivileged LDRT command for 32 bit values.

+
Parameters
+ + +
[in]ptrPointer to data
+
+
+
Returns
value of type uint32_t at (*ptr)
+ +
+
+ +
+
+ + + + + + + + +
void __NOP (void )
+
+

This function does nothing. This instruction can be used for code alignment purposes.

+ +
+
+ +
+
+ + + + + + + + +
uint32_t __RBIT (uint32_t value)
+
+

This function reverses the bit order of the given value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __REV (uint32_t value)
+
+

This function reverses the byte order in integer value.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __REV16 (uint32_t value)
+
+

This function reverses the byte order in two unsigned short values.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + +
int32_t __REVSH (int32_t value)
+
+

This function reverses the byte order in a signed short value with sign extension to integer.

+
Parameters
+ + +
[in]valueValue to reverse
+
+
+
Returns
Reversed value
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __ROR (uint32_t value,
uint32_t shift 
)
+
+

This function rotates a value right by a specified number of bits.

+
Parameters
+ + + +
[in]valueValue to be shifted right
[in]shiftNumber of bits in the range [1..31]
+
+
+
Returns
Rotated value
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __RRX (uint32_t value)
+
+

This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.

+
Parameters
+ + +
[in]valueValue to rotate
+
+
+
Returns
Rotated value
+ +
+
+ +
+
+ + + + + + + + +
void __SEV (void )
+
+

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAT (unint32_t value,
uint32_t sat 
)
+
+

This function saturates a signed value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to [1..32]
+
+
+
Returns
Saturated value
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void __STRBT (uint8_t value,
uint8_t ptr 
)
+
+

This function executed an Unprivileged STRT command for 8 bit values.

+
Parameters
+ + + +
[in]valueValue to store
[in]ptrPointer to location
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __STREXB (uint8_t value,
volatile uint8_t * addr 
)
+
+

This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + + +
[in]valueValue to store
[in]*addrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __STREXH (uint16_t value,
volatile uint16_t * addr 
)
+
+

This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + + +
[in]valueValue to store
[in]*addrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __STREXW (uint32_t value,
volatile uint32_t * addr 
)
+
+

This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + + +
[in]valueValue to store
[in]*addrPointer to location
+
+
+
Returns
0 Function succeeded
+
+1 Function failed
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void __STRHT (uint16_t value,
uint16_t ptr 
)
+
+

This function executed an Unprivileged STRT command for 16 bit values.

+
Parameters
+ + + +
[in]valueValue to store
[in]ptrPointer to location
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
void __STRT (uint32_t value,
uint32_t ptr 
)
+
+

This function executed an Unprivileged STRT command for 32 bit values.

+
Parameters
+ + + +
[in]valueValue to store
[in]ptrPointer to location
+
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAT (uint32_t value,
uint32_t sat 
)
+
+

This function saturates an unsigned value [not for Cortex-M0, Cortex-M0+, or SC000].

+
Parameters
+ + + +
[in]valueValue to be saturated
[in]satBit position to saturate to [0..31]
+
+
+
Returns
Saturated value
+ +
+
+ +
+
+ + + + + + + + +
void __WFE (void )
+
+

Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs:

+
    +
  • If the event register is 0, then WFE suspends execution until one of the following events occurs:
      +
    • An exception, unless masked by the exception mask registers or the current priority level.
      • +
    • An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
      • +
    • A Debug Entry request, if Debug is enabled.
      • +
    • An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.
      • +
    +
    • +
+
    +
  • If the event register is 1, then WFE clears it to 0 and returns immediately.
    • +
+ +
+
+ +
+
+ + + + + + + + +
void __WFI (void )
+
+

WFI is a hint instruction that suspends execution until one of the following events occurs:

+
    +
  • A non-masked interrupt occurs and is taken.
    • +
  • An interrupt masked by PRIMASK becomes pending.
    • +
  • A Debug Entry request.
    • +
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group__intrinsic___c_p_u__gr.js b/Documentation/Core/html/group__intrinsic___c_p_u__gr.js new file mode 100644 index 0000000..1621c07 --- /dev/null +++ b/Documentation/Core/html/group__intrinsic___c_p_u__gr.js @@ -0,0 +1,33 @@ +var group__intrinsic___c_p_u__gr = +[ + [ "__BKPT", "group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7", null ], + [ "__CLREX", "group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412", null ], + [ "__CLZ", "group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02", null ], + [ "__DMB", "group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96", null ], + [ "__DSB", "group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199", null ], + [ "__ISB", "group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5", null ], + [ "__LDRBT", "group__intrinsic___c_p_u__gr.html#ga9464d75db32846aa8295c3c3adfacb41", null ], + [ "__LDREXB", "group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e", null ], + [ "__LDREXH", "group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15", null ], + [ "__LDREXW", "group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c", null ], + [ "__LDRHT", "group__intrinsic___c_p_u__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32", null ], + [ "__LDRT", "group__intrinsic___c_p_u__gr.html#ga616504f5da979ba8a073d428d6e8d5c7", null ], + [ "__NOP", "group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e", null ], + [ "__RBIT", "group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863", null ], + [ "__REV", "group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8", null ], + [ "__REV16", "group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26", null ], + [ "__REVSH", "group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe", null ], + [ "__ROR", "group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024", null ], + [ "__RRX", "group__intrinsic___c_p_u__gr.html#gac09134f1bf9c49db07282001afcc9380", null ], + [ "__SEV", "group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7", null ], + [ "__SSAT", "group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1", null ], + [ "__STRBT", "group__intrinsic___c_p_u__gr.html#gad41aa59c92c0a165b7f98428d3320cd5", null ], + [ "__STREXB", "group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99", null ], + [ "__STREXH", "group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a", null ], + [ "__STREXW", "group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197", null ], + [ "__STRHT", "group__intrinsic___c_p_u__gr.html#ga2b5d93b8e461755b1072a03df3f1722e", null ], + [ "__STRT", "group__intrinsic___c_p_u__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e", null ], + [ "__USAT", "group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a", null ], + [ "__WFE", "group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563", null ], + [ "__WFI", "group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html b/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html new file mode 100644 index 0000000..f5c03c7 --- /dev/null +++ b/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.html @@ -0,0 +1,3126 @@ + + + + + +Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7] +CMSIS-CORE: Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7] + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions
+
+
Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]
+
+
+ +

Access to dedicated SIMD instructions. +More...

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Functions

uint32_t __SADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed addition.
 
uint32_t __QADD8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating addition.
 
uint32_t __SHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed addition with halved results.
 
uint32_t __UADD8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned addition.
 
uint32_t __UQADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating addition.
 
uint32_t __UHADD8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned addition with halved results.
 
uint32_t __SSUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit signed subtraction.
 
uint32_t __QSUB8 (uint32_t val1, uint32_t val2)
 Q setting quad 8-bit saturating subtract.
 
uint32_t __SHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit signed subtraction with halved results.
 
uint32_t __USUB8 (uint32_t val1, uint32_t val2)
 GE setting quad 8-bit unsigned subtract.
 
uint32_t __UQSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned saturating subtraction.
 
uint32_t __UHSUB8 (uint32_t val1, uint32_t val2)
 Quad 8-bit unsigned subtraction with halved results.
 
uint32_t __SADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed addition.
 
uint32_t __QADD16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating addition.
 
uint32_t __SHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition with halved results.
 
uint32_t __UADD16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition.
 
uint32_t __UQADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition.
 
uint32_t __UHADD16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition with halved results.
 
uint32_t __SSUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction.
 
uint32_t __QSUB16 (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit saturating subtract.
 
uint32_t __SHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction with halved results.
 
uint32_t __USUB16 (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract.
 
uint32_t __UQSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction.
 
uint32_t __UHSUB16 (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction with halved results.
 
uint32_t __SASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit addition and subtraction with exchange.
 
uint32_t __QASX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit add and subtract with exchange.
 
uint32_t __SHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed addition and subtraction with halved results.
 
uint32_t __UASX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned addition and subtraction with exchange.
 
uint32_t __UQASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating addition and subtraction with exchange.
 
uint32_t __UHASX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned addition and subtraction with halved results and exchange.
 
uint32_t __SSAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit signed subtraction and addition with exchange.
 
uint32_t __QSAX (uint32_t val1, uint32_t val2)
 Q setting dual 16-bit subtract and add with exchange.
 
uint32_t __SHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed subtraction and addition with halved results.
 
uint32_t __USAX (uint32_t val1, uint32_t val2)
 GE setting dual 16-bit unsigned subtract and add with exchange.
 
uint32_t __UQSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned saturating subtraction and addition with exchange.
 
uint32_t __UHSAX (uint32_t val1, uint32_t val2)
 Dual 16-bit unsigned subtraction and addition with halved results and exchange.
 
uint32_t __USAD8 (uint32_t val1, uint32_t val2)
 Unsigned sum of quad 8-bit unsigned absolute difference.
 
uint32_t __USADA8 (uint32_t val1, uint32_t val2, uint32_t val3)
 Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
 
uint32_t __SSAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit saturate.
 
uint32_t __USAT16 (uint32_t val1, const uint32_t val2)
 Q setting dual 16-bit unsigned saturate.
 
uint32_t __UXTB16 (uint32_t val)
 Dual extract 8-bits and zero-extend to 16-bits.
 
uint32_t __UXTAB16 (uint32_t val1, uint32_t val2)
 Extracted 16-bit to 32-bit unsigned addition.
 
uint32_t __SXTB16 (uint32_t val)
 Dual extract 8-bits and sign extend each to 16-bits.
 
uint32_t __SXTAB16 (uint32_t val1, uint32_t val2)
 Dual extracted 8-bit to 16-bit signed addition.
 
uint32_t __SMUAD (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply.
 
uint32_t __SMUADX (uint32_t val1, uint32_t val2)
 Q setting sum of dual 16-bit signed multiply with exchange.
 
uint32_t __SMMLA (int32_t val1, int32_t val2, int32_t val3)
 32-bit signed multiply with 32-bit truncated accumulator.
 
uint32_t __SMLAD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with single 32-bit accumulator.
 
uint32_t __SMLADX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator.
 
uint64_t __SMLALD (uint32_t val1, uint32_t val2, uint64_t val3)
 Dual 16-bit signed multiply with single 64-bit accumulator.
 
unsigned long long __SMLALDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Dual 16-bit signed multiply with exchange with single 64-bit accumulator.
 
uint32_t __SMUSD (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply returning difference.
 
uint32_t __SMUSDX (uint32_t val1, uint32_t val2)
 Dual 16-bit signed multiply with exchange returning difference.
 
uint32_t __SMLSD (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply subtract with 32-bit accumulate.
 
uint32_t __SMLSDX (uint32_t val1, uint32_t val2, uint32_t val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate.
 
uint64_t __SMLSLD (uint32_t val1, uint32_t val2, uint64_t val3)
 Q setting dual 16-bit signed multiply subtract with 64-bit accumulate.
 
unsigned long long __SMLSLDX (uint32_t val1, uint32_t val2, unsigned long long val3)
 Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate.
 
uint32_t __SEL (uint32_t val1, uint32_t val2)
 Select bytes based on GE bits.
 
uint32_t __QADD (uint32_t val1, uint32_t val2)
 Q setting saturating add.
 
uint32_t __QSUB (uint32_t val1, uint32_t val2)
 Q setting saturating subtract.
 
uint32_t __PKHBT (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3.
 
uint32_t __PKHTB (uint32_t val1, uint32_t val2, uint32_t val3)
 Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3.
 
+

Description

+

Single Instruction Multiple Data (SIMD) extensions are provided only for Cortex-M4 and Cortex-M7 cores to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.

+

SIMD Features:

+
    +
  • Simultaneous computation of 2x16-bit or 4x8-bit operands
    • +
  • Fractional arithmetic
    • +
  • User definable saturation modes (arbitrary word-width)
    • +
  • Dual 16x16 multiply-add/subtract 32x32 fractional MAC
    • +
  • Simultaneous 8/16-bit select operations
    • +
  • Performance up to 3.2 GOPS at 800MHz
    • +
  • Performance is achieved with a "near zero" increase in power consumption on a typical implementation
    • +
+

Examples:

+

Addition: Add two values using SIMD function

+
uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+
{
+
return __SADD16(val1, val2);
+
}
+

Subtraction: Subtract two values using SIMD function

+
uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+
{
+
return __SSUB16(val1, val2);
+
}
+

Multiplication: Performing a multiplication using SIMD function

+
uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+
{
+
return __SMUAD(val1, val2);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __PKHBT (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters
+ + + + +
val1first 16-bit operands
val2second 16-bit operands
val3value for left-shifting val2. Value range [0..31].
+
+
+
Returns
the combination of halfwords.
+
Operation:
res[15:0] = val1[15:0]
+
res[31:16] = val2[31:16]<<val3
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __PKHTB (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.

+
Parameters
+ + + + +
val1second 16-bit operands
val2first 16-bit operands
val3value for right-shifting val2. Value range [1..32].
+
+
+
Returns
the combination of halfwords.
+
Operation:
res[15:0] = val2[15:0]>>val3
+
res[31:16] = val1[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to obtain the saturating add of two integers.
+ The Q bit is set if the operation saturates.

+
Parameters
+ + + +
val1first summand of the saturating add operation.
val2second summand of the saturating add operation.
+
+
+
Returns
the saturating addition of val1 and val2.
+
Operation:
res[31:0] = SAT(val1 + SAT(val2))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the saturated addition of the low halfwords, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfwords, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the saturated addition of the first byte of each operand in the first byte of the return value.
    • +
  • the saturated addition of the second byte of each operand in the second byte of the return value.
    • +
  • the saturated addition of the third byte of each operand in the third byte of the return value.
    • +
  • the saturated addition of the fourth byte of each operand in the fourth byte of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -27 <= x <= 27 - 1.
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value.
    • +
  • the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to obtain the saturating subtraction of two integers.
+ The Q bit is set if the operation saturates.

+
Parameters
+ + + +
val1minuend of the saturating subtraction operation.
val2subtrahend of the saturating subtraction operation.
+
+
+
Returns
the saturating subtraction of val1 and val2.
+
Operation:
res[31:0] = SAT(val1 - SAT(val2))
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -215 <= x <= 215 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
    • +
  • the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • +
+
+
The returned results are saturated to the 16-bit signed integer range -215 <= x <= 215 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __QSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -27 <= x <= 27 - 1.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
The returned results are saturated to the 8-bit signed integer range -27 <= x <= 27 - 1.
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed integer additions.
+ The GE bits in the APSR are set according to the results of the additions.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the addition of the low halfwords in the low halfword of the return value.
    • +
  • the addition of the high halfwords in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the addition of the second bytes of each operand, in the second byte of the return value.
    • +
  • the addition of the third bytes of each operand, in the third byte of the return value.
    • +
  • the addition of the fourth bytes of each operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[7:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SASX (uint32_t val1,
uint32_t val2 
)
+
+

This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APRS are set according to the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SEL (uint32_t val1,
uint32_t val2 
)
+
+

This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.

+
Parameters
+ + + +
val1four selectable 8-bit values.
val2four selectable 8-bit values.
+
+
+
Returns
The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria:
    +
  • if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
    • +
  • if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
    • +
  • if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
    • +
  • if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]
    • +
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two signed 16-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the halved addition of the low halfwords, in the low halfword of the return value.
    • +
  • the halved addition of the high halfwords, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1
+
res[31:16] = val1[31:16] + val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four signed 8-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1
+
res[15:8] = val1[15:8] + val2[15:8] >> 1
+
res[23:16] = val1[23:16] + val2[23:16] >> 1
+
res[31:24] = val1[31:24] + val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.

+
Parameters
+ + + +
val1first 16-bit operands.
val2second 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.

+
Parameters
+ + + +
val1first 16-bit operands.
val2second 16-bit operands.
+
+
+
Returns
    +
  • the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two signed 16-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result.
    • +
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1
+
res[31:16] = val1[31:16] - val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SHSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four signed 8-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1
+
res[15:8] = val1[15:8] - val2[15:8] >> 1
+
res[23:16] = val1[23:16] - val2[23:16] >> 1
+
res[31:24] = val1[31:24] - val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLAD (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value, as a 32-bit integer.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 + p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLADX (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 + p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint64_t __SMLALD (uint32_t val1,
uint32_t val2,
uint64_t val3 
)
+
+

This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
sum = p1 + p2 + val3[63:32][31:0]
+
res[63:32] = sum[63:32]
+
res[31:0] = sum[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
unsigned long long __SMLALDX (uint32_t val1,
uint32_t val2,
unsigned long long val3 
)
+
+

This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the product of each multiplication added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
sum = p1 + p2 + val3[63:32][31:0]
+
res[63:32] = sum[63:32]
+
res[31:0] = sum[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLSD (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.
+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 - p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMLSDX (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 - p2 + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint64_t __SMLSLD (uint32_t val1,
uint32_t val2,
uint64_t val3 
)
+
+

This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[63:0] = p1 - p2 + val3[63:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
unsigned long long __SMLSLDX (uint32_t val1,
uint32_t val2,
unsigned long long val3 
)
+
+

This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo264.

+
Parameters
+ + + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
val3accumulate value.
+
+
+
Returns
the difference of the product of each multiplication, added to the accumulate value.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[63:0] = p1 - p2 + val3[63:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __SMMLA (int32_t val1,
int32_t val2,
int32_t val3 
)
+
+

This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.
+

+
Parameters
+ + + + +
val1first operand for multiplication.
val2second operand for multiplication.
val3accumulate value.
+
+
+
Returns
the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.
+
Operation:
p = val1 * val2
+
res[31:0] = p[61:32] + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUAD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, adding the products together.
+ The Q bit is set if the addition overflows.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the sum of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 + p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUADX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.
+ The Q bit is set if the addition overflows.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 + p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUSD (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the difference of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[15:0]
+
p2 = val1[31:16] * val2[31:16]
+
res[31:0] = p1 - p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SMUSDX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.

+
Parameters
+ + + +
val1first 16-bit operands for each multiplication.
val2second 16-bit operands for each multiplication.
+
+
+
Returns
the difference of the products of the two 16-bit signed multiplications.
+
Operation:
p1 = val1[15:0] * val2[31:16]
+
p2 = val1[31:16] * val2[15:0]
+
res[31:0] = p1 - p2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAT16 (uint32_t val1,
const uint32_t val2 
)
+
+

This function enables you to saturate two signed 16-bit values to a selected signed range.
+ The Q bit is set if either operation saturates.

+
Parameters
+ + + +
val1two signed 16-bit values to be saturated.
val2bit position for saturation, an integral constant expression in the range 1 to 16.
+
+
+
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value:
    +
  • the signed saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
    • +
  • the signed saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • +
+
+
Operation:
Saturate halfwords in val1 to the signed range specified by the bit position in val2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit operands of each subtraction.
val2second two 16-bit operands of each subtraction.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If
    +
  • res is the return value, then:
    • +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit signed integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit operands of each subtraction.
val2second four 8-bit operands of each subtraction.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
the results of the operation.
+
If res is the return value, then:
    +
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __SXTAB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.

+
Parameters
+ + + +
val1values added to the zero-extended to 16-bit values.
val2two 8-bit values to be extracted and zero-extended.
+
+
+
Returns
the addition of val1 and val2, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.
+
Operation:
res[15:0] = val1[15:0] + SignExtended(val2[7:0])
+
res[31:16] = val1[31:16] + SignExtended(val2[23:16])
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __SXTB16 (uint32_t val)
+
+

This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.

+
Parameters
+ + +
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
+
+
Returns
the 8-bit values sign-extended to 16-bit values.
    +
  • sign-extended value of val[7:0] in the low halfword of the return value.
    • +
  • sign-extended value of val[23:16] in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = SignExtended(val[7:0]
+
res[31:16] = SignExtended(val[23:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit unsigned integer additions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit summands for each addition.
val2second two 16-bit summands for each addition.
+
+
+
Returns
    +
  • the addition of the low halfwords in each operand, in the low halfword of the return value.
    • +
  • the addition of the high halfwords in each operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00
    • +
  • if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit summands for each addition.
val2second four 8-bit summands for each addition.
+
+
+
Returns
    +
  • the halved addition of the first bytes from each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes from each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes from each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the halved addition of the low halfwords in each operand, in the low halfword of the return value.
    • +
  • the halved addition of the high halfwords in each operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[15:0] >> 1
+
res[31:16] = val1[31:16] + val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] + val2[7:0] >> 1
+
res[15:8] = val1[15:8] + val2[15:8] >> 1
+
res[23:16] = val1[23:16] + val2[23:16] >> 1
+
res[31:24] = val1[31:24] + val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.

+
Parameters
+ + + +
val1first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword.
val2second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.
+
+
+
Returns
    +
  • the halved subtraction of the high halfword in the second operand from the low halfword in the first operand.
    • +
  • the halved addition of the high halfword in the first operand and the low halfword in the second operand.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] + val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+
res[31:16] = (val1[31:16] - val2[15:0] ) >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0] >> 1
+
res[31:16] = val1[31:16] - val2[31:16] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UHSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0] >> 1
+
res[15:8] = val1[15:8] - val2[15:8] >> 1
+
res[23:16] = val1[23:16] - val2[23:16] >> 1
+
res[31:24] = val1[31:24] - val2[31:24] >> 1
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQADD16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit summands.
val2second two 16-bit summands.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value.
    • +
  • the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[15:0]
+
res[31:16] = val1[31:16] + val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQADD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters
+ + + +
val1first four 8-bit summands.
val2second four 8-bit summands.
+
+
+
Returns
    +
  • the halved addition of the first bytes in each operand, in the first byte of the return value.
    • +
  • the halved addition of the second bytes in each operand, in the second byte of the return value.
    • +
  • the halved addition of the third bytes in each operand, in the third byte of the return value.
    • +
  • the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.
    • +
+
+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
+
Operation:
res[7:0] = val1[7:0] + val2[7:0]
+
res[15:8] = val1[15:8] + val2[15:8]
+
res[23:16] = val1[23:16] + val2[23:16]
+
res[31:24] = val1[31:24] + val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQASX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[31:16]
+
res[31:16] = val1[31:16] + val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1.

+
Parameters
+ + + +
val1first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword.
val2second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 <= x <= 216 - 1.
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 216 - 1.

+
Parameters
+ + + +
val1first two 16-bit operands for each subtraction.
val2second two 16-bit operands for each subtraction.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
The results are saturated to the 16-bit unsigned integer range 0 < x < 216 - 1.
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UQSUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 28 - 1.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
The results are saturated to the 8-bit unsigned integer range 0 < x < 28 - 1.
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAD8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.

+
Parameters
+ + + +
val1first four 8-bit operands for the subtractions.
val2second four 8-bit operands for the subtractions.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • +
+
+
The sum is returned as a single unsigned integer.
+
Operation:
absdiff1 = val1[7:0] - val2[7:0]
+
absdiff2 = val1[15:8] - val2[15:8]
+
absdiff3 = val1[23:16] - val2[23:16]
+
absdiff4 = val1[31:24] - val2[31:24]
+
res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
uint32_t __USADA8 (uint32_t val1,
uint32_t val2,
uint32_t val3 
)
+
+

This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.

+
Parameters
+ + + + +
val1first four 8-bit operands for the subtractions.
val2second four 8-bit operands for the subtractions.
val3accumulation value.
+
+
+
Returns
the sum of the absolute differences of the following bytes, added to the accumulation value:
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.
    • +
+
+
Operation:
absdiff1 = val1[7:0] - val2[7:0]
+
absdiff2 = val1[15:8] - val2[15:8]
+
absdiff3 = val1[23:16] - val2[23:16]
+
absdiff4 = val1[31:24] - val2[31:24]
+
sum = absdiff1 + absdiff2 + absdiff3 + absdiff4
+
res[31:0] = sum[31:0] + val3[31:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAT16 (uint32_t val1,
const uint32_t val2 
)
+
+

This function enables you to saturate two signed 16-bit values to a selected unsigned range.
+ The Q bit is set if either operation saturates.

+
Parameters
+ + + +
val1two 16-bit values that are to be saturated.
val2bit position for saturation, and must be an integral constant expression in the range 0 to 15.
+
+
+
Returns
the saturation of the two signed 16-bit values, as non-negative values.
    +
  • the saturation of the low halfword in val1, saturated to the bit position specified in val2 and returned in the low halfword of the return value.
    • +
  • the saturation of the high halfword in val1, saturated to the bit position specified in val2 and returned in the high halfword of the return value.
    • +
+
+
Operation:
Saturate halfwords in val1 to the unsigned range specified by the bit position in val2
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USAX (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword.
val2second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.
+
+
+
Returns
    +
  • the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value.
    • +
  • the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] + val2[31:16]
+
res[31:16] = val1[31:16] - val2[15:0]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USUB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform two 16-bit unsigned integer subtractions.
+ The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first two 16-bit operands.
val2second two 16-bit operands.
+
+
+
Returns
    +
  • the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value.
    • +
  • the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00
    • +
  • if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00
    • +
+
+
Operation:
res[15:0] = val1[15:0] - val2[15:0]
+
res[31:16] = val1[31:16] - val2[31:16]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __USUB8 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.

+
Parameters
+ + + +
val1first four 8-bit operands.
val2second four 8-bit operands.
+
+
+
Returns
    +
  • the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value.
    • +
  • the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value.
    • +
  • the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value.
    • +
  • the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.
    • +
+
+
Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.
+
If res is the return value, then:
    +
  • if res[8:0] >= 0 then APSR.GE[0] = 1 else 0
    • +
  • if res[15:8] >= 0 then APSR.GE[1] = 1 else 0
    • +
  • if res[23:16] >= 0 then APSR.GE[2] = 1 else 0
    • +
  • if res[31:24] >= 0 then APSR.GE[3] = 1 else 0
    • +
+
+
Operation:
res[7:0] = val1[7:0] - val2[7:0]
+
res[15:8] = val1[15:8] - val2[15:8]
+
res[23:16] = val1[23:16] - val2[23:16]
+
res[31:24] = val1[31:24] - val2[31:24]
+
+ +
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
uint32_t __UXTAB16 (uint32_t val1,
uint32_t val2 
)
+
+

This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.

+
Parameters
+ + + +
val1value added to the zero-extended to 16-bit values.
val2two 8-bit values to be extracted and zero-extended.
+
+
+
Returns
the 8-bit values in val2, zero-extended to 16-bit values and added to val1.
+
Operation:
res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0]
+
res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]
+
+ +
+
+ +
+
+ + + + + + + + +
uint32_t __UXTB16 (uint32_t val)
+
+

This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.

+
Parameters
+ + +
valtwo 8-bit values in val[7:0] and val[23:16] to be sign-extended.
+
+
+
Returns
the 8-bit values zero-extended to 16-bit values.
    +
  • zero-extended value of val[7:0] in the low halfword of the return value.
    • +
  • zero-extended value of val[23:16] in the high halfword of the return value.
    • +
+
+
Operation:
res[15:0] = ZeroExtended(val[7:0] )
+
res[31:16] = ZeroExtended(val[23:16])
+
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.js b/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.js new file mode 100644 index 0000000..ef0bb50 --- /dev/null +++ b/Documentation/Core/html/group__intrinsic___s_i_m_d__gr.js @@ -0,0 +1,65 @@ +var group__intrinsic___s_i_m_d__gr = +[ + [ "__PKHBT", "group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5", null ], + [ "__PKHTB", "group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666", null ], + [ "__QADD", "group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a", null ], + [ "__QADD16", "group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b", null ], + [ "__QADD8", "group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713", null ], + [ "__QASX", "group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3", null ], + [ "__QSAX", "group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520", null ], + [ "__QSUB", "group__intrinsic___s_i_m_d__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096", null ], + [ "__QSUB16", "group__intrinsic___s_i_m_d__gr.html#gad089605c16df9823a2c8aaa37777aae5", null ], + [ "__QSUB8", "group__intrinsic___s_i_m_d__gr.html#ga753493a65493880c28baa82c151a0d61", null ], + [ "__SADD16", "group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984", null ], + [ "__SADD8", "group__intrinsic___s_i_m_d__gr.html#gac20aa0f741d0a1494d58c531e38d5785", null ], + [ "__SASX", "group__intrinsic___s_i_m_d__gr.html#ga5845084fd99c872e98cf5553d554de2a", null ], + [ "__SEL", "group__intrinsic___s_i_m_d__gr.html#gaf5448e591fe49161b6759b48aecb08fe", null ], + [ "__SHADD16", "group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e", null ], + [ "__SHADD8", "group__intrinsic___s_i_m_d__gr.html#ga524575b442ea01aec10c762bf4d85fea", null ], + [ "__SHASX", "group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5", null ], + [ "__SHSAX", "group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9", null ], + [ "__SHSUB16", "group__intrinsic___s_i_m_d__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf", null ], + [ "__SHSUB8", "group__intrinsic___s_i_m_d__gr.html#gac3ec7215b354d925a239f3b31df2b77b", null ], + [ "__SMLAD", "group__intrinsic___s_i_m_d__gr.html#gae0c86f3298532183f3a29f5bb454d354", null ], + [ "__SMLADX", "group__intrinsic___s_i_m_d__gr.html#ga9c286d330f4fb29b256335add91eec9f", null ], + [ "__SMLALD", "group__intrinsic___s_i_m_d__gr.html#gad80e9b20c1736fd798f897362273a146", null ], + [ "__SMLALDX", "group__intrinsic___s_i_m_d__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf", null ], + [ "__SMLSD", "group__intrinsic___s_i_m_d__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd", null ], + [ "__SMLSDX", "group__intrinsic___s_i_m_d__gr.html#ga5290ce5564770ad124910d2583dc0a9e", null ], + [ "__SMLSLD", "group__intrinsic___s_i_m_d__gr.html#ga5611f7314e0c8f53da377918dfbf42ee", null ], + [ "__SMLSLDX", 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+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Macros
+
+
Peripheral Access
+
+
+ +

Describes naming conventions, requirements, and optional features for accessing peripherals. +More...

+ + + + + + + + +

+Macros

#define _VAL2FLD(field, value)
 Mask and shift a bit field value for assigning to result to a peripheral register.
 
#define _FLD2VAL(field, value)
 Extract from a peripheral register value the a bit field value.
 
+

Description

+

The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The Device Header File <device.h> contains typically these definition and also includes the core specific header files.

+

Most of the definitions can be generated using the CMSIS-SVD System View Description for Peripherals. Refer to SVDConv.exe for more information.

+

Each peripheral provides a data type definition with a name that is composed of:

+
    +
  • prefix <device abbreviation>_
    • +
  • <peripheral name>
    • +
  • postfix _Type or _TypeDef to identify a type definition.
    • +
+

Example: LPC_UART_TypeDef for the device LPC and the peripheral UART.

+

The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.

+
    +
  • IO Type Qualifiers are used to specify the access to peripheral variables. + + + + + + + + + + + + + + +
    IO Type Qualifier Type Description
    __IM Struct member Defines 'read only' permissions
    __OM Struct member Defines 'write only' permissions
    __IOM Struct member Defines 'read / write' permissions
    __I Scalar variable Defines 'read only' permissions
    __O Scalar variable Defines 'write only' permissions
    __IO Scalar variable Defines 'read / write' permissions
    +
    • +
+
Note
__IM, __OM, __IOM are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used __I, __O, __IO also for struct member definitions.
+

The typedef <device abbreviation>_UART_TypeDef shown below defines the generic register layout for all UART channels in a device.

+
typedef struct
+
{
+
union {
+
__IM uint8_t RBR; /* Offset: 0x000 (R/ ) Receiver Buffer Register */
+
__OM uint8_t THR; /* Offset: 0x000 ( /W) Transmit Holding Register */
+
__IOM uint8_t DLL; /* Offset: 0x000 (R/W) Divisor Latch LSB */
+
uint32_t RESERVED0;
+
};
+
union {
+
__IOM uint8_t DLM; /* Offset: 0x004 (R/W) Divisor Latch MSB */
+
__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt Enable Register */
+
};
+
union {
+
__IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt ID Register */
+
__OM uint8_t FCR; /* Offset: 0x008 ( /W) FIFO Control Register */
+
};
+
__IOM uint8_t LCR; /* Offset: 0x00C (R/W) Line Control Register */
+
uint8_t RESERVED1[7];
+
__IM uint8_t LSR; /* Offset: 0x014 (R/ ) Line Status Register */
+
uint8_t RESERVED2[7];
+
__IOM uint8_t SCR; /* Offset: 0x01C (R/W) Scratch Pad Register */
+
uint8_t RESERVED3[3];
+
__IOM uint32_t ACR; /* Offset: 0x020 (R/W) Autobaud Control Register */
+
__IOM uint8_t ICR; /* Offset: 0x024 (R/W) IrDA Control Register */
+
uint8_t RESERVED4[3];
+
__IOM uint8_t FDR; /* Offset: 0x028 (R/W) Fractional Divider Register */
+
uint8_t RESERVED5[7];
+
__IOM uint8_t TER; /* Offset: 0x030 (R/W) Transmit Enable Register */
+
uint8_t RESERVED6[39];
+
__IM uint8_t FIFOLVL; /* Offset: 0x058 (R/ ) FIFO Level Register */
+
} LPC_UART_TypeDef;
+

To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.

+

Example: In this example LPC_UART2 and LPC_UART3 are two pointers to UARTs defined with above register structure.
+

+
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+

The registers in the various UARTs can now be referred in the user code as shown below:
+

+
val = LPC_UART2->DR // is the data register of UART1.
+
+

+Minimal Requirements

+

To access the peripheral registers and related function in a device, the files device.h and core_cm#.h define as a minimum:
+
+

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers.
    +
    + Example:
    typedef struct
    +
    {
    +
    __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) SysTick Control and Status Register */
    +
    __IOM uint32_t LOAD; /* Offset: 0x004 (R/W) SysTick Reload Value Register */
    +
    __IOM uint32_t VAL; /* Offset: 0x008 (R/W) SysTick Current Value Register */
    +
    __IM uint32_t CALIB; /* Offset: 0x00C (R/ ) SysTick Calibration Register */
    +
    } SysTick_Type;
    +
    • +
+
    +
  • Base Address for each peripheral (in case of multiple peripherals that use the same register layout typedef multiple base addresses are defined).
    +
    + Example:
    #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
    +
    • +
+
    +
  • Access Definitions for each peripheral. In case of multiple peripherals that are using the same register layout typdef, multiple access definitions exist (LPC_UART0, LPC_UART2).
    +
    + Example:
    #define SysTick ((SysTick_Type *) Systick_BASE) /* SysTick access definition */
    +
    • +
+

These definitions allow accessing peripheral registers with simple assignments.

+
    +
  • Example:
    +
    SysTick->CTRL = 0;
    +
    • +
+
+

+Optional Features

+

Optionally, the file device.h may define:

+
    +
  • Register Bit Fields and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <device abbreviation>_ and <peripheral name>_. It is recommended to use CAPITAL letters for #define constants.
    • +
+
    +
  • More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <device abbreviation>_ and <peripheral name>_.
    • +
+
+

+Register Bit Fields

+

For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.

+

Example:

+

Bit field definitions for register CPUID in SCB (System Control Block).

+
/* SCB CPUID Register Definitions */
+
#define SCB_CPUID_IMPLEMENTER_Pos 24U
+
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
+
#define SCB_CPUID_VARIANT_Pos 20U
+
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
+
#define SCB_CPUID_ARCHITECTURE_Pos 16U
+
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
+
#define SCB_CPUID_PARTNO_Pos 4U
+
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
+
#define SCB_CPUID_REVISION_Pos 0U
+
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
+

The macros _VAL2FLD(field, value) and _FLD2VAL(field, value) enable access to bit fields.

+

Macro Definition Documentation

+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _FLD2VAL( field,
 value 
)
+
+
Parameters
+ + + +
fieldname of bit field.
valuevalue of the register
+
+
+

The macro _FLD2VAL uses the #define's _Pos and _Msk of the related bit field to extract the value of a bit field from a register.

+

Example:

+
id = = _FLD2VAL(SCB_CPUID_REVISION, SCB->CPUID);
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + +
#define _VAL2FLD( field,
 value 
)
+
+
Parameters
+ + + +
fieldname of bit field.
valuevalue for the bit field.
+
+
+

The macro _VAL2FLD uses the #define's _Pos and _Msk of the related bit field to shift bit-field values for assigning to a register.

+

Example:

+
SCB->CPUID = _VAL2FLD(SCB_CPUID_REVISION, 0x3) | _VAL2FLD(SCB_CPUID_VARIANT, 0x3);
+
+
+
+
+
+ + + + diff --git a/Documentation/Core/html/group__peripheral__gr.js b/Documentation/Core/html/group__peripheral__gr.js new file mode 100644 index 0000000..39b83c7 --- /dev/null +++ b/Documentation/Core/html/group__peripheral__gr.js @@ -0,0 +1,5 @@ +var group__peripheral__gr = +[ + [ "_FLD2VAL", "group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444", null ], + [ "_VAL2FLD", "group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/group__system__init__gr.html b/Documentation/Core/html/group__system__init__gr.html new file mode 100644 index 0000000..91fd650 --- /dev/null +++ b/Documentation/Core/html/group__system__init__gr.html @@ -0,0 +1,230 @@ + + + + + +System and Clock Configuration +CMSIS-CORE: System and Clock Configuration + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+Functions | +Variables
+
+
System and Clock Configuration
+
+
+ +

Describes system_device.c file that contains functions for system and clock setup. +More...

+ + + + + + + + +

+Functions

void SystemInit (void)
 Function to Initialize the system.
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock.
 
+ + + + +

+Variables

uint32_t SystemCoreClock
 Variable to hold the system core clock value.
 
+

Description

+

ARM provides a template file system_device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

+
    +
  • A device-specific system configuration function, SystemInit().
    • +
  • A global variable that contains the system frequency, SystemCoreClock.
    • +
+

The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

+

+Code Example

+

The code below shows the usage of the variable SystemCoreClock and the functions SystemInit() and SystemCoreClockUpdate() with an LPC1700.

+
#include "LPC17xx.h"
+
+
uint32_t coreClock_1 = 0; /* Variables to store core clock values */
+
uint32_t coreClock_2 = 0;
+
+
+
int main (void) {
+
+
coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */
+
+
SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */
+
+
coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */
+
+
if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */
+
// Error Handling
+
}
+
+
while(1);
+
}
+

Function Documentation

+ +
+
+ + + + + + + + +
void SystemCoreClockUpdate (void )
+
+

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

+ +
+
+ +
+
+ + + + + + + + +
void SystemInit (void )
+
+

Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

+ +
+
+

Variable Documentation

+ +
+
+ + + + +
uint32_t SystemCoreClock
+
+

Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

+
Attention
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.
+ +
+
+
+
+ + + + diff --git a/Documentation/Core/html/group__system__init__gr.js b/Documentation/Core/html/group__system__init__gr.js new file mode 100644 index 0000000..1ed21ea --- /dev/null +++ b/Documentation/Core/html/group__system__init__gr.js @@ -0,0 +1,6 @@ +var group__system__init__gr = +[ + [ "SystemCoreClockUpdate", "group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f", null ], + [ "SystemInit", "group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2", null ], + [ "SystemCoreClock", "group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/index.html b/Documentation/Core/html/index.html new file mode 100644 index 0000000..0799a18 --- /dev/null +++ b/Documentation/Core/html/index.html @@ -0,0 +1,181 @@ + + + + + +Overview +CMSIS-CORE: Overview + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+

The following sections provide details about the CMSIS-CORE:

+ +
+

CMSIS-CORE in ARM::CMSIS Pack

+

Files relevant to CMSIS-CORE are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Include CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device ARM reference implementations of Cortex-M devices
Device\_Template_Vendor Template Files for extension by silicon vendors
+
+

+Cortex-M Reference Manuals

+

The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

+ +
+

+Tested and Verified Toolchains

+

The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

+
    +
  • ARM: MDK-ARM Version 5.16
    • +
  • GNU: GNU Tools ARM Embedded 4.9 2015.q2
    • +
  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
    • +
+
+
+
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b.preventDefault()}this._mouseDistanceMet(b)&&this._mouseDelayMet(b)&&(this._mouseStarted=this._mouseStart(this._mouseDownEvent,b)!==!1,this._mouseStarted?this._mouseDrag(b):this._mouseUp(b));return!this._mouseStarted},_mouseUp:function(b){a(document).unbind("mousemove."+this.widgetName,this._mouseMoveDelegate).unbind("mouseup."+this.widgetName,this._mouseUpDelegate),this._mouseStarted&&(this._mouseStarted=!1,b.target==this._mouseDownEvent.target&&a.data(b.target,this.widgetName+".preventClickEvent",!0),this._mouseStop(b));return!1},_mouseDistanceMet:function(a){return Math.max(Math.abs(this._mouseDownEvent.pageX-a.pageX),Math.abs(this._mouseDownEvent.pageY-a.pageY))>=this.options.distance},_mouseDelayMet:function(a){return this.mouseDelayMet},_mouseStart:function(a){},_mouseDrag:function(a){},_mouseStop:function(a){},_mouseCapture:function(a){return!0}})})(jQuery); +/* + * jQuery UI Resizable 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Resizables + * + * Depends: + * jquery.ui.core.js + * jquery.ui.mouse.js + * jquery.ui.widget.js + */ +(function(a,b){a.widget("ui.resizable",a.ui.mouse,{widgetEventPrefix:"resize",options:{alsoResize:!1,animate:!1,animateDuration:"slow",animateEasing:"swing",aspectRatio:!1,autoHide:!1,containment:!1,ghost:!1,grid:!1,handles:"e,s,se",helper:!1,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1e3},_create:function(){var b=this,c=this.options;this.element.addClass("ui-resizable"),a.extend(this,{_aspectRatio:!!c.aspectRatio,aspectRatio:c.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:c.helper||c.ghost||c.animate?c.helper||"ui-resizable-helper":null}),this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)&&(this.element.wrap(a('
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');/sw|se|ne|nw/.test(f)&&h.css({zIndex:++c.zIndex}),"se"==f&&h.addClass("ui-icon ui-icon-gripsmall-diagonal-se"),this.handles[f]=".ui-resizable-"+f,this.element.append(h)}}this._renderAxis=function(b){b=b||this.element;for(var c in this.handles){this.handles[c].constructor==String&&(this.handles[c]=a(this.handles[c],this.element).show());if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var d=a(this.handles[c],this.element),e=0;e=/sw|ne|nw|se|n|s/.test(c)?d.outerHeight():d.outerWidth();var f=["padding",/ne|nw|n/.test(c)?"Top":/se|sw|s/.test(c)?"Bottom":/^e$/.test(c)?"Right":"Left"].join("");b.css(f,e),this._proportionallyResize()}if(!a(this.handles[c]).length)continue}},this._renderAxis(this.element),this._handles=a(".ui-resizable-handle",this.element).disableSelection(),this._handles.mouseover(function(){if(!b.resizing){if(this.className)var a=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i);b.axis=a&&a[1]?a[1]:"se"}}),c.autoHide&&(this._handles.hide(),a(this.element).addClass("ui-resizable-autohide").hover(function(){c.disabled||(a(this).removeClass("ui-resizable-autohide"),b._handles.show())},function(){c.disabled||b.resizing||(a(this).addClass("ui-resizable-autohide"),b._handles.hide())})),this._mouseInit()},destroy:function(){this._mouseDestroy();var b=function(b){a(b).removeClass("ui-resizable ui-resizable-disabled ui-resizable-resizing").removeData("resizable").unbind(".resizable").find(".ui-resizable-handle").remove()};if(this.elementIsWrapper){b(this.element);var c=this.element;c.after(this.originalElement.css({position:c.css("position"),width:c.outerWidth(),height:c.outerHeight(),top:c.css("top"),left:c.css("left")})).remove()}this.originalElement.css("resize",this.originalResizeStyle),b(this.originalElement);return this},_mouseCapture:function(b){var c=!1;for(var d in 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e.alsoResize=="object"&&!e.alsoResize.parentNode?e.alsoResize.length?(e.alsoResize=e.alsoResize[0],f(e.alsoResize)):a.each(e.alsoResize,function(a){f(a)}):f(e.alsoResize)},resize:function(b,c){var d=a(this).data("resizable"),e=d.options,f=d.originalSize,g=d.originalPosition,h={height:d.size.height-f.height||0,width:d.size.width-f.width||0,top:d.position.top-g.top||0,left:d.position.left-g.left||0},i=function(b,d){a(b).each(function(){var b=a(this),e=a(this).data("resizable-alsoresize"),f={},g=d&&d.length?d:b.parents(c.originalElement[0]).length?["width","height"]:["width","height","top","left"];a.each(g,function(a,b){var c=(e[b]||0)+(h[b]||0);c&&c>=0&&(f[b]=c||null)}),b.css(f)})};typeof e.alsoResize=="object"&&!e.alsoResize.nodeType?a.each(e.alsoResize,function(a,b){i(a,b)}):i(e.alsoResize)},stop:function(b,c){a(this).removeData("resizable-alsoresize")}}),a.ui.plugin.add("resizable","animate",{stop:function(b,c){var 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a(j){j=j||location.href;return"#"+j.replace(/^[^#]*#?(.*)$/,"$1")}$.fn[c]=function(j){return j?this.bind(c,j):this.trigger(c)};$.fn[c].delay=50;g[c]=$.extend(g[c],{setup:function(){if(d){return false}$(f.start)},teardown:function(){if(d){return false}$(f.stop)}});f=(function(){var j={},p,m=a(),k=function(q){return q},l=k,o=k;j.start=function(){p||n()};j.stop=function(){p&&clearTimeout(p);p=b};function n(){var r=a(),q=o(m);if(r!==m){l(m=r,q);$(e).trigger(c)}else{if(q!==m){location.href=location.href.replace(/#.*/,"")+q}}p=setTimeout(n,$.fn[c].delay)}$.browser.msie&&!d&&(function(){var q,r;j.start=function(){if(!q){r=$.fn[c].src;r=r&&r+a();q=$(' + + +
+
+
Reference
+
+
+
Here is a list of all modules:
+
[detail level 12]
+ + + + + + + + + + + + +
oPeripheral AccessDescribes naming conventions, requirements, and optional features for accessing peripherals
oSystem and Clock ConfigurationDescribes system_device.c file that contains functions for system and clock setup
oInterrupts and Exceptions (NVIC)Explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC)
oCore Register AccessFunctions to access the Cortex-M core registers
oIntrinsic Functions for CPU InstructionsFunctions that generate specific Cortex-M CPU Instructions
oIntrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]Access to dedicated SIMD instructions
oSystick Timer (SYSTICK)Initialize and start the SysTick timer
oDebug AccessDebug Access to the Instrumented Trace Macrocell (ITM)
oFPU Functions (only Cortex-M7)Functions that relate to the Floating-Point Arithmetic Unit
\Cache Functions (only Cortex-M7)Functions for Instruction and Data Cache
 oI-Cache FunctionsFunctions for the instruction cache
 \D-Cache FunctionsFunctions for the data cache
+ + + + + + + diff --git a/Documentation/Core/html/modules.js b/Documentation/Core/html/modules.js new file mode 100644 index 0000000..16d8338 --- /dev/null +++ b/Documentation/Core/html/modules.js @@ -0,0 +1,13 @@ +var modules = +[ + [ "Peripheral Access", "group__peripheral__gr.html", "group__peripheral__gr" ], + [ "System and Clock Configuration", "group__system__init__gr.html", "group__system__init__gr" ], + [ "Interrupts and Exceptions (NVIC)", "group___n_v_i_c__gr.html", "group___n_v_i_c__gr" ], + [ "Core Register Access", "group___core___register__gr.html", "group___core___register__gr" ], + [ "Intrinsic Functions for CPU Instructions", "group__intrinsic___c_p_u__gr.html", "group__intrinsic___c_p_u__gr" ], + [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]", "group__intrinsic___s_i_m_d__gr.html", "group__intrinsic___s_i_m_d__gr" ], + [ "Systick Timer (SYSTICK)", "group___sys_tick__gr.html", "group___sys_tick__gr" ], + [ "Debug Access", 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100644 index 0000000..8001f82 --- /dev/null +++ b/Documentation/Core/html/navtree.css @@ -0,0 +1,143 @@ +#nav-tree .children_ul { + margin:0; + padding:4px; +} + +#nav-tree ul { + list-style:none outside none; + margin:0px; + padding:0px; +} + +#nav-tree li { + white-space:nowrap; + margin:0px; + padding:0px; +} + +#nav-tree .plus { + margin:0px; +} + +#nav-tree .selected { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} + +#nav-tree img { + margin:0px; + padding:0px; + border:0px; + vertical-align: middle; +} + +#nav-tree a { + text-decoration:none; + padding:0px; + margin:0px; + outline:none; +} + +#nav-tree .label { + margin:0px; + padding:0px; + font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; +} + +#nav-tree .label a { + padding:2px; +} + +#nav-tree .selected a { + text-decoration:none; + color:#fff; +} + +#nav-tree .children_ul { + margin:0px; + padding:0px; +} + +#nav-tree .item { + margin:0px; + padding:0px; +} + +#nav-tree { + padding: 0px 0px; + background-color: #FAFAFF; + font-size:14px; + overflow:auto; +} + +#doc-content { + overflow:auto; + display:block; + padding:0px; + margin:0px; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#side-nav { + padding:0 6px 0 0; + margin: 0px; + display:block; + position: absolute; + left: 0px; + width: 300px; +} + +.ui-resizable .ui-resizable-handle { + display:block; +} + +.ui-resizable-e { + background:url("ftv2splitbar.png") repeat scroll right center transparent; + cursor:e-resize; + height:100%; + right:0; + top:0; + width:6px; +} + +.ui-resizable-handle { + display:none; + font-size:0.1px; + position:absolute; + z-index:1; +} + +#nav-tree-contents { + margin: 6px 0px 0px 0px; +} + +#nav-tree { + background-image:url('nav_h.png'); + background-repeat:repeat-x; + background-color: #F9FAFC; + -webkit-overflow-scrolling : touch; /* iOS 5+ */ +} + +#nav-sync { + position:absolute; + top:5px; + right:24px; + z-index:0; +} + +#nav-sync img { + opacity:0.3; +} + +#nav-sync img:hover { + opacity:0.9; +} + +@media print +{ + #nav-tree { display: none; } + div.ui-resizable-handle { display: none; position: relative; } +} + diff --git a/Documentation/Core/html/navtree.js b/Documentation/Core/html/navtree.js new file mode 100644 index 0000000..8e46618 --- /dev/null +++ b/Documentation/Core/html/navtree.js @@ -0,0 +1,522 @@ +var NAVTREE = +[ + [ "CMSIS-CORE", "index.html", [ + [ "Overview", "index.html", null ], + [ "Revision History of CMSIS-CORE", "core_revision_history.html", null ], + [ "Using CMSIS in Embedded Applications", "_using_pg.html", "_using_pg" ], + [ "Template Files", "_templates_pg.html", "_templates_pg" ], + [ "MISRA-C:2004 Compliance Exceptions", "_c_o_r_e__m_i_s_r_a__exceptions_pg.html", null ], + [ "Register Mapping", "_reg_map_pg.html", null ], + [ "Reference", "modules.html", "modules" ], + [ "Data Structures", "annotated.html", "annotated" ], + [ "Data Fields", "functions.html", [ + [ "All", "functions.html", null ], + [ "Variables", "functions_vars.html", null ] + ] ] + ] ] +]; + +var NAVTREEINDEX = +[ +"_c_o_r_e__m_i_s_r_a__exceptions_pg.html", +"struct_m_p_u___type.html#a4d81d6aa73a9287bafba2bcc5ffc6d18" +]; + +var SYNCONMSG = 'click to disable panel synchronisation'; +var SYNCOFFMSG = 'click to enable panel synchronisation'; +var navTreeSubIndices = new Array(); + +function getData(varName) +{ + var i = varName.lastIndexOf('/'); + var n = i>=0 ? varName.substring(i+1) : varName; + return eval(n.replace(/\-/g,'_')); +} + +function stripPath(uri) +{ + return uri.substring(uri.lastIndexOf('/')+1); +} + +function stripPath2(uri) +{ + var i = uri.lastIndexOf('/'); + var s = uri.substring(i+1); + var m = uri.substring(0,i+1).match(/\/d\w\/d\w\w\/$/); + return m ? uri.substring(i-6) : s; +} + +function localStorageSupported() +{ + try { + return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem; + } + catch(e) { + return false; + } +} + + +function storeLink(link) +{ + if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) { + window.localStorage.setItem('navpath',link); + } +} + +function deleteLink() +{ + if (localStorageSupported()) { + window.localStorage.setItem('navpath',''); + } +} + +function cachedLink() +{ + if (localStorageSupported()) { + return window.localStorage.getItem('navpath'); + } else { + return ''; + } +} + +function getScript(scriptName,func,show) +{ + var head = document.getElementsByTagName("head")[0]; + var script = document.createElement('script'); + script.id = scriptName; + script.type = 'text/javascript'; + script.onload = func; + script.src = scriptName+'.js'; + if ($.browser.msie && $.browser.version<=8) { + // script.onload does work with older versions of IE + script.onreadystatechange = function() { + if (script.readyState=='complete' || script.readyState=='loaded') { + func(); if (show) showRoot(); + } + } + } + head.appendChild(script); +} + +function createIndent(o,domNode,node,level) +{ + if (node.parentNode && node.parentNode.parentNode) { + createIndent(o,domNode,node.parentNode,level+1); + } + var imgNode = document.createElement("img"); + imgNode.width = 16; + imgNode.height = 22; + if (level==0 && node.childrenData) { + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() { + if (node.expanded) { + $(node.getChildrenUL()).slideUp("fast"); + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2plastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2pnode.png"; + } + node.expanded = false; + } else { + expandNode(o, node, false, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + } else { + domNode.appendChild(imgNode); + } + if (level==0) { + if (node.isLast) { + if (node.childrenData) { + imgNode.src = node.relpath+"ftv2plastnode.png"; + } else { + imgNode.src = node.relpath+"ftv2lastnode.png"; + domNode.appendChild(imgNode); + } + } else { + if (node.childrenData) { + imgNode.src = node.relpath+"ftv2pnode.png"; + } else { + imgNode.src = node.relpath+"ftv2node.png"; + domNode.appendChild(imgNode); + } + } + } else { + if (node.isLast) { + imgNode.src = node.relpath+"ftv2blank.png"; + } else { + imgNode.src = node.relpath+"ftv2vertline.png"; + } + } + imgNode.border = "0"; +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath($(location).attr('pathname')); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : '#'; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var pos, anchor = $(aname), docContent = $('#doc-content'); + if (anchor.parent().attr('class')=='memItemLeft') { + pos = anchor.parent().position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + window.location.replace(aname); + }); + } + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var anchor = $($(location).attr('hash')); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+ + window.location.hash.substring(1)+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parents().slice(2).prop('tagName')=='TR') { + glowEffect(anchor.parents('div.memitem'),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if (anchor.parent().is(":header")) { + glowEffect(anchor.parent(),1000); // section header + } else { + glowEffect(anchor.next(),1000); // normal member + } +} + +function selectAndHighlight(hash,n) +{ + var a; + if (hash) { + var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1); + a=$('.item a[class$="'+link+'"]'); + } + if (a && a.length) { + a.parent().parent().addClass('selected'); + a.parent().parent().attr('id','selected'); + highlightAnchor(); + } else if (n) { + $(n.itemDiv).addClass('selected'); + $(n.itemDiv).attr('id','selected'); + } + showRoot(); +} + +function showNode(o, node, index, hash) +{ + if (node && node.childrenData) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + showNode(o,node,index,hash); + },true); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } + $(node.getChildrenUL()).show(); + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + var n = node.children[o.breadcrumbs[index]]; + if (index+11) hash = '#'+parts[1]; + else hash=''; + } + if (root==NAVTREE[0][1]) { + $('#nav-sync').css('top','30px'); + } else { + $('#nav-sync').css('top','5px'); + } + if (hash.match(/^#l\d+$/)) { + var anchor=$('a[name='+hash.substring(1)+']'); + glowEffect(anchor.parent(),1000); // line number + hash=''; // strip line number anchors + //root=root.replace(/_source\./,'.'); // source link to doc link + } + var url=root+hash; + var i=-1; + while (NAVTREEINDEX[i+1]<=url) i++; + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath) + } else { + getScript(relpath+'navtreeindex'+i,function(){ + navTreeSubIndices[i] = eval('NAVTREEINDEX'+i); + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath); + } + },true); + } +} + +function showSyncOff(n,relpath) +{ + n.html(''); +} + +function showSyncOn(n,relpath) +{ + n.html(''); +} + +function toggleSyncButton(relpath) +{ + var navSync = $('#nav-sync'); + if (navSync.hasClass('sync')) { + navSync.removeClass('sync'); + showSyncOff(navSync,relpath); + storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash')); + } else { + navSync.addClass('sync'); + showSyncOn(navSync,relpath); + deleteLink(); + } +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; }; + o.node.li.appendChild(o.node.childrenUL); + o.node.depth = 0; + o.node.relpath = relpath; + o.node.expanded = false; + o.node.isLast = true; + o.node.plus_img = document.createElement("img"); + o.node.plus_img.src = relpath+"ftv2pnode.png"; + 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a/Documentation/Core/html/pages.html b/Documentation/Core/html/pages.html new file mode 100644 index 0000000..c584f96 --- /dev/null +++ b/Documentation/Core/html/pages.html @@ -0,0 +1,143 @@ + + + + + +Usage and Description +CMSIS-CORE: Usage and Description + + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.30 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+
    + +
+
+ + + +
+
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Usage and Description
+
+
+
Here is a list of all related documentation pages:
+
[detail level 12]
+ + + + + + + + + + + +
oRevision History of CMSIS-CORE
oUsing CMSIS in Embedded Applications
|oBasic CMSIS Example
|oUsing Interrupt Vector Remap
|\Using CMSIS with generic ARM Processors
oTemplate Files
|oStartup File startup_<device>.s
|oSystem Configuration Files system_<device>.c and system_<device>.h
|\Device Header File <device.h>
oMISRA-C:2004 Compliance Exceptions
\Register Mapping
+
+
+
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+} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/Documentation/Core/html/search/search.js b/Documentation/Core/html/search/search.js new file mode 100644 index 0000000..6fb8704 --- /dev/null +++ b/Documentation/Core/html/search/search.js @@ -0,0 +1,811 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 1: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101001000110000110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 2: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000101001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 3: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000001000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 4: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010111111011001110111111110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 5: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 6: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100010000110100101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 7: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101001000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + 8: "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000000101001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "enums", + 6: "enumvalues", + 7: "groups", + 8: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var hexCode; + if (code<16) + { + hexCode="0"+code.toString(16); + } + else + { + hexCode=code.toString(16); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + if (indexSectionsWithContent[this.searchIndex].charAt(code) == '1') + { + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of . + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e + + + + + + + +
    +
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    + + diff --git a/Documentation/Core/html/search/variables_5f.js b/Documentation/Core/html/search/variables_5f.js new file mode 100644 index 0000000..208e0d9 --- /dev/null +++ b/Documentation/Core/html/search/variables_5f.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['_5freserved0',['_reserved0',['../union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728',1,'APSR_Type::_reserved0()'],['../union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa',1,'IPSR_Type::_reserved0()'],['../unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5',1,'xPSR_Type::_reserved0()'],['../union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50',1,'CONTROL_Type::_reserved0()']]] +]; diff --git a/Documentation/Core/html/search/variables_61.html b/Documentation/Core/html/search/variables_61.html new file mode 100644 index 0000000..ff1f937 --- /dev/null +++ b/Documentation/Core/html/search/variables_61.html @@ -0,0 +1,25 @@ + + + + + + + + +
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    + + diff --git a/Documentation/Core/html/search/variables_61.js b/Documentation/Core/html/search/variables_61.js new file mode 100644 index 0000000..1a8097a --- /dev/null +++ b/Documentation/Core/html/search/variables_61.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['acpr',['ACPR',['../struct_t_p_i___type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3',1,'TPI_Type']]], + ['actlr',['ACTLR',['../struct_s_cn_s_c_b___type.html#a13af9b718dde7481f1c0344f00593c23',1,'SCnSCB_Type']]], + ['adr',['ADR',['../struct_s_c_b___type.html#af084e1b2dad004a88668efea1dfe7fa1',1,'SCB_Type']]], + ['afsr',['AFSR',['../struct_s_c_b___type.html#ab65372404ce64b0f0b35e2709429404e',1,'SCB_Type']]], + ['aircr',['AIRCR',['../struct_s_c_b___type.html#ad3e5b8934c647eb1b7383c1894f01380',1,'SCB_Type']]] +]; diff --git a/Documentation/Core/html/search/variables_62.html b/Documentation/Core/html/search/variables_62.html new file mode 100644 index 0000000..c55a15e --- /dev/null +++ b/Documentation/Core/html/search/variables_62.html @@ -0,0 +1,25 @@ + + + + + + + + +
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    + + diff --git a/Documentation/Core/html/search/variables_76.js b/Documentation/Core/html/search/variables_76.js new file mode 100644 index 0000000..698e362 --- /dev/null +++ b/Documentation/Core/html/search/variables_76.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['v',['V',['../union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e',1,'APSR_Type::V()'],['../unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a',1,'xPSR_Type::V()']]], + ['val',['VAL',['../struct_sys_tick___type.html#a9b5420d17e8e43104ddd4ae5a610af93',1,'SysTick_Type']]], + ['vtor',['VTOR',['../struct_s_c_b___type.html#a187a4578e920544ed967f98020fb8170',1,'SCB_Type']]] +]; diff --git a/Documentation/Core/html/search/variables_77.html b/Documentation/Core/html/search/variables_77.html new file mode 100644 index 0000000..25c3e3a --- /dev/null +++ b/Documentation/Core/html/search/variables_77.html @@ -0,0 +1,25 @@ + + + + + + + + +
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    + + diff --git a/Documentation/Core/html/search/variables_77.js b/Documentation/Core/html/search/variables_77.js new file mode 100644 index 0000000..7681c0f --- /dev/null +++ b/Documentation/Core/html/search/variables_77.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['w',['w',['../union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94',1,'APSR_Type::w()'],['../union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879',1,'IPSR_Type::w()'],['../unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2',1,'xPSR_Type::w()'],['../union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f',1,'CONTROL_Type::w()']]] +]; diff --git a/Documentation/Core/html/search/variables_7a.html b/Documentation/Core/html/search/variables_7a.html new file mode 100644 index 0000000..2ae1676 --- /dev/null +++ b/Documentation/Core/html/search/variables_7a.html @@ -0,0 +1,25 @@ + + + + + + + + +
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    + + diff --git a/Documentation/Core/html/search/variables_7a.js b/Documentation/Core/html/search/variables_7a.js new file mode 100644 index 0000000..ed348a5 --- /dev/null +++ b/Documentation/Core/html/search/variables_7a.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['z',['Z',['../union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5',1,'APSR_Type::Z()'],['../unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562',1,'xPSR_Type::Z()']]] +]; diff --git a/Documentation/Core/html/startup_s_pg.html b/Documentation/Core/html/startup_s_pg.html new file mode 100644 index 0000000..1541b71 --- /dev/null +++ b/Documentation/Core/html/startup_s_pg.html @@ -0,0 +1,370 @@ + + + + + +Startup File startup_<device>.s +CMSIS-CORE: Startup File startup_<device>.s + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    Startup File startup_<device>.s
    +
    +
    +

    The Startup File startup_<device>.s contains:

    +
      +
    • The reset handler which is executed after CPU reset and typically calls the SystemInit function.
      • +
    • The setup values for the Main Stack Pointer (MSP).
      • +
    • Exception vectors of the Cortex-M Processor with weak functions that implement default routines.
      • +
    • Interrupt vectors that are device specific with weak functions that implement default routines.
      • +
    +

    The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.

    +

    To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with IRQn_Type that defines all the IRQ numbers for each interrupt.

    +

    Example:

    +

    The following example shows the extension of the interrupt vector table for the LPC1100 device family.

    +
    ; External Interrupts
    +
    DCD WAKEUP0_IRQHandler ; 16+ 0: Wakeup PIO0.0
    +
    DCD WAKEUP1_IRQHandler ; 16+ 1: Wakeup PIO0.1
    +
    DCD WAKEUP2_IRQHandler ; 16+ 2: Wakeup PIO0.2
    +
    : :
    +
    : :
    +
    DCD EINT1_IRQHandler ; 16+30: PIO INT1
    +
    DCD EINT0_IRQHandler ; 16+31: PIO INT0
    +
    :
    +
    :
    +
    EXPORT WAKEUP0_IRQHandler [WEAK]
    +
    EXPORT WAKEUP1_IRQHandler [WEAK]
    +
    EXPORT WAKEUP2_IRQHandler [WEAK]
    +
    : :
    +
    : :
    +
    EXPORT EINT1_IRQHandler [WEAK]
    +
    EXPORT EINT0_IRQHandler [WEAK]
    +
    +
    WAKEUP0_IRQHandler
    +
    WAKEUP1_IRQHandler
    +
    WAKEUP1_IRQHandler
    +
    :
    +
    :
    +
    EINT1_IRQHandler
    +
    EINT0_IRQHandler
    +
    B .
    +

    +startup_Device.s Template File

    +

    The startup_Device.s Template File for the Cortex-M3 and the ARMCC compiler is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.

    +
    ;/**************************************************************************//**
+; * @file     startup_<Device>.s
+; * @brief    CMSIS Cortex-M# Core Device Startup File for
+; *           Device <Device>
+; * @version  V3.10
+; * @date     23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2012 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+; ToDo:  Add here the vectors for the device specific external interrupts handler
+                DCD     <DeviceInterrupt>_IRQHandler       ;  0: Default
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler\
+                PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler\
+                PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+; ToDo:  Add here the export definition for the device specific external interrupts handler
+                EXPORT  <DeviceInterrupt>_IRQHandler         [WEAK]
+
+; ToDo:  Add here the names for the device specific external interrupts handler
+<DeviceInterrupt>_IRQHandler
+                B       .
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+
    +
    + + + + diff --git a/Documentation/Core/html/struct_core_debug___type.html b/Documentation/Core/html/struct_core_debug___type.html new file mode 100644 index 0000000..9f82c8c --- /dev/null +++ b/Documentation/Core/html/struct_core_debug___type.html @@ -0,0 +1,205 @@ + + + + + +CoreDebug_Type Struct Reference +CMSIS-CORE: CoreDebug_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CoreDebug_Type Struct Reference
    +
    +
    + +

    Structure type to access the Core Debug Register (CoreDebug). +

    + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t DHCSR
     Offset: 0x000 (R/W) Debug Halting Control and Status Register.
     
    __OM uint32_t DCRSR
     Offset: 0x004 ( /W) Debug Core Register Selector Register.
     
    __IOM uint32_t DCRDR
     Offset: 0x008 (R/W) Debug Core Register Data Register.
     
    __IOM uint32_t DEMCR
     Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t CoreDebug_Type::DCRDR
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t CoreDebug_Type::DCRSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t CoreDebug_Type::DEMCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t CoreDebug_Type::DHCSR
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_core_debug___type.js b/Documentation/Core/html/struct_core_debug___type.js new file mode 100644 index 0000000..812a293 --- /dev/null +++ b/Documentation/Core/html/struct_core_debug___type.js @@ -0,0 +1,7 @@ +var struct_core_debug___type = +[ + [ "DCRDR", "struct_core_debug___type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55", null ], + [ "DCRSR", "struct_core_debug___type.html#af907cf64577eaf927dac6787df6dd98b", null ], + [ "DEMCR", "struct_core_debug___type.html#aeb3126abc4c258a858f21f356c0df6ee", null ], + [ "DHCSR", "struct_core_debug___type.html#ad63554e4650da91a8e79929cbb63db66", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_d_w_t___type.html b/Documentation/Core/html/struct_d_w_t___type.html new file mode 100644 index 0000000..2e85193 --- /dev/null +++ b/Documentation/Core/html/struct_d_w_t___type.html @@ -0,0 +1,490 @@ + + + + + +DWT_Type Struct Reference +CMSIS-CORE: DWT_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    DWT_Type Struct Reference
    +
    +
    + +

    Structure type to access the Data Watchpoint and Trace Register (DWT). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t CTRL
     Offset: 0x000 (R/W) Control Register.
     
    __IOM uint32_t CYCCNT
     Offset: 0x004 (R/W) Cycle Count Register.
     
    __IOM uint32_t CPICNT
     Offset: 0x008 (R/W) CPI Count Register.
     
    __IOM uint32_t EXCCNT
     Offset: 0x00C (R/W) Exception Overhead Count Register.
     
    __IOM uint32_t SLEEPCNT
     Offset: 0x010 (R/W) Sleep Count Register.
     
    __IOM uint32_t LSUCNT
     Offset: 0x014 (R/W) LSU Count Register.
     
    __IOM uint32_t FOLDCNT
     Offset: 0x018 (R/W) Folded-instruction Count Register.
     
    __IM uint32_t PCSR
     Offset: 0x01C (R/ ) Program Counter Sample Register.
     
    __IOM uint32_t COMP0
     Offset: 0x020 (R/W) Comparator Register 0.
     
    __IOM uint32_t MASK0
     Offset: 0x024 (R/W) Mask Register 0.
     
    __IOM uint32_t FUNCTION0
     Offset: 0x028 (R/W) Function Register 0.
     
    uint32_t RESERVED0 [1]
     Reserved.
     
    __IOM uint32_t COMP1
     Offset: 0x030 (R/W) Comparator Register 1.
     
    __IOM uint32_t MASK1
     Offset: 0x034 (R/W) Mask Register 1.
     
    __IOM uint32_t FUNCTION1
     Offset: 0x038 (R/W) Function Register 1.
     
    uint32_t RESERVED1 [1]
     Reserved.
     
    __IOM uint32_t COMP2
     Offset: 0x040 (R/W) Comparator Register 2.
     
    __IOM uint32_t MASK2
     Offset: 0x044 (R/W) Mask Register 2.
     
    __IOM uint32_t FUNCTION2
     Offset: 0x048 (R/W) Function Register 2.
     
    uint32_t RESERVED2 [1]
     Reserved.
     
    __IOM uint32_t COMP3
     Offset: 0x050 (R/W) Comparator Register 3.
     
    __IOM uint32_t MASK3
     Offset: 0x054 (R/W) Mask Register 3.
     
    __IOM uint32_t FUNCTION3
     Offset: 0x058 (R/W) Function Register 3.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP0
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::COMP3
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::CPICNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::CTRL
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::CYCCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::EXCCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FOLDCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION0
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::FUNCTION3
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::LSUCNT
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK0
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::MASK3
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t DWT_Type::PCSR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED0[1]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED1[1]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t DWT_Type::RESERVED2[1]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t DWT_Type::SLEEPCNT
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_d_w_t___type.js b/Documentation/Core/html/struct_d_w_t___type.js new file mode 100644 index 0000000..8551743 --- /dev/null +++ b/Documentation/Core/html/struct_d_w_t___type.js @@ -0,0 +1,26 @@ +var struct_d_w_t___type = +[ + [ "COMP0", "struct_d_w_t___type.html#a61c2965af5bc0643f9af65620b0e67c9", null ], + [ "COMP1", "struct_d_w_t___type.html#a38714af6b7fa7c64d68f5e1efbe7a931", null ], + [ "COMP2", "struct_d_w_t___type.html#a5ae6dde39989f27bae90afc2347deb46", null ], + [ "COMP3", "struct_d_w_t___type.html#a85eb73d1848ac3f82d39d6c3e8910847", null ], + [ "CPICNT", "struct_d_w_t___type.html#a2c08096c82abe245c0fa97badc458154", null ], + [ "CTRL", "struct_d_w_t___type.html#add790c53410023b3b581919bb681fe2a", null ], + [ "CYCCNT", "struct_d_w_t___type.html#a102eaa529d9098242851cb57c52b42d9", null ], + [ "EXCCNT", "struct_d_w_t___type.html#a9fe20c16c5167ca61486caf6832686d1", null ], + [ "FOLDCNT", "struct_d_w_t___type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97", null ], + [ "FUNCTION0", "struct_d_w_t___type.html#a579ae082f58a0317b7ef029b20f52889", null ], + [ "FUNCTION1", "struct_d_w_t___type.html#a8dfcf25675f9606aa305c46e85182e4e", null ], + [ "FUNCTION2", "struct_d_w_t___type.html#ab1b60d6600c38abae515bab8e86a188f", null ], + [ "FUNCTION3", "struct_d_w_t___type.html#a52d4ff278fae6f9216c63b74ce328841", null ], + [ "LSUCNT", "struct_d_w_t___type.html#acc05d89bdb1b4fe2fa499920ec02d0b1", null ], + [ "MASK0", "struct_d_w_t___type.html#a821eb5e71f340ec077efc064cfc567db", null ], + [ "MASK1", "struct_d_w_t___type.html#aabf94936c9340e62fed836dcfb152405", null ], + [ "MASK2", "struct_d_w_t___type.html#a00ac4d830dfe0070a656cda9baed170f", null ], + [ "MASK3", "struct_d_w_t___type.html#a2a509d8505c37a3b64f6b24993df5f3f", null ], + [ "PCSR", "struct_d_w_t___type.html#a6353ca1d1ad9bc1be05d3b5632960113", null ], + [ "RESERVED0", "struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59", null ], + [ "RESERVED1", "struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4", null ], + [ "RESERVED2", "struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738", null ], + [ "SLEEPCNT", "struct_d_w_t___type.html#a416a54e2084ce66e5ca74f152a5ecc70", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_f_p_u___type.html b/Documentation/Core/html/struct_f_p_u___type.html new file mode 100644 index 0000000..b84f3c3 --- /dev/null +++ b/Documentation/Core/html/struct_f_p_u___type.html @@ -0,0 +1,235 @@ + + + + + +FPU_Type Struct Reference +CMSIS-CORE: FPU_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    FPU_Type Struct Reference
    +
    +
    + +

    Structure type to access the Floating Point Unit (FPU). +

    + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    uint32_t RESERVED0 [1]
     Reserved.
     
    __IOM uint32_t FPCCR
     Offset: 0x004 (R/W) Floating-Point Context Control Register.
     
    __IOM uint32_t FPCAR
     Offset: 0x008 (R/W) Floating-Point Context Address Register.
     
    __IOM uint32_t FPDSCR
     Offset: 0x00C (R/W) Floating-Point Default Status Control Register.
     
    __IM uint32_t MVFR0
     Offset: 0x010 (R/ ) Media and FP Feature Register 0.
     
    __IM uint32_t MVFR1
     Offset: 0x014 (R/ ) Media and FP Feature Register 1.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t FPU_Type::FPCAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t FPU_Type::FPCCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t FPU_Type::FPDSCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t FPU_Type::MVFR0
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t FPU_Type::MVFR1
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t FPU_Type::RESERVED0[1]
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_f_p_u___type.js b/Documentation/Core/html/struct_f_p_u___type.js new file mode 100644 index 0000000..8af3cda --- /dev/null +++ b/Documentation/Core/html/struct_f_p_u___type.js @@ -0,0 +1,9 @@ +var struct_f_p_u___type = +[ + [ "FPCAR", "struct_f_p_u___type.html#a55263b468d0f8e11ac77aec9ff87c820", null ], + [ "FPCCR", "struct_f_p_u___type.html#af1b708c5e413739150df3d16ca3b7061", null ], + [ "FPDSCR", "struct_f_p_u___type.html#a58d1989664a06db6ec2e122eefa9f04a", null ], + [ "MVFR0", "struct_f_p_u___type.html#a4f19014defe6033d070b80af19ef627c", null ], + [ "MVFR1", "struct_f_p_u___type.html#a66f8cfa49a423b480001a4e101bf842d", null ], + [ "RESERVED0", "struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_i_t_m___type.html b/Documentation/Core/html/struct_i_t_m___type.html new file mode 100644 index 0000000..ba162b2 --- /dev/null +++ b/Documentation/Core/html/struct_i_t_m___type.html @@ -0,0 +1,296 @@ + + + + + +ITM_Type Struct Reference +CMSIS-CORE: ITM_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    ITM_Type Struct Reference
    +
    +
    + +

    Structure type to access the Instrumentation Trace Macrocell Register (ITM). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    union {
       __OM uint8_t   u8
     Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.
     
       __OM uint16_t   u16
     Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.
     
       __OM uint32_t   u32
     Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.
     
    } PORT [32]
     Offset: 0x000 ( /W) ITM Stimulus Port Registers.
     
    uint32_t RESERVED0 [864]
     Reserved.
     
    __IOM uint32_t TER
     Offset: 0xE00 (R/W) ITM Trace Enable Register.
     
    uint32_t RESERVED1 [15]
     Reserved.
     
    __IOM uint32_t TPR
     Offset: 0xE40 (R/W) ITM Trace Privilege Register.
     
    uint32_t RESERVED2 [15]
     Reserved.
     
    __IOM uint32_t TCR
     Offset: 0xE80 (R/W) ITM Trace Control Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __OM { ... } ITM_Type::PORT[32]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ITM_Type::RESERVED0[864]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ITM_Type::RESERVED1[15]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t ITM_Type::RESERVED2[15]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::TCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::TER
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t ITM_Type::TPR
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint16_t ITM_Type::u16
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t ITM_Type::u32
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint8_t ITM_Type::u8
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_i_t_m___type.js b/Documentation/Core/html/struct_i_t_m___type.js new file mode 100644 index 0000000..4c165a2 --- /dev/null +++ b/Documentation/Core/html/struct_i_t_m___type.js @@ -0,0 +1,13 @@ +var struct_i_t_m___type = +[ + [ "PORT", "struct_i_t_m___type.html#af4c205be465780a20098387120bdb482", null ], + [ "RESERVED0", "struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e", null ], + [ "RESERVED1", "struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce", null ], + [ "RESERVED2", "struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b", null ], + [ "TCR", "struct_i_t_m___type.html#a04b9fbc83759cb818dfa161d39628426", null ], + [ "TER", "struct_i_t_m___type.html#acd03c6858f7b678dab6a6121462e7807", null ], + [ "TPR", "struct_i_t_m___type.html#ae907229ba50538bf370fbdfd54c099a2", null ], + [ "u16", "struct_i_t_m___type.html#a962a970dfd286cad7f8a8577e87d4ad3", null ], + [ "u32", "struct_i_t_m___type.html#a5834885903a557674f078f3b71fa8bc8", null ], + [ "u8", "struct_i_t_m___type.html#ae773bf9f9dac64e6c28b14aa39f74275", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_m_p_u___type.html b/Documentation/Core/html/struct_m_p_u___type.html new file mode 100644 index 0000000..ee63cbe --- /dev/null +++ b/Documentation/Core/html/struct_m_p_u___type.html @@ -0,0 +1,310 @@ + + + + + +MPU_Type Struct Reference +CMSIS-CORE: MPU_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    MPU_Type Struct Reference
    +
    +
    + +

    Structure type to access the Memory Protection Unit (MPU). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IM uint32_t TYPE
     Offset: 0x000 (R/ ) MPU Type Register.
     
    __IOM uint32_t CTRL
     Offset: 0x004 (R/W) MPU Control Register.
     
    __IOM uint32_t RNR
     Offset: 0x008 (R/W) MPU Region RNRber Register.
     
    __IOM uint32_t RBAR
     Offset: 0x00C (R/W) MPU Region Base Address Register.
     
    __IOM uint32_t RASR
     Offset: 0x010 (R/W) MPU Region Attribute and Size Register.
     
    __IOM uint32_t RBAR_A1
     Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register.
     
    __IOM uint32_t RASR_A1
     Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register.
     
    __IOM uint32_t RBAR_A2
     Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register.
     
    __IOM uint32_t RASR_A2
     Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register.
     
    __IOM uint32_t RBAR_A3
     Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register.
     
    __IOM uint32_t RASR_A3
     Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::CTRL
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RASR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RASR_A1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RASR_A2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RASR_A3
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RBAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RBAR_A1
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RBAR_A2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RBAR_A3
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t MPU_Type::RNR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t MPU_Type::TYPE
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_m_p_u___type.js b/Documentation/Core/html/struct_m_p_u___type.js new file mode 100644 index 0000000..26696b1 --- /dev/null +++ b/Documentation/Core/html/struct_m_p_u___type.js @@ -0,0 +1,14 @@ +var struct_m_p_u___type = +[ + [ "CTRL", "struct_m_p_u___type.html#a4d81d6aa73a9287bafba2bcc5ffc6d18", null ], + [ "RASR", "struct_m_p_u___type.html#a9236c629b7cf86f8bd2459c610fdf715", null ], + [ "RASR_A1", "struct_m_p_u___type.html#ab5a224ccd12ac55ddfe11d9eca42de48", null ], + [ "RASR_A2", "struct_m_p_u___type.html#ac60e0919871b66446a039838bcaaec3b", null ], + [ "RASR_A3", "struct_m_p_u___type.html#a9c0b2d3e3e16bb4e7dfa069652d5a155", null ], + [ "RBAR", "struct_m_p_u___type.html#ac953770d38a7d322b971d93eb8a5b062", null ], + [ "RBAR_A1", "struct_m_p_u___type.html#a13d69b9bea12861383f3a62764b02f63", null ], + [ "RBAR_A2", "struct_m_p_u___type.html#a57dc551614932150e684fcc60590c2c4", null ], + [ "RBAR_A3", "struct_m_p_u___type.html#a345911aabecd1f7d93a1bff7738b0d86", null ], + [ "RNR", "struct_m_p_u___type.html#aa800d44f4d3520cc891d7b8d711320c1", null ], + [ "TYPE", "struct_m_p_u___type.html#a0433efc1383674bc8e86cc0e830b462d", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_n_v_i_c___type.html b/Documentation/Core/html/struct_n_v_i_c___type.html new file mode 100644 index 0000000..a6b9a0a --- /dev/null +++ b/Documentation/Core/html/struct_n_v_i_c___type.html @@ -0,0 +1,340 @@ + + + + + +NVIC_Type Struct Reference +CMSIS-CORE: NVIC_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    NVIC_Type Struct Reference
    +
    +
    + +

    Structure type to access the Nested Vectored Interrupt Controller (NVIC). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t ISER [8]
     Offset: 0x000 (R/W) Interrupt Set Enable Register.
     
    uint32_t RESERVED0 [24]
     Reserved.
     
    __IOM uint32_t ICER [8]
     Offset: 0x080 (R/W) Interrupt Clear Enable Register.
     
    uint32_t RSERVED1 [24]
     Reserved.
     
    __IOM uint32_t ISPR [8]
     Offset: 0x100 (R/W) Interrupt Set Pending Register.
     
    uint32_t RESERVED2 [24]
     Reserved.
     
    __IOM uint32_t ICPR [8]
     Offset: 0x180 (R/W) Interrupt Clear Pending Register.
     
    uint32_t RESERVED3 [24]
     Reserved.
     
    __IOM uint32_t IABR [8]
     Offset: 0x200 (R/W) Interrupt Active bit Register.
     
    uint32_t RESERVED4 [56]
     Reserved.
     
    __IOM uint8_t IP [240]
     Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
     
    uint32_t RESERVED5 [644]
     Reserved.
     
    __OM uint32_t STIR
     Offset: 0xE00 ( /W) Software Trigger Interrupt Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::IABR[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ICER[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ICPR[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t NVIC_Type::IP[240]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ISER[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t NVIC_Type::ISPR[8]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED0[24]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED2[24]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED3[24]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED4[56]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RESERVED5[644]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t NVIC_Type::RSERVED1[24]
    +
    + +
    +
    + +
    +
    + + + + +
    __OM uint32_t NVIC_Type::STIR
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_n_v_i_c___type.js b/Documentation/Core/html/struct_n_v_i_c___type.js new file mode 100644 index 0000000..ca47fe6 --- /dev/null +++ b/Documentation/Core/html/struct_n_v_i_c___type.js @@ -0,0 +1,16 @@ +var struct_n_v_i_c___type = +[ + [ "IABR", "struct_n_v_i_c___type.html#a4bca5452748ba84d64536fb6a5d795af", null ], + [ "ICER", "struct_n_v_i_c___type.html#a245df8bac1da05c39eadabede9323203", null ], + [ "ICPR", "struct_n_v_i_c___type.html#a8d8f45d9c5c67bba3c153c55574bac95", null ], + [ "IP", "struct_n_v_i_c___type.html#a7ff7364a4260df67a2784811e8da4efd", null ], + [ "ISER", "struct_n_v_i_c___type.html#a9fccef5a60a0d5e81fcd7869a6274f47", null ], + [ "ISPR", "struct_n_v_i_c___type.html#a8f731a9f428efc86e8d311b52ce823d0", null ], + [ "RESERVED0", "struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80", null ], + [ "RESERVED2", "struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72", null ], + [ "RESERVED3", "struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab", null ], + [ "RESERVED4", "struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790", null ], + [ "RESERVED5", "struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8", null ], + [ "RSERVED1", "struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe", null ], + [ "STIR", "struct_n_v_i_c___type.html#a37de89637466e007171c6b135299bc75", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_s_c_b___type.html b/Documentation/Core/html/struct_s_c_b___type.html new file mode 100644 index 0000000..2bc4a47 --- /dev/null +++ b/Documentation/Core/html/struct_s_c_b___type.html @@ -0,0 +1,460 @@ + + + + + +SCB_Type Struct Reference +CMSIS-CORE: SCB_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    SCB_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Control Block (SCB). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IM uint32_t CPUID
     Offset: 0x000 (R/ ) CPUID Base Register.
     
    __IOM uint32_t ICSR
     Offset: 0x004 (R/W) Interrupt Control and State Register.
     
    __IOM uint32_t VTOR
     Offset: 0x008 (R/W) Vector Table Offset Register.
     
    __IOM uint32_t AIRCR
     Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.
     
    __IOM uint32_t SCR
     Offset: 0x010 (R/W) System Control Register.
     
    __IOM uint32_t CCR
     Offset: 0x014 (R/W) Configuration Control Register.
     
    __IOM uint8_t SHP [12]
     Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
     
    __IOM uint32_t SHCSR
     Offset: 0x024 (R/W) System Handler Control and State Register.
     
    __IOM uint32_t CFSR
     Offset: 0x028 (R/W) Configurable Fault Status Register.
     
    __IOM uint32_t HFSR
     Offset: 0x02C (R/W) HardFault Status Register.
     
    __IOM uint32_t DFSR
     Offset: 0x030 (R/W) Debug Fault Status Register.
     
    __IOM uint32_t MMFAR
     Offset: 0x034 (R/W) MemManage Fault Address Register.
     
    __IOM uint32_t BFAR
     Offset: 0x038 (R/W) BusFault Address Register.
     
    __IOM uint32_t AFSR
     Offset: 0x03C (R/W) Auxiliary Fault Status Register.
     
    __IM uint32_t PFR [2]
     Offset: 0x040 (R/ ) Processor Feature Register.
     
    __IM uint32_t DFR
     Offset: 0x048 (R/ ) Debug Feature Register.
     
    __IM uint32_t ADR
     Offset: 0x04C (R/ ) Auxiliary Feature Register.
     
    __IM uint32_t MMFR [4]
     Offset: 0x050 (R/ ) Memory Model Feature Register.
     
    __IM uint32_t ISAR [5]
     Offset: 0x060 (R/ ) Instruction Set Attributes Register.
     
    uint32_t RESERVED0 [5]
     Reserved.
     
    __IOM uint32_t CPACR
     Offset: 0x088 (R/W) Coprocessor Access Control Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::ADR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::AFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::AIRCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::BFAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::CCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::CFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::CPACR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::CPUID
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::DFR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::DFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::HFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::ICSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::ISAR[5]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::MMFAR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::MMFR[4]
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCB_Type::PFR[2]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCB_Type::RESERVED0[5]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::SCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::SHCSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint8_t SCB_Type::SHP[12]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SCB_Type::VTOR
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_s_c_b___type.js b/Documentation/Core/html/struct_s_c_b___type.js new file mode 100644 index 0000000..d82ca54 --- /dev/null +++ b/Documentation/Core/html/struct_s_c_b___type.js @@ -0,0 +1,24 @@ +var struct_s_c_b___type = +[ + [ "ADR", "struct_s_c_b___type.html#af084e1b2dad004a88668efea1dfe7fa1", null ], + [ "AFSR", "struct_s_c_b___type.html#ab65372404ce64b0f0b35e2709429404e", null ], + [ "AIRCR", "struct_s_c_b___type.html#ad3e5b8934c647eb1b7383c1894f01380", null ], + [ "BFAR", "struct_s_c_b___type.html#a3f8e7e58be4e41c88dfa78f54589271c", null ], + [ "CCR", "struct_s_c_b___type.html#a2d6653b0b70faac936046a02809b577f", null ], + [ "CFSR", "struct_s_c_b___type.html#a0cda9e061b42373383418663092ad19a", null ], + [ "CPACR", "struct_s_c_b___type.html#ac6a860c1b8d8154a1f00d99d23b67764", null ], + [ "CPUID", "struct_s_c_b___type.html#a21e08d546d8b641bee298a459ea73e46", null ], + [ "DFR", "struct_s_c_b___type.html#a85dd6fe77aab17e7ea89a52c59da6004", null ], + [ "DFSR", "struct_s_c_b___type.html#a191579bde0d21ff51d30a714fd887033", null ], + [ "HFSR", "struct_s_c_b___type.html#a14ad254659362b9752c69afe3fd80934", null ], + [ "ICSR", "struct_s_c_b___type.html#a0ca18ef984d132c6bf4d9b61cd00f05a", null ], + [ "ISAR", "struct_s_c_b___type.html#ae0136a2d2d3c45f016b2c449e92b2066", null ], + [ "MMFAR", "struct_s_c_b___type.html#a2d03d0b7cec2254f39eb1c46c7445e80", null ], + [ "MMFR", "struct_s_c_b___type.html#aa11887804412bda283cc85a83fdafa7c", null ], + [ "PFR", "struct_s_c_b___type.html#a681c9d9e518b217976bef38c2423d83d", null ], + [ "RESERVED0", "struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6", null ], + [ "SCR", "struct_s_c_b___type.html#a3a4840c6fa4d1ee75544f4032c88ec34", null ], + [ "SHCSR", "struct_s_c_b___type.html#a7b5ae9741a99808043394c4743b635c4", null ], + [ "SHP", "struct_s_c_b___type.html#a85768f4b3dbbc41fd760041ee1202162", null ], + [ "VTOR", "struct_s_c_b___type.html#a187a4578e920544ed967f98020fb8170", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_s_cn_s_c_b___type.html b/Documentation/Core/html/struct_s_cn_s_c_b___type.html new file mode 100644 index 0000000..96a0c00 --- /dev/null +++ b/Documentation/Core/html/struct_s_cn_s_c_b___type.html @@ -0,0 +1,190 @@ + + + + + +SCnSCB_Type Struct Reference +CMSIS-CORE: SCnSCB_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    SCnSCB_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Control and ID Register not in the SCB. +

    + + + + + + + + + + + +

    +Data Fields

    uint32_t RESERVED0 [1]
     Reserved.
     
    __IM uint32_t ICTR
     Offset: 0x004 (R/ ) Interrupt Controller Type Register.
     
    __IOM uint32_t ACTLR
     Offset: 0x008 (R/W) Auxiliary Control Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t SCnSCB_Type::ACTLR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t SCnSCB_Type::ICTR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t SCnSCB_Type::RESERVED0[1]
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_s_cn_s_c_b___type.js b/Documentation/Core/html/struct_s_cn_s_c_b___type.js new file mode 100644 index 0000000..f0d6f06 --- /dev/null +++ b/Documentation/Core/html/struct_s_cn_s_c_b___type.js @@ -0,0 +1,6 @@ +var struct_s_cn_s_c_b___type = +[ + [ "ACTLR", "struct_s_cn_s_c_b___type.html#a13af9b718dde7481f1c0344f00593c23", null ], + [ "ICTR", "struct_s_cn_s_c_b___type.html#a34ec1d771245eb9bd0e3ec9336949762", null ], + [ "RESERVED0", "struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_sys_tick___type.html b/Documentation/Core/html/struct_sys_tick___type.html new file mode 100644 index 0000000..7cea3e3 --- /dev/null +++ b/Documentation/Core/html/struct_sys_tick___type.html @@ -0,0 +1,205 @@ + + + + + +SysTick_Type Struct Reference +CMSIS-CORE: SysTick_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    SysTick_Type Struct Reference
    +
    +
    + +

    Structure type to access the System Timer (SysTick). +

    + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t CTRL
     Offset: 0x000 (R/W) SysTick Control and Status Register.
     
    __IOM uint32_t LOAD
     Offset: 0x004 (R/W) SysTick Reload Value Register.
     
    __IOM uint32_t VAL
     Offset: 0x008 (R/W) SysTick Current Value Register.
     
    __IM uint32_t CALIB
     Offset: 0x00C (R/ ) SysTick Calibration Register.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IM uint32_t SysTick_Type::CALIB
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SysTick_Type::CTRL
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SysTick_Type::LOAD
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t SysTick_Type::VAL
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_sys_tick___type.js b/Documentation/Core/html/struct_sys_tick___type.js new file mode 100644 index 0000000..8833522 --- /dev/null +++ b/Documentation/Core/html/struct_sys_tick___type.js @@ -0,0 +1,7 @@ +var struct_sys_tick___type = +[ + [ "CALIB", "struct_sys_tick___type.html#afcadb0c6d35b21cdc0018658a13942de", null ], + [ "CTRL", "struct_sys_tick___type.html#a875e7afa5c4fd43997fb544a4ac6e37e", null ], + [ "LOAD", "struct_sys_tick___type.html#a4780a489256bb9f54d0ba8ed4de191cd", null ], + [ "VAL", "struct_sys_tick___type.html#a9b5420d17e8e43104ddd4ae5a610af93", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/struct_t_p_i___type.html b/Documentation/Core/html/struct_t_p_i___type.html new file mode 100644 index 0000000..5b68d26 --- /dev/null +++ b/Documentation/Core/html/struct_t_p_i___type.html @@ -0,0 +1,505 @@ + + + + + +TPI_Type Struct Reference +CMSIS-CORE: TPI_Type Struct Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    TPI_Type Struct Reference
    +
    +
    + +

    Structure type to access the Trace Port Interface Register (TPI). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    __IOM uint32_t SSPSR
     Offset: 0x000 (R/ ) Supported Parallel Port Size Register.
     
    __IOM uint32_t CSPSR
     Offset: 0x004 (R/W) Current Parallel Port Size Register.
     
    uint32_t RESERVED0 [2]
     Reserved.
     
    __IOM uint32_t ACPR
     Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.
     
    uint32_t RESERVED1 [55]
     Reserved.
     
    __IOM uint32_t SPPR
     Offset: 0x0F0 (R/W) Selected Pin Protocol Register.
     
    uint32_t RESERVED2 [131]
     Reserved.
     
    __IM uint32_t FFSR
     Offset: 0x300 (R/ ) Formatter and Flush Status Register.
     
    __IOM uint32_t FFCR
     Offset: 0x304 (R/W) Formatter and Flush Control Register.
     
    __IM uint32_t FSCR
     Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.
     
    uint32_t RESERVED3 [759]
     Reserved.
     
    __IM uint32_t TRIGGER
     Offset: 0xEE8 (R/ ) TRIGGER.
     
    __IM uint32_t FIFO0
     Offset: 0xEEC (R/ ) Integration ETM Data.
     
    __IM uint32_t ITATBCTR2
     Offset: 0xEF0 (R/ ) ITATBCTR2.
     
    uint32_t RESERVED4 [1]
     Reserved.
     
    __IM uint32_t ITATBCTR0
     Offset: 0xEF8 (R/ ) ITATBCTR0.
     
    __IM uint32_t FIFO1
     Offset: 0xEFC (R/ ) Integration ITM Data.
     
    __IOM uint32_t ITCTRL
     Offset: 0xF00 (R/W) Integration Mode Control.
     
    uint32_t RESERVED5 [39]
     Reserved.
     
    __IOM uint32_t CLAIMSET
     Offset: 0xFA0 (R/W) Claim tag set.
     
    __IOM uint32_t CLAIMCLR
     Offset: 0xFA4 (R/W) Claim tag clear.
     
    uint32_t RESERVED7 [8]
     Reserved.
     
    __IM uint32_t DEVID
     Offset: 0xFC8 (R/ ) TPIU_DEVID.
     
    __IM uint32_t DEVTYPE
     Offset: 0xFCC (R/ ) TPIU_DEVTYPE.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::ACPR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::CLAIMCLR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::CLAIMSET
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::CSPSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::DEVID
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::DEVTYPE
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::FFCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FFSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FIFO0
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FIFO1
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::FSCR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::ITATBCTR0
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::ITATBCTR2
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::ITCTRL
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED0[2]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED1[55]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED2[131]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED3[759]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED4[1]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED5[39]
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t TPI_Type::RESERVED7[8]
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::SPPR
    +
    + +
    +
    + +
    +
    + + + + +
    __IOM uint32_t TPI_Type::SSPSR
    +
    + +
    +
    + +
    +
    + + + + +
    __IM uint32_t TPI_Type::TRIGGER
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/struct_t_p_i___type.js b/Documentation/Core/html/struct_t_p_i___type.js new file mode 100644 index 0000000..e95d25f --- /dev/null +++ b/Documentation/Core/html/struct_t_p_i___type.js @@ -0,0 +1,27 @@ +var struct_t_p_i___type = +[ + [ "ACPR", "struct_t_p_i___type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3", null ], + [ "CLAIMCLR", "struct_t_p_i___type.html#a0e10e292cb019a832b03ddd055b2f6ac", null ], + [ "CLAIMSET", "struct_t_p_i___type.html#af8b7d15fa5252b733dd4b11fa1b5730a", null ], + [ "CSPSR", "struct_t_p_i___type.html#a8826aa84e5806053395a742d38d59d0f", null ], + [ "DEVID", "struct_t_p_i___type.html#abc0ecda8a5446bc754080276bad77514", null ], + [ "DEVTYPE", "struct_t_p_i___type.html#ad98855854a719bbea33061e71529a472", null ], + [ "FFCR", "struct_t_p_i___type.html#a3f68b6e73561b4849ebf953a894df8d2", null ], + [ "FFSR", "struct_t_p_i___type.html#a6c47a0b4c7ffc66093ef993d36bb441c", null ], + [ "FIFO0", "struct_t_p_i___type.html#aa4d7b5cf39dff9f53bf7f69bc287a814", null ], + [ "FIFO1", "struct_t_p_i___type.html#a061372fcd72f1eea871e2d9c1be849bc", null ], + [ "FSCR", "struct_t_p_i___type.html#ad6901bfd8a0089ca7e8a20475cf494a8", null ], + [ "ITATBCTR0", "struct_t_p_i___type.html#aaa573b2e073e76e93c51ecec79c616d0", null ], + [ "ITATBCTR2", "struct_t_p_i___type.html#ab358319b969d3fed0f89bbe33e9f1652", null ], + [ "ITCTRL", "struct_t_p_i___type.html#aaa4c823c10f115f7517c82ef86a5a68d", null ], + [ "RESERVED0", "struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9", null ], + [ "RESERVED1", "struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12", null ], + [ "RESERVED2", "struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096", null ], + [ "RESERVED3", "struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c", null ], + [ "RESERVED4", "struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46", null ], + [ "RESERVED5", "struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30", null ], + [ "RESERVED7", "struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550", null ], + [ "SPPR", "struct_t_p_i___type.html#a12f79d4e3ddc69893ba8bff890d04cc5", null ], + [ "SSPSR", "struct_t_p_i___type.html#a7b72598e20066133e505bb781690dc22", null ], + [ "TRIGGER", "struct_t_p_i___type.html#a4d4cd2357f72333a82a1313228287bbd", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/sync_off.png b/Documentation/Core/html/sync_off.png new file mode 100644 index 0000000..e8e314d Binary files /dev/null and b/Documentation/Core/html/sync_off.png differ diff --git a/Documentation/Core/html/sync_on.png b/Documentation/Core/html/sync_on.png new file mode 100644 index 0000000..f80906a Binary files /dev/null and b/Documentation/Core/html/sync_on.png differ diff --git a/Documentation/Core/html/system_c_pg.html b/Documentation/Core/html/system_c_pg.html new file mode 100644 index 0000000..c298350 --- /dev/null +++ b/Documentation/Core/html/system_c_pg.html @@ -0,0 +1,310 @@ + + + + + +System Configuration Files system_<device>.c and system_<device>.h +CMSIS-CORE: System Configuration Files system_<device>.c and system_<device>.h + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +
    System Configuration Files system_<device>.c and system_<device>.h
    +
    +
    +

    The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System and Clock Configuration. These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.

    +

    For devices with external memory BUS the system_<device>.c also configures the BUS system.

    +

    The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.

    +

    +system_Device.c Template File

    +

    The system_Device.c Template File for the Cortex-M3 is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.c
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Source File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#include <stdint.h>
+#include "<Device>.h"
+
+
+/*----------------------------------------------------------------------------
+  DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+/* ToDo: add here your necessary defines for device initialization
+         following is an example for different system frequencies             */
+#define __HSI             ( 6000000UL)
+#define __XTAL            (12000000UL)    /* Oscillator frequency             */
+#define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
+
+#define __SYSTEM_CLOCK    (4*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* ToDo: initialize SystemCoreClock with the system core clock frequency value
+         achieved after system intitialization.
+         This means system core clock frequency after call to SystemInit()    */
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;  /*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+/* ToDo: add code to calculate the system frequency based upon the current
+         register settings.
+         This function can be used to retrieve the system core clock frequeny
+         after user changed register sittings.                                */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+/* ToDo: add code to initialize the system
+         do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+  SystemCoreClock = __SYSTEM_CLOCK;
+}
+

    +system_Device.h Template File

    +

    The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The system_Device.h Template File is shown below.

    +
    /**************************************************************************//**
+ * @file     system_<Device>.h
+ * @brief    CMSIS Cortex-M# Device Peripheral Access Layer Header File for
+ *           Device <Device>
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */
+#define SYSTEM_<Device>_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_<Device>_H */
+
    +
    + + + + diff --git a/Documentation/Core/html/tab_a.png b/Documentation/Core/html/tab_a.png new file mode 100644 index 0000000..fffadc1 Binary files /dev/null and b/Documentation/Core/html/tab_a.png differ diff --git a/Documentation/Core/html/tab_b.png b/Documentation/Core/html/tab_b.png new file mode 100644 index 0000000..f69d988 Binary files /dev/null and b/Documentation/Core/html/tab_b.png differ diff --git a/Documentation/Core/html/tab_h.png b/Documentation/Core/html/tab_h.png new file mode 100644 index 0000000..5e9188f Binary files /dev/null and b/Documentation/Core/html/tab_h.png differ diff --git a/Documentation/Core/html/tab_s.png b/Documentation/Core/html/tab_s.png new file mode 100644 index 0000000..956e1c2 Binary files /dev/null and b/Documentation/Core/html/tab_s.png differ diff --git a/Documentation/Core/html/tab_topnav.png b/Documentation/Core/html/tab_topnav.png new file mode 100644 index 0000000..b257b77 Binary files /dev/null and b/Documentation/Core/html/tab_topnav.png differ diff --git a/Documentation/Core/html/tabs.css b/Documentation/Core/html/tabs.css new file mode 100644 index 0000000..ffbab50 --- /dev/null +++ b/Documentation/Core/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/Documentation/Core/html/union_a_p_s_r___type.html b/Documentation/Core/html/union_a_p_s_r___type.html new file mode 100644 index 0000000..5450446 --- /dev/null +++ b/Documentation/Core/html/union_a_p_s_r___type.html @@ -0,0 +1,266 @@ + + + + + +APSR_Type Union Reference +CMSIS-CORE: APSR_Type Union Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    APSR_Type Union Reference
    +
    +
    + +

    Union type to access the Application Program Status Register (APSR). +

    + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   _reserved0:27
     bit: 0..26 Reserved
     
       uint32_t   Q:1
     bit: 27 Saturation condition flag
     
       uint32_t   V:1
     bit: 28 Overflow condition code flag
     
       uint32_t   C:1
     bit: 29 Carry condition code flag
     
       uint32_t   Z:1
     bit: 30 Zero condition code flag
     
       uint32_t   N:1
     bit: 31 Negative condition code flag
     
    } b
     Structure used for bit access.
     
    uint32_t w
     Type used for word access.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t APSR_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } APSR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::C
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::N
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::Q
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::V
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::w
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t APSR_Type::Z
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/union_a_p_s_r___type.js b/Documentation/Core/html/union_a_p_s_r___type.js new file mode 100644 index 0000000..cbea61b --- /dev/null +++ b/Documentation/Core/html/union_a_p_s_r___type.js @@ -0,0 +1,11 @@ +var union_a_p_s_r___type = +[ + [ "_reserved0", "union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728", null ], + [ "b", "union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14", null ], + [ "C", "union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6", null ], + [ "N", "union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0", null ], + [ "Q", "union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de", null ], + [ "V", "union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e", null ], + [ "w", "union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94", null ], + [ "Z", "union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html b/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html new file mode 100644 index 0000000..f9b889b --- /dev/null +++ b/Documentation/Core/html/union_c_o_n_t_r_o_l___type.html @@ -0,0 +1,236 @@ + + + + + +CONTROL_Type Union Reference +CMSIS-CORE: CONTROL_Type Union Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    CONTROL_Type Union Reference
    +
    +
    + +

    Union type to access the Control Registers (CONTROL). +

    + + + + + + + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   nPRIV:1
     bit: 0 Execution privilege in Thread mode
     
       uint32_t   SPSEL:1
     bit: 1 Stack to be used
     
       uint32_t   FPCA:1
     bit: 2 FP extension active flag
     
       uint32_t   _reserved0:29
     bit: 3..31 Reserved
     
    } b
     Structure used for bit access.
     
    uint32_t w
     Type used for word access.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t CONTROL_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } CONTROL_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::FPCA
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::nPRIV
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::SPSEL
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t CONTROL_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js b/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js new file mode 100644 index 0000000..eb2c173 --- /dev/null +++ b/Documentation/Core/html/union_c_o_n_t_r_o_l___type.js @@ -0,0 +1,9 @@ +var union_c_o_n_t_r_o_l___type = +[ + [ "_reserved0", "union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50", null ], + [ "b", "union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9", null ], + [ "FPCA", "union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd", null ], + [ "nPRIV", "union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605", null ], + [ "SPSEL", "union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2", null ], + [ "w", "union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/union_i_p_s_r___type.html b/Documentation/Core/html/union_i_p_s_r___type.html new file mode 100644 index 0000000..9685687 --- /dev/null +++ b/Documentation/Core/html/union_i_p_s_r___type.html @@ -0,0 +1,206 @@ + + + + + +IPSR_Type Union Reference +CMSIS-CORE: IPSR_Type Union Reference + + + + + + + + + + + + + + + +
    +
    + + + + + + + +
    +
    CMSIS-CORE +  Version 4.30 +
    +
    CMSIS-CORE support for Cortex-M processor-based devices
    +
    +
    + +
    +
      + +
    +
    + + + + +
    +
    + +
    +
    +
    + +
    + + + + +
    + +
    + +
    +
    +Data Fields
    +
    +
    IPSR_Type Union Reference
    +
    +
    + +

    Union type to access the Interrupt Program Status Register (IPSR). +

    + + + + + + + + + + + + + + + +

    +Data Fields

    struct {
       uint32_t   ISR:9
     bit: 0.. 8 Exception number
     
       uint32_t   _reserved0:23
     bit: 9..31 Reserved
     
    } b
     Structure used for bit access.
     
    uint32_t w
     Type used for word access.
     
    +

    Field Documentation

    + +
    +
    + + + + +
    uint32_t IPSR_Type::_reserved0
    +
    + +
    +
    + +
    +
    + + + + +
    struct { ... } IPSR_Type::b
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IPSR_Type::ISR
    +
    + +
    +
    + +
    +
    + + + + +
    uint32_t IPSR_Type::w
    +
    + +
    +
    +
    +
    + + + + diff --git a/Documentation/Core/html/union_i_p_s_r___type.js b/Documentation/Core/html/union_i_p_s_r___type.js new file mode 100644 index 0000000..ca9eac6 --- /dev/null +++ b/Documentation/Core/html/union_i_p_s_r___type.js @@ -0,0 +1,7 @@ +var union_i_p_s_r___type = +[ + [ "_reserved0", "union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa", null ], + [ "b", "union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50", null ], + [ "ISR", "union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5", null ], + [ "w", "union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879", null ] +]; \ No newline at end of file diff --git a/Documentation/Core/html/unionx_p_s_r___type.html b/Documentation/Core/html/unionx_p_s_r___type.html new file mode 100644 index 0000000..1cd3267 --- /dev/null +++ b/Documentation/Core/html/unionx_p_s_r___type.html @@ -0,0 +1,311 @@ + + + + + +xPSR_Type Union Reference +CMSIS-CORE: xPSR_Type Union Reference + + + + + + + + + + + + + + + +
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    CMSIS-CORE +  Version 4.30 +
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    CMSIS-CORE support for Cortex-M processor-based devices
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    +Data Fields
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    xPSR_Type Union Reference
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    Union type to access the Special-Purpose Program Status Registers (xPSR). +

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    +Data Fields

    struct {
       uint32_t   ISR:9
     bit: 0.. 8 Exception number
     
       uint32_t   _reserved0:15
     bit: 9..23 Reserved
     
       uint32_t   T:1
     bit: 24 Thumb bit (read 0)
     
       uint32_t   IT:2
     bit: 25..26 saved IT state (read 0)
     
       uint32_t   Q:1
     bit: 27 Saturation condition flag
     
       uint32_t   V:1
     bit: 28 Overflow condition code flag
     
       uint32_t   C:1
     bit: 29 Carry condition code flag
     
       uint32_t   Z:1
     bit: 30 Zero condition code flag
     
       uint32_t   N:1
     bit: 31 Negative condition code flag
     
    } b
     Structure used for bit access.
     
    uint32_t w
     Type used for word access.
     
    +

    Field Documentation

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    uint32_t xPSR_Type::_reserved0
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    struct { ... } xPSR_Type::b
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    uint32_t xPSR_Type::C
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    uint32_t xPSR_Type::ISR
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    uint32_t xPSR_Type::IT
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    uint32_t xPSR_Type::N
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    uint32_t xPSR_Type::Q
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    uint32_t xPSR_Type::T
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    uint32_t xPSR_Type::V
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    uint32_t xPSR_Type::w
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    uint32_t xPSR_Type::Z
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    + + + + diff --git a/Documentation/Core/html/unionx_p_s_r___type.js b/Documentation/Core/html/unionx_p_s_r___type.js new file mode 100644 index 0000000..b02f482 --- /dev/null +++ b/Documentation/Core/html/unionx_p_s_r___type.js @@ -0,0 +1,14 @@ +var unionx_p_s_r___type = +[ + [ "_reserved0", "unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5", null ], + [ "b", "unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70", null ], + [ "C", "unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d", null ], + [ "ISR", "unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970", null ], + [ "IT", "unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328", null ], + [ "N", "unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5", null ], + [ "Q", "unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c", null ], + [ "T", "unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658", null ], + [ "V", "unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a", null ], + [ "w", "unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2", null ], + [ "Z", "unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562", null ] +]; \ No newline at end of file -- cgit